Ultrasonic phased array timing control method and device, ultrasonic equipment

Abstract

The present invention discloses a timing control method and device for an ultrasonic phased array, and an ultrasonic device. The ultrasonic phased array includes multiple channels, and the timing control method for the ultrasonic phased array includes: obtaining an input signal and a clock signal, and processing the input signal according to the clock signal to form multiple delay signals; wherein the delay times of the multiple delay signals are different; obtaining a chip select signal, and selecting the delay signal output to the channel corresponding to the chip select signal according to the chip select signal; wherein the number of the chip select signals is the same as the number of the channels. The embodiment of the present invention can simplify the timing control method for the ultrasonic phased array and improve its operability on the basis of ensuring the delay accuracy.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of ultrasonic technology, and in particular to a timing control method and device of an ultrasonic phased array, and ultrasonic equipment. Background Art

[0002] With the rapid development of microelectronics and computer technology, ultrasound has been used more and more widely in life; especially ultrasonic phased array, which has attracted more and more attention due to its precision advantages in positioning, quantification and orientation. Ultrasonic phased array generates a dynamically focused sound beam by changing the excitation signal of the array element array in the phased array probe, so that the focal point has greater energy, and then uses the focal point to achieve ultrasonic imaging and nerve stimulation. In the design of the driving system of the ultrasonic phased array, there are strict requirements on the delay accuracy between the channels of the ultrasonic phased array. Therefore, how to ensure the phase delay accuracy of the ultrasonic phased array is one of the key issues faced in the research of ultrasonic phased array.

[0003] The prior art generally uses a tap delay line for hardware delay, or performs timing control through DSP programming. However, the equipment used in the hardware delay method is large in size, complex in structure, easily affected by factors such as temperature, and cannot dynamically adjust the delay according to requirements. The existing timing control made by DSP programming usually requires the programming of functional devices such as delay counters and comparators, which makes the delay algorithm complex and the operability poor. For example, a phased-control transmission delay module in the prior art is composed of a delay counter, a parameter register and a comparator. During phased transmission, under the action of a trigger signal, the delay counter starts counting, and the comparator compares the values ​​in the delay counter and the delay value parameter register. When the two are equal, a high-level pulse signal is output as an enable signal for the subsequent address generator; the delay algorithm is complex and the delay accuracy is not high. In addition, in the prior art, each channel of the ultrasonic phased array needs to correspond to a complete delay structure respectively; when there are many channels of the ultrasonic phased array, the overall logic of the delay controller is more complex and difficult to coordinate. Therefore, the timing control method of the ultrasonic phased array in the prior art has the problem of poor delay stability or complex control method. Summary of the invention

[0004] The embodiments of the present invention provide a timing control method and device for an ultrasonic phased array, and ultrasonic equipment, so as to simplify the timing control method for an ultrasonic phased array and improve its operability while ensuring delay accuracy.

[0005] In a first aspect, an embodiment of the present invention provides a timing control method of an ultrasonic phased array, wherein the ultrasonic phased array includes a plurality of channels; the timing control method includes:

[0006] Acquire an input signal and a clock signal, and process the input signal according to the clock signal to form a plurality of delayed signals; wherein the delay times of the plurality of delayed signals are different;

[0007] A chip select signal is obtained, and a delay signal is selected and output to the channel corresponding to the chip select signal according to the chip select signal; wherein the number of the chip select signals is the same as the number of the channels.

[0008] Optionally, processing the input signal according to the clock signal to form a plurality of delayed signals includes:

[0009] Performing shift processing on the input signal to obtain a first delayed signal;

[0010] The i-th delayed signal is shifted to obtain the i+1-th delayed signal; i is an integer greater than 0.

[0011] Optionally, the delay interval between the i-th delayed signal and the (i+1)-th delayed signal is one clock cycle of the clock signal.

[0012] Optionally, before obtaining the input signal and the clock signal, the following steps are further included:

[0013] Get the initial clock signal;

[0014] The initial clock signal is frequency-multiplied to obtain the clock signal.

[0015] Optionally, the initial clock signal is provided by an active crystal oscillator.

[0016] Optionally, before obtaining the input signal and the clock signal, the following steps are further included:

[0017] Acquire a reset signal; and reset the ultrasonic phased array according to the reset signal.

[0018] In a second aspect, an embodiment of the present invention further provides a timing control device for an ultrasonic phased array, comprising:

[0019] A delay module, used for acquiring an input signal and a clock signal, and processing the input signal according to the clock signal to form a plurality of delayed signals; wherein the delay times of the plurality of delayed signals are different;

[0020] A selection module is used to obtain a chip select signal and select, according to the chip select signal, a delay signal output to a channel of the ultrasonic phased array corresponding to the chip select signal; wherein the number of the selection modules is the same as the number of the channels.

[0021] Optionally, the delay module includes:

[0022] A plurality of cascaded shift register units; the first shift register unit receives the input signal, the other shift register units receive the output signal of the previous shift register unit, and all the shift register units receive the clock signal; the shift register unit is used to control the shift output of the received signal according to the clock signal; the output signal of the i-th shift register unit is used as the i-th delay signal; i is an integer greater than 0.

[0023] Optionally, the timing control device of the ultrasonic phased array further includes: a clock signal generating module, used to obtain an initial clock signal before obtaining the input signal and the clock signal; and perform frequency multiplication processing on the initial clock signal to obtain the clock signal.

[0024] In a third aspect, an embodiment of the present invention further provides an ultrasonic device, comprising:

[0025] An ultrasonic probe, comprising a plurality of array elements, wherein the plurality of array elements are combined into an ultrasonic phased array;

[0026] A memory, a processor, and a computer program stored in the memory and executable on the processor; when the processor executes the program, the timing control method of the ultrasonic phased array provided in any embodiment of the present invention is implemented.

[0027] The timing control method of the ultrasonic phased array provided in the embodiment of the present invention adopts a digital control method. Compared with the method of using hardware taps, it can realize flexible adjustment of the delay time, and the anti-interference ability is stronger than that of the hardware tap, and the accuracy of the delay timing control can be guaranteed. In the embodiment of the present invention, a series of delay signals with different delay times can be obtained by processing the input signal according to the clock signal; then, the delay signals required by each channel of the ultrasonic phased array can be selected from a series of delay signals according to the chip select signal corresponding to each channel. In this way, by giving the chip select signal corresponding to each channel, the delay time of each channel can be independently adjustable, so that the focus point position of the phased array can be freely changed to realize the scanning of the ultrasonic phased array. In addition, in the embodiment of the present invention, only a set of delay signal generation logic and a series of multiple-selection data selection logic are required to control the delay timing of each channel of the ultrasonic phased array. When the number of phased array channels increases, only the corresponding increase in data selection logic is required to realize independent control of each channel, without the need to equip each channel with a complete set of delay control, which effectively reduces the complexity of the algorithm and is easy to implement. Therefore, compared with the prior art, the embodiments of the present invention can simplify the timing control method of the ultrasonic phased array and improve its operability while ensuring the delay accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a flow chart of a timing control method of an ultrasonic phased array provided by an embodiment of the present invention;

[0029] Figure 2 is a flow chart of another timing control method of an ultrasonic phased array provided by an embodiment of the present invention;

[0030] Figure 3 is a structural schematic diagram of a timing control device for an ultrasonic phased array provided by an embodiment of the present invention;

[0031] Figure 4 is a structural schematic diagram of another timing control device for an ultrasonic phased array provided in an embodiment of the present invention;

[0032] Figure 5 It is a schematic diagram of the structure of an ultrasonic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0034] An embodiment of the present invention provides a timing control method for an ultrasonic phased array. The timing control method can be implemented based on a timing control device for an ultrasonic phased array and is applicable to driving requirements for a multi-channel ultrasonic phased array, especially for an ultrasonic phased array with a large number of channels. Figure 1 FIG. 1 is a flow chart of a timing control method of an ultrasonic phased array provided by an embodiment of the present invention. Figure 1 As shown, the timing control method of the ultrasonic phased array includes:

[0035] S110, acquiring an input signal and a clock signal, and processing the input signal according to the clock signal to form a plurality of delayed signals; wherein the delay times of the plurality of delayed signals are different.

[0036] Exemplarily, the delay time difference of multiple delay signals is the same. The number of delay signals can be less than or equal to the number of channels, and the specific number can be set according to actual needs and is not limited here. The process of forming multiple delay signals can specifically be: under the control of the clock signal, the input signal is shifted to obtain the first delay signal; the i-th delay signal is shifted to obtain the i+1-th delay signal; i is an integer greater than 0. In other words, the input signal is controlled by the clock signal to shift and output step by step to form a series of delay signals. The above control process can be achieved by writing a cascaded shift register. Exemplarily, the shift register is implemented by the logic function of a D flip-flop, and the delay interval between the i-th delay signal and the i+1-th delay signal is one clock cycle of the clock signal. The delay accuracy can be controlled by controlling the frequency of the clock signal.

[0037] S120, obtaining a chip select signal, and selecting a delay signal to be output to a channel corresponding to the chip select signal according to the chip select signal; wherein the number of chip select signals is the same as the number of channels.

[0038] The chip select signal may be given by the user according to actual needs; the chip select signal may include the delay time information required by the corresponding channel. Exemplarily, this step may be implemented by programming data selectors with the same number as the channels.

[0039] The timing control method of the ultrasonic phased array provided in the embodiment of the present invention adopts a digital control method. Compared with the method of using hardware taps, it can realize flexible adjustment of the delay time, and the anti-interference ability is stronger than that of the hardware tap, and the accuracy of the delay timing control can be guaranteed. In the embodiment of the present invention, a series of delay signals with different delay times can be obtained by processing the input signal according to the clock signal; then, the delay signals required by each channel of the ultrasonic phased array can be selected from a series of delay signals according to the chip select signal corresponding to each channel. In this way, by giving the chip select signal corresponding to each channel, the delay time of each channel can be independently adjustable, so that the focus point position of the phased array can be freely changed to realize the scanning of the ultrasonic phased array. In addition, in the embodiment of the present invention, only a set of delay signal generation logic and a series of multiple-selection data selection logic are required to control the delay timing of each channel of the ultrasonic phased array. When the number of phased array channels increases, only the corresponding increase of chip select signals and data selection logic is required to realize independent control of each channel, without the need to equip each channel with a complete set of delay control, which effectively reduces the complexity of the algorithm and is easy to implement. Therefore, compared with the prior art, the embodiments of the present invention can simplify the timing control method of the ultrasonic phased array and improve its operability while ensuring the delay accuracy.

[0040] Figure 2 FIG. 1 is a flow chart of another method for timing control of an ultrasonic phased array provided by an embodiment of the present invention. Figure 2 In one embodiment, optionally, the timing control method of the ultrasonic phased array includes:

[0041] S210: Acquire an initial clock signal.

[0042] The initial constant signal may be provided by an active crystal oscillator, such as a 50 MHz crystal oscillator.

[0043] S220, performing frequency multiplication processing on the initial clock signal to obtain a clock signal.

[0044] Among them, the frequency can be multiplied by a PLL phase-locked loop to increase the clock period and improve the delay accuracy.

[0045] S230, obtaining a reset signal; and resetting the ultrasonic phased array according to the reset signal.

[0046] This step may be to control each delayed signal to be converted into an invalid level through a reset signal, so that each channel of the ultrasonic phased array has the same initial state.

[0047] S240: Generate an input signal.

[0048] Among them, the input signal can be generated by writing a waveform generator function module.

[0049] S250: Obtain input signal and clock signal.

[0050] S260, processing the input signal according to the clock signal to form a plurality of delayed signals; wherein the delay times of the plurality of delayed signals are different.

[0051] S270, obtain a chip select signal.

[0052] S280, determine whether the delay signal is the delay signal corresponding to the chip select signal; if so, execute S290; if not, continue to execute S280.

[0053] Exemplarily, the chip select signal may represent the delay time required by the corresponding channel.

[0054] S290, output delay signal.

[0055] This embodiment designs a timing control logic of an ultrasonic phased array through S210-S290, which can realize high-precision and high-resolution phase delay control, so that the ultrasound can focus on the target more accurately. By controlling the period of the clock signal, the delay accuracy can be effectively adjusted, and the delay time accuracy can reach the nanosecond level. In this embodiment, when there are many channels of the ultrasonic phased array, the delay time of each channel can also be adjusted independently. Therefore, under the control of the delay method, various styles of changes to the focus point can be freely completed, such as plane scanning, space scanning, scanning with regular time intervals, etc. In addition, all programs in this embodiment can be written by FPGA. Compared with the use of hardware taps, this method does not have problems such as hardware wear, and the frequency of the crystal oscillator can remain stable for a long time. Therefore, the delay control stability of the present invention is relatively high, and the delay can still maintain high precision under long-term high-intensity continuous work. In addition, most of the existing technologies have only realized simulation, and have not made finished products applied to experiments or technologies; but the logic of this embodiment is concise and clear, easy to implement, and conducive to the realization of finished products.

[0056] An embodiment of the present invention provides a timing control device for an ultrasonic phased array, which can be used to implement the timing control method for an ultrasonic phased array provided by any embodiment of the present invention, and has corresponding beneficial effects. Figure 3is a schematic diagram of the structure of a timing control device for an ultrasonic phased array provided by an embodiment of the present invention. Figure 3 The timing control device of the ultrasonic phased array includes: a delay module 310 and multiple selection modules 320.

[0057] The delay module 310 is used to obtain an input signal and a clock signal, and process the input signal according to the clock signal to form a plurality of delay signals; wherein the delay times of the plurality of delay signals are different. The selection module 320 is used to obtain a chip select signal, and select the delay signal of the channel of the ultrasonic phased array corresponding to the chip select signal according to the chip select signal; wherein the number of the selection modules 320 is the same as the number of the channels.

[0058] In the timing control device of the ultrasonic phased array provided by the embodiment of the present invention, the delay module 310 can obtain a series of delay signals with different delay times by processing the input signal according to the clock signal; the selection module 320 can select the delay signal required by the channel from the series of delay signals according to the chip select signal corresponding to the channel. In this way, by giving the chip select signal corresponding to each channel, the independent adjustment of the delay time of each channel can be achieved. In addition, when the number of phased array channels increases, it is only necessary to increase the chip select signal and the selection module 320 accordingly, without adding a delay module 310, and without equipping each channel with a complete set of delay structures, which effectively reduces the complexity of the control device and is easy to implement. Therefore, compared with the prior art, the embodiment of the present invention can simplify the timing control device of the ultrasonic phased array and improve its operability on the basis of ensuring the delay accuracy.

[0059] Combine the following Figure 4 , the structure of the timing control device is described through a specific embodiment, but it is not intended to limit the present invention. Figure 4 is a schematic diagram of the structure of another timing control device for an ultrasonic phased array provided by an embodiment of the present invention. Figure 4 On the basis of the above embodiments, the delay module 310 optionally includes: a plurality of cascaded shift register units; the first shift register unit 311-1 receives an input signal insignal, the other shift register units receive an output signal of the previous shift register unit, and all shift register units receive a clock signal clk; the shift register unit is used to control the shift output of the received signal according to the clock signal clk; the output signal of the i-th shift register unit 311-i is used as the i-th delay signal delay_i; i is an integer greater than 0. Exemplarily, the shift register unit can be composed of a D flip-flop or other programmable logic devices.

[0060] Continue to see Figure 4On the basis of the above embodiments, optionally, all shift register units are connected to a reset signal rst. Before driving the ultrasonic phased array, the reset signal rst can control all shift register units to reset uniformly.

[0061] Continue to see Figure 4 On the basis of the above embodiments, the selection module 320 can be optionally implemented by a multiple-select-one data selector or other logic devices with the same function. Taking the data selector as an example, each data selector is connected to a chip select signal. For example, the first data selector is connected to the first chip select signal sel_1, and selects a suitable delay signal as the first output signal out_1 according to the first chip select signal sel_1, and outputs it to the corresponding channel.

[0062] Continue to see Figure 4 On the basis of the above embodiments, optionally, the timing control device of the ultrasonic phased array further includes: an input signal generating module 330, which is used to generate an input signal insignal. The module may be composed of a waveform generator, for example.

[0063] On the basis of the above embodiments, the timing control device of the ultrasonic phased array may further include: a clock signal generating module, which is used to obtain an initial clock signal before obtaining an input signal and a clock signal; and to perform frequency multiplication processing on the initial clock signal to obtain a clock signal. The frequency multiplication processing may be implemented by a phase-locked loop; or by replacing an onboard crystal oscillator or an active crystal oscillator with a higher frequency.

[0064] by Figure 4 For example, the control process of the timing control device of the ultrasonic phased array includes: resetting the delay module 31 through the reset signal rst; generating the input signal insignal through the waveform generator; under the control of the clock signal clk, the input signal insignal is transmitted from the previous D flip-flop to the next D flip-flop after each clock cycle. The series-connected D flip-flops act as a delay device under the control of the clock signal clk, and all D flip-flops lead to an output to all data selectors, and multiple chip select signals are used to control multiple multi-select data selectors respectively, so that they output the delay signal required by the corresponding channel.

[0065] An embodiment of the present invention further provides an electronic device. Figure 5 It is a schematic diagram of the structure of an ultrasonic device provided by an embodiment of the present invention. Figure 5 The block diagram of an exemplary ultrasonic device suitable for implementing the timing control method of an ultrasonic phased array provided by any embodiment of the present invention is shown, and does not bring any limitation to the function and scope of use of the embodiments of the present invention.

[0066] See also Figure 5 The ultrasonic device includes an input device 540, an ultrasonic probe 530, a memory 510, a processor 520, and a computer program stored in the memory 510 and executable on the processor 520. The ultrasonic probe 530 includes a plurality of array elements, which are combined into an ultrasonic phased array; when the processor 520 executes the program, the timing control method of the ultrasonic phased array provided in any embodiment of the present invention is implemented, which is used to drive the ultrasonic phased array in the ultrasonic probe 530.

[0067] Exemplarily, the processor 520, the memory 510, the input device 540 and the ultrasound probe 530 in the ultrasound device may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0068] The memory 510, as a computer-readable storage medium, can be used to store software programs, computer executable programs and modules, such as program instructions / modules corresponding to the timing control method of the ultrasonic phased array in the embodiment of the present invention (for example, a delay module and a selection module of the timing control device of the ultrasonic phased array). The processor 520 executes various functional applications and data processing of the device / terminal / server by running the software programs, instructions and modules stored in the memory 510.

[0069] The memory 510 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the terminal, etc. In addition, the memory 510 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 510 may further include a memory remotely arranged relative to the processor 520, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0070] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A timing control method for an ultrasonic phased array, characterized in that: The ultrasonic phased array includes a plurality of channels; the timing control method includes: Acquire an input signal and a clock signal, and process the input signal according to the clock signal to form a plurality of delayed signals; wherein the delay times of the plurality of delayed signals are different; Obtain a chip select signal, and select, according to the chip select signal, a delay signal output to the channel corresponding to the chip select signal; wherein the number of the chip select signals is the same as the number of the channels; Processing the input signal according to the clock signal to form a plurality of delayed signals includes: Performing shift processing on the input signal to obtain a first delayed signal; Shifting the i-th delayed signal to obtain the i+1-th delayed signal; i is an integer greater than 0; The input signal is controlled by the clock signal to shift the output step by step, forming a series of delayed signals.

2. The timing control method of ultrasonic phased array according to claim 1, characterized in that: The delay interval between the i-th delayed signal and the (i+1)-th delayed signal is one clock cycle of the clock signal.

3. The timing control method of ultrasonic phased array according to claim 1, characterized in that: Before obtaining the input signal and clock signal, it also includes: Get the initial clock signal; The initial clock signal is frequency-multiplied to obtain the clock signal.

4. The timing control method of ultrasonic phased array according to claim 3, characterized in that: The initial clock signal is provided by an active crystal oscillator.

5. The timing control method of ultrasonic phased array according to claim 1, characterized in that: Before obtaining the input signal and clock signal, it also includes: Acquire a reset signal; and reset the ultrasonic phased array according to the reset signal.

6. A timing control device for an ultrasonic phased array, characterized in that: include: A delay module, used for acquiring an input signal and a clock signal, and processing the input signal according to the clock signal to form a plurality of delayed signals; wherein the delay times of the plurality of delayed signals are different; A selection module, used for acquiring a chip selection signal, and selecting, according to the chip selection signal, a delay signal output to a channel of the ultrasonic phased array corresponding to the chip selection signal; wherein the number of the selection modules is the same as the number of the channels; The delay module comprises: A plurality of cascaded shift register units; the first shift register unit receives the input signal, the other shift register units receive the output signal of the previous shift register unit, and all the shift register units receive the clock signal; the shift register unit is used to control the shift output of the received signal according to the clock signal; the output signal of the i-th shift register unit is used as the i-th delay signal; i is an integer greater than 0.

7. The timing control device of ultrasonic phased array according to claim 6, characterized in that: Also includes: A clock signal generating module, used for obtaining an initial clock signal before obtaining an input signal and a clock signal; The initial clock signal is frequency-multiplied to obtain the clock signal.

8. An ultrasonic device, characterized in that: include: An ultrasonic probe, comprising a plurality of array elements, wherein the plurality of array elements are combined into an ultrasonic phased array; A memory, a processor, and a computer program stored in the memory and executable on the processor; when the processor executes the program, the timing control method for an ultrasonic phased array as described in any one of claims 1 to 5 is implemented.

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