SIMD Multiplier and Digital Processor

Abstract

The present disclosure provides new SIMD multipliers and digital processors, wherein an input unit distributes a multiplicand and a multiplier to each partial product generation unit or its corresponding constant multiplication unit according to a control signal; each selector selects, according to the control signal, to provide the partial products generated by the partial product generation unit or its corresponding constant multiplication unit to a partial product compression unit; the partial product compression unit outputs the signals obtained by compressing the partial products received from the respective selectors to adders corresponding to the respective partial product generation units for combination to generate a first product, and outputs the signals obtained by compressing all the partial products provided by the selectors to a final product synthesis unit to generate a second product; an output unit selects, according to the control signal, to output a plurality of first products or a second product. This solution reuses existing components and improves the operation speed of the multiplier with a small amount of hardware modification.

Description

Technical Field

[0001] The present invention relates to digital signal processing, and particularly to a multiplier and a digital processor including the multiplier. Background Art

[0002] A multiplier is an important basic component in a microprocessor and a digital signal processor, and is the core of real-time signal processing such as image processing. Its performance largely affects the performance of the system in processing data. Traditional hardware multipliers often adopt a method combining "serial shift" and "parallel addition", but this serial accumulation and shift method is difficult to meet the requirements of real-time signal processing. Therefore, many high-performance digital signal processors add SIMD (Single Instruction Multiple Data) multiplier components to improve the parallelism of data processing.

[0003] Generally, a high-order SIMD multiplier can be implemented by using multiple low-order multipliers. For example, a 64-bit multiplier can be implemented by 2 32×32-bit multipliers or 4 64×16-bit multipliers, and a 32×32-bit multiplier can be implemented by 4 32×8 multipliers or 2 32×16 multipliers, and a 64×16-bit multiplier can be implemented by 2 64×8-bit multipliers. However, for an N-bit multiplier, only one N×N-bit multiplication operation can still be completed in one cycle. Summary of the Invention

[0004] The inventors found in their research that there are a large number of multiplication operations of variables multiplied by constants in high-performance operations. For example, in hash operations such as the FNV hash algorithm, there are a large number of operations of multiplying the data to be hashed by a certain constant. Using the existing N-bit multiplier, only one multiplication operation result of an N-bit variable and a constant (Constant, hereinafter denoted as Con) can be obtained in each cycle, and the execution efficiency is not high. In an embodiment of the present invention, a new N-bit SIMD multiplier and a digital processor are provided, which can not only implement one N×N-bit multiplication operation in one cycle, but also support the implementation of multiple parallel N×Con multiplication operations, where Con is an N-bit binary constant, so as to improve the efficiency of the multiplier.

[0005] According to the first aspect of the embodiments of the present invention, a SIMD multiplier is provided, including an input unit, an output unit, a plurality of partial product generation units, a partial product compression unit, a final product synthesis unit, a constant multiplication unit corresponding to each partial product generation unit, a selector, and an adder. The input unit is configured to distribute corresponding multiplicands and multipliers to each partial product generation unit or each constant multiplication unit according to the received control signal. Each selector is configured to select and provide the partial products generated by the partial product generation unit or its corresponding constant multiplication unit to the partial product compression unit according to the control signal. The partial product compression unit is configured to compress the partial products received from each selector to obtain a sum signal and a carry signal and provide them to the final product synthesis unit, and to compress the partial products provided by each selector to obtain a sum signal and a carry signal and provide them to the corresponding adder for combination to generate a first product. The final product synthesis unit is configured to combine the sum signal and the carry signal from the partial product compression unit to generate a second product. The output unit is configured to output the first product generated by each adder or the second product generated by the final product synthesis unit according to the control signal.

[0006] In some embodiments of the present invention, the multiplicands and multipliers assigned to each constant multiplication unit have the same number of bits, the multiplier is a constant, and the number of bits that are 1 in the multiplier does not exceed the ratio between the bit width of the multiplier and the number of partial product generation units.

[0007] In some embodiments of the present invention, the input unit is configured to: in response to a control signal indicating the execution of a normal multiplication operation, segment the multiplier according to the number of partial product generation units, and distribute the multiplicand and the segmented multiplier to each partial product generation unit; in response to a control signal indicating the execution of a constant multiplication operation, distribute each multiplicand and its corresponding multiplier to each constant multiplication unit.

[0008] In some embodiments of the present invention, the partial product compression unit can be a Wallace tree structure that performs 4-2 compression using a carry-save adder.

[0009] In some embodiments of the present invention, the bit width of the multiplier can be 32, 64, or 128. The number of partial product generation units can be 2, 4, 8, or 16.

[0010] According to the second aspect of the embodiments of the present invention, a digital processor is provided, including a controller and a multiplier according to the first aspect of the embodiments of the present invention, wherein the multiplier performs a corresponding multiplication operation according to the control signal, multiplicand, and multiplier received from the controller.

[0011] The technical solutions provided by the embodiments of the present invention can include the following beneficial effects:

[0012] It can not only reuse the components of the existing multiplier to implement normal N×N-bit multiplication operations, but also support parallel multi-channel N×N-bit constant multiplication operations within one cycle, which improves the operation speed of the multiplier to a certain extent. For specific algorithms with a large number of N×constant multiplication operations, it can significantly improve their execution efficiency. For example, in encryption and decryption algorithms, a large number of FNV hash operations are often cyclically called. By using the multiplier according to the embodiments of the present invention, these FNV hash operations can be quickly executed, thereby improving the utilization rate of computing resources.

[0013] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments in accordance with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0015] In the drawings:

[0016] Figure 1 is a schematic diagram of the binary multiplication process;

[0017] Figure 2 is a schematic diagram of the structure of a 32-bit SIMD multiplier including 4 32×8-bit multipliers;

[0018] Figure 3 is a schematic diagram of the structure of a 32-bit SIMD multiplier according to an embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of the functional modules of a digital processor including a multiplier according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below through specific embodiments with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0021] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present invention. However, those skilled in the art will realize that the technical solutions of the present invention may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present invention.

[0022] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0023] The flowcharts shown in the drawings are only illustrative and do not necessarily include all the content and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps may be decomposed, while some operations / steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

[0024] Figure 1 A schematic diagram of the binary multiplication process is given. As Figure 1 shown, when performing multiplication, the first operand is the multiplicand (such as 101010), the second operand is the multiplier (1011), and the result of multiplying each bit in the multiplier with the multiplicand is called a partial product. After adding all the partial products, the operation result is called the product. In Figure 1 the multiplier is 4 bits, so 4 partial products 101010, 101010, 000000, 101010 can be obtained. After shifting and adding the four partial products, the final product 111001110 is obtained. It can be seen that the multiplication operation is mainly completed in three steps: generating partial products, accumulating partial products, and finally adding.

[0025] The implementation circuit structure of a common multiplier usually includes an input unit, a partial product generation unit, a partial product compression unit, a final product synthesis unit, and an output unit. Among them, the input unit is used to input the multiplier and the multiplicand into the partial product generation unit. The partial product generation unit is used to operate on each bit of the multiplier and the multiplicand received from the input unit to generate partial products. The number of partial products directly affects the performance of the multiplier. Usually, the Booth encoding algorithm can be used to reduce the number of generated partial products. The partial product generation unit outputs the generated partial products to the partial product compression unit. The accumulation speed of the generated partial products has a direct impact on the latency of the multiplier. Usually, the Wallace tree algorithm can be used in the partial product compression unit to improve the accumulation speed of partial products. The Wallace tree structure is a commonly used adder array structure for multiplication operations currently. The commonly used Wallace tree algorithm in SIMD multipliers is CSA&4-2 compressor, that is, using the Carry-Save Adder (CSA) as the basic unit to construct a Wallace tree structure with successive 4-2 compression to accumulate and compress the partial products. The sum signal and the carry signal obtained after the partial product compression unit accumulates and compresses the partial products from the partial product generation unit using the carry-save adder are provided to the final product synthesis unit. The final product synthesis unit combines the sum signal and the carry signal from the partial product compression unit to generate the product and provides it to the output unit. The output unit can output the signal received from the final product synthesis unit in an asynchronous operation or synchronous operation mode.

[0026] Higher-bit SIMD multipliers can be implemented using multiple lower-bit multipliers. For example, a 32-bit SIMD multiplier can be implemented by 4 32×8-bit multipliers, and a 64-bit SIMD multiplier can be implemented by 8 32×8-bit multipliers, 4 32×16-bit multipliers, or two 32×32-bit multipliers. For the convenience of description, in this article, the 32×8-bit multiplier is used as an example of the lower-bit multiplier to describe the specific structure of the higher-bit SIMD multiplier, but it is not intended to impose any restrictions on this. As Figure 2As shown, to improve the parallelism of data processing, a 32-bit SIMD multiplier can complete a 32×32-bit multiplication operation through the simultaneous parallel operation of four 32×8-bit multipliers. Each of these 32×8-bit multipliers serves as a partial product generation unit. The input unit divides the 32-bit multiplier B in the received multiplication instruction into several multiplier segments B[7:0], B[15:8], B[23:16], and B[31:24] according to the number of partial product generation units, and distributes these multiplier segments and the multiplicand A[31:0] to each partial product generation unit. Since the number of bits of each multiplier segment is 8, each partial product generation unit can generate 8 partial products, and the four partial product generation units generate a total of 32 partial products. The partial product compression unit consists of a four-stage 4-2 compression Wallace tree structure constructed with carry-save adders (CSA) as the basic unit. In the first stage, every 4 partial products from the partial product generation unit are processed by a CSA 4:2 compressor to generate a sum signal and a carry signal, which are then passed to the CSA 4:2 compressor in the next stage for processing. Each CSA 4:2 compressor in the second stage processes the four signals from the previous stage and outputs two signals (sum signal and carry signal), which are continuously passed to the CSA 4:2 compressor in the next stage until the final two signals are obtained in the fourth stage. As the number of partial products generated by the partial product generation unit varies, the number of stages of this Wallace tree will increase or decrease accordingly. The two signals (sum signal and carry signal) obtained after accumulating and compressing the 32 partial products through the partial product compression unit are passed to the final product merging unit. The final product synthesis unit merges the sum signal and the carry signal from the partial product compression unit through a 64-bit adder to generate the product, which is then provided to the output unit.

[0027] For such a 32-bit SIMD multiplier, 1 32×32-bit multiplication operation or 4 32×8 multiplications can be performed in one cycle. However, in high-performance operations, there are a large number of multiplication operations involving variables and constants, such as in hash operations like the FNV hash algorithm, which involve a large number of operations of multiplying the data to be hashed by a certain constant. Using the existing N-bit multiplier, only 1 multiplication result of an N-bit variable and an N-bit constant can be obtained per cycle, and the data processing efficiency is not high.

[0028] Therefore, in an embodiment of the present invention, a new N-bit SIMD multiplier is provided. In addition to including the above-mentioned input unit, multiple partial product generation units, partial product compression unit, final product synthesis unit, and output unit, a constant multiplication unit, a selector, and an adder corresponding to each partial product generation unit are added. It can perform 1 N×N-bit multiplication operation or multiple parallel N×Con multiplication operations (for convenience, hereinafter simply referred to as constant multiplication operations or operations) within one cycle to improve the data processing efficiency of the multiplier. In an embodiment of the present application, Con is an N-bit binary constant, and N can be 2 t , and t is a natural number greater than or equal to 4. N is preferably 32, 64, 128, or 256. For ease of description and comparison with Figure 2 , hereinafter, N is still taken as 32 to illustrate the structure of the SIMD multiplier. The low-bit multiplier still uses a 32×8-bit multiplier as an example. However, it should be understood that a similar structure can be extended to  64-bit, 128-bit, and 256-bit multipliers, and the low-bit multiplier is not limited to a 32×8-bit multiplier.

[0029] Figure 3 FIG. is a schematic structural diagram of a 32-bit SIMD multiplier according to an embodiment of the present invention. Compared with Figure 2 the existing 32-bit SIMD multiplier shown, four constant multiplication units a, b, c, and d are added in this embodiment. These four constant multiplication units have the same function and are all used for constant multiplication operations where one of the operands is a constant, and they respectively correspond to the original partial product generation units (i.e., multipliers a, b, c, and d). The operands of multipliers a, b, c, and d are a 32-bit multiplicand and an 8-bit multiplier; while the operands of constant multiplication units a, b, c, and d can be a 32-bit multiplicand and a 32-bit constant. Compared with Figure 2 , in Figure 3 the multiplier structure, selectors a, b, c, and d corresponding to each partial product generation unit are also added. In this way, when performing a normal multiplication operation, selectors a, b, c, and d respectively select the 8 partial products output by multipliers a, b, c, and d and provide them to the subsequent partial product compression unit. When performing a constant multiplication operation, selectors a, b, c, and d respectively select the 8 partial products output by constant multiplication units a, b, c, and d and provide them to the subsequent partial product compression unit.

[0030] Compared with Figure 2Similarly, the partial product compression unit still adopts a four-stage 4-2 compression Wallace tree structure constructed with carry-save adders (CSA) as the basic units. Through each selector, the 8 partial products generated by the corresponding partial product generation units are sent to the first-stage 4:2 compressor module (hereinafter also abbreviated as the CSA_4_2 module) constructed with CSA as the basic unit and the second-stage CSA_4_2 module. Each CSA_4_2 module compresses the corresponding partial products into two signals, namely the sum signal and the carry signal. As Figure 3 shown, after the first-stage and second-stage CSA_4_2 compression, the partial products from each partial product generation unit are compressed into a sum signal and a carry signal, which can be denoted as {sum0, carry0}, {sum1, carry1}, {sum2, carry2}, {sum3, carry3}.

[0031] Different from Figure 2 this, in the embodiment of the present invention, a corresponding adder is also set for each partial product generation unit to generate the product corresponding to the partial product generation unit. As Figure 3 shown, the signals {sum0, carry0}, {sum1, carry1}, {sum2, carry2}, {sum3, carry3} corresponding to each partial product generation unit are respectively sent to their corresponding 32-bit adders a, b, c, d. Each 32-bit adder generates the first product a, the first product b, the first product c, and the first product d and directly provides them to the output unit. It can be understood that different from Figure 2Similarly, the signals {sum0, carry0}, {sum1, carry1}, {sum2, carry2}, {sum3, carry3} corresponding to each partial product generation unit can also be output to the third-level CSA_4_2. Among them, {sum0, carry0} is directly output to the third-level CSA_4_2 module, {sum1, carry1} is shifted left by 8 bits respectively, {sum2, carry2} is shifted left by 16 bits respectively, and {sum3, carry3} is shifted left by 24 bits respectively and then output to the third-level CSA_4_2 module. The third-level CSA_4_2 module continues to compress the 8 received signals into 4 signals and provides them to the fourth-level CSA_4_2 module. The fourth-level CSA_4_2 module compresses the 4 received signals into 2 signals. In this way, the 2 signals obtained after the fourth-level compression are denoted as {final_sum, final_carry}, which are output to the final product synthesis unit implemented by a 64-bit adder, thereby obtaining the second product representing the normal multiplication operation. In this embodiment, the output unit can select whether to output a second product or four first products as the execution result of the SIMD multiplier according to the control signal from the input unit. It can be seen that Figure 3 The multiplier architecture can not only be used to perform a normal 1-time N×N bit multiplication operation in one cycle, but also be used to implement multiple N×N bit constant multiplication operations (such as FNV operation) in one cycle. And Figure 2 The multiplier architecture shown can only perform 1-time 32×32 bit multiplication operation in one cycle, and cannot perform multiple FNV operations. Compared with Figure 2 The multiplier architecture shown, through Figure 3 The multiplier architecture of the example, in the case of reusing the 32-bit multiplier architecture, by adding a small amount of hardware resources, multiple SIMD FNV operations can be implemented in one cycle, and the FNV performance can be increased to 4 times that of the ordinary 32×32 multiplier.

[0032] It can be understood that based on Figure 3 The principle of the shown structure, in other embodiments, for the specific quantity of each unit module in the multiplier architecture, it can be set according to actual requirements.

[0033] In the embodiment of the present invention, in addition to receiving the multiplicand and the multiplier, the input unit also receives a control signal, which is used to indicate whether to perform a normal multiplication operation or a constant multiplication operation. The input unit can allocate the corresponding multiplicand and multiplier to the partial product generation unit according to the received control signal (such as Figure 3The 32×8 multiplier shown in or a constant multiplication unit. For example, if the control signal is 1, the input unit distributes the received operands to the partial product generation unit. If the control signal is 0, the input unit distributes the received operands to the constant multiplication unit, and vice versa. In the following, it is described by taking the control signal being 1 to indicate the execution of a normal multiplication operation and the control signal being 0 to indicate the execution of a constant multiplication operation as an example. When the input unit receives a control signal of 1, it segments the multiplier according to the number of partial product generation units, and distributes the multiplicand and the segmented multiplier to each partial product generation unit. When the input unit receives a control signal of 0, it distributes the multiple received multiplicands and the constant Con to each constant multiplication unit.

[0034] Taking Figure 3 the multiplier structure shown as an example, if the received control signal is 1 (indicating the execution of a normal multiplication operation, that is, 1 N×N-bit multiplication operation; for example, performing A*B), then the 4 identical multiplicands (A, A, A, A) and the segmented multiplier (B[31:24], B[23:16], B[15:8], B[7:0]) are distributed to 4 32x8 multipliers. If the received control signal is 0 (indicating the execution of a constant multiplication operation, at this time, 4 N×N-bit multiplication operations can be performed in parallel; for example, performing A0*B0, A1*B1, A2*B2, A3*B3), then the 4 different multiplicands (A0, A1, A2, A3) and the corresponding multipliers (at this time, the corresponding multipliers B0, B1, B2, B3 are all constants) are sent to 4 constant multiplication units respectively. The multipliers B0, B1, B2, B3 as constants can be different binary constants or the same binary constants. In some embodiments, when the input unit determines that the control signal indicates the execution of a constant multiplication operation, it can also set each segment of the multiplier input to the 32×8 multiplier to 0.

[0035] It should be understood that the above control signal is only an example, and it can adopt various implementation forms to indicate whether to execute a normal multiplication operation or a constant multiplication operation. Optionally, the number of the above control signals can also be more than one. For example, two signals can be set: a first control signal and a second control signal. When the first control signal is valid, it indicates the execution of a normal multiplication operation. When the second control signal is valid, it indicates the execution of a constant multiplication operation.

[0036] Optionally, to better utilize the multiplier of the embodiment of the present invention, a new parallel constant multiplication SIMD instruction can be set in the instruction set of the processor, and the parallel constant multiplication SIMD instruction can include multiple multiplicands and multipliers.

[0037] In an embodiment of the present invention, when performing a constant multiplication operation, the multiplier Con as a constant has the same number of bits as the multiplicand, and the number of bits that are 1 in the multiplier does not exceed the ratio between the bit width of the multiplier and the number of partial product generation units. Taking the 32-bit SIMD multiplier including 4 32×8-bit multipliers mentioned above as an example, when performing a 32-bit variable × 32-bit constant operation, the number of bits that are 1 in the 32-bit constant does not exceed 32 / 4, that is, does not exceed 8 bits.

[0038] As mentioned above, the selector corresponding to each partial product generation unit can determine whether to output the result generated by the partial product generation unit or the constant multiplication unit to the subsequent partial product compression unit according to the control signal. Optionally, the partial product compression unit can also selectively transmit the compressed result according to the control signal. Optionally, the output unit can also select whether to output a second product or multiple first products according to the control signal.

[0039] Continuing to refer to Figure 3 , the input unit can, according to the control signal, allocate the multiplicand and the multiplier to be multiplied to each partial product generation unit or constant multiplication unit. The input unit can also provide the control signal to each selector and output unit. The output of each partial product generation unit and its corresponding constant multiplication unit are connected to the selector. The selector selects, according to the control signal, the partial product generated by its corresponding partial product generation unit or constant multiplication unit and provides it to the partial product compression unit. Still taking the 32-bit SIMD multiplier including 4 32×8-bit multipliers mentioned above as an example, where each partial product generation unit outputs 8 partial products. When a constant multiplication unit corresponding to the partial product generation unit is added to perform a 32-bit variable × 32-bit constant multiplication operation in this multiplier, since the number of bits that are 1 in the 32-bit constant does not exceed 8, the partial products generated by the added constant multiplication unit do not exceed 8 either. Thus, the partial product compression unit in the existing multiplier can be basically reused directly.

[0040] In this embodiment, the partial product compression unit can perform carry-save adder accumulation compression on all partial products from each selector to obtain a sum signal and a carry signal, and output them to the final product synthesis unit. The partial product compression unit can also perform carry-save adder accumulation compression on the partial products provided by each selector respectively to obtain a sum signal and a carry signal, and output them to the adder corresponding to the selector for merging to generate a first product, and then provide it to the output unit. The final product synthesis unit merges the sum signal and the carry signal from the partial product compression unit to generate a second product, and provides it to the output unit. The output unit can select to output multiple first products generated by each adder or the second product generated by the final product synthesis unit according to the control signal from the input unit. For example, when the control signal indicates that a normal multiplication operation is being performed, the output unit outputs the second product; when the control signal indicates that a multi-way parallel constant multiplication operation is being performed, the output unit outputs multiple first products.

[0041] Compared with the existing general 32×32 multiplier, Figure 3 the 32×32 multiplier according to the embodiment of the present invention shown only needs to add 4 constant multiplication units and 4 32-bit adders, and at the same time reuse the existing partial product compression unit circuit, and can implement 1 time of 32×32-bit multiplication operation or 4-way parallel 32×Con multiplication operation (such as FNV operation) within one cycle, thereby improving the efficiency of the multiplier in processing data.

[0042] Still below in conjunction with Figure 3 the operation process of the partial products in the multiplier according to the embodiment of the present invention will be described in more detail. Taking the 32*32-bit multiplication operation A[31:0]*B[31:0] as an example, during the operation, the multiplier B[31:0] is split into 4 parts of 8 bits: {B[31:24], B[23:16], B[15:8], B[7:0]}, and partial products are generated through four modules a, b, c, and d of the multiplier. The 8 partial products output after encoding by each module are as follows:

[0043] mul0_pp_{i} = (src1[31:0] * src2[0 + i]) << i; where i is a natural number between [0, 7]; mul1_pp_{i} = (src1[31:0] * src2[8 + i]) << i;

[0044] mul2_pp_{i} = (src1[31:0] * src2[16 + i]) << i;

[0045] mul3_pp_{i} = (src1[31:0] * src2[24 + i]) << i;

[0046] Since each of the four multiplier modules a, b, c, and d outputs 8 partial products, the partial products output by the corresponding constant multiplier units a, b, c, and d should also be less than or equal to 8, so that the subsequent Wallace compression tree structure can be fully reused to complete the compression of the partial products. Therefore, in Figure 3 In the constant multiplication operation supported by the 32-bit SIMD multiplier shown in the figure, which includes 4 partial product generation units, the number of 1s in the operand as a constant should be less than or equal to 32 / 4 = 8. When the number of 1s in the constant is less than 8, the output partial products can be supplemented to 8 using 0s.

[0047] In this example, the encoding process of each constant multiplier unit is as follows: Assume the constant participating in the multiplication operation is Con. If the bits that are 1 in Con are Con[j0], Con[j1], Con[j2], Con[j3], Con[j4], Con[j5], Con[j6], Con[j7] respectively, where j0, j1, j2, j3, j4, j5, j6, j7 represent the bit numbers of the bits that are 1 in the constant Con, then the 8 partial products output after encoding by this constant multiplier unit are as follows:

[0048] FNV1_pp0 = src1[31:0] << j0

[0049] FNV1_pp1 = src1[31:0] << j1;

[0050] FNV1_pp2 = src1[31:0] << j2;

[0051] FNV1_pp3 = src1[31:0] << j3

[0052] FNV1_pp4 = src1[31:0] << j4;

[0053] FNV1_pp5 = src1[31:0] << j5;

[0054] FNV1_pp6 = src1[31:0] << j6;

[0055] FNV1_pp7 = src1[31:0] << j7;

[0056] If the number of bits that are 1 in the constant Con is less than 8, only the partial products corresponding to the bits that are 1 in the constant Con are output, and the partial products are supplemented to 8. The supplemented partial products are 0.

[0057] Taking one of the constants Con = 0x1000193 as an example for illustration, it should be noted that the constant 0x1000193 is only for illustration and does not impose any restrictions. Encode the bits of the constant 0x1000193 that are 1. Among them, the number of bits that are 1 is 6, which is less than or equal to 8 and is applicable to the multiplier structure of the present invention. There are 6 bits that are 1 in the constant Con, which are Con[0], Con[1], Con[4], Con[7], Con[8], Con

[24] respectively. The partial products encoded by the constant multiplication unit are 6, and the other 2 supplementary partial products are 0. The generated partial products are as follows:

[0058] FNV1_pp0[31:0] = {src1[31:0]};

[0059] FNV1_pp1[31:0] = {src1[30:0], 1'b0};

[0060] FNV1_pp2[31:0] = {src1[27:0], 4'b0};

[0061] FNV1_pp3[31:0] = {src1[24:0], 7'b0};

[0062] FNV1_pp4[31:0] = {src1[23:0], 8'b0};

[0063] FNV1_pp5[31:0] = {src1[7:0], 24'b0};

[0064] FNV1_pp6[31:0] = 32'b0;

[0065] FNV1_pp7[31:0] = 32'b0.

[0066] In another embodiment of the present invention, a digital processor that supports the multiplication operation of the above-mentioned multi-way parallel N*N-bit constants is also provided. As Figure 4 shown, the digital processor 400 includes a controller 401 and a multiplier 402. Among them, the multiplier 402 is the SIMD multiplier introduced above in combination with Figure 3 . The multiplier 402 performs corresponding multiplication operations according to the control signals, multiplicands, and multipliers received from the controller 401. To better utilize the multiplier of the embodiment of the present invention, new parallel constant multiplication SIMD instructions can be set in the instruction set of the processor. Multiple multiplicands and multipliers can be included in the parallel constant multiplication SIMD instructions.

[0067] It should be understood that the above embodiments can be implemented in any of a variety of ways. For example, these embodiments can be implemented using hardware, software, or a combination of hardware and software. When implemented in software, the software code can be executed on any suitable processor or set of processors, whether those processors are provided in a single computer or distributed among multiple computers.

[0068] References in this specification to "each embodiment", "some embodiments", "an embodiment", or "embodiments", etc., refer to a particular feature, structure, or property described in connection with the embodiment being included in at least one embodiment. Thus, the appearances of the phrases "in each embodiment", "in some embodiments", "in an embodiment", or "in embodiments", etc., throughout the specification are not necessarily referring to the same embodiment. Additionally, the particular features, structures, or properties can be combined in any suitable manner in one or more embodiments. Accordingly, a particular feature, structure, or property shown or described in connection with one embodiment can be combined, in whole or in part, with the features, structures, or properties of one or more other embodiments without limitation, so long as the combination is not illogical or non - working.

[0069] Terms such as "including" and "having" and terms with similar meanings in this specification are intended to cover non - exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices. The use of "a" or "an" does not exclude a plurality of instances. Additionally, the elements in the drawings of this application are merely for illustrative purposes and are not drawn to scale.

[0070] Although the present invention has been described through the above embodiments, the present invention is not limited to the embodiments described herein, and various changes and variations are also included without departing from the scope of the present invention.

Claims

1. A SIMD multiplier, characterized in that, Comprising: An input unit, an output unit, a plurality of partial product generation units, a partial product compression unit, a final product synthesis unit, a constant multiplication unit corresponding to each partial product generation unit, a selector, and an adder, wherein the constant multiplication unit is used for constant multiplication operations where one of the operands is a constant, and wherein: The input unit is configured to distribute the corresponding multiplicand and multiplier to each partial product generation unit or each constant multiplication unit according to the received control signal; Each selector is configured to select and provide the partial products generated by the partial product generation unit or its corresponding constant multiplication unit to the partial product compression unit according to the control signal; The partial product compression unit is configured to compress the partial products received from each selector to obtain a sum signal and a carry signal and provide them to the final product synthesis unit, and is also configured to compress the partial products provided by each selector to obtain a sum signal and a carry signal and provide them to the corresponding adder for combination to generate a first product; The final product synthesis unit is configured to combine the sum signal and the carry signal from the partial product compression unit to generate a second product; The output unit is configured to output the first product generated by each adder or the second product generated by the final product synthesis unit according to the control signal.

2. The multiplier according to claim 1, wherein The multiplicand and multiplier assigned to each constant multiplication unit have the same number of bits, the multiplier is a constant, and the number of bits that are 1 in the multiplier does not exceed the ratio between the bit width of the multiplier and the number of partial product generation units.

3. The multiplier according to claim 1, characterized in that, The input unit is configured as follows: In response to a control signal indicating the execution of a normal multiplication operation, segment the multiplier according to the number of partial product generation units, and distribute the multiplicand and the segmented multiplier to each partial product generation unit; In response to a control signal indicating the execution of a constant multiplication operation, distribute each multiplicand and the corresponding multiplier to each constant multiplication unit.

4. The multiplier according to claim 1, wherein The partial product compression unit is a Wallace tree structure that uses a carry-save adder for 4-2 compression.

5. The multiplier according to any one of claims 1-4, characterized in that, Its bit width is 32, 64, or 128.

6. The multiplier according to claim 5, wherein The number of partial product generation units is 2, 4, 8, or 16.

7. The multiplier according to claim 3, characterized in that, The constant multiplication operation is an FNV operation.

8. A digital processor, characterized in that, Comprising a controller and a multiplier according to any one of claims 1-7, wherein the multiplier performs corresponding multiplication operations according to the control signal, multiplicand, and multiplier received from the controller.

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