System architecture for heterogeneous multicore inter-core communication and method of operation of a system architecture

Abstract

The embodiment of the application provides a system architecture for heterogeneous multi-core inter-core communication and a running method of the system architecture, and belongs to the chip technical field.The system architecture for heterogeneous multi-core inter-core communication is designed based on a remote processor (Remote Proc) framework, and comprises a first processor system, a second processor system and a control device.The first processor system comprises a first control device and a first operating system module;the second processor system comprises a second control device and a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor (AMP) communication software component, and the second processor system is used for controlling the first processor system to run through the Remote Proc and the AMP communication software component.The Linux Remote Proc framework is expanded by configuring the second processor system with the asymmetric multiprocessor (AMP) communication software component, so that efficient work of the heterogeneous multi-core inter-core communication is achieved, and the heterogeneous inter-core collaborative processing is completed.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more specifically to a system architecture and a method for operating the system architecture for heterogeneous multi-core inter-core communication. Background Technology

[0002] With the development of advanced semiconductor and microprocessor technologies, several heterogeneous multi-core (System-on-Chips) chips have emerged. These chips integrate a high-performance microprocessor unit (MPU) and a microcontroller unit (MCU) with strong real-time capabilities, thus constituting a heterogeneous multi-core SoC. On a heterogeneous multi-core SoC, the MPU can run embedded operating system software to support various communication methods and graphics / image display; the MCU runs an embedded real-time operating system or bare-metal program software to achieve real-time system control and signal processing. This allows multiple operating systems and applications to run in parallel on different processor cores, and enables partitioning, isolation, and synchronous collaboration between operating systems. To achieve synchronous collaborative work between heterogeneous multi-cores, software support for inter-core communication is needed to achieve efficient inter-core operation and collaborative processing.

[0003] Remote Processor Messaging (Rpmsg) is a mechanism that provides inter-process communication (IPC) functionality between the kernel driver of the host operating system (e.g., Linux) and remote processors. The Remoteproc framework allows control from different platforms / architectures while abstracting hardware differences, thus eliminating the need for repetitive operations. Furthermore, the framework adds Rpmsg's virtio devices to remote processors that support this type of communication. Only a few low-level remote processor operation methods need to be provided to the Remoteproc driver, and all Rpmsg drivers can then function. However, the existing Remoteproc framework has some limitations in its infrastructure, affecting inter-core communication in heterogeneous multi-core systems. Summary of the Invention

[0004] The purpose of this invention is to provide a method for inter-core communication in heterogeneous multi-core systems, which can achieve efficient communication between heterogeneous multi-core systems.

[0005] To achieve the above objectives, embodiments of the present invention provide a system architecture for heterogeneous multi-core inter-core communication, characterized in that the system architecture for heterogeneous multi-core inter-core communication is designed based on the Remoteproc framework, and the system architecture for heterogeneous multi-core inter-core communication includes: a first processor system, including a first control device and a first operating system module; and a second processor system, including a second control device and a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor (AMP) communication software component, and the second processor system is used to control the first processor system to run the first processor system through the Remoteproc framework and the AMP communication software component.

[0006] Optionally, the first processor system may further include a first upper-layer module, and the second processor system may further include a second upper-layer module.

[0007] Optionally, the second upper-layer module communicates with the first upper-layer module through the remote processor message passing (RPMSG) mechanism.

[0008] Optionally, the second operating system module includes bare metal and / or an embedded real-time operating system (RTOS).

[0009] Optionally, the physical layer of the AMP communication software component is configured as follows: a hardware mechanism Mailbox and its device driver are responsible for data transmission and reception and inter-core interrupt mechanisms; a small block of memory is set up so as not to occupy the main memory of the second processor system; and a synchronization mutual exclusion mechanism is used to protect the access of different processors.

[0010] Optionally, the media access layer of the AMP communication software component is configured to: parse message formats, wherein the message format includes a message header and a message body, the message header information including the message length and verification of the data within the message; and manage message buffering through send and receive buffers.

[0011] Optionally, the transport layer of the AMP communication software component is configured to: set the API interface of the Rpmsg standard protocol and shield the interfaces of the physical layer and the media access layer.

[0012] This invention also provides a method for operating a system architecture for heterogeneous multi-core inter-core communication. In any of the above-described systems architectures for heterogeneous multi-core inter-core communication, the method for operating the system architecture for heterogeneous multi-core inter-core communication includes: a second control device starting a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor (AMP) communication software component; and the second control device controlling the first control device through the Remoteproc and the AMP communication software component.

[0013] Optionally, the operation method of the system architecture for heterogeneous multi-core inter-core communication further includes: the first control device operates under the control of the Remoteproc and the AMP communication software component;

[0014] The first control device controls the operation of the first operating system module.

[0015] Optionally, the first processor system further includes a first upper-layer module, and the second processor system further includes a second upper-layer module. The method of operating the system architecture for communication between heterogeneous multi-core cores further includes: the second upper-layer module and the first upper-layer module communicate through the remote processor message passing (RPMSG) mechanism.

[0016] Through the above technical solution, the embodiments of the present invention extend the Linux Remoteproc framework by configuring an asymmetric multiprocessor (AMP) communication software component on the second processor system, so as to achieve efficient communication between heterogeneous multi-cores and complete collaborative processing between heterogeneous cores.

[0017] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0019] Figure 1 This is a schematic diagram of a heterogeneous multi-core software example structure;

[0020] Figure 2 This is a schematic diagram illustrating the principle of remote processor message passing;

[0021] Figure 3 This is a schematic diagram of the system architecture for inter-core communication in heterogeneous multi-core systems provided in an embodiment of the present invention;

[0022] Figure 4This is a schematic diagram of an example structure of a system architecture for inter-core communication in heterogeneous multi-core systems provided in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the operation method of the system architecture for inter-core communication in heterogeneous multi-core systems provided in the embodiments of the present invention.

[0024] Explanation of reference numerals in the attached figures

[0025] 10 First processor system 20 Second processor system

[0026] 11 First control device 21 Second control device

[0027] 12 First Operating System Module 22 Second Operating System Module

[0028] 13 First upper-level module 23 Second upper-level module Detailed Implementation

[0029] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0030] Before explaining the embodiments of the present invention in detail, a brief overview of the prior art, the defects of the prior art, and the design concept of the embodiments of this application will be provided.

[0031] On a heterogeneous multi-core (System on Chip, SoC) architecture, the microprocessor unit (MPU) can run embedded operating system software (e.g., Linux) to support various communication technologies and graphics / image display. The microcontroller unit (MCU) runs an embedded real-time operating system or bare-metal software to achieve real-time system control and signal processing. This allows multiple operating systems and applications to run in parallel on different processor cores, and enables partitioning, isolation, and synchronous collaboration between operating systems. To achieve synchronous collaborative work between heterogeneous multi-core cores, software support for inter-core communication is needed to achieve efficient operation and collaborative processing. A schematic diagram of a heterogeneous multi-core software example structure is shown below. Figure 1 As shown.

[0032] Remote Processor Messaging (Rpmsg) is a mechanism that provides inter-process communication (IPC) functionality between the kernel driver of the host operating system (e.g., Linux) and remote processors. The Remoteproc framework allows control from different platforms / architectures while abstracting hardware differences, thus eliminating the need for repetitive operations. Furthermore, the framework adds Rpmsg's virtio device to remote processors that support this type of communication. Only a few low-level remote processor operation methods need to be provided to the Remoteproc driver, and all Rpmsg drivers will then function. A schematic diagram of an Rpmsg example is shown below. Figure 2 As shown.

[0033] However, the existing Remoteproc framework has some limitations in its infrastructure. For example, the Linux Remoteproc framework always implicitly assumes Linux as the primary operating system and does not support Linux as a remote operating system configured in Asymmetric Multi-Processing (AMP) systems. Furthermore, the Linux kernel space can only be obtained from Rpmsg, and there are no equivalent APIs or libraries for other operating systems and runtimes.

[0034] Figure 3 This is a schematic diagram of a system architecture for inter-core communication in heterogeneous multi-core systems provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of an example structure. Please refer to it. Figure 3 and Figure 4 The system architecture for heterogeneous multi-core inter-core communication is designed based on the Remoteproc framework, and the system architecture for heterogeneous multi-core inter-core communication includes: a first processor system (e.g., Master) 10, including a first control device (e.g., Core1 MPU) 11 and a first operating system module (e.g., Linux) 12; a second processor system (e.g., Remote) 20, including a second control device (e.g., Core2 MCU) 21 and a second operating system module 22, wherein the second operating system module 22 is further configured with an asymmetric multiprocessor (AMP) communication software component, and the second processor system 20 is used to control the first processor system to run the first processor system through the Remoteproc and the AMP communication software component.

[0035] The first control device 11 may include: a memory, a processor, and a computer program stored in the memory and executable on the processor.

[0036] The second control device 21 may include: a memory, a processor, and a computer program stored in the memory and executable on the processor.

[0037] Preferably, the second operating system module includes bare metal and / or an embedded real-time operating system (RTOS).

[0038] like Figure 4 As shown, the system architecture for heterogeneous multi-core inter-core communication provided in this embodiment of the invention can extend the Linux Remoteproc framework by configuring an asymmetric multiprocessor (AMP) communication software component on the Remote, enabling control of a second processor system without using the first processor system (e.g., Master) as the master system. For example, the second control device can control the first control device, enabling the bare-metal and / or embedded real-time operating system (RTOS) of the Remote to open, load firmware, and shut down the Linux of the Master.

[0039] Furthermore, the Remoteproc framework provides a way to control a second control device (e.g., Core2 MCU) through a first control device (e.g., Core1 MPU). In fact, bidirectional control between the Master and Remote processors can be achieved through embodiments of the present invention.

[0040] The AMP communication software group mainly provides the underlying three-layer communication services. In a preferred embodiment of the present invention, an application service architecture is provided on this basis to perform functional design on the underlying three-layer communication services.

[0041] Preferably, the physical layer of the AMP communication software component can be configured as follows: a hardware mechanism Mailbox and its device driver are responsible for data transmission and reception and inter-core interrupt mechanisms; a small block of memory is set up so as not to occupy the main memory of the second processor system; and a synchronization mutual exclusion mechanism is used to protect the access of different processors.

[0042] Mailbox, as a hardware mechanism for inter-processor synchronization and data exchange in multiprocessor systems, has the advantages of wide application and high speed. The mailbox approach primarily facilitates multiprocessor communication by transmitting control information.

[0043] As an example, the Mailbox hardware and its device driver are responsible for the most basic data transmission and reception and inter-core interrupt mechanism. The Mailbox device can realize data transmission function when it has a small block of memory and does not occupy the main memory of the system. The Mailbox device can allow different processors (cores) to access it under the protection of the synchronization and mutual exclusion mechanism, write or read messages to the Mailbox unit, and then send an interrupt information to the core that uses the message. The corresponding core uses the message to read it under the protection of the synchronization and mutual exclusion mechanism.

[0044] Preferably, the media access layer of the AMP communication software component can be configured to: parse message formats, wherein the message format includes a message header and a message body, the message header information including the message length and the verification of data within the message; and manage message buffering through send and receive buffers.

[0045] As illustrated by the example, the main functions of the media access layer include message format parsing and send / receive buffer management. The message format consists of a message header and a message body. The message header contains the message length and validation information for the data within the message body to ensure error-free message output. The send / receive buffer manages message buffering, ensuring reliable message transmission and enabling message retransmission upon detecting transmission errors. The maximum transmission capacity of the media access layer is calculated by subtracting a certain number of bytes from the message header from the physical layer's capacity.

[0046] Preferably, the transport layer of the AMP communication software component can be configured to: set the API interface of the Rpmsg standard protocol and shield the interfaces of the physical layer and the media access layer.

[0047] As an example, the transport layer primarily provides the API standard interface for the RPMSG standard protocol, shielding the interfaces of the media access layer and the physical layer, making the architecture easier to use.

[0048] Preferably, the first processor system 10 further includes a first upper-layer module 13, and the second processor system 20 further includes a second upper-layer module 23.

[0049] More preferably, the second upper-layer module 23 communicates with the first upper-layer module 13 through the remote processor message passing (RPMSG) mechanism.

[0050] Figure 5 This is a schematic diagram of the operation method of the system architecture for inter-core communication in heterogeneous multi-core systems provided in this embodiment of the invention. Please refer to it. Figure 4 and Figure 5 In the above-described system architecture for heterogeneous multi-core inter-core communication, the method for operating the system architecture for heterogeneous multi-core inter-core communication may include the following steps:

[0051] Step S110: The second control device starts the second operating system module, wherein the second operating system module is also configured with an asymmetric multiprocessor (AMP) communication software component.

[0052] As an example, the Linux Remoteproc framework can be extended by configuring a heterogeneous multi-core AMP communication software component on the remote, enabling control of a second processor system without the first processor system (e.g., the Master) being the primary system. For instance, the Core2 MCU can directly control the startup of the second operating system module 22.

[0053] Step S120: The second control device controls the first control device through the Remoteproc and the AMP communication software component.

[0054] The first control device can remotely control the second control device via the Remoteproc and the AMP communication software component to control the operation of the first operating system module (e.g., Linux). For example, the second control device can control the first control device to enable opening, loading firmware, and shutting down the Master's Linux via the Remote's RTOS or Bare Metal.

[0055] Preferably, the operation method of the system architecture for heterogeneous multi-core inter-core communication further includes: the first control device operating under the control of the Remoteproc and the AMP communication software component; and the first control device controlling the operation of the first operating system module.

[0056] As described in steps S110-S120, the Core2 MCU can first start up to launch the RTOS or Bare Metal, and then run the Core1 MPU through Remoteproc and the AMP communication software component of the second processor system. The Core1 MPU runs Linux, thus realizing the running of Linux through the RTOS or Bare Metal, such as opening, loading firmware, and closing Linux.

[0057] Preferably, the first processor system further includes a first upper-layer module, and the second processor system further includes a second upper-layer module. The method of operating the system architecture for communication between heterogeneous multi-core cores further includes: the second upper-layer module and the first upper-layer module communicate through the remote processor message passing (RPMSG) mechanism.

[0058] It should be noted that the functional design of the underlying three-layer communication services for the AMP communication software group is described above and will not be repeated here.

[0059] Accordingly, this embodiment of the invention extends the Linux Remoteproc framework by configuring a heterogeneous multi-core AMP communication software component on the Remote device, thereby achieving efficient inter-core communication among heterogeneous multi-core processors and completing collaborative processing between them. Simultaneously, this heterogeneous multi-core AMP communication software component runs on the host device, enabling lifecycle management of the remote processor and its related software environment. It can control the remote processor's clock, enable remote processor startup, and shut down the remote processor when necessary after completing its tasks, thus reducing system power consumption. The host processor loads the remote processor's application into a suitable memory location and completes functions such as registering virtio and Rpmsg devices, establishing a channel for IPC communication among the multi-core processors.

[0060] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0061] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0062] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0063] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0064] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0065] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0066] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0067] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0068] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A system architecture for heterogeneous multi-core inter-core communication, characterized by, The system architecture for heterogeneous multi-core inter-core communication is based on a remote processor (Remoteproc) framework design, and comprises: a first processor system comprising a first control device and a first operating system module; a second processor system comprising a second control device and a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor (AMP) communication software component, and the second processor system is configured to control the first processor system to run the first processor system through the Remoteproc and the AMP communication software component. The second operating system module comprises a Bare Metal and / or an embedded real-time operating system (RTOS), and the Remoteproc provides a way to control the second control device through the first control device, a physical layer of the AMP communication software component is configured to: use a hardware mechanism Mailbox and its device driver to be responsible for data transceiving and inter-core interrupt mechanism; set a small block of memory that does not occupy the main memory of the second processor system; and allow different processors to access through protection of a synchronization mutual exclusion mechanism, a media access layer of the AMP communication software component is configured to: parse a message format, wherein the message format comprises a message header and a message body, and information of the message header comprises a length of the message and a check of data in the message; and buffer manage the message through a transceiving buffer, a transport layer of the AMP communication software component is configured to: set an API interface of an Rpmsg standard protocol to shield interfaces of the physical layer and the media access layer.

2. The system architecture for heterogeneous multicore inter-core communication according to claim 1, wherein, The first processor system further comprises a first upper layer module, and the second processor system further comprises a second upper layer module.

3. The system architecture for heterogeneous multicore interkernel communication of claim 2, wherein, The second upper layer module communicates with the first upper layer module through a remote processor message passing (Rpmsg) mechanism.

4. A method of operation of a system architecture for heterogeneous multi-core inter-core communication, characterized in that, In the system architecture for heterogeneous multi-core inter-core communication according to any one of claims 1-3, a method for running the system architecture for heterogeneous multi-core inter-core communication comprises: the second control device starts the second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor (AMP) communication software component; and the second control device controls the first control device through the Remoteproc and the AMP communication software component.

5. The method of claim 4, wherein, The method for running the system architecture for heterogeneous multi-core inter-core communication further comprises: the first control device runs according to control of the Remoteproc and the AMP communication software component; the first control device controls the first operating system module to run.

6. The method of claim 4, wherein the method further comprises: The first processor system further comprises a first upper layer module, and the second processor system further comprises a second upper layer module, and the method for running the system architecture for heterogeneous multi-core inter-core communication further comprises: the second upper layer module communicates with the first upper layer module through a remote processor message passing (Rpmsg) mechanism.

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