Information extraction method, system and electronic device for chip pads

Abstract

Embodiments of the present application relate to the field of storage device applications, and disclose a method, a system, and an electronic device for extracting information of chip pads. The method includes obtaining configuration information of a chip layout, where the configuration information includes length information and width information of the chip layout, and pad area information of each pad area of the chip. Each pad area includes a plurality of pads. Determine the coordinate information of each pad of the chip layout, determine the pad area corresponding to each pad, and generate a pad layout of the chip according to the length information, width information, and coordinate information of each pad of the chip layout. Process the pad layout to generate a pad distribution map. Embodiments of the present application can improve the speed of extracting information of chip pads, output the pad layout of the chip, and thus improve the efficiency of packaging production.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and particularly to a method, a system, and an electronic device for extracting information of chip pads. Background Art

[0002] In the manufacturing process of flash memory devices, such as Solid State Drives (SSDs), it is usually necessary to package chips. In chip packaging, the connection between the chip and the lead frame (or substrate) provides a circuit connection for power and signal distribution. Ensuring the electrical connection and unobstructed input / output between the chip and the outside of the package is an important step in the packaging process. Currently, the mainstream methods are Flip Chip Bonding and Wire Bonding, which can achieve the connection between the chip and the lead frame (or substrate). Although the application of flip chip bonding has grown rapidly, currently, the majority of the connection methods are still wire bonding.

[0003] On the chip die, the pad (Pad Open) of the chip pin refers to opening a hole in the top metal of the chip, and the bonding wire can be pulled through this pad to the lead frame.

[0004] However, the existing method for extracting padopen data has low accuracy due to manual recording, and the method of extracting padopen embedded in EDA tools cannot be statistically analyzed.

[0005] Based on this, the existing technology urgently needs to be improved. Summary of the Invention

[0006] Embodiments of the present application provide a method, a system, and an electronic device for extracting information of chip pads, so as to improve the speed of extracting information of chip pads, and further improve the efficiency of packaging production.

[0007] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0008] In a first aspect, an embodiment of the present application provides a method for extracting information of chip pads, the method including:

[0009] Obtaining configuration information of a chip layout, where the configuration information includes length information and width information of the chip layout, and pad area information of each pad area of the chip, and each pad area includes a plurality of pads;

[0010] Extracting coordinate information of each pad of the chip layout;

[0011] According to the pad area information, dividing each pad into areas, and determining the pad area corresponding to each pad;

[0012] Generate the pad layout of the chip according to the length information, width information of the chip layout and the coordinate information of each pad.

[0013] Process the pad layout of the chip to generate the pad distribution map of the chip.

[0014] In some embodiments, extracting the coordinate information of each pad of the chip layout includes:

[0015] Extract the bottom layer coordinates of the four vertices of each pad from the chip layout;

[0016] Based on the first function, determine the top layer coordinates of the four vertices of each pad, where the first function is used to map the bottom layer coordinates of the vertex to the top layer coordinates of the layout top layer.

[0017] In some embodiments, the method further includes:

[0018] After extracting the top layer coordinates of the four vertices of each pad, convert them into the center point coordinates of each pad according to the top layer coordinates of the four vertices of each pad.

[0019] In some embodiments, the method further includes:

[0020] Calculate the minimum pad pitch of the chip layout according to the coordinate information of each pad in each pad area.

[0021] In some embodiments, calculating the minimum pad pitch of the chip layout according to the coordinate information of each pad in each pad area includes:

[0022] Determine the minimum pad pitch of each pad area according to the coordinate information of each pad in each pad area;

[0023] Determine the minimum pad pitch of the chip layout according to the minimum pad pitch of each pad area, where the minimum pad pitch of the chip layout is the minimum value among the minimum pad pitches of all pad areas.

[0024] In some embodiments, the arrangement of the chips includes single-layer arrangement and / or double-layer arrangement. Calculating the minimum pad pitch of each pad area includes:

[0025] Based on the second function, calculate the single-layer minimum pad pitch and / or double-layer minimum pad pitch of the chip, where the second function is used to calculate the single-layer minimum pad pitch and / or double-layer minimum pad pitch according to the center point coordinates of each pad.

[0026] In some embodiments, the pad area includes an upper area, a lower area, a left area, and a right area. The method further includes:

[0027] Perform a counterclockwise sorting for each pad in the upper region, lower region, left region, and right region respectively.

[0028] In some embodiments, the method further includes:

[0029] Traverse each pad of the chip layout to extract the label name of each pad of the chip layout, wherein the label name of each pad is bound to the coordinate information;

[0030] If a certain pad does not have a label name or the label name is not unique, determine that the pad is in error and generate an error message.

[0031] In a second aspect, an information extraction system for chip pads provided by an embodiment of the present application includes:

[0032] An input module, configured to obtain the configuration information of the chip layout, wherein the configuration information includes the length information and width information of the chip layout and the pad area information of each pad area of the chip, and each pad area includes a plurality of pads;

[0033] An extraction module, configured to extract the coordinate information of each pad of the chip layout;

[0034] An algorithm module, configured to perform area division on each pad according to the pad area information to determine the pad area corresponding to each pad;

[0035] An output module, configured to generate the pad layout of the chip according to the length information, width information of the chip layout and the coordinate information of each pad; process the pad layout of the chip to generate the pad distribution map of the chip.

[0036] In a third aspect, an electronic device provided by an embodiment of the present application includes:

[0037] At least one processor; and

[0038] A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can be used to execute the method as in the first aspect.

[0039] In a fourth aspect, an embodiment of the present application further provides a non-volatile computer-readable storage medium, and the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a flash device to execute the method as in the first aspect.

[0040] The beneficial effects of the embodiments of the present application are as follows: Different from the prior art, the present application provides a method, a system and an electronic device for extracting information of chip pads. The method includes: obtaining configuration information of a chip layout, where the configuration information includes length information and width information of the chip layout and pad area information of each pad area of the chip, and each pad area includes a plurality of pads; extracting coordinate information of each pad of the chip layout; dividing each pad into regions according to the pad area information to determine the pad area corresponding to each pad; generating a pad layout of the chip according to the length information, width information of the chip layout and the coordinate information of each pad; and processing the pad layout of the chip to generate a pad distribution map of the chip. By obtaining the configuration information of the chip layout, determining the coordinate information of each pad of the chip layout, determining the pad area corresponding to each pad, generating the pad layout of the chip, and processing the pad layout to generate a pad distribution map, the embodiments of the present application can improve the speed of extracting information of chip pads, and thus improve the efficiency of package production. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] One or more embodiments are illustrated by way of example in the accompanying drawings, which do not constitute a limitation to the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the figures do not constitute a proportional limitation.

[0042] Figure 1 is a schematic diagram of wire bonding provided by an embodiment of the present application;

[0043] Figure 2 is a top view and a side view of a chip package provided by an embodiment of the present application;

[0044] Figure 3 is a schematic diagram of pad pitch provided by an embodiment of the present application;

[0045] Figure 4 is a flowchart of a method for extracting information of chip pads provided by an embodiment of the present application;

[0046] Figure 5 is a schematic diagram of a graphical user interface of configuration information of a chip layout provided by an embodiment of the present application;

[0047] Figure 6 is Figure 4 a refined flowchart of step S402 in

[0048] Figure 7 is a flowchart of a method for calculating the minimum pad pitch of a chip layout provided by an embodiment of the present application;

[0049] Figure 8It is a schematic diagram of the chip arrangement provided by the embodiments of the present application;

[0050] Figure 9 It is a schematic diagram of the wire bonding rules for single-layer arrangement provided by the embodiments of the present application;

[0051] Figure 10 It is a schematic diagram of a pad pitch provided by the embodiments of the present application;

[0052] Figure 11 It is a schematic diagram of an information table of pads provided by the embodiments of the present application;

[0053] Figure 12 It is a pad distribution diagram of a chip provided by the embodiments of the present application;

[0054] Figure 13 It is a schematic diagram of the structure of an information extraction system for chip pads provided by the embodiments of the present application;

[0055] Figure 14 It is a schematic diagram of the structure of an electronic device provided by the embodiments of the present application. Detailed implementation manners

[0056] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0057] It should be noted that if there is no conflict, the various features in the embodiments of the present application can be combined with each other, and all are within the scope of protection of the present application. In addition, although functional module division is performed in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the device or the flowchart. Furthermore, the terms "first", "second", "third", etc. used in the present application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0058] Before the present application is described in detail, the nouns and terms involved in the embodiments of the present application are described. The nouns and terms involved in the embodiments of the present application are applicable to the following explanations:

[0059] (1) Wire Bonding refers to the process of connecting the pads on the chip and the lead frame (or substrate) with very thin wires.

[0060] (2) Pad Open refers to an opening in the top metal layer of the chip, through which the bonding wire can be pulled to the lead frame.

[0061] (3) Pad Pitch refers to the distance between the same edges of two adjacent identical Pad Open.

[0062] Please refer to Figure 1 , Figure 1 which is a schematic diagram of wire bonding provided by an embodiment of the present application;

[0063] As Figure 1 shown, wire bond is the process of connecting the pads on the chip to the lead frame (or substrate) with very thin wires.

[0064] Please refer to Figure 2 , Figure 2 which are a top view and a side view of a chip package provided by an embodiment of the present application;

[0065] As Figure 2 shown, on the chip die, Pad Open refers to the pad of the chip pin, which means an opening in the top metal layer of the chip, through which the bonding wire can be pulled to the lead frame. Among them, PAD is the interface connecting the inside of the chip and the chip package.

[0066] Please refer to Figure 3 , Figure 3 which is a schematic diagram of pad pitch provided by an embodiment of the present application;

[0067] As Figure 3 shown, Pad Pitch refers to the distance between the same edges of two adjacent identical Pad Open, or when there are adjacent different Pad Open sizes on a chip die, the center distance between two Pad Open is taken as Pad Pitch. Generally, the minimum Pad Pitch among all the pad pitches on a die should be selected.

[0068] For currently mainstream chips adopting the wire bond packaging form, the data of Pad Open generally reach dozens. In order to determine whether the arrangement of Pad Open meets the packaging requirements, it is very necessary to quickly and automatically extract information such as Pad Open coordinates and form a table during the design stage. On the one hand, it can assist in judging whether Pad Open is reasonable in the layout design. On the other hand, taking this table information as part of the chip packaging materials and providing it to the packaging factory to determine the packaging feasibility.

[0069] Currently, the existing methods for extracting PadOpen data are as follows:

[0070] (1) Manual recording, where PadOpen data is recorded one by one into a table, and the pad pitch is extracted and checked. Its disadvantages are as follows: the workload is large, repeated extraction is required every time the design is modified, human errors are likely to occur, and the minimum pad pitch of the chip cannot be accurately obtained.

[0071] (2) The EDA tool has an embedded function for extracting PadOpen data, but the function is not perfect. Its disadvantages are that the function is not perfect and the Pad Open distribution map cannot be output.

[0072] Based on this, the embodiments of the present application provide a method for extracting information of chip pads to improve the speed of extracting information of chip pads, output the pad layout of the chip, and thus improve the efficiency of packaging production.

[0073] Please refer to Figure 4 , Figure 4 which is a schematic flowchart of a method for extracting information of chip pads provided by the embodiments of the present application;

[0074] Among them, the method for extracting information of chip pads is applied to an electronic device. Specifically, the execution subject of the method for extracting information of chip pads is one or more processors of the electronic device.

[0075] As Figure 4 shown, the method for extracting information of chip pads includes:

[0076] Step S401: Obtain the configuration information of the chip layout, where the configuration information includes the length information, width information of the chip layout, and the pad area information of each pad area of the chip, and each pad area includes multiple pads;

[0077] Specifically, the configuration information of the chip layout is generated from the data input by the user through a graphical user interface. Specifically, a graphical user interface is established in advance, and the graphical user interface is used to receive the configuration information of the chip layout input by the user, where the configuration information includes the length information, width information of the chip layout, and the pad area information of each pad area of the chip. In the embodiments of the present application, the graphical user interface is generated by the built-in function of the image interface of the EDA tool.

[0078] Please refer to Figure 5 , Figure 5 which is a schematic diagram of a graphical user interface for the configuration information of a chip layout provided by the embodiments of the present application;

[0079] As Figure 5As shown, in this graphical user interface, the configuration information input by the user will be printed in the output table and the output distribution map. Among them, the configuration information includes the project name, the information extraction date, the length and width of the chip layout, the library name for generating the pad layout (the library name for generating the pad open layout), the layout cell name, and specifying the process of the chip and the description information of the process. Specifically, the description information of the process includes information such as the foundry / process node / metal layers used in the chip / the thickness of the top metal, etc. For example: the foundry is Factory A, the process node is 40nm, the metal layers used in the chip are one layer of poly and 7 layers of metal, and one of them is thick metal.

[0080] Among them, the configuration information also includes: single-layer arrangement information and / or double-layer arrangement information. If the user selects to include a single-layer arrangement (InLinepadopen arrangement), it is determined that the configuration information includes single-layer arrangement information; if the user selects to include a double-layer arrangement (stagger pad open arrangement), it is determined that the configuration information includes double-layer arrangement information. It can be understood that if the configuration information includes double-layer arrangement information, generally the configuration information also includes single-layer arrangement information; if the user selects to include single-layer arrangement information, the configuration information only includes single-layer arrangement information.

[0081] Among them, the configuration information also includes: the pad area information of each pad area. Among them, the pad area includes the upper area, the lower area, the left area, the right area, and the internal area. The user determines the coordinate values of each pad area by using the mouse to enclose the pad areas (pad open areas) on the four sides and inside of the chip in the graphical user interface. For example: the coordinate range of each pad area.

[0082] In the embodiment of the present application, by using the graphical user interface to input the configuration information of the chip layout, the configuration information of the chip layout can be quickly output to the information table of the pads.

[0083] In the embodiment of the present application, the configuration information is saved in the form of a configuration information file. For example: the configuration information input by the user is saved to a configuration information file, so that the configuration information has the functions of saving and reloading. When the information of the chip pads (pad open information) needs to be extracted again later, the configuration information file can be read in again to save the operation of re-entering relevant information and save time.

[0084] Step S402: Extract the coordinate information of each pad of the chip layout;

[0085] Specifically, please refer to Figure 6 , Figure 6 is Figure 4 the detailed flowchart of step S402 in

[0086] As shown Figure 6 in FIG. Figure 6 , step S402: Extract the coordinate information of each pad on the chip layout, including:

[0087] Step S4021: Extract the bottom-layer coordinates of the four vertices of each pad from the chip layout;

[0088] Specifically, extract the coordinate information (pad open coordinate information) of each pad of the entire chip.

[0089] Step S4022: Based on the first function, determine the top-layer coordinates of the four vertices of each pad, where the first function is used to map the bottom-layer coordinates of the vertices to the top-layer coordinates of the layout top layer.

[0090] Specifically, the first function is predefined, where the first function is used to map the bottom-layer coordinates of the vertices to the top-layer coordinates of the layout top layer, that is, to determine the top-layer coordinates of the four vertices of each pad. For example: The first function includes the boxCoord function, and the function of the boxCoord function is to extract the coordinates of the four vertices of a rectangle from the layout and map them to the coordinates of the layout top layer. It can be understood that the pad (pad open) is rectangular, and mapping to the top-layer coordinates is to ensure that the coordinates of all pad opens are unique. Then use the boxCoord function to extract the pad opens of the chip one by one and save them with variables, which is beneficial for subsequent processing.

[0091] In the embodiment of the present application, the method further includes:

[0092] Traverse each pad of the chip layout to extract the label name of each pad on the chip layout, where the label name of each pad is bound to the coordinate information;

[0093] If there is no label name or the label name is not unique for a certain pad, it is determined that the pad is in error and an error message is generated.

[0094] Specifically, the label name of each pad is bound to the coordinate information of the pad. It can be understood that generally, labels need to be added to each pad (pad open) on the chip layout to mark the name of the chip pin corresponding to the pad open. By traversing all pad opens, it is judged whether there is a unique label name on them. If it is found that there is no label name on the pad open, or the label name is not the only one, an error message is generated, which is beneficial for the layout engineer to add or correct the label name.

[0095] Step S403: According to the pad area information, divide the area of each pad to determine the pad area corresponding to each pad;

[0096] Specifically, according to the pad area information, each pad (pad open) is divided into areas to determine the pad area corresponding to each pad. Moreover, each pad in each pad area is sorted, and the minimum pad pitch of the chip layout is calculated.

[0097] It can be understood that since each pad in each pad area is sorted, the position of each pad in the subsequent output pad information table is easier to locate, which is beneficial for the layout engineer to add labels or correct label names.

[0098] Among them, dividing each pad into areas to determine the pad area corresponding to each pad includes:

[0099] The chip layout is divided into an upper area, a lower area, a left area, a right area, and a middle area. The pad open area coordinate values input from the graphical user interface, that is, the coordinate range of each pad area, are compared with the coordinate values (padopen coordinate values) of all pads. If the pad open coordinate value falls within the pad open area coordinate value, then the pad open is classified into the corresponding area. For example, if the coordinate value of pad open1 is within the left area (left pad open area) of the chip layout, then pad open1 is classified into the left area (left pad open area). And so on, thus determining the pad area corresponding to each pad.

[0100] In the embodiment of the present application, after extracting the top-layer coordinates of the four vertices of each pad, according to the top-layer coordinates of the four vertices of each pad, the center point coordinates of each pad are obtained.

[0101] According to the coordinate information of each pad in each pad area, the minimum pad pitch of the chip layout is calculated.

[0102] Specifically, please refer to Figure 7 , Figure 7 which is a schematic flowchart of a method for calculating the minimum pad pitch of a chip layout provided by an embodiment of the present application;

[0103] As Figure 7 shown, according to the coordinate information of each pad in each pad area, calculating the minimum pad pitch of the chip layout includes:

[0104] Step S701: Determine the minimum pad pitch of each pad area according to the coordinate information of each pad in each pad area;

[0105] Please refer to Figure 8 , Figure 8It is a schematic diagram of the chip arrangement provided by an embodiment of the present application;

[0106] As Figure 8 shown, the chip arrangement includes single-layer arrangement and double-layer arrangement. It can be understood that the arrangement of chip PadOpen is generally divided into Iline (single-layer arrangement or linear arrangement) and Stagger (double-layer arrangement or staggered arrangement). Chip pad Open is generally placed around the chip. However, there may also be some enhanced power pad Open or test pad Open inside the chip, and these internal Pad Open will not pull wires outside the chip. As Figure 8 shown, the pad Open arrangement of the left chip is In line, and the right one is Stagger.

[0107] Please refer to Figure 9 , Figure 9 It is a schematic diagram of the wire bonding rule of the single-layer arrangement provided by an embodiment of the present application;

[0108] It can be understood that in the chip layout design, the placement of pad open must consider the wirebond rule to prevent the chip from not being able to be packaged and produced because it cannot meet the rules of the packaging factory after the chip design is completed. Therefore, during the layout design, it is necessary to extract all the pad open placement information from the layout, count the length and width of each padopen, the center point coordinates of the pad open, the In-line / Stagger pad pitch, etc. The layout engineer makes a preliminary comparison based on this information and the wire bond rule of the packaging factory to see if it meets the requirements, so as to judge whether to promote the design. Next, the statistical information also needs to be given to the packaging engineer, and the packaging engineer will perform a wire bond simulation to finally determine whether the arrangement of the pad open meets the packaging requirements.

[0109] As Figure 9 shown, LP represents the padpitch of the InLine arrangement, B and H respectively represent the width and length of the PadOpen, P1 represents the padpitch of the corner area of the four corners of the chip, and L represents the spacing (space) between two adjacent padopens.

[0110] Step S702: Determine the minimum pad pitch of the chip layout according to the minimum pad pitch of each pad area, where the minimum pad pitch of the chip layout is the minimum value among the minimum pad pitches of all pad areas.

[0111] In the embodiments of the present application, the minimum pad pitch of different arrangement modes is different. The pad region includes an upper region, a lower region, a left region, and a right region. To better calculate the minimum pad pitch, the method further includes: performing a counterclockwise sorting on each pad in the upper region, the lower region, the left region, and the right region respectively. By performing a counterclockwise sorting on each pad in the upper region, the lower region, the left region, and the right region and numbering each pad in sequence, it is beneficial to locate the pad where an error message appears.

[0112] Specifically, the arrangement mode of the chip includes a single-layer arrangement and / or a double-layer arrangement. Calculating the minimum pad pitch of each pad region includes:

[0113] Based on the second function, calculating the single-layer minimum pad pitch and / or the double-layer minimum pad pitch of the chip, where the second function is used to calculate the single-layer minimum pad pitch and / or the double-layer minimum pad pitch according to the center point coordinates of each pad.

[0114] In the embodiments of the present application, the pad pitch is the difference between the center point coordinates of two adjacent pads. Specifically, the pad pitch is the difference between the abscissa or the ordinate of the center point coordinates of two adjacent pads. According to the origin position of the coordinate system established based on the chip layout and the orientation of the pads, it is determined whether to take the difference of the abscissa or the difference of the ordinate.

[0115] Specifically, the second function is predefined, where the second function is used to calculate the single-layer minimum pad pitch and / or the double-layer minimum pad pitch according to the center point coordinates of each pad.

[0116] Specifically, the second function includes the findPitch function, and a pad pitch operation is performed on the upper region, the lower region, the left region, and the right region respectively, that is, the pad pitches of the upper region, the lower region, the left region, and the right region are calculated, and different algorithms are used for different arrangement modes of single-layer arrangement (Inline) and double-layer arrangement (stagger).

[0117] Specifically, based on the second function, a plurality of single-layer pad pitches of each pad region are calculated to determine the single-layer minimum pad pitch of each pad region, where the single-layer minimum pad pitch is the minimum value of the plurality of single-layer pad pitches; and, based on the second function, a plurality of double-layer pad pitches of each pad region are calculated to determine the double-layer minimum pad pitch of each pad region, where the double-layer minimum pad pitch is the minimum value of the plurality of double-layer pad pitches;

[0118] According to the single-layer minimum pad pitch and the double-layer minimum pad pitch of each pad region, the minimum pad pitch of each pad region is determined, where the minimum pad pitch of each pad region is the minimum value of the single-layer minimum pad pitch and the double-layer minimum pad pitch of the pad region.

[0119] Determine the minimum pad pitch of the chip layout according to the minimum pad pitch of each pad area, where the minimum pad pitch of the chip layout is the minimum value among the minimum pad pitches of all pad areas.

[0120] For example: Determine the minimum In line pad pitch and the minimum stagger pad pitch value of each pad area. Finally, compare the minimum In line pad pitch and the minimum stagger pad pitch values of each pad area to find the minimum In line pad pitch and stagger pad pitch values of the chip, so as to determine the minimum pad pitch of the chip layout, where the minimum pad pitch of the chip layout is the smaller value among the minimum In line pad pitch and the minimum stagger pad pitch values.

[0121] Please refer to Figure 10 , Figure 10 which is a schematic diagram of a pad pitch provided by an embodiment of the present application;

[0122] As Figure 10 shown, first take the X value of the center point coordinate of the pad Open, subtract the X values of two adjacent Pad Opens to obtain the pad pitch. For single-layer arrangement (inline) and double-layer arrangement (stagger) respectively, determine all the pad pitches. For example, single-layer pad pitches InlinePadPitch1, Inline Pad Pitch2, Inline Pad Pitch3, and double-layer pad pitches Stagger Pad Pitch1, Stagger Pad Pitch2, Stagger Pad Pitch3, Stagger PadPitch4, Stagger Pad Pitch5, Stagger Pad Pitch6, and find the minimum double-layer pad pitch min stagger pad pitch and the minimum single-layer pad pitch min inline pad pitch from all the pad pitches to determine the minimum pad pitch.

[0123] Step S404: Generate the pad layout of the chip according to the length information, width information of the chip layout and the coordinate information of each pad.

[0124] In the embodiment of the present application, before generating the pad layout of the chip, the method further includes:

[0125] Format and output the information table of the pads.

[0126] Please refer to Figure 11 , Figure 11 which is a schematic diagram of the information table of a pad provided by an embodiment of the present application;

[0127] As Figure 11 shown, the information table of the pad includes the item name and process information description, the length and width of the chip layout, the minimum single-layer pad spacing (InLine) and the minimum double-layer pad spacing (stagger), as well as the center point coordinate values of each pad (PadOpen center point coordinate values), the pad length (PadOpen length), and the pad width (Pad Open width).

[0128] Specifically, according to the length information, width information of the chip layout, and the coordinate information of each pad, a pad layout of the chip is generated, including:

[0129] According to the length, width of the chip layout, and the coordinate information of each pad, a layout command supported by the EDA tool is automatically generated, and then the EDA tool is used to automatically generate the pad layout (Pad open layout) of the chip, where the coordinate information of each pad includes the coordinate information of the four vertices of each pad (the coordinate values of the four vertices of pad open).

[0130] In an embodiment of the present application, the method further includes: determining the length and width of each pad according to the top-layer coordinates of the four vertices of each pad.

[0131] Step S405: Process the pad layout of the chip to generate a pad distribution diagram of the chip.

[0132] Specifically, a screenshot command is called to take a screenshot of the pad layout of the chip to generate a pad distribution diagram of the chip. Please refer to Figure 12 , Figure 12 which is a pad distribution diagram of a chip provided by an embodiment of the present application.

[0133] In an embodiment of the present application, the output information table of the pad and the pad distribution diagram are helpful for judging in advance whether the packaging rules of the packaging factory are met during chip design, avoiding repeated design steps, and can also be used as packaging materials for the packaging factory to finally determine whether the chip pads can achieve final production, thereby improving the efficiency of packaging production.

[0134] It can be understood that chip design can be divided into logic circuit design and physical design. Among them, physical design refers to the process of converting logic circuit design into a layout that can be produced by a foundry. Therefore, the pad layout of a chip can be directly used to produce wafers. And the packaging factory only needs the relevant information of padopen to perform chip packaging and does not need to use the pad layout of the chip. Therefore, by taking a screenshot of the pad layout of the chip, it can be provided for packaging engineers to use.

[0135] In the embodiment of the present application, by providing a method for extracting information of chip pads, the method obtains the configuration information of the chip layout. The configuration information includes the length information, width information of the chip layout, and the pad area information of each pad area of the chip. Each pad area includes multiple pads, determines the coordinate information of each pad of the chip layout, determines the pad area corresponding to each pad, and generates the pad layout of the chip according to the length information, width information of the chip layout, and the coordinate information of each pad, and processes the pad layout to generate a pad distribution map. The embodiment of the present application can improve the speed of extracting information of chip pads and output the pad layout of the chip, thereby improving the efficiency of packaging production.

[0136] Please refer to Figure 13 , Figure 13 which is a schematic structural diagram of a system for extracting information of chip pads provided by an embodiment of the present application;

[0137] Among them, the system for extracting information of chip pads is applied to an electronic device. Specifically, the system for extracting information of chip pads is applied to one or more processors of the electronic device, and the electronic device includes a terminal.

[0138] As Figure 13 shown, the system 130 for extracting information of chip pads includes:

[0139] An input module 131, configured to obtain the configuration information of the chip layout, where the configuration information includes the length information, width information of the chip layout, and the pad area information of each pad area of the chip, and each pad area includes multiple pads;

[0140] An extraction module 132, configured to extract the coordinate information of each pad of the chip layout;

[0141] An algorithm module 133, configured to perform area division on each pad according to the pad area information to determine the pad area corresponding to each pad;

[0142] An output module 134, configured to generate the pad layout of the chip according to the length information, width information of the chip layout, and the coordinate information of each pad; process the pad layout of the chip to generate a pad distribution map of the chip.

[0143] In the embodiments of the present application, the information extraction system for the chip pad can also be built by hardware devices. For example, the information extraction system for the chip pad can be built by one or more than two chips, and each chip can work in coordination with each other to complete the information extraction method for the chip pad described in the above embodiments. For another example, the information extraction system for the chip pad can also be built by various logic devices, such as being built by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a single-chip microcomputer, an ARM (Acorn RISC Machine), or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components.

[0144] The information extraction system for the chip pad in the embodiments of the present application can be a device, or a component, an integrated circuit, or a chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device can be a mobile phone, a tablet computer, a laptop computer, a handheld computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc., and the non-mobile electronic device can be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, etc. The embodiments of the present application do not make specific limitations.

[0145] The information extraction system for the chip pad in the embodiments of the present application can be a device with an operating system. The operating system can be the Android operating system, the iOS operating system, or other possible operating systems. The embodiments of the present application do not make specific limitations.

[0146] The information extraction system for the chip pad provided in the embodiments of the present application can achieve Figure 4 each process achieved. To avoid repetition, it will not be elaborated here.

[0147] It should be noted that the above information extraction system for the chip pad can execute the information extraction system method provided in the embodiments of the present application, and has the corresponding functional modules and beneficial effects for executing the method. For the technical details not described in detail in the embodiments of the information extraction system for the chip pad, reference can be made to the information extraction method for the chip pad provided in the above embodiments.

[0148] In an embodiment of the present application, by providing an information extraction system for chip pads, including: an input module for obtaining configuration information of a chip layout, where the configuration information includes length information, width information of the chip layout, and pad area information of each pad area of the chip, and each pad area includes a plurality of pads; an extraction module for extracting coordinate information of each pad of the chip layout; an algorithm module for performing area division on each pad according to the pad area information to determine the pad area corresponding to each pad; an output module for generating a pad layout of the chip according to the length information, width information of the chip layout, and coordinate information of each pad; and processing the pad layout of the chip to generate a pad distribution map of the chip. By obtaining the configuration information of the chip layout, determining the coordinate information of each pad of the chip layout, determining the pad area corresponding to each pad, generating the pad layout of the chip, and processing the pad layout to generate a pad distribution map, the embodiment of the present application can improve the information extraction speed of chip pads, and thus improve the efficiency of packaging production.

[0149] Please refer to again Figure 14 , Figure 14 which is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0150] As Figure 14 shown, the electronic device 140 includes one or more processors 141 and a memory 142. Among them, Figure 14 one processor 141 is taken as an example in

[0151] The processor 141 and the memory 142 can be connected through a bus or other means, Figure 14 and taking the connection through a bus as an example in

[0152] The processor 141 is used to provide computing and control capabilities to control the electronic device 140 to execute corresponding tasks. For example, controlling the electronic device 140 to execute the information extraction method of chip pads in any of the above method embodiments, including: obtaining configuration information of a chip layout, where the configuration information includes length information, width information of the chip layout, and pad area information of each pad area of the chip, and each pad area includes a plurality of pads; extracting coordinate information of each pad of the chip layout; performing area division on each pad according to the pad area information to determine the pad area corresponding to each pad; generating a pad layout of the chip according to the length information, width information of the chip layout, and coordinate information of each pad; and processing the pad layout of the chip to generate a pad distribution map of the chip.

[0153] By obtaining the configuration information of the chip layout, determining the coordinate information of each pad of the chip layout, determining the pad area corresponding to each pad, and generating the pad layout of the chip, and processing the pad layout to generate a pad distribution map, the embodiments of the present application can improve the information extraction speed of the chip pads, thereby improving the efficiency of the packaging production.

[0154] The processor 141 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The above PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0155] The memory 142, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the chip pad information extraction method in the embodiments of the present application. By running the non-transitory software programs, instructions, and modules stored in the memory 112, the processor 141 can implement the chip pad information extraction method in any of the following method embodiments. Specifically, the memory 142 may include a volatile memory (VM), such as a random access memory (RAM); the memory 142 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), or other non-transitory solid-state storage devices; the memory 142 may further include a combination of the above types of memories.

[0156] The memory 142 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 142 optionally includes a memory remotely disposed relative to the processor 141, and these remote memories may be connected to the processor 141 through a network. Examples of the above networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0157] One or more modules are stored in the memory 142, and when executed by one or more processors 141, perform the information extraction method of the chip pad in any of the above method embodiments. For example, perform the respective steps described above Figure 4 shown; it can also implement Figure 13 the functions of the respective modules or units.

[0158] In the embodiments of the present application, the electronic device 140 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input / output. The electronic device 140 may further include other components for implementing the functions of the device, which will not be elaborated here.

[0159] The electronic device in the embodiments of the present application exists in various forms. When performing the respective steps described above Figure 4 shown; it can also implement Figure 13 the functions of the respective units, including but not limited to: fixed terminals, mobile terminals, and other devices.

[0160] The embodiments of the present application also provide a computer-readable storage medium, such as a memory including program code, and the above program code can be executed by a processor to complete the information extraction method of the chip pad in the above embodiments. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0161] The embodiments of the present application also provide a computer program product, which includes one or more program codes, and the program codes are stored in a computer-readable storage medium. The processor of the electronic device reads the program codes from the computer-readable storage medium, and the processor executes the program codes to complete the method steps of the information extraction method of the chip pad provided in the above embodiments.

[0162] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by hardware related to program code. The program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disk, etc.

[0163] Through the description of the above embodiments, those of ordinary skill in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform, and of course, it can also be implemented by hardware. Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other changes in different aspects of the present application as described above. For the sake of brevity, they are not provided in detail; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for extracting information of a chip pad, characterized in that, The method includes: Obtaining the configuration information of the chip layout, where the configuration information includes the length information, width information of the chip layout, and the pad area information of each pad area of the chip, and each pad area includes a plurality of pads; Extracting the coordinate information of each pad of the chip layout; According to the pad area information, performing area division on each pad to determine the pad area corresponding to each pad; Generating the pad layout of the chip according to the length information, width information of the chip layout, and the coordinate information of each pad; Processing the pad layout of the chip to generate the pad distribution map of the chip; The extracting the coordinate information of each pad of the chip layout includes: Extracting the bottom layer coordinates of the four vertices of each pad from the chip layout; Based on the first function, determining the top layer coordinates of the four vertices of each pad, where the first function is used to map the bottom layer coordinates of the vertex to the top layer coordinates of the layout top layer; Calculating the minimum pad pitch of the chip layout according to the coordinate information of each pad in each pad area; The calculating the minimum pad pitch of the chip layout according to the coordinate information of each pad in each pad area includes: Determining the minimum pad pitch of each pad area according to the coordinate information of each pad in each pad area; Determining the minimum pad pitch of the chip layout according to the minimum pad pitch of each pad area, where the minimum pad pitch of the chip layout is the minimum value among the minimum pad pitches of all pad areas.

2. The method according to claim 1, wherein The method further includes: After extracting the top layer coordinates of the four vertices of each pad, converting the top layer coordinates of the four vertices of each pad into the center point coordinates of each pad.

3. The method according to claim 2, wherein The arrangement mode of the chips includes single-layer arrangement and / or double-layer arrangement, and the calculating the minimum pad pitch of each pad area includes: Based on the second function, calculating the single-layer minimum pad pitch and / or double-layer minimum pad pitch of the chip, where the second function is used to calculate the single-layer minimum pad pitch and / or double-layer minimum pad pitch according to the center point coordinates of each pad.

4. The method according to claim 1, wherein The pad area includes an upper area, a lower area, a left area, and a right area, and the method further includes: Performing counterclockwise sorting on each pad in the upper area, lower area, left area, and right area respectively.

5. The method according to claim 1, characterized in that, The method further includes: Traversing each pad of the chip layout to extract the label name of each pad of the chip layout, where the label name of each pad is bound to the coordinate information; If the label name of a certain pad does not exist or is not unique, it is determined that the pad is in error and an error message is generated.

6. An information extraction system for a chip pad, characterized in that, The system includes: An input module, configured to obtain the configuration information of the chip layout, where the configuration information includes the length information, width information of the chip layout, and the pad area information of each pad area of the chip, and each pad area includes a plurality of pads; An extraction module, configured to extract the coordinate information of each pad of the chip layout; An algorithm module, configured to divide each pad into regions according to the pad region information, and determine the pad region corresponding to each pad; An output module, configured to generate a pad layout of the chip according to the length information, width information of the chip layout and the coordinate information of each pad; process the pad layout of the chip to generate a pad distribution map of the chip; The extraction module is specifically configured to extract the bottom layer coordinates of the four vertices of each pad from the chip layout, and determine the top layer coordinates of the four vertices of each pad based on a first function, where the first function is used to map the bottom layer coordinates of the vertices to the top layer coordinates of the layout top layer; The algorithm module is further configured to calculate the minimum pad pitch of the chip layout according to the coordinate information of each pad in each pad region; The algorithm module is specifically configured to determine the minimum pad pitch of each pad region according to the coordinate information of each pad in each pad region; determine the minimum pad pitch of the chip layout according to the minimum pad pitch of each pad region, where the minimum pad pitch of the chip layout is the minimum value among the minimum pad pitches of all pad regions.

7. An electronic device, characterized in that, Comprising: At least one processor; And A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can be used to execute the method according to any one of claims 1-5.

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