Flash memory physical layer testing method and flash memory device

Abstract

The embodiments of the present application relate to the field of storage device applications and disclose a method for testing a flash memory physical layer and a flash memory device. The method comprises: docking the flash memory physical layer of a flash memory controller with the flash memory physical layer of an analog particle; having the flash memory physical layer of the flash memory controller perform a read operation on the flash memory physical layer of the analog particle, so that the flash memory physical layer of the flash memory controller obtains data sent by the flash memory physical layer of the analog particle; if the data obtained by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle, then it is determined that the flash memory physical layer of the flash memory controller is functioning normally. By setting up an analog particle, docking the flash memory physical layer of the analog particle with the flash memory physical layer of the flash memory controller, and if the data obtained by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle, then it is determined that the flash memory physical layer of the flash memory controller is functioning normally, the present application can improve the testing capability of the flash memory physical layer.

Description

Technical Field

[0001] The present application relates to the field of storage device applications, and in particular to a flash memory physical layer testing method and a flash memory device. Background Art

[0002] Flash memory devices, such as solid-state drives (SSDs), are hard disks made of solid-state electronic memory chip arrays. SSDs include a control unit and a storage unit (FLASH memory chip or DRAM memory chip).

[0003] Currently, testing the flash physical layer (NAND PHY) of solid-state drives requires mounting a test structure for the NAND chip. The NAND PHY performs write and read operations on the NAND chip to determine if the NAND PHY is functioning correctly. For example, current NAND chips support Timing Mode 19, corresponding to a 1200MHz operating frequency. If existing testing methods are used, there are no NAND chips that support testing at frequencies exceeding 1200MHz, resulting in insufficient testing capabilities.

[0004] Based on this, the existing technology is in urgent need of improvement. Summary of the Invention

[0005] The embodiments of the present application provide a flash memory physical layer testing method and a flash memory device, which solve the current problem of insufficient testing capability of the flash memory physical layer and improve the testing capability of the flash memory physical layer.

[0006] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a method for testing a flash memory physical layer, which is applied to a flash memory device. The method includes:

[0008] Connect the flash memory physical layer of the flash memory controller to the flash memory physical layer of the analog particles;

[0009] The flash memory physical layer of the flash memory controller performs a read operation on the flash memory physical layer of the analog particle, so that the flash memory physical layer of the flash memory controller obtains data sent by the flash memory physical layer of the analog particle;

[0010] If the data acquired by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle, it is determined that the flash memory physical layer of the flash memory controller functions normally.

[0011] In some embodiments, the flash memory controller includes a first flash memory physical layer and a second flash memory physical layer, wherein the first flash memory physical layer and the second flash memory physical layer are connected, wherein the first flash memory physical layer serves as the flash memory physical layer to be tested, and the flash memory channel where the second flash memory physical layer is located serves as an analog particle.

[0012] In some embodiments, the flash memory device includes a first flash memory controller and a second flash memory controller, wherein the flash memory physical layer of the first flash memory controller is connected to the flash memory physical layer of the second flash memory controller, wherein the flash memory physical layer of the first flash memory controller serves as the flash memory physical layer to be tested, and the second flash memory controller serves as an analog particle.

[0013] In some embodiments, before interfacing the flash memory physical layer of the flash memory controller with the flash memory physical layer of the analog particle, the method further includes:

[0014] Setting the operating frequency of the flash memory physical layer of the flash memory controller to a first operating frequency, wherein the first operating frequency is greater than the maximum operating frequency of the flash memory particles;

[0015] The operating frequency of the flash memory physical layer of the analog particle is set to a second operating frequency, wherein the first operating frequency is equal to the second operating frequency.

[0016] In some embodiments, the method further comprises:

[0017] Updating the first operating frequency to obtain an updated first operating frequency;

[0018] Updating the second operating frequency according to the updated first operating frequency to obtain an updated second operating frequency;

[0019] The flash memory physical layer of the flash memory controller is tested again based on the updated first operating frequency and the updated second operating frequency.

[0020] In some embodiments, interfacing a flash memory physical layer of a flash memory controller with a flash memory physical layer of an analog particle includes:

[0021] Connect the DBI signal of the flash memory physical layer of the flash memory controller to the DBI signal of the flash memory physical layer of the analog particle to test the DBI function of the flash memory physical layer of the flash memory controller;

[0022] The DQ signal of the flash memory physical layer of the flash memory controller is connected to the DQ signal of the flash memory physical layer of the analog particle, and the DQS signal of the flash memory physical layer of the flash memory controller is connected to the DQS signal of the flash memory physical layer of the analog particle.

[0023] In some embodiments, the method further comprises:

[0024] The phase relationship between the DQ signal and the DQS signal of the flash memory physical layer of the analog particle is adjusted multiple times to obtain multiple phase relationships, and the flash memory physical layer of the flash memory controller is tested based on each phase relationship.

[0025] In some embodiments, the method further comprises:

[0026] If the data acquired by the flash memory physical layer of the flash memory controller is inconsistent with the data sent by the flash memory physical layer of the analog particle, it is determined that the flash memory physical layer of the flash memory controller is not functioning properly.

[0027] In some embodiments, the data sent by the flash memory physical layer of the analog particle is preset standard data.

[0028] In a second aspect, an embodiment of the present application provides a flash memory device, including:

[0029] Flash memory particles;

[0030] at least one processor; and

[0031] A memory communicatively connected to at least one processor; wherein the memory stores instructions executable by at least one processor, and the instructions are executed by at least one processor to enable the at least one processor to perform the flash memory physical layer testing method as described in the first aspect.

[0032] In a third aspect, an embodiment of the present application further provides a non-volatile computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to enable a flash memory device to execute the flash memory physical layer testing method as in the first aspect.

[0033] The beneficial effects of the embodiments of the present application are as follows: Different from the prior art, the embodiments of the present application provide a flash memory physical layer testing method and a flash memory device. The flash memory physical layer testing method is applied to a flash memory device, the flash memory device including a flash memory controller. The method includes: connecting the flash memory physical layer of the flash memory controller with the flash memory physical layer of an analog particle; having the flash memory physical layer of the flash memory controller perform a read operation on the flash memory physical layer of the analog particle, so that the flash memory physical layer of the flash memory controller obtains data sent by the flash memory physical layer of the analog particle; if the data obtained by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle, then it is determined that the flash memory physical layer of the flash memory controller is functioning normally. By setting up an analog particle, connecting the flash memory physical layer of the analog particle with the flash memory physical layer of the flash memory controller, and if the data obtained by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle, then it is determined that the flash memory physical layer of the flash memory controller is functioning normally. The present application can improve the testing capability of the flash memory physical layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0035] Figure 1 This is a schematic structural diagram of a flash memory device provided in an embodiment of the present application;

[0036] Figure 2 This is a schematic diagram of the connection relationship between a NAND controller and NAND chips provided in an embodiment of the present application;

[0037] Figure 3 This is a flow chart of a testing method provided in an embodiment of the present application;

[0038] Figure 4 This is a flow chart of a flash memory physical layer testing method provided by an embodiment of the present application;

[0039] Figure 5 This is a schematic structural diagram of a flash memory controller provided by an embodiment of the present application;

[0040] Figure 6 This is a connection diagram of the first test method provided in the embodiment of the present application;

[0041] Figure 7 This is a specific connection diagram of the first test method provided in the embodiment of the present application;

[0042] Figure 8 This is a connection diagram of the second test method provided in the embodiment of the present application;

[0043] Figure 9 This is a specific connection diagram of the second test method provided in the embodiment of the present application;

[0044] Figure 10 This is a schematic diagram of the overall process of a flash memory physical layer testing method provided by an embodiment of the present application;

[0045] Figure 11 This is a flow chart of another method for testing the physical layer of a flash memory provided in an embodiment of the present application;

[0046] Figure 12 This is a schematic structural diagram of another flash memory device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0048] It should be noted that, if there is no conflict, the various features in the embodiments of the present application can be combined with each other and are all within the scope of protection of the present application. In addition, although the functional modules are divided in the device schematic and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a different order than the module division in the device or the order in the flow chart. Furthermore, the words "first", "second", "third", etc. used in this application do not limit the data and execution order, but only distinguish between the same items or similar items with basically the same functions and effects.

[0049] Before explaining the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations:

[0050] (1) Flash memory physical layer refers to NAND PHY. NAND Flash (non-volatile flash memory) storage devices include NAND Flash particles for storing data and a flash memory controller for managing the data stored in the NAND Flash particles. Among them, the NAND PHY (Port Physical Layer) in the flash memory controller is connected to the NAND Flash particles through IO (Input / Output) to manage the data stored in the NAND Flash particles.

[0051] The technical solution of this application is described in detail below with reference to the accompanying drawings:

[0052] See also Figure 1 , Figure 1 This is a schematic structural diagram of a flash memory device provided in an embodiment of the present application;

[0053] like Figure 1 As shown, the flash memory device 100 includes a flash memory medium 110 and a controller 120 connected to the flash memory medium 110. The flash memory device 100 is connected to the host 200 in a wired or wireless manner to implement data exchange.

[0054] Flash memory medium 110, as the storage medium of flash memory device 100, is also called flash memory, Flash, Flash memory or Flash particles. It is a type of storage device and a non-volatile memory that can store data for a long time even without current supply. Its storage characteristics are equivalent to those of a hard disk, making flash memory medium 110 the basis of storage media for various portable digital devices.

[0055] The controller 120 includes a data converter 121 , a processor 122 , a buffer 123 , a flash memory controller 124 , and an interface 125 .

[0056] The data converter 121 is connected to the processor 122 and the flash memory controller 124 respectively. The data converter 121 is used to convert binary data into hexadecimal data, and convert hexadecimal data into binary data. Specifically, when the flash memory controller 124 writes data to the flash memory medium 110, the binary data to be written is converted into hexadecimal data through the data converter 121, and then written into the flash memory medium 110. When the flash memory controller 124 reads data from the flash memory medium 110, the hexadecimal data stored in the flash memory medium 110 is converted into binary data through the data converter 121, and then the converted data is read from the binary data page register. The data converter 121 may include a binary data register and a hexadecimal data register. The binary data register can be used to store data converted from hexadecimal to binary, and the hexadecimal data register can be used to store data converted from binary to hexadecimal.

[0057] The processor 122 is respectively connected to the data converter 121, the cache 123, the flash memory controller 124 and the interface 125, wherein the processor 122 and the data converter 121, the cache 123, the flash memory controller 124 and the interface 125 can be connected via a bus or other means, and the processor is used to run the non-volatile software programs, instructions and modules stored in the cache 123, so as to implement any method embodiment of the present application.

[0058] The buffer 123 is mainly used to buffer the read / write instructions sent by the host 200 and the read data or write data obtained from the flash memory medium 110 according to the read / write instructions sent by the host 200.

[0059] The flash memory controller 124 is connected to the flash memory medium 110, the data converter 121, the processor 122 and the cache 123, and is used to access the back-end flash memory medium 110 and manage various parameters and data I / O of the flash memory medium 110; or, it is used to provide an access interface and protocol, implement the corresponding SAS / SATA target protocol end or NVMe protocol end, obtain I / O instructions issued by the host 200, and decode and generate internal private data results for execution; or, it is responsible for the core processing of the flash translation layer (FTL).

[0060] Interface 125 connects the host 200 and the data converter 121, the processor 122 and the buffer 123, and is used to receive data sent by the host 200, or receive data sent by the processor 122, to realize data transmission between the host 200 and the processor 122. Interface 125 can be a SATA-2 interface, a SATA-3 interface, a SAS interface, an MSATA interface, a PCI-E interface, an NGFF interface, a CFast interface, an SFF-8639 interface and an M.2 NVME / SATA protocol.

[0061] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the connection relationship between a NAND controller and NAND chips provided in an embodiment of the present application;

[0062] like Figure 2 As shown, the NAND controller is connected to the NAND particles, wherein the NAND controller refers to a flash memory controller, and the NAND particles refer to NAND Flash particles.

[0063] Please refer to Figure 3 , Figure 3 This is a flow chart of a testing method provided in an embodiment of the present application;

[0064] like Figure 3 As shown in FIG, the process of the test method includes:

[0065] Step S301: Setting NAND PHY;

[0066] Step S302: NANDPHY writes data to the particle;

[0067] Step S303: NANDPHY reads data from the particle;

[0068] Step S304: Compare the written data and the read data to see if they are consistent;

[0069] Among them, since the existing physical layer testing methods all require particle support, when the test frequency is high, there are no corresponding NAND particles to support the test, resulting in insufficient testing capabilities.

[0070] Based on this, an embodiment of the present application provides a method for testing a flash memory physical layer to improve the testing capability of the flash memory physical layer.

[0071] See also Figure 4 , Figure 4 This is a flow chart of a flash memory physical layer testing method provided by an embodiment of the present application;

[0072] Among them, the testing method of the flash memory physical layer is applied to a flash memory device, wherein the flash memory device includes a flash memory controller, and the flash memory controller includes a flash memory physical layer (NANDPHY), namely NAND PHY (Port Physical Layer). Specifically, the testing method of the flash memory physical layer is applied to one or more processors of the flash memory controller.

[0073] like Figure 4 As shown, the flash memory physical layer testing method includes:

[0074] Step S401: connecting the flash memory physical layer of the flash memory controller with the flash memory physical layer of the analog particle;

[0075] For details, please refer to Figure 5 , Figure 5 This is a schematic structural diagram of a flash memory controller provided by an embodiment of the present application;

[0076] like Figure 5 As shown, the flash memory controller (NAND controller) includes: a control module, several flash memory physical layers (NANDPHY), such as: NAND PHY0, ..., NAND PHYn and IO modules, such as: IO_0, ..., IO_n.

[0077] The control module is used to control the flash memory physical layer (NAND PHY) and send read and write operation commands to the NAND PHY.

[0078] The flash memory physical layer (NAND PHY) is used to convert the operation of the control module into an operation that meets the interface requirements of the flash memory particles.

[0079] Among them, the IO module, namely the NAND input and output interface, namely NAND IO (Input / Output), is used for data input or output of the flash memory controller. The IO module is connected to the flash memory physical layer, and the flash memory physical layer inputs or outputs data through the IO module.

[0080] In the embodiment of the present application, the flash memory physical layer (NAND PHY) and the IO module are combined into a flash memory channel (NAND channel). Generally, there are multiple flash memory channels (NAND channels) in a flash memory controller. Multiple flash memory channels can operate independently of each other.

[0081] In the embodiment of the present application, a NAND controller is used to simulate NAND particles to test the NAND PHY in the NAND controller. One NAND channel can simulate one NAND particle. Therefore, two channels in a NAND controller can be used, and one channel simulates a NAND particle for testing.

[0082] Alternatively, since a NAND controller has multiple NAND channels, two NAND controllers can be used, and one NAND controller (all NAND channels) can be used to simulate NAND chips for testing.

[0083] In an embodiment of the present application, the flash memory controller includes a first flash memory physical layer and a second flash memory physical layer, wherein the first flash memory physical layer and the second flash memory physical layer are connected, wherein the first flash memory physical layer serves as the flash memory physical layer to be tested, and the flash memory channel where the second flash memory physical layer is located serves as an analog particle.

[0084] For details, please refer to Figure 6 , Figure 6 This is a connection diagram of the first test method provided in the embodiment of the present application;

[0085] like Figure 6 As shown, the first test method is to test the flash physical layer between the same flash controller of the flash memory device, for example, the flash physical layer of flash memory controller 0 is connected to the analog particle of flash memory controller 0. Specifically, the DQ signal of the flash physical layer of the flash memory controller is connected to the DQ signal of the flash physical layer of the analog particle, the DQS signal of the flash physical layer of the flash memory controller is connected to the DQS signal of the flash physical layer of the analog particle, and the DBI signal of the flash physical layer of the flash memory controller is connected to the DBI signal of the flash physical layer of the analog particle.

[0086] It can be understood that the connection link between the flash memory physical layer of the flash memory controller and the flash memory physical layer of the analog particles includes a DQS (Bi-directional Data Strobe) link and a DQ (data I / O channel) link, wherein the DQ link is used to read and write NANDFlash particles, and the data signal transmitted thereon is called a DQ signal; the DBI signal transmitted on the DBI link is used to indicate whether the current DQ signal needs to be flipped; the DQS signal transmitted on the DQS link is used as a reference signal for collecting DQ signals and DBI signals to determine when to collect DQ signals and DBI signals, wherein the DQ signal (datainput / output), that is, the data signal, is used to support input / output, and the DQS signal (datastrobe), that is, the data valid signal.

[0087] In the embodiment of the present application, in order to ensure the correctness of data transmission between the flash memory physical layer of the flash memory controller and the flash memory physical layer of the analog particles, it is necessary to ensure that the phase relationship between the DQS signal, DQ signal and DBI signal is within a correct range.

[0088] In an embodiment of the present application, the simulated particles are also implemented using a flash memory controller, for example: the simulated particles are simulated by the flash memory channel of the flash memory controller, for example: the behavior of the simulated particles is simulated, thereby realizing the corresponding functions of the simulated particles.

[0089] For details, please refer to Figure 7 , Figure 7 This is a specific connection diagram of the first test method provided in the embodiment of the present application;

[0090] like Figure 7 As shown, NAND PHY0 in flash memory controller 0 serves as the flash memory physical layer to be tested, and the flash memory channel composed of NAND PHYn and IO_n in flash memory controller 0 serves as the simulated particle. NAND PHY0 in flash memory controller 0 is tested, wherein one flash memory channel (NAND channel) can simulate one flash memory particle (NAND particle). Therefore, the embodiment of the present application uses two flash memory channels in a flash memory controller, wherein one flash memory channel is used to simulate the NAND particle for testing.

[0091] In the embodiment of the present application, the flash memory physical layer NAND PHY0 and the flash memory physical layer NAND PHYn are connected through the IO module. Specifically, Figure 7 As shown, the flash memory physical layer NAND PHY0 interacts with IO_n through IO_0 to achieve docking with NAND PHYn.

[0092] It is understandable that the connection between the flash memory physical layers in the embodiments of the present application can also be achieved through other media, such as the hardware module or transport layer of the flash memory controller, which is not limited here.

[0093] In an embodiment of the present application, the flash memory device includes a first flash memory controller and a second flash memory controller, wherein the flash memory physical layer of the first flash memory controller is connected to the flash memory physical layer of the second flash memory controller, wherein the flash memory physical layer of the first flash memory controller serves as the flash memory physical layer to be tested, and the second flash memory controller serves as an analog particle.

[0094] For details, please refer to Figure 8 , Figure 8 This is a connection diagram of the second test method provided in the embodiment of the present application;

[0095] like Figure 8 As shown, the second test method is to test the flash memory physical layer between the two flash memory controllers of the flash memory device. For example, a flash memory physical layer of flash memory controller 0 is used as the flash memory physical layer to be tested, and flash memory controller 1 is used as the simulated particle, that is, the flash memory physical layer of flash memory controller 1 is used as the flash memory physical layer of the simulated particle.

[0096] It is understandable that, since a flash memory controller has multiple flash memory channels, two flash memory controllers can be used, and all flash memory channels of one flash memory controller are used to simulate NAND particles for testing.

[0097] Please refer to Figure 9 , Figure 9 This is a specific connection diagram of the second test method provided in the embodiment of the present application;

[0098] like Figure 9 As shown, both flash memory controller 0 and flash memory controller 1 have multiple flash memory channels, wherein the flash memory physical layer of flash memory controller 0 serves as the flash memory physical layer to be tested, flash memory controller 1 serves as the simulation particle, and all NAND channels of flash memory controller 1 are used to simulate flash memory particles for testing.

[0099] In the embodiment of the present application, the flash memory physical layer NAND PHY0 of the flash memory controller 0 and the flash memory physical layer NAND PHY0 of the flash memory controller 1 are connected through the IO module. Specifically, Figure 9 As shown, the flash memory physical layer NAND PHY0 of the flash memory controller 0 interacts with the IO_0 of the flash memory physical layer NAND PHY0 of the flash memory controller 1 through the IO_0 of the flash memory controller 0 to achieve docking with the two flash memory physical layers.

[0100] It is understandable that the connection between the flash memory physical layers in the embodiments of the present application can also be achieved through other media, such as the hardware module or transport layer of the flash memory controller, which is not limited here.

[0101] Step S402: the flash memory physical layer of the flash memory controller performs a read operation on the flash memory physical layer of the analog particle, so that the flash memory physical layer of the flash memory controller obtains data sent by the flash memory physical layer of the analog particle;

[0102] Specifically, the flash memory physical layer (NAND PHY0) of the flash memory controller performs a read operation on the flash memory physical layer (NAND PHY1) of the simulated particle, so that the flash memory physical layer (NAND PHY0) of the flash memory controller obtains the data sent by the flash memory physical layer (NAND PHY1) of the simulated particle, wherein the data sent by the flash memory physical layer (NAND PHY1) of the simulated particle is preset standard data, that is, the data written by the flash memory physical layer (NAND PHY1) of the simulated particle is preset standard data, and the flash memory physical layer (NAND PHY1) of the simulated particle writes the preset standard data to the flash memory controller.

[0103] Step S403: If the data acquired by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the simulation particle, it is determined that the flash memory physical layer of the flash memory controller functions normally.

[0104] For details, please refer to Figure 10 , Figure 10 This is a schematic diagram of the overall process of a flash memory physical layer testing method provided by an embodiment of the present application;

[0105] like Figure 10 As shown, the overall process of the flash memory physical layer testing method includes:

[0106] Step S101: connecting the flash memory physical layer of the flash memory controller with the flash memory physical layer of the analog particle;

[0107] Step S102: the flash memory physical layer of the flash memory controller performs a read operation on the flash memory physical layer of the analog particle, so that the flash memory physical layer of the flash memory controller obtains data sent by the flash memory physical layer of the analog particle;

[0108] Specifically, after the flash memory physical layer (NAND PHY1) of the simulated particle writes the preset standard data to the flash memory controller, a command to read the preset standard data is sent to the flash memory controller so that the flash memory physical layer (NAND PHY0) of the flash memory controller obtains the preset standard data sent by the flash memory physical layer (NAND PHY1) of the simulated particle.

[0109] Step S103: determining whether the data acquired by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle;

[0110] Specifically, the data acquired by the flash memory physical layer of the flash memory controller is compared with the data sent by the flash memory physical layer of the simulation particle to determine whether the two are consistent.

[0111] Step S104: Determine whether the flash memory physical layer of the flash memory controller functions normally;

[0112] Specifically, if the data acquired by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle, it is determined that the flash memory physical layer of the flash memory controller functions normally.

[0113] Step S105: determining whether the flash memory physical layer of the flash memory controller is functionally abnormal;

[0114] Specifically, if the data acquired by the flash memory physical layer of the flash memory controller is inconsistent with the data sent by the flash memory physical layer of the analog particle, it is determined that the flash memory physical layer of the flash memory controller has a function abnormality.

[0115] In the embodiment of the present application, before connecting the flash memory physical layer of the flash memory controller with the flash memory physical layer of the analog particle, the method further includes:

[0116] Setting the operating frequency of the flash memory physical layer of the flash memory controller to a first operating frequency;

[0117] The operating frequency of the flash memory physical layer of the analog particle is set to a second operating frequency, wherein the first operating frequency is equal to the second operating frequency.

[0118] In the embodiment of the present application, the first operating frequency is greater than the maximum operating frequency of the flash memory particles. For example, assuming the maximum operating frequency of the flash memory particles is 1200 MHz and the first operating frequency is 1600 MHz, since the first operating frequency is greater than the maximum operating frequency of the flash memory particles, the operating frequency of the flash memory controller can be tested, thereby improving testing capabilities.

[0119] For details, please refer to Figure 11 , Figure 11 This is a flow chart of another method for testing the physical layer of a flash memory provided in an embodiment of the present application;

[0120] like Figure 11 As shown, the process of the flash memory physical layer testing method includes:

[0121] Step S111: setting a first operating frequency of NANDPHY0;

[0122] Specifically, the operating frequency of the flash physical layer (NANDPHY0) of the flash controller is set to a first operating frequency, wherein the first operating frequency exceeds the upper limit of the operating frequency supported by the current flash memory particles, that is, the first operating frequency is greater than the maximum operating frequency of the flash memory particles of the flash memory device.

[0123] Step S112: setting a second operating frequency of NAND PHY1, wherein the second operating frequency is equal to the first operating frequency;

[0124] In an embodiment of the present application, in order to test multiple operating frequencies, the method further includes:

[0125] Updating the first operating frequency to obtain an updated first operating frequency;

[0126] Updating the second operating frequency according to the updated first operating frequency to obtain an updated second operating frequency;

[0127] The flash memory physical layer of the flash memory controller is tested again based on the updated first operating frequency and the updated second operating frequency.

[0128] Step S113: Adjust the test parameters of NANDPHY1 so that the output timing meets the test requirements;

[0129] It is understandable that the flash memory physical layer has multiple sets of test parameters, including operating frequency, input delay value of DQ signal, output delay value of DQ signal, input delay value of DQS signal, output delay value of DQS signal, etc. Different parameters need to be set in different test processes.

[0130] In the embodiment of the present application, three test processes are included, namely PHY high frequency test, DBI function test and DQ-DQS multi-phase relationship test, among which different test processes require setting and adjusting corresponding test parameters.

[0131] For example, in a PHY high-frequency test, if you need to test the PHY at 1600MHz, set the PHY operating frequency to 1600MHz, and the analog particle will then operate at 1600MHz. The DBI functional test mainly enables the DBI signal. The DQ-DQS multi-phase relationship test mainly adjusts the input delay value of the DQ signal, the output delay value of the DQ signal, the input delay value of the DQS signal, and the output delay value of the DQS signal to obtain different phase relationships. Based on these different phase relationships, determine whether the data obtained by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer (NAND PHY1) of the analog particle, so as to determine whether the flash memory physical layer of the flash memory controller functions normally.

[0132] Step S114: NAND PHY0 performs a read operation;

[0133] Step S115: NAND PHY1 performs a write operation;

[0134] Step S116: NAND PHY0 obtains the data sent by NAND PHY1;

[0135] Step S117: Compare the data acquired by NAND PHY0 and the data sent by NAND PHY1 to see if they are consistent.

[0136] In the embodiment of the present application, three different test processes are used, namely, PHY high frequency test, DBI functional test, and DQ-DQS multi-phase relationship test. The test processes all involve adjusting the test parameters and then performing the operations of steps S114 to S117, which will not be repeated here.

[0137] It is understandable that since the output timing of a specific flash memory particle is fixed, the specific flash memory particle can only test a fixed output timing and cannot cover multiple timing relationships. Therefore, the present application controls the test parameters of the flash memory controller and the analog particle, that is, adjusts the input delay value of the DQ signal, the output delay value of the DQ signal, the input delay value of the DQS signal, and the output delay value of the DQS signal to obtain different phase relationships, so as to achieve coverage of multiple timing relationships, thereby improving the test efficiency of the flash memory physical layer.

[0138] In an embodiment of the present application, a method for testing a flash memory physical layer is provided, including: docking the flash memory physical layer of a flash memory controller with the flash memory physical layer of an analog particle; performing a read operation by the flash memory physical layer of the flash memory controller to the flash memory physical layer of the analog particle, so that the flash memory physical layer of the flash memory controller obtains data sent by the flash memory physical layer of the analog particle; if the data obtained by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle, it is determined that the function of the flash memory physical layer of the flash memory controller is normal.

[0139] On the one hand, by setting up an analog particle and connecting the flash memory physical layer of the analog particle with the flash memory physical layer of the flash memory controller, it is possible to test the NAND PHY without the need for particle support. On the other hand, by adjusting the operating frequency of the analog particle, it is possible to test the NAND PHY even when the existing particle does not support a higher operating frequency, thereby improving the testing capability of the flash memory physical layer. On the other hand, by controlling the test parameters of the flash memory controller and the analog particle to obtain different phase relationships to cover a variety of timing relationships, if the data obtained by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle, it is determined that the flash memory physical layer of the flash memory controller is functioning normally. This application can improve the testing efficiency of the flash memory physical layer.

[0140] Please refer to Figure 12 , Figure 12 is a structural diagram of another flash memory device provided in an embodiment of the present application;

[0141] like Figure 12 As shown, the flash memory device 1200 includes one or more processors 1210, a memory 1220, and flash memory particles 1230. Figure 12 A processor 1210 is taken as an example.

[0142] The processor 1210 and the memory 1220 may be connected via a bus or other means. Figure 12 The bus connection is taken as an example.

[0143] Processor 1210 is used to provide computing and control capabilities to control the flash memory device 1200 to perform corresponding tasks, for example, controlling the flash memory device 1200 to perform the flash memory physical layer testing method in any of the above method embodiments, including: docking the flash memory physical layer of the flash memory controller with the flash memory physical layer of the simulated particles; performing a read operation by the flash memory physical layer of the flash memory controller to the flash memory physical layer of the simulated particles, so that the flash memory physical layer of the flash memory controller obtains data sent by the flash memory physical layer of the simulated particles; if the data obtained by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the simulated particles, it is determined that the function of the flash memory physical layer of the flash memory controller is normal.

[0144] By setting up an analog particle, the flash memory physical layer of the analog particle is connected to the flash memory physical layer of the flash memory controller. If the data obtained by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle, it is determined that the function of the flash memory physical layer of the flash memory controller is normal. This application can improve the testing capability of the flash memory physical layer.

[0145] The processor 1210 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or any combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0146] The memory 1220 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as the program instructions / modules corresponding to the flash memory physical layer test method in the embodiment of the present application. The processor 1210 can implement the flash memory physical layer test method in any of the following method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 1220. Specifically, the memory 1220 may include a volatile memory (VM), such as a random access memory (RAM); the memory 1220 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD) or other non-transitory solid-state storage device; the memory 1220 may also include a combination of the above types of memory.

[0147] The memory 1220 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state memory device. In some embodiments, the memory 1220 may optionally include a memory remotely located relative to the processor 1210, and such remote memory may be connected to the processor 1210 via a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0148] One or more modules are stored in the memory 1220, and when executed by one or more processors 1210, execute the flash memory physical layer test method in any of the above method embodiments, for example, execute the above described Figure 4 The steps shown.

[0149] Flash memory particles 1230, also known as flash memory, are a type of non-volatile memory, that is, they can still save written data even when the power is off, and are stored in fixed blocks rather than individual bytes. In the embodiment of the present application, the flash memory particles 123 include NAND flash memory particles. Among them, according to the difference in the density of the electronic cells in the NAND flash memory, they can be divided into single-level cell (SLC), double-level cell (MLC), triple-level cell (TLC) and quad-level cell (QLC).

[0150] In an embodiment of the present application, the flash memory device 1200 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The flash memory device 1200 may also include other components for realizing device functions, which will not be described in detail here.

[0151] The flash memory device of the embodiment of the present application exists in various forms. Figure 4 The steps shown include, but are not limited to, storage devices such as solid-state drives.

[0152] The present application also provides a computer-readable storage medium, such as a memory including program code, wherein the program code can be executed by a processor to perform the flash memory physical layer test method in the above embodiment. For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0153] The present application also provides a computer program product including one or more program codes stored in a computer-readable storage medium. A processor of an electronic device reads the program code from the computer-readable storage medium and executes the program code to perform the steps of the flash memory physical layer testing method provided in the above embodiment.

[0154] Those skilled in the art will understand that all or part of the steps of implementing the above embodiments can be completed by hardware, or by hardware related to program code, and the program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a disk or an optical disk, etc.

[0155] Through the description of the above embodiments, it can be clearly understood by those skilled in the art that each embodiment can be implemented by means of software plus a general hardware platform, or of course by hardware. It can be understood by those skilled in the art that all or part of the processes in the above embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Based on the idea of ​​the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as mentioned above. For the sake of simplicity, they are not provided in detail. Although the present application has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for testing the physical layer of a flash memory, characterized in that: Applied to a flash memory device, the flash memory device including a flash memory controller, the method comprising: Connecting the flash memory physical layer of the flash memory controller to the flash memory physical layer of the analog particle; The flash memory physical layer of the flash memory controller performs a read operation on the flash memory physical layer of the analog particle, so that the flash memory physical layer of the flash memory controller obtains data sent by the flash memory physical layer of the analog particle; If the data acquired by the flash memory physical layer of the flash memory controller is consistent with the data sent by the flash memory physical layer of the analog particle, it is determined that the function of the flash memory physical layer of the flash memory controller is normal; Before connecting the flash memory physical layer of the flash memory controller with the flash memory physical layer of the analog particle, the method further includes: Setting the operating frequency of the flash memory physical layer of the flash memory controller to a first operating frequency, wherein the first operating frequency is greater than the maximum operating frequency of the flash memory particles; The operating frequency of the flash memory physical layer of the analog particle is set to a second operating frequency, wherein the first operating frequency is equal to the second operating frequency.

2. The method according to claim 1, characterized in that The flash memory controller includes a first flash memory physical layer and a second flash memory physical layer, wherein the first flash memory physical layer and the second flash memory physical layer are connected, wherein the first flash memory physical layer serves as the flash memory physical layer to be tested, and the flash memory channel where the second flash memory physical layer is located serves as an analog particle.

3. The method according to claim 1, characterized in that The flash memory device includes a first flash memory controller and a second flash memory controller, wherein the flash memory physical layer of the first flash memory controller is connected to the flash memory physical layer of the second flash memory controller, wherein the flash memory physical layer of the first flash memory controller serves as the flash memory physical layer to be tested, and the second flash memory controller serves as a simulation particle.

4. The method according to claim 1, wherein The method further comprises: Updating the first operating frequency to obtain an updated first operating frequency; updating the second operating frequency according to the updated first operating frequency to obtain an updated second operating frequency; The flash memory physical layer of the flash memory controller is tested again based on the updated first operating frequency and the updated second operating frequency.

5. The method according to claim 1, wherein The step of connecting the flash memory physical layer of the flash memory controller with the flash memory physical layer of the analog particles includes: Connecting the DBI signal of the flash memory physical layer of the flash memory controller to the DBI signal of the flash memory physical layer of the analog particle to test the DBI function of the flash memory physical layer of the flash memory controller; The DQ signal of the flash memory physical layer of the flash memory controller is connected to the DQ signal of the flash memory physical layer of the analog particle, and the DQS signal of the flash memory physical layer of the flash memory controller is connected to the DQS signal of the flash memory physical layer of the analog particle.

6. The method according to claim 5, characterized in that The method further comprises: The phase relationship between the DQ signal and the DQS signal of the flash memory physical layer of the analog particle is adjusted multiple times to obtain multiple phase relationships, and the flash memory physical layer of the flash memory controller is tested based on each phase relationship.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: If the data acquired by the flash memory physical layer of the flash memory controller is inconsistent with the data sent by the flash memory physical layer of the analog particle, it is determined that the flash memory physical layer of the flash memory controller is not functioning properly.

8. The method according to any one of claims 1 to 6, characterized in that The data sent by the flash memory physical layer of the analog particle is preset standard data.

9. A flash memory device, characterized in that: include: Flash memory particles; at least one processor; as well as A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor so as to enable the at least one processor to execute the method for testing the flash memory physical layer according to any one of claims 1 to 8.

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