Semiconductor process method capable of eliminating shallow trench pits

Abstract

The present invention provides a semiconductor process method for eliminating shallow trench pits, comprising the following steps: providing a substrate comprising a plurality of spaced active areas and a shallow trench isolation structure located in the middle of the active areas; forming a well region within the active areas; forming a sacrificial material layer of a first thickness, the sacrificial material layer covering the active areas and the shallow trench isolation structure, the sacrificial material layer being made of the same material as the shallow trench isolation structure; performing chemical mechanical polishing on the sacrificial material layer to reduce the thickness of the sacrificial material layer to a second thickness, the difference between the first thickness and the second thickness being greater than or equal to 400 angstroms; performing wet etching to remove the remaining sacrificial material layer and to flush the upper surface of the active area with the upper surface of the shallow trench isolation structure; and sequentially forming a gate oxide layer and a gate polysilicon layer on the upper surface of the active area. The present invention can effectively prevent the formation of pits around the shallow trench isolation structure, prevent partial conduction of the device, and help improve device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, in particular to a semiconductor process method capable of eliminating front trench pits. Background Art

[0002] In the manufacturing process of most existing semiconductor devices, a plurality of active areas 12 are separated by a shallow trench isolation structure 11. Then, ion implantation is performed on the active area 12 under the protection of a sacrificial oxide layer 16 to form a well region. Then, a gate oxide layer 13 and a gate polysilicon layer 14 are formed on the surface of the active area 12. This process can be referred to Figure 1-4 In conventional semiconductor manufacturing processes, after the silicon nitride layer on the surface of the active area 12 is removed, a height difference d is formed between the upper surface of the shallow trench isolation structure 11 and the upper surface of the active area 12. This results in a shallow trench pit 15 approximately 200 Å wide being formed during the subsequent wet stripping and wet removal of the sacrificial oxide layer 16 in the well implantation step. After the gate polysilicon layer 14 is filled into this pit 15, the electric field there is stronger, which can easily cause the device to be partially turned on, resulting in device performance degradation. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a semiconductor process method that can eliminate shallow trench pits, which is used to solve the problems in the existing device manufacturing process, such as the height difference between the upper surface of the shallow trench isolation structure and the upper surface of the active area, resulting in the formation of shallow trench pits during the wet stripping of the subsequent well injection step and the wet removal of the sacrificial oxide layer. After the gate polysilicon layer is filled in this pit, the electric field at this location is stronger, which easily causes the device to be locally turned on, resulting in a decrease in device performance.

[0004] To achieve the above-mentioned and other related objectives, the present invention provides a semiconductor process method capable of eliminating shallow trench pits, comprising the steps of:

[0005] Providing a substrate, the substrate comprising a plurality of active areas spaced apart and a shallow trench isolation structure located in the middle of the active areas, wherein the upper surface of the shallow trench isolation structure is higher than the upper surface of the active area;

[0006] forming a well region in the active region;

[0007] forming a sacrificial material layer of a first thickness, the sacrificial material layer covering the active area and the shallow trench isolation structure, the material of the sacrificial material layer being the same as that of the shallow trench isolation structure;

[0008] performing chemical mechanical polishing on the sacrificial material layer so that the thickness of the sacrificial material layer is reduced to a second thickness, wherein the difference between the first thickness and the second thickness is greater than or equal to 400 angstroms;

[0009] Performing wet etching to remove the remaining sacrificial material layer and make the upper surface of the active area flush with the upper surface of the shallow trench isolation structure;

[0010] A gate oxide layer and a gate polysilicon layer are sequentially formed on the upper surface of the active area.

[0011] Optionally, the shallow trench isolation structure and the sacrificial material layer are both made of silicon oxide layer.

[0012] Optionally, the shallow trench isolation structure is formed by chemical vapor deposition.

[0013] Optionally, before forming the well region in the active region, a step of forming a protective layer on the surface of the active region is also included, and the material of the protective layer is the same as the material of the shallow trench isolation structure; then, under the action of the protective layer, ion implantation and high-temperature annealing are performed on the active region to form the well region.

[0014] Optionally, the protective layer is formed by thermal oxidation, and the thickness of the protective layer is 100 angstroms to 200 angstroms.

[0015] Optionally, the first thickness is 800 angstroms to 1200 angstroms, and the second thickness is 300 angstroms to 600 angstroms.

[0016] Optionally, the first thickness is 1000 angstroms and the second thickness is 500 angstroms.

[0017] Optionally, the gate oxide layer is formed by dry oxygen thermal oxidation, and the thickness of the formed gate oxide layer is 200 angstroms to 500 angstroms.

[0018] Optionally, the gate polysilicon layer is formed by chemical vapor deposition, and the thickness of the formed gate polysilicon layer is 1000 angstroms to 2000 angstroms.

[0019] The present invention also provides a semiconductor device, which is manufactured according to the semiconductor process method described in any of the above solutions.

[0020] As described above, the semiconductor process method of the present invention that can eliminate shallow trench pits has the following beneficial effects: through improved process design, the present invention first adopts a chemical mechanical polishing process and then adopts a wet etching process to remove the sacrificial material layer. In this process, the height difference between the shallow trench isolation structure and the active area surface can be eliminated, thereby effectively avoiding the formation of pits around the shallow trench isolation structure, avoiding local conduction of the device, and helping to improve device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1-4 It is a cross-sectional schematic diagram showing a prior art method of forming a pit next to a shallow trench isolation structure.

[0022] Figure 5-11 Schematic diagrams of exemplary cross-sectional structures presented in various steps of the manufacturing process of the semiconductor process method for eliminating shallow trench pits provided by the present invention are shown.

[0023] Figure 12 The flowchart of the semiconductor process method for eliminating shallow trench pits provided by the present invention is shown.

[0024] Component number description

[0025] 21 Active region

[0026] 22 Shallow Trench Isolation Structure

[0027] 23 Sacrificial material layer

[0028] 24 Gate oxide layer

[0029] 25 Gate polysilicon layer

[0030] 26 protective layer DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional views showing the device structure will not be partially enlarged according to the general proportion, and the schematic views are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0032] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0033] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0034] It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components relevant to the present invention and are not drawn to the exact number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be varied arbitrarily, and the component layout may be more complex. To minimize the illustrations, not all structures are labeled in the drawings.

[0035] See also Figures 5 to 12 .

[0036] like Figure 12 As shown, the present invention provides a semiconductor process method for eliminating shallow trench pits, comprising the steps of:

[0037] S01: Provide a substrate, the substrate comprising a plurality of spaced active areas 21 and a shallow trench isolation structure 22 located in the middle of the active area 21, that is, the shallow trench isolation structure 22 separates the active area 21, and the upper surface of the shallow trench isolation structure 22 is higher than the upper surface of the active area 21, that is, there is a height difference d between the upper surface of the shallow trench isolation structure 22 and the upper surface of the active area 21. If this height difference is not eliminated, pits will be formed around the shallow trench isolation structure 22 in the subsequent process, resulting in a decrease in device performance. The present invention can effectively solve this problem; the structure of this step refers to Figure 5 As shown; the substrate includes but is not limited to a silicon substrate, a germanium substrate, a germanium silicon substrate, an SOI substrate or other semiconductor substrates, and a silicon substrate is preferably used in this embodiment;

[0038] S02: forming a well region in the active region 21; in a preferred example, before forming the well region in the active region 21, the step of forming a protective layer 26 on the surface of the active region 21 is also included. The material of the protective layer 26 and the material of the shallow trench isolation structure 22 are both silicon oxide, but are usually formed by different processes. For example, the protective layer 26 is preferably formed by wet oxygen thermal oxidation, and the shallow trench isolation structure 22 is preferably formed by chemical vapor deposition. Thereafter, under the action of the protective layer 26, ion implantation and high temperature annealing are performed on the active region 21 to form the well region, and the following is obtained: Figure 6The structure shown; when the substrate is a silicon substrate, the protective layer 26 is preferably a silicon oxide layer, and is preferably formed by a thermal oxidation process, and the thickness of the protective layer 26 is preferably 100 angstroms to 200 angstroms; using a thermal oxidation process to form a silicon oxide layer as the protective layer 26 can not only shorten the process time, but also the silicon oxide layer formed by thermal oxidation is an amorphous structure, while the silicon substrate is a single crystal silicon structure, and the single crystal silicon atoms are regularly arranged, which is prone to channeling. When ions are implanted into the amorphous silicon oxide, they collide with silicon atoms or oxygen atoms, and the direction of ion movement is more random, which reduces the channeling effect. Therefore, compared with directly implanting ions on the exposed active area 21, the method of the present invention helps to improve the quality of ion implantation;

[0039] S03: forming a sacrificial material layer 23 of a first thickness, the sacrificial material layer 23 covering the active area 21 and the shallow trench isolation structure 22. The material of the sacrificial material layer 23 is the same as that of the shallow trench isolation structure 22, so that in the subsequent wet etching process, the sacrificial material layer 23 and the surface of the shallow trench isolation structure 22 can be locally etched simultaneously. If a protective layer 26 of a silicon oxide layer is formed in advance, the protective layer 26 will be integrated with the sacrificial material layer 23. The structure obtained after this step is as follows: Figure 7 As shown;

[0040] S04: Chemical mechanical polishing is performed on the sacrificial material layer 23 so that the thickness of the sacrificial material layer 23 is reduced to a second thickness. The difference between the first thickness and the second thickness is greater than or equal to 400 angstroms. That is, during the chemical mechanical polishing process, the thickness of the sacrificial material layer 23 removed is greater than or equal to 400 angstroms. The structure obtained after this step is as follows: Figure 8 As shown;

[0041] S05: Perform wet etching to remove the remaining sacrificial material layer 23. Since the material of the sacrificial material layer 23 is the same as that of the shallow trench isolation structure 22, the wet etching process has the same etching rate. After sufficient etching, the upper surface of the active area 21 and the upper surface of the shallow trench isolation structure 22 can be made flush, that is, the original height difference between the shallow trench isolation structure 22 and the active area 21 has disappeared, and no pits or other defects will be formed around the shallow trench. The structure obtained after this step is as follows: Figure 9 As shown;

[0042] S06: forming a gate oxide layer 24 and a gate polysilicon layer 25 on the upper surface of the active area 21 in sequence; preferably, the gate oxide layer 24 is formed by a dry oxygen thermal oxidation process, and the obtained structure is as follows: Figure 10 As shown, the gate polysilicon layer 25 is then formed using a process including but not limited to vapor deposition, and the resulting structure is as shown Figure 11 shown.

[0043] The present invention utilizes an improved process design, sequentially employing chemical mechanical polishing (CMP) and wet etching to remove the sacrificial material layer. This process eliminates the height difference between the shallow trench isolation structure and the active area surface, effectively preventing the formation of pits around the shallow trench isolation structure and localized device conduction, thereby improving device performance. It is also important to note that the present invention utilizes both CMP and wet etching for surface planarization, which effectively avoids damage to the active area compared to a single CMP process, thereby improving production yield.

[0044] In a preferred example, the materials of the shallow trench isolation structure 22 and the sacrificial material layer 23 are both silicon oxide layers, and the process for forming the shallow trench isolation structure 22 and the sacrificial material layer 23 is preferably a chemical vapor deposition process, because the chemical vapor deposition process has the advantage of a fast growth rate, which helps to shorten the process time and improve production efficiency.

[0045] The thickness of the sacrificial material layer 23 is a key parameter in this embodiment. If the initial parameter is too small, it is difficult to achieve a good chemical mechanical planarization effect. If it is too large, it will not only extend the process time but also affect the subsequent planarization effect. The inventors have found through extensive experiments that, preferably, the first thickness is 800 angstroms to 1200 angstroms (including the endpoint values, and when describing numerical ranges in this specification, unless otherwise specified, all include the endpoint values), and the second thickness is 300 angstroms to 600 angstroms. Optimally, the first thickness is 1000 angstroms and the second thickness is 500 angstroms, that is, the thickness of the sacrificial material layer 23 removed by chemical mechanical polishing is 500 angstroms.

[0046] In a preferred example, the thickness of the gate oxide layer 24 is 200 angstroms to 500 angstroms.

[0047] In a preferred example, the gate polysilicon layer 25 is formed to have a thickness of 1000 angstroms to 2000 angstroms.

[0048] According to different device requirements, the semiconductor process method may further include removing the gate oxide layer and gate polysilicon layer on the surface of the shallow trench isolation structure, and then forming an extraction electrode. Since this part is not the core of the present invention, it will not be expanded one by one.

[0049] The present invention also provides a semiconductor device, fabricated according to the semiconductor process method described in any of the aforementioned embodiments. As can be seen from the foregoing, the semiconductor device provided by the present invention includes at least spaced active regions and shallow trench isolation structures located between the active regions. Well regions are formed within the active regions, and a gate oxide layer and a gate polysilicon layer are formed on the surfaces of the active regions. Due to the fabrication method described above, the semiconductor device fabricated by the present invention can effectively avoid the formation of pits around the shallow trench isolation structures, helping to prevent localized conduction of the device, thereby significantly improving device performance.

[0050] In summary, the present invention provides a semiconductor process method for eliminating shallow trench pits, comprising the steps of: providing a substrate, the substrate comprising a plurality of spaced active areas and a shallow trench isolation structure located in the middle of the active areas, the upper surface of the shallow trench isolation structure being higher than the upper surface of the active area; forming a well area in the active area; forming a sacrificial material layer of a first thickness, the sacrificial material layer covering the active area and the shallow trench isolation structure, the material of the sacrificial material layer being the same as the material of the shallow trench isolation structure; performing chemical mechanical polishing on the sacrificial material layer to reduce the thickness of the sacrificial material layer to a second thickness, the difference between the first thickness and the second thickness being greater than or equal to 400 angstroms; performing wet etching to remove the remaining sacrificial material layer, and making the upper surface of the active area flush with the upper surface of the shallow trench isolation structure; and forming a gate oxide layer and a gate polysilicon layer in sequence on the upper surface of the active area. The present invention utilizes an improved process design, first employing a chemical mechanical polishing process, followed by a wet etching process to remove the sacrificial material layer. This process eliminates the height difference between the shallow trench isolation structure and the active area surface, effectively preventing the formation of pits around the shallow trench isolation structure, thus avoiding partial conduction of the device and improving device performance. Therefore, the present invention effectively overcomes the shortcomings of the prior art and has high industrial application value.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A semiconductor process method for eliminating shallow trench pits, characterized in that: Including steps: Providing a substrate, the substrate comprising a plurality of active areas spaced apart and a shallow trench isolation structure located in the middle of the active areas, wherein the upper surface of the shallow trench isolation structure is higher than the upper surface of the active area; forming a protective layer on the surface of the active area, wherein the material of the protective layer is the same as that of the shallow trench isolation structure; Performing ion implantation and high-temperature annealing on the active region to form a well region in the active region; forming a sacrificial material layer of a first thickness, the sacrificial material layer covering the active area and the shallow trench isolation structure, the material of the sacrificial material layer being the same as that of the shallow trench isolation structure; performing chemical mechanical polishing on the sacrificial material layer so that the thickness of the sacrificial material layer is reduced to a second thickness, wherein the difference between the first thickness and the second thickness is greater than or equal to 400 angstroms; Performing wet etching to remove the remaining sacrificial material layer and make the upper surface of the active area flush with the upper surface of the shallow trench isolation structure; A gate oxide layer and a gate polysilicon layer are sequentially formed on the upper surface of the active area.

2. The semiconductor process method according to claim 1, wherein: The shallow trench isolation structure and the sacrificial material layer are both made of silicon oxide layer.

3. The semiconductor process method according to claim 2, wherein: The shallow trench isolation structure is formed by chemical vapor deposition.

4. The semiconductor process method according to claim 1, wherein: The protective layer is formed by thermal oxidation, and the thickness of the protective layer is 100 angstroms to 200 angstroms.

5. The semiconductor process method according to claim 1, wherein: The first thickness is 800 angstroms to 1200 angstroms, and the second thickness is 300 angstroms to 600 angstroms.

6. The semiconductor process method according to claim 5, wherein: The first thickness is 1000 angstroms, and the second thickness is 500 angstroms.

7. The semiconductor process method according to claim 1, wherein: The gate oxide layer is formed by dry oxygen thermal oxidation, and the thickness of the formed gate oxide layer is 200 angstroms to 500 angstroms.

8. The semiconductor process method according to claim 1, wherein: The gate polysilicon layer is formed by chemical vapor deposition, and the thickness of the formed gate polysilicon layer is 1000 angstroms to 2000 angstroms.

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