Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a semiconductor substrate, an interlayer dielectric layer formed on the semiconductor substrate, a contact structure in the interlayer dielectric layer, a top surface of the contact structure being lower than a top surface of the interlayer dielectric layer, and a protective layer on a surface of the contact structure, a top surface of the protective layer being lower than the top surface of the interlayer dielectric layer. The semiconductor structure and the forming method thereof can form the protective layer on the surface of the contact structure after partial etching, so that the metal atoms in the contact structure on the source and the drain can be prevented from migrating into the dielectric layer, the subsequent process can be affected, and the device reliability can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] As semiconductor technology has advanced to the 5-nanometer node, the process of creating contact structures on the gate (Contact Over Active Gate, COAG) has begun to be used. To avoid short circuits between the contact structures on the source and drain and the contact structures on the gate during the COAG process, the contact structures on the source and drain need to be partially etched so that their top surfaces are lower than the top surface of the gate structure, and then a dielectric layer is used to cover the contact structures on the source and drain.

[0003] However, metal atoms in the contact structures on the source and drain electrodes may migrate into the dielectric layer, damaging it and affecting subsequent processes. Therefore, it is necessary to provide a more efficient and reliable technical solution. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same, which can prevent metal atoms in the contact structure on the source and drain from migrating into the dielectric layer, affecting subsequent processes and reducing device reliability.

[0005] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate and an interlayer dielectric layer located on the semiconductor substrate; forming a contact structure penetrating the interlayer dielectric layer in the interlayer dielectric layer; partially etching the contact structure such that the top surface of the contact structure is lower than the top surface of the interlayer dielectric layer; and forming a protective layer on the surface of the contact structure, wherein the top surface of the protective layer is lower than the top surface of the interlayer dielectric layer.

[0006] In some embodiments of this application, the method for forming a protective layer on the surface of the contact structure includes: partially etching the contact structure so that the top surface of the contact structure is lower than the top surface of the interlayer dielectric layer, and then forming a trench in the interlayer dielectric layer to expose the contact structure; depositing a protective material layer on the surface of the interlayer dielectric layer, the trench sidewalls, and the surface using a chemical vapor deposition process, wherein the reaction temperature of the chemical vapor deposition process is 450 degrees Celsius to 600 degrees Celsius; forming the protective material layer on the surface of the contact structure in situ with the contact structure; and etching away the protective material layer on the surface of the interlayer dielectric layer and the trench sidewalls, wherein the etching gas of the etching process includes one of the reaction gases of the chemical vapor deposition process.

[0007] In some embodiments of this application, the material of the contact structure includes cobalt, and the material of the protective layer includes a titanium-cobalt alloy.

[0008] In some embodiments of this application, the reaction gas of the chemical vapor deposition process includes titanium tetrachloride and hydrogen; the etching gas of the etching process includes titanium tetrachloride.

[0009] In some embodiments of this application, the method for forming a protective layer on the surface of the contact structure includes: a plasma-enhanced chemical vapor deposition process.

[0010] In some embodiments of this application, the method of depositing a protective material layer on the surface of the interlayer dielectric layer, the trench sidewalls, and the surface using a chemical vapor deposition process includes: turning on the radio frequency, introducing titanium tetrachloride and hydrogen gas, wherein the titanium tetrachloride and hydrogen gas react to generate titanium metal, and the titanium metal is deposited on the surface of the interlayer dielectric layer, the trench sidewalls, and the surface to form a protective material layer.

[0011] In some embodiments of this application, the method for etching away the protective material layer on the surface of the interlayer dielectric layer and the trench sidewalls includes: turning off the radio frequency, stopping the introduction of hydrogen gas, continuing to introduce the titanium tetrachloride, and the titanium tetrachloride reacting with titanium metal to remove the protective material layer.

[0012] In some embodiments of this application, the semiconductor substrate includes a semiconductor substrate and fins integral with the semiconductor substrate, wherein a gate structure and source and drain electrodes located on both sides of the gate structure are formed on the surface of the fins.

[0013] In some embodiments of this application, the top surface of the contact structure is 2 to 20 nanometers lower than the top surface of the interlayer dielectric layer.

[0014] Another aspect of this application provides a semiconductor structure, comprising: a semiconductor substrate on which an interlayer dielectric layer is formed; a contact structure located in the interlayer dielectric layer, wherein the top surface of the contact structure is lower than the top surface of the interlayer dielectric layer; and a protective layer located on the surface of the contact structure, wherein the top surface of the protective layer is lower than the top surface of the interlayer dielectric layer.

[0015] In some embodiments of this application, the semiconductor substrate includes a semiconductor substrate and fins integral with the semiconductor substrate, wherein a gate structure and source and drain electrodes located on both sides of the gate structure are formed on the surface of the fins.

[0016] In some embodiments of this application, the material of the contact structure includes cobalt, and the material of the protective layer includes a titanium-cobalt alloy.

[0017] In some embodiments of this application, the top surface of the contact structure is 2 to 20 nanometers lower than the top surface of the interlayer dielectric layer.

[0018] The semiconductor structure and its formation method described in this application form a protective layer on the surface of the partially etched contact structure, which can prevent metal atoms in the contact structure on the source and drain from migrating into the dielectric layer, affecting subsequent processes and reducing device reliability. Attached Figure Description

[0019] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0020] Figures 1 to 10 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0022] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0023] As semiconductor process dimensions shrink, the distances between structures within semiconductor devices also decrease. To prevent short circuits between the source / drain contact structures and the gate contact structures during the COAG process due to insufficient spacing, the contact structures on the source and drain need to be partially etched so that their top surfaces are lower than the top surface of the gate structure. Then, a dielectric layer is used to cover the contact structures on the source and drain. However, metal atoms in the contact structures on the source and drain may migrate into the dielectric layer, damaging it and affecting subsequent processes.

[0024] To address the aforementioned issues, this application provides a semiconductor structure and its formation method, which forms a protective layer on the surface of the partially etched contact structure. This prevents metal atoms in the contact structure on the source and drain electrodes from migrating into the dielectric layer, affecting subsequent processes and reducing device reliability.

[0025] Figures 1 to 10This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings. It should be noted that this embodiment only uses a FinFET device as an exemplary embodiment to illustrate the technical solution of this application, but this is not a limitation on the solution of this application; the technical solution of this application can also be applied to other devices.

[0026] Embodiments of this application provide a method for forming a semiconductor structure, including: referencing Figures 1 to 3 A semiconductor substrate 110 and an interlayer dielectric layer 140 located on the semiconductor substrate 110 are provided; Reference Figure 4 A contact structure 150 is formed in the interlayer dielectric layer 140, penetrating the interlayer dielectric layer 140; Reference Figure 5 Partial etching of the contact structure 150 such that the top surface of the contact structure 150 is lower than the top surface of the interlayer dielectric layer 140; Reference Figures 6 to 8 A protective layer 160 is formed on the surface of the contact structure 150, and the top surface of the protective layer 160 is lower than the top surface of the interlayer dielectric layer 140.

[0027] refer to Figures 1 to 2 A semiconductor substrate 110 is provided, the semiconductor substrate 110 including a semiconductor substrate 101 and a fin 102 integral with the semiconductor substrate 101. A gate structure 130 and source and drain electrodes (not shown in the figure) located on both sides of the gate structure 130 are formed on the surface of the fin 102. An isolation structure 120 surrounding a portion of the fin 102 is also formed on the semiconductor substrate 110. Figure 2 yes Figure 1 A cross-sectional view along the plane containing the dashed line.

[0028] In some embodiments of this application, the material of the semiconductor substrate 101 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) combinations thereof. Furthermore, the semiconductor substrate 101 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of this application, the semiconductor substrate 101 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0029] In some embodiments of this application, the method of forming the fin 102 may include: growing an epitaxial layer on the semiconductor substrate 101; forming a patterned mask layer on the epitaxial layer; and using the patterned mask layer as a mask to etch the epitaxial layer and the semiconductor substrate 101 to form the fin 102. For example, etching may be performed using a dry etching process, a wet etching process, or a combination thereof. In some embodiments of this application, the mask layer may be a thin film comprising silicon oxide formed using a thermal oxidation process. In other embodiments of this application, the mask layer may be a thin film comprising silicon nitride formed using a low-pressure chemical vapor deposition (LPCVD) process or a plasma-enhanced CVD (PECVD) process.

[0030] refer to Figure 3 An interlayer dielectric layer 140 is formed on the surface of the semiconductor substrate 110. The top surface of the interlayer dielectric layer 140 is coplanar with the top surface of the gate structure 130.

[0031] In some embodiments of this application, the method of forming the interlayer dielectric layer 140 includes: forming an interlayer dielectric material layer on the surface of the semiconductor substrate 110 and the gate structure 130 using a chemical vapor deposition process; and polishing the interlayer dielectric material layer using a chemical mechanical polishing process so that the top surface of the interlayer dielectric material layer is coplanar with the top surface of the gate structure to form the interlayer dielectric layer 140.

[0032] In some embodiments of this application, the material of the interlayer dielectric layer 140 includes silicon oxide and the like.

[0033] refer to Figure 4 A contact structure 150 is formed in the interlayer dielectric layer 140, penetrating the interlayer dielectric layer 140. It should be noted that, although from... Figure 4 In view, the interlayer dielectric layer 140 is completely filled and replaced by the contact structure 150, but reference Figure 1 , Figure 4 Only Figure 1 The cross-sectional view along the dashed line shows the remaining portion of the interlayer dielectric layer 140 located on the surface of the isolation structure 120. For simplicity, a complete perspective view is not shown in this embodiment, but it should be understood that... Figures 2 to 10 All in Figure 1 The cross-sectional view is based on the three-dimensional drawing.

[0034] In some embodiments of this application, the method of forming the contact structure 150 includes: forming a patterned mask layer on the surface of the interlayer dielectric layer 140, the patterned mask layer defining the location of the contact structure; etching the interlayer dielectric layer 140 using the patterned mask layer as a mask to form a trench penetrating the interlayer dielectric layer 140; and filling the trench with a metallic material to form the contact structure 150.

[0035] In some embodiments of this application, the contact structure 150 is made of cobalt. The contact structure 150 is electrically connected to the source and drain (not shown) in the fins 102 on both sides of the gate structure 130.

[0036] refer to Figure 5 The contact structure 150 is partially etched so that the top surface of the contact structure 150 is lower than the top surface of the interlayer dielectric layer 140. After partially etching the contact structure 150 so that the top surface of the contact structure 150 is lower than the top surface of the interlayer dielectric layer 140, a trench 151 is formed in the interlayer dielectric layer 140 to expose the contact structure 150.

[0037] In some embodiments of this application, after partial etching, the top surface of the contact structure 150 is 2 nanometers to 20 nanometers lower than the top surface of the interlayer dielectric layer 140.

[0038] In some embodiments of this application, the method for partially etching the contact structure 150 includes wet etching or dry etching, etc.

[0039] refer to Figures 6 to 8 A protective layer 160 is formed on the surface of the contact structure 150, and the top surface of the protective layer 160 is lower than the top surface of the interlayer dielectric layer 140. The protective layer 160 can protect the contact structure 150 and prevent metal atoms in the contact structure 150 from migrating to the subsequently formed dielectric layer, which would affect subsequent processes and reduce device reliability.

[0040] refer to Figure 6 A protective material layer 160a is deposited on the surface of the interlayer medium layer 140, the sidewalls of the trench 151, and the surface using a chemical vapor deposition process. The reaction temperature of the chemical vapor deposition process is 450 degrees Celsius to 600 degrees Celsius.

[0041] In some embodiments of this application, the reaction gases of the chemical vapor deposition process include titanium tetrachloride and hydrogen.

[0042] In some embodiments of this application, the chemical vapor deposition process is a plasma-enhanced chemical vapor deposition process.

[0043] In some embodiments of this application, the method of depositing a protective material layer 160a on the surface of the interlayer dielectric layer 140, the sidewalls of the trench 151, and the surface using a chemical vapor deposition process includes: turning on the radio frequency, introducing the reactive gases titanium tetrachloride and hydrogen, and the protective gas argon, wherein the titanium tetrachloride and hydrogen react to generate titanium metal, and the titanium metal is deposited on the surface of the interlayer dielectric layer 140, the sidewalls of the trench 151, and the surface to form the protective material layer 160a.

[0044] In some embodiments of this application, the reaction equation for the reaction of titanium tetrachloride and hydrogen to produce titanium metal includes: TiCl4 + H2 + Ar = TiCl x +HCl +Ar; TiCl x +H2=Ti+HCl.

[0045] refer to Figure 7 The protective material layer 160a on the surface of the contact structure 150 forms the protective layer 160 in situ with the contact structure 150. Under high temperature conditions, the materials of the contact structure 150 and the protective material layer 160a form the material of the protective layer 160 in situ.

[0046] In some embodiments of this application, the material of the contact structure 150 includes cobalt, and the material of the protective layer 160 includes a titanium-cobalt alloy.

[0047] refer to Figure 8 The protective material layer 160a on the surface of the interlayer dielectric layer 140 and the sidewall of the trench 151 is removed by etching, wherein the etching gas in the etching process includes one of the reaction gases in the chemical vapor deposition process.

[0048] In some embodiments of this application, the etching gas in the etching process includes titanium tetrachloride.

[0049] In some embodiments of this application, the method of etching away the protective material layer 160a on the surface of the interlayer dielectric layer 140 and the sidewall of the trench 151 includes: turning off the radio frequency, stopping the introduction of hydrogen gas, continuing to introduce the titanium tetrachloride, and the titanium tetrachloride reacting with titanium metal to remove the protective material layer.

[0050] In some embodiments of this application, the reaction equation for the reaction of titanium tetrachloride with titanium metal to remove the protective material layer includes: TiCl4 + Ti = TiCl x After turning off the radio frequency and stopping the hydrogen supply, the heat supply is maintained, and titanium tetrachloride and titanium metal continue to react at high temperature to remove the titanium metal.

[0051] In the method for forming the protective layer 160 described in this application embodiment, the deposition of the protective material layer, the in-situ formation of the protective layer, and the removal of excess protective material layer are completed in the same reaction chamber. This saves process steps and only requires adjusting the switch of radio frequency energy and the introduction of hydrogen. The process is simple and easy to implement.

[0052] Table 1

[0053] Before the reaction Deposition reaction Etching reaction Titanium tetrachloride Access Access Access hydrogen Access Access closure Argon Access Access Access Radio frequency closure Open closure thermal energy Open Open Open

[0054] Table 1 shows the reaction environment at each stage of the method for forming the protective layer 160 described in the embodiments of this application. All steps can be completed in the same reaction chamber, saving process steps. Moreover, only the switching of radio frequency energy and the introduction of hydrogen need to be adjusted during the reaction process, making the process simple and easy to implement.

[0055] refer to Figure 9 A dielectric layer 170 is formed on the surface of the protective layer 160 and the surface of the gate structure 130.

[0056] In some embodiments of this application, the method for forming the dielectric layer 170 includes chemical vapor deposition or physical vapor deposition processes, etc.

[0057] In some embodiments of this application, the material of the dielectric layer 170 includes silicon oxide and the like.

[0058] refer to Figure 10 A second contact structure 180 and a third contact structure 190 are formed in the dielectric layer 170, respectively penetrating the dielectric layer 170 and electrically connecting the gate structure 130 and the protective layer 160. The protective layer 160 is also conductive and can electrically connect the third contact structure 190 and the contact structure 150. Therefore, the protective layer 160 does not need to be removed.

[0059] In some embodiments of this application, the material of the second contact structure 180 is tungsten, copper, cobalt, etc.

[0060] In some embodiments of this application, the material of the third contact structure 190 is tungsten, copper, cobalt, etc.

[0061] The semiconductor structure formation method described in this application forms a protective layer on the surface of the partially etched contact structure, which can prevent metal atoms in the contact structure on the source and drain from migrating into the dielectric layer, affecting subsequent processes and reducing device reliability.

[0062] Embodiments of this application also provide a semiconductor structure, referencing Figure 10The semiconductor structure includes: a semiconductor substrate 110 on which an interlayer dielectric layer 140 is formed; a contact structure 150 located in the interlayer dielectric layer 140, the top surface of the contact structure 150 being lower than the top surface of the interlayer dielectric layer 140; and a protective layer 160 located on the surface of the contact structure 150, the top surface of the protective layer 160 being lower than the top surface of the interlayer dielectric layer 140.

[0063] refer to Figure 1 and Figure 10 The semiconductor substrate 110 includes a semiconductor substrate 101 and a fin 102 integral with the semiconductor substrate 101. A gate structure 130 and source and drain electrodes (not shown in the figure) located on both sides of the gate structure 130 are formed on the surface of the fin 102. An isolation structure 120 surrounding a portion of the fin 102 is also formed on the semiconductor substrate 110. Figure 10 yes Figure 1 A cross-sectional view along the plane containing the dashed line.

[0064] In some embodiments of this application, the material of the semiconductor substrate 101 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) combinations thereof. Furthermore, the semiconductor substrate 101 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of this application, the semiconductor substrate 101 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0065] Continue to refer to Figure 1 and Figure 10 An interlayer dielectric layer 140 is formed on the surface of the isolation structure 120, and the top surface of the interlayer dielectric layer 140 is coplanar with the top surface of the gate structure 130. It should be noted that, although... Figure 10 The interlayer dielectric layer 140 is not shown in the diagram, but it is referenced in the diagram. Figure 1 , Figure 10 Only Figure 1 The cross-sectional view along the dashed line shows the interlayer dielectric layer 140 located on the surface of the isolation structure 120. For simplicity, a complete perspective view is not shown in this embodiment, but it should be understood that... Figure 10 Is Figure 1 The cross-sectional view is based on the three-dimensional drawing.

[0066] In some embodiments of this application, the material of the interlayer dielectric layer 140 includes silicon oxide and the like.

[0067] refer to Figure 10 A contact structure 150 is formed in the interlayer dielectric layer 140. The top surface of the contact structure 150 is lower than the top surface of the interlayer dielectric layer 140.

[0068] In some embodiments of this application, the contact structure 150 is made of cobalt. The contact structure 150 is electrically connected to the source and drain (not shown) in the fins 102 on both sides of the gate structure 130.

[0069] In some embodiments of this application, the top surface of the contact structure 150 is 2 to 20 nanometers lower than the top surface of the interlayer dielectric layer 140.

[0070] Continue to refer to Figure 10 A protective layer 160 is formed on the surface of the contact structure 150, and the top surface of the protective layer 160 is lower than the top surface of the interlayer dielectric layer 140. The protective layer 160 can protect the contact structure 150 and prevent metal atoms in the contact structure 150 from migrating to the subsequently formed dielectric layer, which would affect subsequent processes and reduce device reliability.

[0071] In some embodiments of this application, the material of the contact structure 150 includes cobalt, and the material of the protective layer 160 includes a titanium-cobalt alloy.

[0072] Continue to refer to Figure 10 A dielectric layer 170 is formed on the surface of the protective layer 160 and the surface of the gate structure 130.

[0073] In some embodiments of this application, the material of the dielectric layer 170 includes silicon oxide and the like.

[0074] Continue to refer to Figure 10 A second contact structure 180 and a third contact structure 190 are formed in the dielectric layer 170, respectively penetrating the dielectric layer 170 and electrically connecting the gate structure 130 and the protective layer 160. The protective layer 160 is also conductive and can electrically connect the third contact structure 190 and the contact structure 150.

[0075] In some embodiments of this application, the material of the second contact structure 180 is tungsten, copper, cobalt, etc.

[0076] In some embodiments of this application, the material of the third contact structure 190 is tungsten, copper, cobalt, etc.

[0077] The semiconductor structure described in this application forms a protective layer on the surface of the partially etched contact structure, which can prevent metal atoms in the contact structure on the source and drain from migrating into the dielectric layer, affecting subsequent processes and reducing device reliability.

[0078] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0079] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0080] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. In contrast, the term "directly" means without intermediate elements.

[0081] It should also be understood that the terms “comprising,” “including,” “including,” or “comprise”, when used in this application, indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0082] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0083] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate and an interlayer dielectric layer located on the semiconductor substrate are provided; A contact structure penetrating the interlayer dielectric layer is formed in the interlayer dielectric layer; Partial etching of the contact structure so that the top surface of the contact structure is lower than the top surface of the interlayer dielectric layer to form a trench in the interlayer dielectric layer that exposes the contact structure; A protective layer is formed on the surface of the contact structure, the top surface of the protective layer being lower than the top surface of the interlayer dielectric layer. The method for forming the protective layer on the surface of the contact structure includes: depositing a protective material layer on the surface of the interlayer dielectric layer, the trench sidewalls, and the surface using a chemical vapor deposition process, wherein the protective material layer on the surface of the contact structure forms the protective layer in situ with the contact structure. The protective material layer on the surface of the interlayer dielectric layer and the sidewalls of the trench is removed by etching.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The reaction temperature of the chemical vapor deposition process is 450 degrees Celsius to 600 degrees Celsius; the etching gas of the etching process includes one of the reaction gases of the chemical vapor deposition process.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the contact structure includes cobalt, and the material of the protective layer includes a titanium-cobalt alloy.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The reaction gases in the chemical vapor deposition process include titanium tetrachloride and hydrogen; the etching gases in the etching process include titanium tetrachloride.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, Methods for forming a protective layer on the surface of the contact structure include: plasma-enhanced chemical vapor deposition process.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, A method for depositing a protective material layer on the surface of the interlayer dielectric layer, the trench sidewalls, and the surface using chemical vapor deposition includes: turning on the radio frequency, introducing titanium tetrachloride and hydrogen gas, wherein the titanium tetrachloride and hydrogen gas react to generate titanium metal, and the titanium metal is deposited on the surface of the interlayer dielectric layer, the trench sidewalls, and the surface to form a protective material layer.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for etching away the protective material layer on the surface of the interlayer dielectric layer and the trench sidewalls includes: turning off the radio frequency, stopping the introduction of hydrogen gas, continuing to introduce the titanium tetrachloride, and the titanium tetrachloride reacting with titanium metal to remove the protective material layer.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The semiconductor substrate includes a semiconductor substrate and fins integral with the semiconductor substrate. A gate structure and source and drain electrodes located on both sides of the gate structure are formed on the surface of the fins.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The top surface of the contact structure is 2 to 20 nanometers lower than the top surface of the interlayer dielectric layer.

10. A semiconductor structure formed using the semiconductor structure formation method according to any one of claims 1 to 9, characterized in that, include: A semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate; A contact structure is located in the interlayer dielectric layer, and the top surface of the contact structure is lower than the top surface of the interlayer dielectric layer. A protective layer is located on the surface of the contact structure, and the top surface of the protective layer is lower than the top surface of the interlayer dielectric layer.

11. The semiconductor structure as claimed in claim 10, characterized in that, The semiconductor substrate includes a semiconductor substrate and fins integral with the semiconductor substrate. A gate structure and source and drain electrodes located on both sides of the gate structure are formed on the surface of the fins.

12. The semiconductor structure as claimed in claim 10, characterized in that, The material of the contact structure includes cobalt, and the material of the protective layer includes a titanium-cobalt alloy.

13. The semiconductor structure as described in claim 10, characterized in that, The top surface of the contact structure is 2 to 20 nanometers lower than the top surface of the interlayer dielectric layer.

Images