Semiconductor structure and its formation method

Abstract

A semiconductor structure and its formation method are disclosed. The formation method includes: providing a substrate; forming a pattern memory layer on the substrate, the pattern memory layer having a first trench, a second trench, and a third trench with parallel extending directions, the first trench, the second trench, and the third trench being formed using different photomasks; forming a core material layer, the core material layer filling the first trench, the second trench, and the third trench; patterning the core material layer to form a core layer, the core layer having isolation openings; filling the isolation openings to form an isolation layer, the top of the isolation layer being flush with the top of the core layer; removing the core layer to form a fourth trench, the fourth trench corresponding to a metal interconnect layer. Since the cutting of multiple first trenches, second trenches, and third trenches can be completed in the same process step, the method can enable the processing of smaller patterns in subsequent processing steps, even when the pattern size is close to the limits of device parameters.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] As semiconductor manufacturing technology becomes increasingly sophisticated, integrated circuits are undergoing significant changes. The number of components integrated on a single chip has increased from tens or hundreds initially to millions today. To meet circuit density requirements, semiconductor integrated circuit chip fabrication processes utilize batch processing techniques to form various types of complex devices on a substrate and interconnect them using interconnect structures to enable them to have complete electronic functions. Currently, most methods employ ultra-low k interlayer dielectric layers between wires as the dielectric material to isolate the metal interconnects. The interconnect structures provide wiring between the devices on the IC chip and the entire package. In this technology, devices such as field-effect transistors (FETs) are first formed on the surface of the semiconductor substrate, and then the interconnect structures are formed in the back-end of line (BEOL) process of integrated circuit manufacturing.

[0003] As predicted by Moore's Law, the continuous shrinking of semiconductor substrate dimensions and the formation of more transistors on semiconductor substrates to improve device performance have made interconnect structures an inevitable choice for connecting transistors. However, with the miniaturization and increasing integration of components, the number of conductor connections in circuits is constantly increasing. The formation quality of interconnect structures has a significant impact on the performance of back-end of line (BEOL) circuits, and in severe cases, it can affect the normal operation of semiconductor devices.

[0004] Therefore, how to form smaller interconnect structures in the back-end process has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the electrical performance of the semiconductor structure.

[0006] To address the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising:

[0007] A substrate is provided, the substrate including a metal interconnect layer;

[0008] A pattern memory layer is formed on the substrate. The pattern memory layer has a first trench, a second trench, and a third trench. The extension directions of the first trench, the second trench, and the third trench are parallel to each other, and the first trench, the second trench, and the third trench are formed using different photomasks.

[0009] A core material layer is formed, which fills the first trench, the second trench, and the third trench;

[0010] The core material layer is graphically represented to form a core layer, and the core layer has an isolation opening;

[0011] The isolation opening is filled to form an isolation layer, the top of which is at least flush with the top of the core layer;

[0012] The core layer is removed to form a fourth trench, which corresponds to the metal interconnect layer.

[0013] Accordingly, embodiments of the present invention provide a semiconductor structure, including:

[0014] The substrate includes a metal interconnect layer;

[0015] Both the graphics memory layer and the isolation layer are disposed on the substrate, and the top of the isolation layer is flush with the top of the graphics memory layer. The graphics memory layer and the isolation layer form a fourth trench, which corresponds to the metal interconnect layer, and the extension direction of each fourth trench is the same.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0017] In the semiconductor structure formation method provided in this embodiment of the invention, a pattern memory layer is first formed on a substrate. Then, a first trench, a second trench, and a third trench are formed on the pattern memory layer using different photomasks, wherein the extension direction of the first trench is parallel to the extension direction of the second and third trenches. Next, a core material layer is filled into the first trench, the second trench, and the third trench. Then, the core material layer is patterned to form a core layer with isolation openings. Next, the isolation openings are filled to form an isolation layer. Finally, the core layer is removed to form a fourth trench, which corresponds to a metal interconnect layer in the substrate. As can be seen, the semiconductor structure formation method provided in this embodiment of the invention forms a first trench, a second trench, and a third trench on a pattern memory layer using a multi-stage photolithography process with different photomasks. Then, an isolation layer is used to simultaneously adjust the trench shapes of the first, second, and third trenches to form a fourth trench that meets the size requirements. Thus, when etching downwards using the medium composed of the pattern memory layer and the isolation layer surrounding the fourth trench as a mask, a trench with the same morphology as the fourth trench can be formed on the substrate. Since the fourth trench corresponds to the metal interconnect layer in the substrate, the trench formed on the substrate can expose the metal interconnect layer. In this way, by subsequently forming a metal layer that can contact the metal interconnect layer in the trench of the substrate, electrical connection between the metal layer and the metal interconnect layer can be achieved. The semiconductor structure formation method provided in this embodiment of the invention simplifies the process flow because the adjustment of the pattern state of multiple first trenches, second trenches, and third trenches can be completed in the same process step. On the other hand, by forming multiple first trenches, second trenches, and third trenches using three photomasks, and by forming isolation layers in the first trenches, second trenches, and third trenches to adjust the trench shape, it is possible to process smaller patterns in the back-end processing even when the pattern size is close to the limit of the equipment parameters, thereby ensuring processing quality while reducing production costs. Attached Figure Description

[0018] Figures 1 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0019] With the miniaturization and increasing integration of components, the number of conductor connections in circuits is constantly increasing. This requires the pattern size of metal interconnects to become smaller and smaller, and the pattern size is getting closer and closer to the limit of photolithography equipment. How to form smaller interconnect structures in the back-end process has become an urgent technical problem to be solved.

[0020] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate including a metal interconnect layer; forming a pattern memory layer on the substrate, the pattern memory layer having a first trench, a second trench, and a third trench, the extension direction of the first trench being parallel to the extension directions of the second and third trenches, the first trench, the second trench, and the third trench being formed using different photomasks; forming a core material layer filling the first trench, the second trench, and the third trench; patterning the core material layer to form a core layer, the core layer having an isolation opening; filling the isolation opening to form an isolation layer, the top of the isolation layer being at least flush with the top of the core layer; removing the core layer to form a fourth trench corresponding to the metal interconnect layer.

[0021] In the semiconductor structure formation method provided in this embodiment of the invention, a first trench, a second trench, and a third trench are formed on a pattern memory layer using a multi-pass photolithography process with different photomasks. Then, an isolation layer is used to simultaneously adjust the trench shapes of the first trench, the second trench, and the third trench to form a fourth trench that meets the size requirements. Thus, when etching downwards using the medium composed of the pattern memory layer and the isolation layer surrounding the fourth trench as a mask, a trench with the same morphology as the fourth trench can be formed on the substrate. Since the fourth trench corresponds to the metal interconnect layer in the substrate, the trench formed on the substrate can expose the metal interconnect layer. In this way, by subsequently forming a metal layer that can contact the metal interconnect layer in the trench of the substrate, electrical connection between the metal layer and the metal interconnect layer can be achieved. The semiconductor structure formation method provided in this embodiment of the invention simplifies the process flow because the adjustment of the pattern state of multiple first trenches, second trenches, and third trenches can be completed in the same process step. On the other hand, by forming multiple first trenches, second trenches, and third trenches using three photomasks and by forming isolation layers in the first trenches, second trenches, and third trenches to adjust the trench shape, it is possible to process smaller patterns in the back-end processing even when the pattern size is close to the limits of the equipment parameters, thereby ensuring processing quality while reducing production costs.

[0022] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figures 1 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0024] Please refer to Figure 1 and Figure 2 , Figure 1A top view of a semiconductor structure. Figure 2 yes Figure 1 The sectional view obtained by cutting along the AA' direction.

[0025] As shown in the figure, a substrate 100 is provided, the substrate 100 including a metal interconnect layer (not shown in the figure);

[0026] The substrate 100 is used to provide a process platform for the fabrication process. Semiconductor devices such as transistors and capacitors can be formed in the substrate 100, and functional structures such as resistive structures and conductive structures can also be formed in the substrate.

[0027] The substrate 100 includes a metal interconnect layer. After the metal layer is subsequently formed on the substrate 100, the metal interconnect layer is used to realize electrical connection with the metal layer in the back end of line (BEOL) process, thereby enabling the semiconductor device (e.g., transistor) or functional structure to be electrically connected to external circuits or other interconnect structures.

[0028] The substrate further includes a dielectric layer 101 that covers the metal interconnect layer. The dielectric layer 101 is used to achieve electrical isolation between adjacent interconnects of the metal layer in the back end of line (BEOL) process.

[0029] Continue to combine Figure 1 refer to Figure 2 A pattern memory layer 104 is formed on the substrate. The pattern memory layer 104 has a first trench 107, a second trench 110 and a third trench 113. The extension directions of the first trench 107, the second trench and the third trench 113 are parallel to each other. The first trench 107, the second trench 110 and the third trench 113 are formed using different photomasks.

[0030] It is easy to understand that as the integration density of semiconductor devices increases, the number of metal interconnects in the circuit also increases, resulting in smaller and smaller linewidths for the metal interconnect patterns. Due to process limitations, multiple patterns cannot be formed using a single photomask. To ensure pattern quality and prevent multiple adjacent patterns from connecting after simultaneous exposure, the first trench 107, the second trench 110, and the third trench 113 are formed using different photomasks; that is, the three trenches are formed through three photolithography and etching processes. In this embodiment, the first photolithography and etching process forms the first trench 107; the second photolithography and etching process forms the second trench 110; and the third photolithography and etching process forms the third trench 113.

[0031] The graphics memory layer 104 is used to provide a support platform for the three photomasks, so that the patterns of the three photomasks are eventually transferred to the graphics memory layer respectively.

[0032] In this embodiment, the material of the graphics memory layer 104 is silicon oxide. In other embodiments, the material of the graphics memory layer can be one or a combination of silicon oxide, silicon nitride, and silicon oxynitride.

[0033] Specifically, please combine Figure 2 refer to Figures 3-7 The steps for forming the graphics memory layer 104 include:

[0034] First, the first trench 107 is formed.

[0035] Specifically, such as Figure 3 and Figure 4 As shown, a pattern memory material layer 104a is formed on the substrate 100;

[0036] A patterned first photoresist layer 106 is formed on the pattern memory material layer 104a;

[0037] The pattern memory material layer 104a is etched using the first photoresist layer 106 as a mask to form the first trench 107;

[0038] In this embodiment, the first antireflective material layer 105 is etched using the first photoresist layer 106 as a mask to form a first reflective layer (not shown in the figure). Then, the pattern memory material layer 104a is etched using the first photoresist and the first reflective layer as masks to form a first trench 107.

[0039] Next, the second trench 110 is formed.

[0040] like Figure 5 and Figure 6 As shown, a patterned second photoresist layer 109 is formed on the pattern memory material layer;

[0041] The pattern memory material layer is etched using the second photoresist layer 109 as a mask to form the second trench 110;

[0042] In this embodiment, before forming the second photoresist layer, a second anti-reflective material layer is first formed to fill the first trench 107 and cover the pattern memory material layer. The second anti-reflective material layer 108 is etched using the second photoresist layer 109 as a mask to form a second reflective layer (not shown in the figure). Then, the pattern memory material layer 104a is etched using the second photoresist layer 109 and the second reflective layer as masks to form the second trench 110.

[0043] Then, the third trench 113 is formed.

[0044] like Figure 2 and Figure 7As shown, a patterned third photoresist layer 112 is formed on the pattern memory material layer 104;

[0045] The pattern memory material layer is etched using the third photoresist layer 112 as a mask to form the third trench 113.

[0046] In this embodiment, before forming the third photoresist layer 112, a third anti-reflective material layer 111 is first formed to fill the first trench 107 and the second trench 110 and cover the pattern memory material layer. The third anti-reflective material layer 111 is etched using the third photoresist layer 112 as a mask to form a third reflective layer (not shown in the figure). Then, the pattern memory material layer 104a is etched using the third photoresist layer 112 and the third reflective layer as masks to form a third trench 113.

[0047] The first trench 107, the second trench 110, and the third trench 113 provide space for the subsequent formation of the core material layer.

[0048] refer to Figures 8-13 ,in, Figure 9 and Figure 11 This is a top view schematic diagram of the semiconductor structure according to an embodiment of the present invention; Figure 10 It is along Figure 9 A cross-sectional view along the AA' direction; Figure 13 It is along Figure 11 A cross-sectional view along the BB' direction.

[0049] A core material layer 114a is formed, which fills the first trench, the second trench and the third trench respectively;

[0050] like Figure 8 As shown, in this embodiment, a deposition process is used to form a core material layer that fills the first trench and the second trench. To ensure that the core material layer completely fills the first trench, the second trench, and the third trench, and to better form the morphology of the core material layer, the core material layer 114a also covers the graphics memory layer 104. Next, the core material layer 114a is planarized until the graphics memory layer is exposed. Of course, in other embodiments, the core material layer may only fill the first trench, the second trench, and the third trench.

[0051] Next, refer to Figures 11-13 The core material layer 114a is graphically represented to form an isolation opening 115, thus forming the core layer 114.

[0052] It is easy to understand that, taking the first trench as an example, in the actual process, due to process limitations, if the distance between two adjacent first trenches is too small along the extension direction of the first trench, it is impossible to directly form two first trenches by photolithography. Therefore, in order to form a smaller-sized first trench, a complete trench is first formed, and then the complete trench is cut off. Therefore, in this embodiment of the invention, after forming the first trench, the second trench, and the third trench, it is also necessary to fill the three trenches with a core material layer. Figure 9 ) and graphical ( Figure 11 ( ), to form a pattern that meets the process requirements.

[0053] The core layer 114 is used to provide space for the subsequent formation of the fourth trench.

[0054] In this embodiment, the core layer 114 is made of polycrystalline silicon. In other embodiments, the core layer may also be made of one or a combination of at least two of amorphous carbon, photoresist, organic dielectric layer material, and dielectric antireflective coating material.

[0055] It should be noted that, in the extension direction of the core layer 114, through the isolation opening 115 (shown in...) Figure 11 The continuous core material layer is cut off, so that the complete core material layer 114a is dispersed into several core layers of different lengths, thereby reducing the size of the core layer in the direction of core layer extension to meet the process size requirements.

[0056] In this embodiment, the formed isolation opening 115 simultaneously cuts off the core material layer filling the first trench, the second trench and the third trench in one process step, thereby simplifying the processing technology.

[0057] Specifically, such as Figure 12 and Figure 13 As shown, the core material layer 114a is graphically represented, and the steps to form the core layer 114 include:

[0058] A shielding layer 117 is formed on the core material layer 114a, and the shielding layer 117 exposes a portion of the core material layer 114a;

[0059] Using the shielding layer 117 as a mask, the core material layer 114a is etched to form an isolation opening 115 (shown in...). Figure 11 ), with the remaining core material layer as the core layer 114.

[0060] It should be noted that the exposed portion of the core material layer in the shielding layer refers to the exposed portion of the shielding layer. Figure 11The core material layer at the location where the isolation opening 115 is formed is a shielding layer used to shield the core material layer area that does not need to be etched, so that when etching downward with the shielding layer as a mask, the formed isolation opening 115 can meet the morphological requirements.

[0061] Next, as Figures 14-16 As shown, the isolation opening is filled to form an isolation layer 116, the top of which is at least flush with the top of the core layer; wherein, Figure 16 It is a top view; Figure 15 yes Figure 16 A cross-sectional view along the BB' direction.

[0062] The isolation layer 116 is used to fill the isolation opening. In the direction of extension along the core layer 114, the isolation layer 116 contacts the adjacent core layer 114 respectively to ensure that after the core layer is removed to form the fourth trench, the isolation layer can cut the fourth trench, so that the fourth trench formed can meet the morphological requirements. When etching downward with the sidewalls around the fourth trench as a mask, the final pattern formed can meet the size and morphological requirements.

[0063] The material of the isolation layer 116 is different from that of the core layer to ensure that the materials of the isolation layer and the core layer have different etching rates.

[0064] It should be noted that the isolation layer being at least flush with the top of the core layer means that the top surface of the isolation layer can be flush with the top surface of the core layer, or the top surface of the isolation layer is higher than the top surface of the core layer.

[0065] Specifically, such as Figure 14 and Figure 15 As shown, in this embodiment, the steps for forming the isolation layer 116 include:

[0066] An isolation material layer 116a is formed, which fills the isolation opening and covers the core layer 114 and the graphics memory layer 104.

[0067] The isolation material layer 116a is planarized to form an isolation layer 116, the top surface of which is flush with the top surface of the core layer 114.

[0068] When planarizing the isolation material layer 116a to form the isolation layer 116, the core layer is used as the etching stop layer.

[0069] Combination Figure 16 refer to Figure 17 and Figure 18 ,in, Figure 17 It is along Figure 16 A cross-sectional view along the BB' direction. Figure 18 It is along Figure 16 A cross-sectional view along the AA' direction.

[0070] Remove the core layer 114 (shown in) Figure 10 In the middle), a fourth trench 118 is formed, the fourth trench 114 corresponding to the metal interconnect layer (not shown in the figure).

[0071] It should be noted that the fourth trench corresponds to the metal interconnect layer, meaning that when the substrate is etched downwards using the sidewalls around the fourth trench as a mask, the metal interconnect layer inside the substrate can be exposed.

[0072] The process for removing the core layer can be either a dry etching process or a wet etching process, as long as the core layer can be completely removed.

[0073] As can be seen, the semiconductor structure formation method provided in this embodiment of the invention forms a first trench, a second trench, and a third trench on a pattern memory layer using a multi-stage photolithography process with different photomasks. Then, an isolation layer is used to simultaneously adjust the trench shapes of the first, second, and third trenches to form a fourth trench that meets the size requirements. Thus, when etching downwards using the medium composed of the pattern memory layer and the isolation layer surrounding the fourth trench as a mask, a trench with the same morphology as the fourth trench can be formed on the substrate. Since the fourth trench corresponds to the metal interconnect layer in the substrate, the trench formed on the substrate can expose the metal interconnect layer. In this way, by subsequently forming a metal layer that can contact the metal interconnect layer in the trench of the substrate, electrical connection between the metal layer and the metal interconnect layer can be achieved. The semiconductor structure formation method provided in this embodiment of the invention simplifies the process flow because the adjustment of the pattern state of multiple first trenches, second trenches, and third trenches can be completed in the same process step. On the other hand, by forming multiple first trenches, second trenches, and third trenches using three photomasks, and by forming isolation layers in the first trenches, second trenches, and third trenches to adjust the trench shape, it is possible to process smaller patterns in the back-end processing even when the pattern size is close to the limit of the equipment parameters, thereby ensuring processing quality while reducing production costs.

[0074] like Figures 18-21 As shown, after removing the core layer to form the fourth trench 118, the system further includes:

[0075] Using the pattern memory layer 104 and the isolation layer 116 as masks, the dielectric layer 101 of the substrate exposed by the fourth trench 118 is etched to form the fifth trench (shown in...). Figure 21 The fifth trench is used to form a metal layer, and the fifth trench corresponds to the metal interconnect layer below.

[0076] It should be noted that the fifth trench corresponds to the metal interconnect layer, meaning that the fifth trench can expose the metal interconnect layer in the substrate. After a metal layer is formed in the fifth trench, the metal layer can be electrically connected to the metal interconnect layer.

[0077] Of course, in order to improve the accuracy of transferring the pattern onto the substrate and avoid premature mask consumption when using the sidewalls (pattern memory layer and isolation layer) around the fourth trench as a mask, which would cause a decrease in pattern accuracy, the semiconductor structure formation method provided in this embodiment of the invention further includes, before forming the pattern memory layer 104: forming a mask layer 102 (shown in...) on the substrate. Figure 18 (in the middle); when mask layer 102 is present, the graphic memory layer is formed on the mask layer.

[0078] The mask layer 102 is used to protect the top surface of the dielectric layer 101 in subsequent process steps; in the subsequent formation of the fifth trench, the patterned mask layer 102 is also used as an etching mask for etching the fifth trench.

[0079] Combination Figure 18 refer to Figure 19 and Figure 20 The step of forming the fifth trench 120 includes:

[0080] With the graphics memory layer 104 and the isolation layer 116 (shown in...) Figure 17 (middle) is a mask, and the mask layer 102 exposed by the fourth trench 118 is etched to form the sixth trench 119;

[0081] Using the mask layer 102 as a mask, the dielectric layer 101 of the substrate 100 exposed by the sixth trench 119 is etched to form the fifth trench 120.

[0082] In this embodiment, during the step of forming the fifth trench, both the graphics memory layer and the isolation layer are consumed, and the mask layer may remain. In other embodiments, the mask layer may also be consumed after the fifth trench is formed.

[0083] like Figure 20 and Figure 21 As shown, after the fifth trench 120 is formed, if a mask layer 102 exists, the process also includes removing the remaining mask layer 102.

[0084] In this embodiment, the mask layer 102 is made of titanium nitride. In other embodiments, the mask layer may be made of one or a combination of at least two of tantalum nitride, titanium oxide, tantalum oxide, and tungsten-carbon composite materials.

[0085] It is easy to understand that, in order to improve the robustness of the core material layer formed on the mask layer, after the mask layer is formed and before the pattern memory layer is formed, the following steps are also included:

[0086] An adhesive layer 103 is formed on the substrate, and the adhesive layer 103 covers the mask layer 102. When the adhesive layer is present, a pattern memory layer is formed on the adhesive layer.

[0087] In this embodiment, the adhesive layer 103 is made of aluminum oxide. In other embodiments, the adhesive layer may also be made of silicon oxide.

[0088] When an adhesive layer is present, the graphic memory layer 104 and the isolation layer 116 (shown in...) Figure 17 When etching the mask layer 102 exposed by the fourth trench 118 to form the sixth trench 119, the adhesive layer above the mask layer is also etched at the same time.

[0089] like Figure 22 and Figure 23 As shown, the fifth groove 120 is formed (shown in...) Figure 20 After (in Chinese), it also includes:

[0090] A metal layer 121 is formed, which fills the fifth trench, and the top surface of the metal layer 121 is flush with the top surface of the dielectric layer 101. The metal layer is electrically connected to the metal interconnect layer.

[0091] The metal layer is used to achieve electrical connection with the metal interconnect layer in the substrate during the back end of line (BEOL) process, thereby enabling the semiconductor device (e.g., transistor) or functional structure to be electrically connected to external circuits or other interconnect structures.

[0092] In this embodiment, the material of the metal layer is copper. In other embodiments, the material of the metal layer may be one or a combination of at least two of tungsten, cobalt, or aluminum.

[0093] Specifically, the steps for forming the metal layer 121 include:

[0094] A metal material layer 121a is formed, which fills the fifth trench and covers the substrate;

[0095] The metal material layer 121a is planarized to form a metal layer 121, the top surface of which is flush with the top surface of the dielectric layer 101.

[0096] When planarizing the metal material layer 121a to form the metal layer 121, the dielectric layer is used as the etching stop layer.

[0097] Correspondingly, combined Figure 16 refer to Figure 17 The present invention also provides a semiconductor structure.

[0098] The semiconductor structure includes: a substrate 100, the substrate 100 including a metal interconnect layer (not shown); a pattern memory layer 104 and an isolation layer 116, both disposed on the substrate 100, and the top of the isolation layer 116 is flush with the top of the pattern memory layer 104. The pattern memory layer 104 and the isolation layer 116 form a fourth trench 118, the fourth trench 118 corresponding to the metal interconnect layer, and the extension direction of each fourth trench 118 is the same.

[0099] Semiconductor devices such as transistors and capacitors can be formed in the substrate 100, and functional structures such as resistive structures and conductive structures can also be formed in the substrate.

[0100] The substrate 100 includes a metal interconnect layer. After the metal layer is subsequently formed on the substrate 100, the metal interconnect layer is used to realize electrical connection with the metal layer in the back end of line (BEOL) process, thereby enabling the semiconductor device (e.g., transistor) or functional structure to be electrically connected to external circuits or other interconnect structures.

[0101] It should be noted that the fourth trench, corresponding to the metal interconnect layer, means that when the substrate is subsequently etched downwards using the sidewalls surrounding the fourth trench as a mask, the metal interconnect layer within the substrate can be exposed. When the substrate is subsequently etched downwards using the dielectric layer surrounding the fourth trench as a mask, trenches with the same morphology as the fourth trench can be formed on the substrate. Since the fourth trench corresponds to the metal interconnect layer within the substrate, the trenches formed on the substrate can expose the metal interconnect layer. Therefore, the metal layer subsequently formed within the trenches on the substrate can contact the metal interconnect layer, and after power is applied, the metal layer and the metal interconnect layer become electrically connected.

[0102] In this embodiment, the formation process of the fourth groove first involves forming the first, second, and third grooves using three photomasks, and then cutting off multiple first, second, and third grooves in the same process step, thus simplifying the process flow. On the other hand, by forming multiple first, second, and third grooves using three photomasks, even when the graphic size is close to the limits of the equipment parameters, it is possible to process smaller graphics in the subsequent processing, thereby reducing production costs.

[0103] In this embodiment, the material of the graphics memory layer 104 is silicon oxide. In other embodiments, the material of the graphics memory layer can be one or a combination of silicon oxide, silicon nitride, and silicon oxynitride.

[0104] The isolation layer 116 is used to cut the fourth groove, so that the fourth groove formed can meet the morphological requirements. When etching downwards using the sidewalls around the fourth groove as a mask, it ensures that the final pattern meets the size and morphological requirements.

[0105] A mask layer 102 is disposed between the substrate 100, the graphics memory layer 104 and the isolation layer 116.

[0106] It should be noted that the mask layer being disposed between the substrate, the pattern memory layer, and the isolation layer means that along the semiconductor structure growth direction, the mask layer covers the substrate, the pattern memory layer and the isolation layer are located on the same film layer, and the pattern memory layer and the isolation layer are located on the mask layer.

[0107] In this embodiment, the mask layer 102 is made of titanium nitride. In other embodiments, the mask layer may be made of one or a combination of at least two of tantalum nitride, titanium oxide, tantalum oxide, and tungsten-carbon composite materials.

[0108] An adhesive layer 103 is provided between the mask layer 102, the graphic memory layer 104 and the isolation layer 116.

[0109] Similarly, the adhesive layer being disposed between the mask layer, the pattern memory layer, and the isolation layer means that along the semiconductor structure growth direction, the adhesive layer covers the mask layer, the pattern memory layer and the isolation layer are located on the same film layer, and the pattern memory layer and the isolation layer are located on the adhesive layer.

[0110] In this embodiment, the adhesive layer 103 is made of aluminum oxide. In other embodiments, the adhesive layer may also be made of silicon oxide.

[0111] The semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0112] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a metal interconnect layer; A pattern memory layer is formed on the substrate. The pattern memory layer has a first trench, a second trench, and a third trench. The extension directions of the first trench, the second trench, and the third trench are parallel to each other, and the first trench, the second trench, and the third trench are formed using different photomasks. A core material layer is formed, which fills the first trench, the second trench, and the third trench; The core material layer is graphically represented to form a core layer, and the core layer has an isolation opening; The isolation opening is filled to form an isolation layer, the top of which is at least flush with the top of the core layer; The core layer is removed to form a fourth trench, which corresponds to the metal interconnect layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of graphically representing the core material layer and forming the core layer include: A shielding layer is formed on the core material layer, and the shielding layer exposes a portion of the core material layer; The core material layer is etched using the shielding layer as a mask to form an isolation opening, and the remaining core material layer is used as the core layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The steps for forming the isolation layer include: An isolation material layer is formed, which fills the isolation opening and covers the core layer and the graphics memory layer; Using the core layer as a stop layer, the isolation material layer is planarized to form an isolation layer.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps for forming the graphics memory layer include: A pattern memory material layer is formed on the substrate; A patterned first photoresist layer is formed on the pattern memory material layer; The pattern memory material layer is etched using the first photoresist layer as a mask to form the first trench; A patterned second photoresist layer is formed on the pattern memory material layer; The pattern memory material layer is etched using the second photoresist layer as a mask to form the second trench; A patterned third photoresist layer is formed on the pattern memory material layer; The pattern memory material layer is etched using the third photoresist layer as a mask to form the third trench.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate also includes a dielectric layer located above the metal interconnect layer; After removing the core layer to form the fourth trench, the process further includes: Using the pattern memory layer and the isolation layer as masks, the dielectric layer of the substrate exposed by the fourth trench is etched to form a fifth trench, which corresponds to the metal interconnect layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, After the fifth trench is formed, the process also includes: A metal layer is formed, which fills the fifth trench, and the top surface of the metal layer is flush with the top surface of the dielectric layer. The metal layer is electrically connected to the metal interconnect layer.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The steps for forming the metal layer include: A metallic material layer is formed, which fills the fifth trench and covers the substrate; Using the dielectric layer as a stop layer, the metal material layer is planarized to form a metal layer.

8. The method for forming a semiconductor structure as described in claim 5, characterized in that, Before the graphical memory layer is formed, it also includes: A mask layer is formed on the substrate; The step of forming the fifth trench includes: Using the graphics memory layer and the isolation layer as masks, the mask layer exposed by the fourth trench is etched to form the sixth trench; Using the mask layer as a mask, the dielectric layer of the substrate exposed by the sixth trench is etched to form the fifth trench.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, After the mask layer is formed and before the pattern memory layer is formed, the process also includes: An adhesive layer is formed on the substrate, and the adhesive layer covers the mask layer.

10. The method for forming a semiconductor structure according to any one of claims 1-9, characterized in that, The material of the graphic memory layer is one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination of at least two of them.

11. The method for forming a semiconductor structure according to any one of claims 1-9, characterized in that, The core layer is made of one or a combination of at least two of the following: amorphous carbon, photoresist, organic dielectric layer material, dielectric antireflective coating material, and polycrystalline silicon.

12. The method for forming a semiconductor structure according to any one of claims 1-9, characterized in that, The material of the isolation layer is different from that of the core layer.

13. The method for forming a semiconductor structure as described in claim 6, characterized in that, The material of the metal layer is one or a combination of at least two of copper, tungsten, cobalt, or aluminum.

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, The adhesive layer is made of aluminum oxide or silicon oxide.

15. The method for forming a semiconductor structure as described in claim 8 or 9, characterized in that, The material of the mask layer is one or a combination of at least two of titanium nitride, tantalum nitride, titanium oxide, tantalum oxide, and tungsten-carbon composite materials.

16. The method for forming a semiconductor structure according to any one of claims 1-9, characterized in that, The process for removing the core layer is either a dry etching process or a wet etching process.

17. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method for forming a semiconductor structure according to any one of claims 1-16, comprising: The substrate includes a metal interconnect layer; Both the graphics memory layer and the isolation layer are disposed on the substrate, and the top of the isolation layer is flush with the top of the graphics memory layer. The graphics memory layer and the isolation layer form a fourth trench, which corresponds to the metal interconnect layer, and the extension direction of each fourth trench is the same.

18. The semiconductor structure as claimed in claim 17, characterized in that, Also includes: A mask layer is disposed between the substrate, the graphics memory layer, and the isolation layer.

19. The semiconductor structure as claimed in claim 18, characterized in that, Also includes: An adhesive layer is disposed between the mask layer, the pattern memory layer, and the isolation layer.

20. The semiconductor structure as claimed in claim 17, characterized in that, The material of the graphic memory layer is one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination of at least two of them.

Images