Integrated circuit, memory circuit, method for forming an integrated circuit, and method for forming a memory circuit

Abstract

This application relates to integrated circuits, memory circuits, methods for forming integrated circuits, and methods for forming memory circuits. A method for forming an integrated circuit system includes forming a conductive material over a substrate. The conductive material is patterned into horizontally elongated longitudinal conductive lines. The conductive material is vertically recessed into longitudinally spaced first regions of the conductive lines to form longitudinally spaced conductive pillars, each located in a separate longitudinally spaced second region, the second regions alternating longitudinally with the first regions along the conductive lines. The conductive pillars protrude vertically relative to the conductive material in the longitudinally spaced and vertically recessed first regions of the conductive lines. Electronic components are formed directly above the conductive pillars. The individual electronic components are directly electrically coupled to the individual conductive pillars. Additional methods are disclosed, including structures independent of the methods.

Description

Technical Field

[0001] The embodiments disclosed herein relate to integrated circuit systems, memory circuit systems, methods for forming integrated circuit systems, and methods for forming memory circuit systems. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines or gate lines). Digital lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed using a combination of digital lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically specified as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of a few milliseconds or less. In any case, memory cells are configured to retain or store memory in at least two different selectable states. In binary systems, the state is considered as "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two level or information states.

[0004] A capacitor is a type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy, as an electric field, can be stored electrostatically within this material. Depending on the composition of the insulating material, the stored field will be volatile or non-volatile. For example, a capacitor insulating material containing only SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor having a ferroelectric material as at least a portion of the insulating material. The ferroelectric material is characterized by having two stable polarization states and thus being a programmable material that can comprise a capacitor and / or a memory cell. The polarization states of the ferroelectric material can be changed by applying a suitable programming voltage and remain (at least for a period of time) after the programming voltage is removed. Each polarization state has a different charge storage capacitance than the others, which is ideally used to write (i.e., store) and read the memory state without reversing the polarization state until it is desired to reverse such polarization. Less desirablely, in a memory having ferroelectric capacitors, the act of reading the memory state can reverse the polarization. Therefore, after determining the polarization state, the memory cell is rewritten to place it in a prefetch state immediately following the polarization state determination. In any case, due to the bistable nature of the ferroelectric material forming the capacitor portion, the memory cell incorporating the ferroelectric capacitor is ideally non-volatile. Other programmable materials can be used as capacitor insulators to make the capacitor non-volatile.

[0005] Field-effect transistors (FETs) are another type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is greatly prevented. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate. In any case, the gate insulator can be programmable, for example, ferroelectric.

[0006] Of course, capacitors and transistors can be used in integrated circuit systems other than memory circuit systems.

[0007] Some conductive lines in integrated circuits (such as the digital lines mentioned above) are elongated horizontally in the longitudinal direction. Electronic components (such as field-effect transistors in memory cells) can be directly electrically coupled along the conductive lines in the longitudinal direction. Summary of the Invention

[0008] In one aspect, this application provides a method for forming an integrated circuit system, comprising: forming a conductive material over a substrate; patterning the conductive material into horizontally elongated longitudinal conductive lines; vertically recessing the conductive material into longitudinally spaced first regions of the conductive lines to form longitudinally spaced conductive pillars located in individual longitudinally spaced second regions, the longitudinally spaced second regions alternating longitudinally with the conductive lines and the longitudinally spaced first regions, the conductive pillars protruding vertically relative to the conductive material in the longitudinally spaced and vertically recessed first regions of the conductive lines; and forming an electronic component directly electrically coupled to the individual conductive pillar above the conductive pillars.

[0009] In another aspect, this application provides a method for forming a memory circuit system, comprising: forming a conductive material over a substrate; patterning the conductive material into a plurality of horizontally elongated and laterally spaced conductive lines; vertically recessing the conductive material into longitudinally spaced first regions of the individual conductive lines to form longitudinally spaced conductive pillars located in individual longitudinally spaced second regions, the longitudinally spaced second regions alternating longitudinally with the individual conductive lines and the longitudinally spaced first regions, the conductive pillars protruding vertically relative to the conductive material in the longitudinally spaced and vertically recessed first regions of the individual conductive lines; forming a vertical transistor directly above the conductive pillars; the individual vertical transistor including a top source / drain region, a bottom source / drain region, and a channel region vertically located between the top and bottom source / drain regions; the bottom source / drain region being directly above and abutting the individual conductive pillars; and forming a memory device directly electrically coupled to the top source / drain region directly above the top source / drain region.

[0010] In another aspect, this application provides an integrated circuit system comprising: a conductive line, which is horizontally elongated longitudinally, the conductive line including alternating longitudinally spaced first regions along the conductive line and longitudinally spaced second regions, the longitudinally spaced second regions being characterized as conductive pillars vertically projecting relative to the conductive material of the conductive line in the longitudinally spaced first regions; the conductive pillars having uppermost conductive surfaces, and the conductive material of the individual longitudinally spaced first regions having uppermost conductive surfaces; the maximum length of the uppermost conductive surface of the conductive pillar along a straight line orthogonal to the longitudinal orientation of the conductive line being shorter than the maximum length of the uppermost conductive surface of the conductive material of the individual longitudinally spaced first regions along the straight line; and an electronic component located directly above the conductive pillar, the individual electronic component being directly electrically coupled to the individual conductive pillar.

[0011] In another aspect, this application provides a memory circuit system comprising: a plurality of conductive lines, which are horizontally elongated longitudinally and laterally spaced apart from each other; each individual conductive line includes a first region longitudinally spaced apart alternating with a second region longitudinally spaced apart along the individual conductive line; the second region longitudinally spaced apart is characterized as a conductive post vertically protruding relative to the conductive material of the corresponding individual conductive line in the first region longitudinally spaced apart; the conductive post has a uppermost conductive surface, and the conductive material of the conductive line in the first region longitudinally spaced apart has an uppermost conductive surface; the uppermost conductive surface of the conductive post is perpendicular to the second region. The maximum length of the longitudinally oriented straight line of the wire is shorter than the maximum length of the uppermost conductive surface of the conductive material of the corresponding conductive wire in the individual longitudinally spaced first regions along the straight line; a vertical transistor is located directly above the conductive pillar; the individual vertical transistor includes a top source / drain region, a bottom source / drain region, and a channel region vertically located between the top and bottom source / drain regions; the bottom source / drain region is located directly above and abuts the individual conductive pillar; and a storage device is located directly above the top source / drain region and is directly electrically coupled to the top source / drain region. Attached Figure Description

[0012] Figure 1 Is it through Figure 3 The schematic cross-sectional view of a portion of the substrate during processing according to an embodiment of the present invention is shown in line 1-1.

[0013] Figure 2 Is it through Figure 3 The cross-sectional view taken from line 2-2 in the diagram.

[0014] Figure 3 Is it through Figure 1 and 2 The cross-sectional view taken from line 3-3 in the diagram.

[0015] Figure 4-23 25-27 are examples of processes according to some embodiments of the present invention. Figure 1-3 Schematic continuous cross-sectional views, unfolded views, enlarged views and / or partial views of the structure or its parts.

[0016] Figure 24 Alternative examples of methods and / or structural embodiments of the present invention are shown. Detailed Implementation

[0017] Embodiments of the present invention include methods for forming integrated circuit systems (e.g., memory circuit systems), and integrated circuit systems independent of manufacturing methods. First, refer to... Figure 1-23An example method embodiment for forming a memory integrated circuit system is described.

[0018] refer to Figure 1-3 This illustrates a portion of a substrate configuration 10 including a base substrate 11, comprising any one or more conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, and insulating / insulator / isolator (i.e., electrically insulating herein) materials. Various materials may be formed vertically above and within the base substrate 11. The materials may... Figure 1-3 The material depicted is adjacent to, vertically inward, or vertically outward. For example, components that are fabricated or fully fabricated in other parts of the integrated circuit may be disposed above, around, or inside the substrate 11. Control circuitry and / or other peripheral circuitry for operating components within the memory cell array may also be fabricated relative to the memory circuitry system, and said circuitry may or may not be fully or partially within the array or subarray. Furthermore, multiple subarrays may be fabricated and operated relatively independently, sequentially, or otherwise. As used herein, "subarray" may also be considered an array.

[0019] Example substrate 11 is shown to include an insulating material 13 (e.g., silicon nitride and / or silicon dioxide), a conductive material 36 (e.g., conductive doped semiconducting material and / or metallic material) formed on the insulating material 13, and an insulating material 50 (e.g., silicon nitride and / or silicon dioxide) formed on the conductive material 36.

[0020] refer to Figure 4-6 The conductive material 36 has been patterned into horizontally elongated longitudinal conductive lines 38. Multiple conductive lines 38 are shown as having been formed; however, a single conductive line is also contemplated in the method and structural embodiments described herein. Any existing or future-developed technique can be used and the conductive lines 38 can be patterned using pitch doubling. Photolithographic patterning and etching are merely one example. The insulating material 50 (when present) can also be patterned as shown.

[0021] refer to Figure 7-9 In one embodiment, the lateral spaces immediately adjacent to the conductive lines 38 are filled with an insulating material 45 (e.g., silicon nitride and / or silicon dioxide). This can be achieved by first filling such spaces, and then planarizing the insulating material 45 back at least to the top surface of the insulator material 50. The insulating material 45 and the insulator material 50 may have relatively identical compositions (illustrated by the dashed lines between them) or relatively different compositions.

[0022] The conductive lines 38 can be considered as comprising longitudinally spaced first regions 40 and longitudinally spaced second regions 42 alternating longitudinally with the longitudinally spaced first regions 40 along the individual conductive lines 38. These regions may be indistinguishable at this processing point. In any case, refer to Figure 10-12 In one embodiment, the patterned masking material 55 has been formed on Figure 7-9 The top of the structure is used to conceal the second zone 42 and expose the first zone 40.

[0023] refer to Figure 13-17 A patterned masking material 55 (not shown) is used as a mask. When conductive, for example, it is anisotropically etched into the conductive material 36 at timings such that the conductive material 36 is vertically recessed in the longitudinally spaced first regions 40, thereby forming longitudinally spaced conductive pillars 35 respectively located in individual longitudinally spaced second regions 42. Example masking material 55 (not shown) has been removed during and / or after such example etching. The conductive pillars 35 protrude vertically relative to the longitudinally spaced and vertically recessed conductive material 36 in the first regions 40 of the conductive lines 38. In one embodiment where an insulating material 50 is present on top of the conductive material 36, and as shown, such insulating material 50 has been removed from the top of the conductive material 36 in the longitudinally spaced first regions 40 of the individual conductive lines 38 prior to such vertical recesses. Insulating material 50 (at least some of such insulating materials 50) may be retained on top of the conductive pillars 35 after their formation, and if so, may be present in the completed construction of the integrated circuit system, as will be apparent, for example, in a sequential sequence of diagrams in one embodiment. The process described above is merely one example of vertically recessed conductive material 35 in a longitudinally spaced first region 40 to form longitudinally spaced conductive pillars 35. Any other existing or future-developed methods may be used.

[0024] In one embodiment, the top 48 of the conductive material 36 of the vertically recessed conductive lines 38 in the longitudinally spaced first region 40 is formed below the top 49 of the insulating material 45 laterally located between the conductive lines 38. Figure 17 In one embodiment, during the formation of the conductive pillars 35, the space between the conductive wires 38 has an insulating material 45. The vertical recesses have formed gap spaces 44 above the longitudinally spaced first regions 40 of the conductive wires 38, the gap spaces 44 being longitudinally positioned between the longitudinally adjacent conductive pillars 35. In one embodiment, the conductive material 36 of the conductive pillars 35 of the conductive wires 38, the conductive material 36 of the conductive wires 38 below the conductive pillars 35, and the conductive material 36 of the conductive wires 38 in the longitudinally spaced first regions 40 have a composition that is relatively identical to each other. By way of example only, such compositions may be homogeneous or alternatively heterogeneous, for example comprising multiple layers of different compositions (not shown).

[0025] refer to Figure 18-22 In one embodiment, the sidewalls of the void space 44 are lined with a first insulating material 46, which does not completely fill the void space 44. The remaining volume of the void space 44 is then filled with a second insulating material 47 having a different composition from the first insulating material 46. This can be formed, for example, by the following steps: firstly, depositing a thin conformal layer of the first insulating material 46; then forming the second insulating material 47; and then planarizing the first insulating material 46 and the second insulating material 47 back at least to the top surface of the insulating material 50, as shown. By way of example, the first insulating material 46 may be silicon nitride or silicon dioxide, and the second insulating material 47 may be the other of silicon nitride or silicon dioxide. One example is that the first insulating material 46 is silicon nitride and the second insulating material 47 is silicon dioxide, formed by spin-coating a dielectric and subsequently densifying it. In any case, and in one embodiment as shown, the sidewalls of the void space 44 can be considered to include sidewalls 52 of conductive material 36 and sidewalls 54 of insulating material 50, said sidewalls being located on top of the conductive pillar 35. Figure 20 In such examples, the first insulating material 46 and the second insulating material 47 are laterally positioned above both the sidewall 52 of the conductive material 36 and the sidewall 54 of the insulating material 50. However, in one embodiment, the insulating material 50 and the first insulating material 46 have the same composition relative to each other.

[0026] Figure 23 This is an enlarged perspective view of a portion of a single conductive wire 38 having two posts 35 as its part, with other material around the posts 35 removed for clarity. Each individual conductive post 35 can be considered to have a topmost conductive surface 56 and, in one embodiment, is planar. The conductive material 36 of the conductive wires 38 in the individual longitudinally spaced first regions 40 can be considered to have a topmost conductive surface 58 and, in one embodiment, is planar. In one embodiment, the topmost conductive surface 56 of the posts and the topmost surface 58 of the first regions are along a straight direction 60 orthogonal to the longitudinal orientation of the individual conductive wires 38 (e.g., along the longitudinal axis 65). Figure 19 (or 22 cross sections) have the same maximum length L relative to each other.

[0027] Any other attributes or aspects shown and / or described herein with reference to other embodiments may be used in the embodiments shown and described above.

[0028] refer to Figure 24Alternative example embodiments are shown and described relative to a portion of construction 10a. Similar numbering to the embodiments described above is used where appropriate, with the suffix "a" or different numbers or letters indicating some construction differences. In construction 10a, the maximum length D of the uppermost conductive surface 56a of the strut along the straight direction 60 is shorter than the maximum length E of the uppermost conductive surface 58a of the first region along the straight direction 60. In one embodiment, the straight direction 60 may be considered as the first straight direction 60, and construction 10a includes a second straight direction 62 orthogonal to the first straight direction 60. The maximum length G of the uppermost conductive surface 56a of an individual conductive post 35 along the second straight direction 62 is shorter than the maximum length H of the uppermost conductive surface 58a of the conductive material 36 of the individual longitudinally spaced first regions 40 along the second straight direction 62. In one embodiment, and as shown, the maximum length J of the bottom surface 64 of an individual conductive line 38 along the first linear direction 60 is longer than the maximum length E of the uppermost conductive surface 58a of the conductive material 36 of the individual conductive lines 38 in the individual longitudinally spaced first regions 40 along the first linear direction 60. The practitioner can select appropriate anisotropic etching conditions that affect whether the sidewalls under sub-etching are vertical or gradually narrow from a vertical direction. For example, variations in one or more of the temperature, pressure, or energy in plasma etching can be used to influence such anisotropic etching conditions, and these can vary for different chemical substances. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0029] Electronic components are formed directly above conductive pillars 35, with individual electronic components directly electrically coupled to individual conductive pillars 35. In one embodiment, individual electronic components directly abut against the uppermost conductive surface 56 / 56a of an individual conductive pillar, and the corresponding electronic components are directly electrically coupled to said uppermost conductive surface 56 / 56a. Any existing or future-developed electronic components can be used. In one embodiment, each electronic component includes a vertical transistor.

[0030] For example, and refer to Figure 25The illustration shows an example embodiment where a vertical transistor 18 is schematically shown as being formed directly above and electrically coupled to an individual conductive post 35 in configuration 10. Such a vertical transistor includes a top source / drain region 32, a bottom source / drain region 30, and a channel region 15 vertically situated therebetween. A conductive gate 20 and a gate insulator 17 are operatively located adjacent to the channel region 15. The example bottom source / drain region 30 is located directly above and abuts the individual conductive post 35, for example, directly abutting the uppermost conductive surface 56. In one embodiment, and as shown, for example in a method for forming a memory circuit system, a memory device 85 is formed directly above and electrically coupled to the top source / drain region 32, where the example memory device 85 is schematically depicted as a capacitor 85.

[0031] Figure 26 and 27 Show more details in only one instance. Figure 19 and 20 The associated structure. For example, the vertical transistor 18 mentioned above is shown. Such a vertical transistor 18 is shown as being laterally separated by a dielectric material 12 (e.g., silicon dioxide). As shown, gate 20 and gate insulator 17 are located on opposite sides of channel region 15. Gate 20 may include gate lines that interconnect transistors 18 along the row direction. Regions 32, 15, and 30 may have any suitable one or more horizontal cross-sectional shapes, wherein a square (as shown) or a rectangle (not shown) is ideal, at least for channel region 15, to maximize the lateral overlap of gate lines 20 with channel region 15. Capacitor 85 is shown as being directly electrically coupled to individual top source / drain regions 32 of the individual vertical transistor 18. By way of example, the shown configuration includes a bottom capacitor electrode / memory node 70, a shared top capacitor electrode 74, and a capacitor insulator 72 therebetween. A single capacitor 85 and the single vertical transistor 18 directly below it may comprise a single memory cell, such as a transistor-capacitor DRAM cell in a DRAM integrated circuit system.

[0032] Alternative embodiments may be constructed from the method embodiments described above or otherwise. In any case, embodiments of the invention cover integrated circuit systems independent of manufacturing methods. However, such integrated circuit systems may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may incorporate having, forming, and / or having any of the properties described relative to the device embodiments.

[0033] In one embodiment, the integrated circuit system includes horizontally elongated longitudinal conductive lines (e.g., 38). The conductive lines include longitudinally spaced first regions (e.g., 40) alternating with longitudinally spaced second regions (e.g., 42) along the conductive lines. The longitudinally spaced second regions are characterized as conductive pillars (e.g., 35) projecting vertically relative to the conductive material (e.g., 36) of the conductive lines in the longitudinally spaced first regions. Each conductive pillar has a superior conductive surface (e.g., 56a), and the conductive material of the individual longitudinally spaced first regions has a superior conductive surface (e.g., 58a). The maximum length (e.g., D) of the superior conductive surface of the conductive pillar along a straight direction (e.g., 60) orthogonal to the longitudinal orientation (e.g., 62 / 65) of the conductive lines is shorter than the maximum length (e.g., E) of the superior conductive surface of the individual longitudinally spaced first regions along a straight direction. An electronic component (e.g., 18) is positioned directly above the conductive pillar. Individual electronic components are directly electrically coupled to individual conductive pillars. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0034] In one embodiment, the memory circuit system includes a plurality of conductive lines (e.g., 38) that are horizontally elongated longitudinally and laterally spaced apart from each other. Each conductive line includes a first region (e.g., 40) that is longitudinally spaced along the individual conductive line and alternates with a second region (e.g., 42) that is longitudinally spaced apart. The longitudinally spaced second region is characterized by a conductive post (e.g., 35) that protrudes vertically relative to the conductive material (e.g., 36) of the corresponding individual conductive line in the longitudinally spaced first region. The conductive post has a uppermost conductive surface (e.g., 56a), and the conductive material of the conductive line in the individual longitudinally spaced first region has an uppermost conductive surface (e.g., 58a). The maximum length (e.g., D) of the uppermost conductive surface of the conductive post in a straight line direction (e.g., 60) orthogonal to the longitudinal orientation (e.g., 62 / 65) of the conductive line is shorter than the maximum length (e.g., E) of the uppermost conductive surface of the conductive material of the corresponding conductive line in the individual longitudinally spaced first region in a straight line direction. A vertical transistor (e.g., 18) is positioned directly above the conductive post. Each vertical transistor includes a top source / drain region (e.g., 32), a bottom source / drain region (e.g., 30), and a channel region (e.g., 15) vertically situated between the top and bottom source / drain regions. The bottom source / drain region is directly above and abuts the individual conductive pillar. A memory device (e.g., 85) is directly above and electrically coupled to the top source / drain region. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0035] The above processing or construction can be viewed as being performed relative to an array of components formed as a single stack or a single group of such components, or within a single stack or a single group of such components, which is above or part of an underlying substrate (but a single stack / group may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array can also be formed as part of the final construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / groups may be provided or fabricated above and / or below the stacks / groups shown in the diagram or described above. Furthermore, the arrays of components in different stacks / groups may be the same or different from each other, and the different stacks / groups may have the same or different thicknesses relative to each other. Intermediate structures (e.g., additional circuitry and / or dielectric layers) may be provided between vertically adjacent stacks / groups. And, the different stacks / groups may be electrically coupled relative to each other. Multiple stacks / groups can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / groups can be manufactured substantially simultaneously.

[0036] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0037] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” refers to a generally relative direction (i.e., within 10 degrees) along the surface of the main substrate, where the substrate is processed during manufacturing, and which is generally orthogonal to vertical. “Just horizontal” is a generally relative direction (i.e., not at an angle) along the surface of the main substrate. Furthermore, “vertical” and “horizontal” as used herein are generally perpendicular to each other and independent of the orientation of the substrate in three-dimensional space. Additionally, “vertically extending” and “vertically extending” refer to a direction deviating at least 45° from just horizontal. Furthermore, “vertically extending,” “vertically extending,” “horizontally extending,” “horizontally extending,” etc., relative to a field-effect transistor, refer to the orientation of the transistor’s channel length along which current flows between the source / drain regions during operation. For bipolar junction transistors, terms such as "vertically extending," "vertically extending," "horizontally extending," and "horizontally extending" refer to the orientation of the substrate length along which current flows between the emitter and collector during operation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within a vertical 10°.

[0038] Furthermore, "directly above," "directly below," and "directly below" require that the two stated areas / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. Moreover, using "above" without the preceding "direct" only requires that a portion of the stated area / material / component above the other stated area / material / component extends vertically outward from the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "under" without the preceding "direct" only requires that a portion of the stated area / material / component below / under the other stated area / material / component extends vertically inward from the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0039] Any of the materials, regions, and structures described herein may be homogeneous or non-homogeneous, and in any event may be continuous or discontinuous over any material covering them. When one or more example compositions are provided for any material, the material may comprise, consist primarily of, or consist of such one or more compositions. Furthermore, unless otherwise stated, any suitable existing or future-developed techniques may be used to form each material, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0040] Additionally, the term "thickness" used alone (without a directional adjective) is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions with different compositions, passing through a given material or region. Furthermore, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and the material or region will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, "different compositions" only requires that the portions of two stated materials or regions that can directly contact each other are chemically and / or physically different, for example, in cases where such materials or regions are not homogeneous. If two stated materials or regions are not directly contacting each other, then in cases where such materials or regions are not homogeneous, "different compositions" only requires that the portions of two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, one material, region, or structure "directly contacts" another material, region, or structure when there is at least some physical contact between the stated materials, regions, or structures. In contrast, the words "over", "on", "near", "along", and "against" without the preceding "positive" encompass "direct contact" and constructions in which the intervention of materials, areas, or structures results in no physical contact between the stated materials, areas, or structures relative to each other.

[0041] In this text, if, during normal operation, current can flow continuously from one region-material-component to another, and this flow is primarily accomplished by the movement of said subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the region-material-components are “electrically coupled” relative to each other. Another electronic component may be electrically coupled between and to the region-material-components. In contrast, when region-material-components are referred to as “directly electrically coupled,” there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled region-material-components.

[0042] Any use of the terms "row" and "column" in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features, and for which components have been or may be formed along said "row" and "column". "Row" and "column" are used synonymously with any series of areas, components, and / or features, regardless of function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be the same. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles (i.e., other than straight angles).

[0043] The components of any of the conductive / conductor / conductive materials mentioned herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconductive materials. "Metallic material" means any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds.

[0044] In this document, any use of “selective” in relation to etching, removal, deposition, formation, and / or shaping is an action in which a stated material is performed relative to another stated material at a volume ratio of at least 2:1. Additionally, any use of selective deposition, selective growth, or selective formation is the deposition, growth, or formation of one material relative to one or more stated materials at a volume ratio of at least 2:1 for a depth of at least 75 angstroms.

[0045] Unless otherwise indicated, the use of "or" in this document covers either one or both.

[0046] in conclusion

[0047] In some embodiments, a method for forming an integrated circuit system includes forming a conductive material over a substrate. The conductive material is patterned into horizontally elongated longitudinal conductive lines. The conductive material is vertically recessed into longitudinally spaced first regions of the conductive lines to form longitudinally spaced conductive pillars, each located in a separately longitudinally spaced second region, the second regions alternating longitudinally with the conductive lines and the first regions. The conductive pillars protrude vertically relative to the conductive material in the longitudinally spaced and vertically recessed first regions of the conductive lines. Electronic components are formed directly above the conductive pillars. The individual electronic components are directly electrically coupled to the individual conductive pillars.

[0048] In some embodiments, a method for forming a memory circuit system includes forming a conductive material over a substrate. The conductive material is patterned into a plurality of horizontally elongated and laterally spaced conductive lines. The conductive material is vertically recessed into longitudinally spaced first regions of the individual conductive lines to form longitudinally spaced conductive pillars located in individual longitudinally spaced second regions, the longitudinally spaced second regions alternating longitudinally with the individual conductive lines and the longitudinally spaced first regions. The conductive pillars protrude vertically relative to the conductive material in the longitudinally spaced and vertically recessed first regions of the individual conductive lines. A vertical transistor is formed directly above the conductive pillar. The individual vertical transistor includes a top source / drain region, a bottom source / drain region, and a channel region vertically located between the top and bottom source / drain regions. The bottom source / drain region is directly above and abuts the individual conductive pillar. A memory device is formed directly above the top source / drain region and electrically coupled directly to the top source / drain region.

[0049] In some embodiments, an integrated circuit system includes horizontally elongated longitudinal conductive lines. The conductive lines include longitudinally spaced first regions alternating with second regions spaced longitudinally along the conductive lines. The longitudinally spaced second regions are characterized as conductive pillars protruding vertically relative to the conductive material of the conductive lines in the individual longitudinally spaced first regions. Each conductive pillar has a uppermost conductive surface, and the conductive material of the conductive lines in the individual longitudinally spaced first regions also has an uppermost conductive surface. The maximum length of the uppermost conductive surface of the conductive pillar along a straight line orthogonal to the longitudinal orientation of the conductive lines is shorter than the maximum length of the uppermost conductive surface of the conductive material of the conductive lines in the individual longitudinally spaced first regions along the straight line. Electronic components are positioned directly above the conductive pillars. The individual electronic components are directly electrically coupled to the individual conductive pillars.

[0050] In some embodiments, a memory circuit system includes a plurality of conductive lines that are horizontally elongated longitudinally and laterally spaced from each other. Each individual conductive line includes a first region that is longitudinally spaced, alternating with a second region that is longitudinally spaced along the individual conductive line. The second region is characterized as a conductive post that projects vertically relative to the conductive material of the corresponding individual conductive line in the first region. The conductive post has a uppermost conductive surface, and the conductive material of the conductive line in the first region has an uppermost conductive surface. The maximum length of the uppermost conductive surface of the conductive post along a straight line orthogonal to the longitudinal orientation of the conductive line is shorter than the maximum length of the uppermost conductive surface of the conductive material of the corresponding conductive line in the first region along the same straight line. A vertical transistor is positioned directly above the conductive post. Each vertical transistor includes a top source / drain region, a bottom source / drain region, and a channel region vertically located between the top and bottom source / drain regions. The bottom source / drain region is positioned directly above and abuts the individual conductive post. The storage device is located directly above the top source / drain region and is directly electrically coupled to the top source / drain region.

[0051] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A method for forming integrated circuitry, comprising: forming conductive material over a substrate; patterning the conductive material into horizontally longitudinally elongated conductive lines; vertically recessing the conductive material in longitudinally spaced-apart first regions of the conductive lines to form longitudinally spaced-apart conductive pillars in respective longitudinally spaced-apart second regions, the longitudinally spaced-apart second regions longitudinally alternating with the longitudinally spaced-apart first regions along the conductive lines, the conductive pillars vertically projecting relative to the longitudinally spaced-apart and vertically recessed first regions of the conductive material of the conductive lines; and forming electronic components directly electrically coupled to respective ones of the conductive pillars directly over the conductive pillars, wherein the vertically recessing forms void space over the longitudinally spaced-apart first regions of the conductive lines, the void space longitudinally between longitudinally immediately adjacent ones of the conductive pillars, and the method additionally comprising: lining sidewalls of the void space with first insulative material, the first insulative material not filling the void space; and filling a remaining volume of the void space with second insulative material having a different composition than the first insulative material.

2. The method of claim 1, wherein the conductive material of the conductive pillars of the conductive lines, the conductive material of the conductive lines under the conductive pillars, and the conductive material of the conductive lines in the longitudinally spaced-apart first regions have a same composition relative to one another.

3. The method of claim 1, wherein, the respective ones of the conductive pillars have uppermost conductive surfaces, and the conductive material of the conductive lines in the respective ones of the longitudinally spaced-apart first regions has an uppermost conductive surface; and the uppermost conductive surfaces of the respective ones of the conductive pillars and the uppermost conductive surfaces of the conductive material of the conductive lines in the respective ones of the longitudinally spaced-apart first regions have a same maximum length relative to one another along a straight direction that is orthogonal to a longitudinal direction of the conductive lines.

4. The method of claim 1, wherein the electronic components comprise vertical transistors.

5. A method for forming integrated circuitry, comprising: forming conductive material over a substrate; patterning the conductive material into horizontally longitudinally elongated conductive lines; vertically recessing the conductive material in longitudinally spaced-apart first regions of the conductive lines to form longitudinally spaced-apart conductive pillars in respective longitudinally spaced-apart second regions, the longitudinally spaced-apart second regions longitudinally alternating with the longitudinally spaced-apart first regions along the conductive lines, the conductive pillars vertically projecting relative to the longitudinally spaced-apart and vertically recessed first regions of the conductive material of the conductive lines; forming electronic components directly electrically coupled to respective ones of the conductive pillars directly over the conductive pillars; the patterning forms a plurality of the conductive lines laterally spaced-apart relative to one another; the vertically recessing, the forming of the longitudinally spaced-apart conductive pillars, and the forming of the electronic components occur relative to the plurality of the conductive lines; and the forming of the plurality of the conductive lines comprises: filling spaces between immediately adjacent ones of the electrically conductive lines laterally in the electrically conductive lines with insulator material prior to forming the electrically conductive pillars, the spaces having the insulator material therein during the forming of the electrically conductive pillars.

6. The method of claim 5 wherein the vertical recessing forms tops of the electrically conductive material of the electrically conductive lines in the longitudinally spaced-apart first regions to be lower than tops of the insulator material laterally between the electrically conductive lines.

7. The method of claim 5 comprising: forming insulator material atop the electrically conductive material prior to forming the electrically conductive pillars; removing the insulator material from atop the electrically conductive material in the longitudinally spaced-apart first regions of the electrically conductive lines prior to the vertical recessing; and the insulator material remaining atop the electrically conductive pillars after the electrically conductive pillars are formed and in a completed construction of the integrated circuitry.

8. The method of claim 7 comprising forming the insulator material atop the electrically conductive material prior to forming the electrically conductive lines.

9. The method of claim 7 wherein the vertical recessing forms a void space above the longitudinally spaced-apart first regions of the electrically conductive lines, the void space being longitudinally between longitudinally immediately adjacent ones of the electrically conductive pillars; and the method additionally comprising: lining sidewalls of the void space with first insulator material, the first insulator material not filling the void space; and filling a remaining volume of the void space with second insulator material above and having a different composition than the first insulator material.

10. The method of claim 9 wherein the sidewalls of the void space comprise sidewalls of the electrically conductive material and sidewalls of the insulator material atop the electrically conductive pillars, the first insulator material and the second insulator material being laterally above both the sidewalls of the electrically conductive material and the sidewalls of the insulator material.

11. The method of claim 9 wherein the insulator material and the first insulator material have the same composition relative to each other.

12. The method of claim 5 wherein, the individual ones of the electrically conductive pillars have uppermost electrically conductive surfaces, and the electrically conductive material of the individual ones of the electrically conductive lines in the longitudinally spaced-apart first regions have uppermost electrically conductive surfaces; and the uppermost electrically conductive surfaces of the individual ones of the electrically conductive pillars and the uppermost electrically conductive surfaces of the electrically conductive material of the individual ones of the electrically conductive lines in the longitudinally spaced-apart first regions have the same maximum length relative to each other along a straight direction that is orthogonal to a longitudinal orientation of the electrically conductive lines.

13. A method for forming integrated circuitry comprising: forming electrically conductive material over a substrate; patternizing the electrically conductive material into electrically conductive lines that are horizontally longitudinally elongated; vertically recessing the conductive material in longitudinally spaced-apart first regions of the conductive lines to form longitudinally spaced-apart conductive pillars in individually longitudinally spaced-apart second regions, the longitudinally spaced-apart second regions longitudinally alternating along the conductive lines with the longitudinally spaced-apart first regions, the conductive pillars vertically protruding relative to the conductive material in the longitudinally spaced-apart and vertically recessed first regions of the conductive lines; and forming electronic components directly electrically coupled to the conductive pillars, wherein the individually the conductive pillars have uppermost conductive surfaces, and the conductive material of the conductive lines in the individually the longitudinally spaced-apart first regions has uppermost conductive surfaces; and wherein the uppermost conductive surfaces of the individually the conductive pillars are shorter in maximum length along a straight direction orthogonally oriented to a longitudinal direction of the conductive lines than the uppermost conductive surfaces of the conductive material of the conductive lines in the individually the longitudinally spaced-apart first regions are in maximum length along the straight direction.

14. The method of claim 13, wherein, the straight direction is a first straight direction and includes a second straight direction orthogonal to the first straight direction; and the uppermost conductive surfaces of the individually the conductive pillars are shorter in maximum length along the second straight direction than the uppermost conductive surfaces of the conductive material of the conductive lines in the individually the longitudinally spaced-apart first regions are in maximum length along the second straight direction.

15. The method of claim 14, wherein a bottom surface of the conductive lines is longer in maximum length along the first straight direction than the uppermost conductive surfaces of the conductive material of the conductive lines in the individually the longitudinally spaced-apart first regions are in maximum length along the first straight direction.

16. The method of claim 13, wherein the electronic components comprise vertical transistors.

17. A method for forming memory circuitry, comprising: forming conductive material over a substrate; patterning the conductive material into a plurality of conductive lines that are horizontally longitudinally elongated and laterally spaced apart from one another; vertically recessing the conductive material in longitudinally spaced-apart first regions of the conductive lines to form longitudinally spaced-apart conductive pillars in individually longitudinally spaced-apart second regions, the longitudinally spaced-apart second regions longitudinally alternating along the individually the conductive lines with the longitudinally spaced-apart first regions, the conductive pillars vertically protruding relative to the conductive material in the longitudinally spaced-apart and vertically recessed first regions of the individually the conductive lines; forming vertical transistors directly over the conductive pillars; the individually the vertical transistors comprising top source / drain regions, bottom source / drain regions, and channel regions vertically between the top and bottom source / drain regions; the bottom source / drain regions being directly against the individually the conductive pillars; and forming storage devices directly electrically coupled to the top source / drain regions directly over the top source / drain regions, wherein the conductive pillars each have an uppermost conductive surface, and the conductive material of the conductive lines in the individual longitudinally spaced-apart first regions each has an uppermost conductive surface; and wherein the uppermost conductive surface of the individual conductive pillars has a maximum length along a straight direction orthogonal to a longitudinal orientation of the individual conductive lines that is shorter than a maximum length of the uppermost conductive surface of the conductive material of the conductive lines in the individual longitudinally spaced-apart first regions along the straight direction.

18. The method of claim 17, wherein the memory circuitry comprises DRAM.

19. Integrated circuitry comprising: a conductive line horizontally longitudinally elongated, the conductive line comprising longitudinally spaced-apart first regions alternating with longitudinally spaced-apart second regions along the conductive line, the longitudinally spaced-apart second regions characterized as conductive pillars vertically protruding relative to a conductive material of the conductive lines in the longitudinally spaced-apart first regions; the conductive pillars each having an uppermost conductive surface, and the conductive material of the conductive lines in the individual longitudinally spaced-apart first regions each having an uppermost conductive surface; the uppermost conductive surface of the conductive pillars having a maximum length along a straight direction orthogonal to a longitudinal orientation of the conductive lines that is shorter than a maximum length of the uppermost conductive surface of the conductive material of the conductive lines in the individual longitudinally spaced-apart first regions along the straight direction; and electronic components directly above the conductive pillars, the individual electronic components directly electrically coupled to the individual conductive pillars.

20. The integrated circuitry of claim 19, wherein the individual electronic components are directly against an uppermost surface of the individual conductive pillars, the respective electronic components directly electrically coupled to the uppermost surface.

21. The integrated circuitry of claim 19, wherein the conductive material of the conductive pillars of the conductive line, the conductive material of the conductive line below the conductive pillars, and the conductive material of the conductive lines in the longitudinally spaced-apart first regions have a same composition relative to one another.

22. The integrated circuit system of claim 19, comprising a void space over the longitudinally spaced-apart first regions of the conductive lines, the void space being longitudinally between longitudinally immediately adjacent ones of the conductive pillars; and the integrated circuitry further comprising: a first insulative material lining sidewalls of the void space and not filling the void space; and a second insulative material having a different composition than the first insulative material and being radially inward of the first insulative material.

23. The integrated circuitry of claim 19, wherein, the straight direction is a first straight direction and comprises a second straight direction orthogonal to the first straight direction; and the uppermost conductive surface of the individual conductive pillars has a maximum length along the second straight direction that is shorter than a maximum length of the uppermost conductive surface of the conductive material of the conductive lines in the individual longitudinally spaced-apart first regions along the second straight direction.

24. The integrated circuitry of claim 23 wherein a maximum length of a bottom surface of the conductive lines along the first rectilinear direction is longer than a maximum length of the uppermost conductive surface of the conductive material of the conductive lines in the individual of the longitudinally spaced-apart first regions along the first rectilinear direction.

25. The integrated circuitry of claim 19 wherein the electronic components comprise vertical transistors.

26. Memory circuitry comprising: a plurality of conductive lines horizontally longitudinally elongated and laterally spaced-apart from one another, individual of the conductive lines comprising longitudinally spaced-apart first regions alternating with longitudinally spaced-apart second regions along the individual of the conductive lines; the longitudinally spaced-apart second regions characterized as conductive pillars vertically protruding relative to the conductive material of the respective individual conductive lines in the longitudinally spaced-apart first regions; the conductive pillars having an uppermost conductive surface, and the conductive material of the conductive lines in the individual of the longitudinally spaced-apart first regions having an uppermost conductive surface; a maximum length of the uppermost conductive surface of the conductive pillars along a rectilinear direction orthogonal to a longitudinal orientation of the conductive lines shorter than a maximum length of the uppermost conductive surface of the conductive material of the respective conductive lines in the individual of the longitudinally spaced-apart first regions along the rectilinear direction; vertical transistors directly over the conductive pillars; individual of the vertical transistors comprising a top source / drain region, a bottom source / drain region, and a channel region vertically between the top and bottom source / drain regions; the bottom source / drain region directly over and directly against the individual of the conductive pillars; and storage devices directly electrically coupled to the top source / drain regions.

27. The memory circuitry of claim 26 wherein the storage devices are capacitors of individual memory cells comprising the capacitors and respective vertical transistors, the capacitors directly coupled to top source / drain regions of the respective vertical transistors.

28. The memory circuitry of claim 27 wherein the individual memory cells are one-transistor one-capacitor memory cells.

29. The memory circuitry of claim 26 wherein respective storage devices are directly electrically coupled to uppermost surfaces of the top source / drain regions.

31. The memory circuitry of claim 26, comprising void space above the longitudinally spaced first regions of the individual of the conductive lines, the void space longitudinally between longitudinally immediately adjacent ones of the conductive pillars; 30. The memory circuitry of claim 26 wherein the conductive material of the conductive pillars of the conductive lines, the conductive material of the conductive lines below the conductive pillars, and the conductive material of the conductive lines in the longitudinally spaced-apart first regions have a same composition relative to one another. and the memory circuitry additionally comprising: a first insulative material lining sidewalls of the void space and not filling the void space; and a second insulative material having a different composition than the first insulative material and being radially inward of the first insulative material.

32. The memory circuitry of claim 26 wherein, The straight direction is a first straight direction and includes a second straight direction orthogonal to the first straight direction; and A maximum length of the uppermost conductive surface of the individual conductive pillar along the second straight direction is shorter than a maximum length of the uppermost conductive surface of the conductive material of the conductive line in the individual longitudinally spaced-apart first region along the second straight direction.

33. The memory circuitry of claim 32, wherein a maximum length of a bottom surface of the conductive line along the first straight direction is longer than a maximum length of the uppermost conductive surface of the conductive material of the conductive line in the individual longitudinally spaced-apart first region along the first straight direction.

34. The memory circuitry of claim 33, wherein the storage devices are capacitors of individual memory cells, the individual memory cells including the capacitors and respective vertical transistors, the capacitors directly coupled to top source / drain regions of the respective vertical transistors, the individual memory cells being one-transistor one-capacitor memory cells.

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