Memory Element and Method of Forming the Same

Abstract

A memory element includes: a plurality of stacked structures disposed on a substrate; and a dielectric layer. Each stacked structure includes: a first conductor layer, a second conductor layer, an intergate dielectric layer, a metal silicide layer, and a barrier layer. The second conductor layer is disposed on the first conductor layer. The intergate dielectric layer is disposed between the first conductor layer and the second conductor layer. The metal silicide layer is disposed on the second conductor layer. The barrier layer is disposed between the metal silicide layer and the second conductor layer. The dielectric layer laterally surrounds a lower portion of the plurality of stacked structures to expose a part of the metal silicide layers of the plurality of stacked structures. A method for forming a memory element is further provided.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a memory device and a method for forming the same. Background Art

[0002] Nonvolatile memories are currently used in various electronic devices, such as for storing structural data, program data, etc. Flash memory is a type of nonvolatile memory, which can perform operations such as multiple data writing, reading, and erasing, and thus has become one of the products with relatively rapid growth in the memory market.

[0003] With the progress of technology, various electronic products are developing towards the trend of being thinner, lighter, shorter, and smaller. Under this trend, the critical dimensions of memories are gradually reduced, which causes the processes of flash memories to face many challenges. For example, in the process of using a metal silicide layer to reduce the resistance of word lines, it is often difficult to control the uniformity of the metal silicide layer, which in turn leads to low yield and poor reliability. Therefore, how to provide a memory device and a method for forming the same to effectively control the uniformity of the metal silicide layer will become an important topic. Summary of the Invention

[0004] The present invention provides a memory device and a method for forming the same, which can improve the uniformity of the resistance of word lines to enhance reliability and yield.

[0005] The present invention provides a memory device including: a plurality of stacked structures disposed on a substrate; and a dielectric layer. Each stacked structure includes: a first conductor layer, a second conductor layer, an inter-gate dielectric layer, a metal silicide layer, and a barrier layer. The second conductor layer is disposed on the first conductor layer. The inter-gate dielectric layer is disposed between the first conductor layer and the second conductor layer. The metal silicide layer is disposed on the second conductor layer. The barrier layer is disposed between the metal silicide layer and the second conductor layer. The dielectric layer laterally surrounds the lower portions of the plurality of stacked structures to expose a part of the metal silicide layers of the plurality of stacked structures.

[0006] The present invention provides a method for forming a memory device including: forming a plurality of stacked structures on a substrate, wherein each stacked structure sequentially includes: a first conductor layer, an inter-gate dielectric layer, a second conductor layer, a barrier layer, and a third conductor layer; forming a dielectric layer on the substrate to laterally surround the lower portions of the plurality of stacked structures and expose a part of the third conductor layers of the plurality of stacked structures; forming a metal layer to cover the dielectric layer and the portions of the third conductor layers exposed from the dielectric layer; and performing a metal silicidation process to convert the third conductor layers into metal silicide layers.

[0007] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are given below and described in detail in conjunction with the accompanying drawings. Description of the Drawings

[0008] Figures 1A to 1F is a cross-sectional schematic view of a manufacturing process of a storage element according to an embodiment of the present invention;

[0009] Figures 2A to 2D is a cross-sectional schematic view of a salicide process according to an embodiment of the present invention. Detailed Description of the Embodiments

[0010] Refer to the accompanying drawings of this embodiment to more comprehensively elaborate the present invention. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of the layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals represent the same or similar elements, and will not be repeated in the following paragraphs.

[0011] Figures 1A to 1F is a cross-sectional schematic view of a manufacturing process of a storage element according to an embodiment of the present invention. The storage element described in the following embodiments is exemplified by a flash memory, but the present invention is not limited thereto.

[0012] Please refer to Figure 1A , an embodiment of the present invention provides a method for manufacturing a storage element, and the steps are as follows. First, a substrate 100 is provided. In one embodiment, the substrate 100 can be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor-on-insulator (SOI) substrate. In this embodiment, the substrate 100 is a silicon substrate.

[0013] Next, a tunneling dielectric layer 102 is formed on the substrate 100. In one embodiment, the material of the tunneling dielectric layer 102 can be, for example, silicon oxide, and the forming method can be chemical vapor deposition, thermal oxidation, etc., and its thickness can be between 3 nm and 12 nm, for example, 7 nm.

[0014] Thereafter, a stacked layer 104 is formed on the tunneling dielectric layer 102. Specifically, each stacked layer 104 sequentially includes, from bottom to top: a first conductor layer 106, an inter-gate dielectric layer 108, a second conductor layer 110, a barrier layer 112, and a third conductor layer 114. In one embodiment, the material of the first conductor layer 106 can be, for example, doped polysilicon, undoped polysilicon, or a combination thereof. The formation method can be chemical vapor deposition, and its thickness can be between 70 nm and 90 nm, for example, 80 nm. The inter-gate dielectric layer 108 can be, for example, a composite layer composed of nitride / oxide / nitride / oxide / nitride (NONON), but the present invention is not limited thereto. This composite layer can be three layers, five layers, or more layers. The formation method of the inter-gate dielectric layer 108 can be, for example, chemical vapor deposition, and its thickness can be between 9 nm and 16 nm, for example, 14.5 nm. The material of the second conductor layer 110 can be, for example, doped polysilicon, undoped polysilicon, or a combination thereof. The formation method can be chemical vapor deposition, and its thickness can be between 25 nm and 35 nm, for example, 30 nm. The material of the barrier layer 112 can be, for example, Ti, TiN, Ta, TaN, or a combination thereof. The formation method can be chemical vapor deposition, atomic layer deposition, etc., and its thickness can be between 5 nm and 15 nm, for example, 10 nm. The material of the third conductor layer 114 can be, for example, doped polysilicon, undoped polysilicon, or a combination thereof. The formation method can be chemical vapor deposition, and its thickness can be between 80 nm and 120 nm, for example, 90 nm. In this embodiment, the first conductor layer 106, the second conductor layer 110, and the third conductor layer 114 have the same material, such as doped polysilicon. Additionally, the thickness of the third conductor layer 114 can be greater than the thickness of the second conductor layer 110.

[0015] Then, an oxide layer 116, a polysilicon layer 118, and a hard mask layer 120 are sequentially formed on the stacked layer 104. In one embodiment, the material of the oxide layer 116 can be, for example, tetraethyl orthosilicate (TEOS), which can be formed by chemical vapor deposition, and its thickness can be between 160 nm and 200 nm, for example, 170 nm. The material of the polysilicon layer 118 can be, for example, tensile polysilicon, which can be formed by chemical vapor deposition, and its thickness can be between 70 nm and 90 nm, for example, 80 nm. The hard mask layer 120 can include a carbide layer 122 and an anti-reflection layer 124 located on the carbide layer 122. The material of the carbide layer 122 can be, for example, spin-on-carbon (SoC), and its thickness can be between 120 nm and 200 nm, for example, 165 nm. The material of the anti-reflection layer 124 can be, for example, silicon oxynitride, and its thickness can be between 15 nm and 40 nm, for example, 27 nm.

[0016] Please refer to Figure 1A and Figure 1B , and perform a Self-Aligning Double Patterning (SADP) process to pattern the stacked layer 104 into a plurality of stacked structures 204. The detailed steps of the above self-aligning double patterning process should be well-known to those of ordinary skill in the art and will not be elaborated herein. In an alternative embodiment, a Self-Aligning Quadruple Patterning (SAQP) process can also be performed to pattern the stacked layer 104 into a stacked structure with a higher pattern density.

[0017] Specifically, as Figure 1B shown, each stacked structure 204 sequentially includes, from bottom to top: a first conductor layer 206, an inter-gate dielectric layer 208, a second conductor layer 210, a barrier layer 212, and a third conductor layer 214. The materials and thicknesses of the first conductor layer 206, the inter-gate dielectric layer 208, the second conductor layer 210, the barrier layer 212, and the third conductor layer 214 are similar to those of the first conductor layer 106, the inter-gate dielectric layer 108, the second conductor layer 110, the barrier layer 112, and the third conductor layer 114 described above and will not be elaborated herein. In this embodiment, the first conductor layer 206 can be used as a floating gate (FG); the second conductor layer 210 can be used as a control gate (CG); the third conductor layer 214 can be used to form a subsequent metal silicide layer 234 (as Figure 1FAs shown); and the entire stacked structure 204 can be used as a word line. After performing the self-aligned double patterning process, it further includes a plurality of capping layers 216 and a plurality of spacer walls 218. The capping layers 216 are respectively disposed on the stacked structure 204. The spacer walls 218 are respectively disposed on the sidewalls of the stacked structure 204.

[0018] Please refer to Figure 1C , a dielectric layer 220 is formed between the stacked structures 204. The dielectric layer 220 laterally surrounds the stacked structure 204 and the capping layer 216. In one embodiment, the material of the dielectric layer 220 can be, for example, tetraethyl orthosilicate (TEOS), and its forming method includes forming a dielectric material by chemical vapor deposition, and then removing part of the dielectric material by a chemical mechanical polishing (CMP) process. In this embodiment, the top surface of the dielectric layer 220 can be substantially coplanar with the top surface of the capping layer 216.

[0019] After that, an oxide layer 222 and a nitride layer 224 are sequentially formed on the dielectric layer 220. The oxide layer 222 covers the top surface of the dielectric layer 220 and the top surface of the capping layer 216. In one embodiment, the material of the oxide layer 222 can be, for example, tetraethyl orthosilicate (TEOS), and its forming method can be chemical vapor deposition, and its thickness can be between 7 nm and 15 nm. The material of the nitride layer 224 can be, for example, silicon nitride, and its forming method can be chemical vapor deposition, and its thickness can be between 15 nm and 25 nm.

[0020] Please refer to Figure 1C and Figure 1D , a chemical mechanical polishing (CMP) process is performed to remove the nitride layer 224 and the oxide layer 222, thereby exposing the top surface of the capping layer 216 and / or the top surface of the dielectric layer 220. Then, an etching back process is performed to remove the capping layer 216, part of the spacer walls 218, and part of the dielectric layer 220 to form a recess 225 between the stacked structures 204. In one embodiment, the etching back process includes multiple etching steps. For example, the etching back process includes a first etching step for removing the capping layer 216, a second etching step for removing the spacer walls 218, and a third etching step for removing the dielectric layer 220. The first etching step, the second etching step, and the third etching step can be performed in different orders. In one embodiment, the etching back process includes a dry etching process, a wet etching process, or a combination thereof. In the above etching back process, the dielectric layer 220 (or the spacer walls 218) has a high etching selectivity with respect to the third conductor layer 214. That is to say, in the above etching back process, the etching rate of the dielectric layer 220 or the spacer walls 218 is greater than the etching rate of the third conductor layer 214. Therefore, most of the dielectric layer 220 and the spacer walls 218 are removed, while the third conductor layer 214 is not removed or only slightly removed, as Figure 1DAs shown. In this embodiment, during the etch-back process, the etch selectivity of the dielectric layer 220 (or the spacer 218) to the third conductor layer 214 is greater than 100:1.

[0021] After performing the etch-back process, as Figure 1D shown, the dielectric layer 220a laterally surrounds the lower part of the stacked structure 204 and exposes the top surface and part of the sidewalls of the third conductor layer 214. The spacer 218a is located between the lower part of the stacked structure 204 and the dielectric layer 220a. That is to say, the spacer 218a also covers the lower part of the stacked structure 204 and exposes the top surface and part of the sidewalls of the third conductor layer 214. In one embodiment, the top surface of the spacer 218a and the top surface of the dielectric layer 220a are substantially coplanar. However, the present invention is not limited thereto. In other embodiments, according to the type of etchant used in the above etch-back process, the top surface of the spacer 218a may also be higher or lower than the top surface of the dielectric layer 220a.

[0022] It should be noted that the top surface of the dielectric layer 220a is at least higher than the top surface of the barrier layer 212 to prevent the second conductor layer 210 under the barrier layer 212 from being silicided by subsequent metal silicidation processes. From another perspective, the bottom surface of the recess 225 is at least higher than the top surface of the barrier layer 212. In one embodiment, the depth 225d of the recess 225 may be between 60 nm and 75 nm, for example, 65 nm. In other embodiments, the ratio of the depth 225d of the recess 225 to the thickness 214t of the third conductor layer 214 may be greater than two-thirds, so that the third conductor layer 214 can be completely metal silicided by subsequent metal silicidation processes.

[0023] Please refer to Figure 1E , a metal layer 226 is formed. The metal layer 226 conformally covers the top surface of the spacer 218a, the top surface of the dielectric layer 220a, and the top surface and part of the sidewalls of the third conductor layer 214 exposed outside the dielectric layer 220a. In one embodiment, the metal layer 226 includes a single-layer structure, a double-layer structure, or a multi-layer structure. For example, when the metal layer 226 is a double-layer structure, the double-layer structure includes a first metal material and a second metal material with different materials. The first metal material can contact the third conductor layer 214 and includes tungsten, titanium, cobalt, tantalum, nickel, platinum, palladium, molybdenum, or a combination thereof, for example, cobalt. The second metal material is disposed on the first metal material and covers the first metal material to prevent the first metal material from oxidizing. The second metal material includes TiN, TaN, ZrN, WN, or a combination thereof, for example, TiN. On the other hand, when the metal layer 226 is a single-layer structure, the material of the metal layer 226 can be, for example, a metal material such as tungsten, titanium, cobalt, tantalum, nickel, platinum, palladium, molybdenum, or a combination thereof. However, the present invention is not limited thereto. In other embodiments, as long as a metal silicide layer can be formed with the third conductor layer 214 (i.e., polysilicon material), it is within the scope of the present invention.

[0024] Please refer to Figure 1E and Figure 1F , perform a metal silicidation process to transform the third conductor layer 214 into a metal silicide layer 234. In this embodiment, the third conductor layer 214 can be completely transformed into the metal silicide layer 234, and the metal silicide layer 234 is in direct contact with the barrier layer 212. It should be noted that the barrier layer 212 can be used as a barrier layer in the metal silicidation process to completely metal-silicidize the upper third conductor layer 214 while preventing the lower second conductor layer 210 from being metal-silicidized. In this case, as Figure 1F shown, the metal silicide layers 234 of each stacked structure 204 have substantially the same shape. Specifically, the stacked structure 204 includes a first stacked structure 204a and a second stacked structure 204b. The first metal silicide layer 234a of the first stacked structure 204a has a first bottom area A1, and the second metal silicide layer 234b of the second stacked structure 204b has a second bottom area A2 that is substantially equal to the first bottom area A1. Based on the above, the embodiment of the present invention improves the uniformity of the metal silicide layer 234 through the barrier layer 212 to improve the uniformity of the resistance value of the word line (i.e., the stacked structure 204), thereby improving the reliability and yield.

[0025] Figures 2A to 2D is a cross-sectional schematic diagram of a metal silicidation process according to an embodiment of the present invention.

[0026] Please refer to Figure 2A , an embodiment of the present invention provides a metal silicidation process, and the steps are as follows. First, a metal layer 226 is conformally formed to cover the top surface of the dielectric layer 220a and the top surface and part of the sidewalls of the third body layer 214 exposed to the dielectric layer 220a. Figure 2A The structure of Figure 1E corresponds to the structure of

[0027] Please refer to Figure 2B , perform a first heat treatment 10 to transform the metal layer 226 and the first part of the third conductor layer 214 in contact therewith into a first metal silicide material 230. Specifically, when the metal layer 226 is a cobalt layer and the third conductor layer 214 is a polysilicon layer, in the first heat treatment 10, Si in the polysilicon layer 214 diffuses to the surface where the cobalt layer 226 contacts the polysilicon layer 214 to form a high-resistance phase cobalt silicide (Co2Si / CoSi) 230. In one embodiment, the first heat treatment 10 can be, for example, rapid thermal annealing (RTA), with a temperature between 300 °C and 600 °C and a time between 10 seconds and 20 seconds.

[0028] Please refer to Figure 2B andFigure 2C , an etching process is performed to remove the unreacted metal layer 226. In one embodiment, the etching process includes a wet etching process. It is worth mentioning that since Si in the polysilicon layer 214 diffuses into the cobalt layer 226 to form cobalt silicide 230 with a high-resistance phase, the cobalt silicide 230 with a high-resistance phase has an extension 232 that extends to cover the top surface of the gap wall 218a and a part of the top surface of the dielectric layer 220a, as Figure 2C shown.

[0029] Please refer to Figure 2D , after removing the unreacted metal layer 226, a second heat treatment 20 is performed to convert the first metal silicide material 230 and the second part of the third conductor layer 214 in contact therewith into a second metal silicide material 234. Herein, the second metal silicide material 234 can be regarded as the metal silicide layer 234 of Figure 1F . The dielectric layer 220a laterally surrounds the lower part of the stacked structure 204 to expose a part of the metal silicide layer 234 of the stacked structure 204. In this embodiment, the resistance value of the second metal silicide material 234 is lower than that of the first metal silicide material 230. Specifically, when the metal layer 226 is a cobalt layer and the third conductor layer 214 is a polysilicon layer, in the second heat treatment 20, Si in the polysilicon layer 214 can further diffuse into the cobalt silicide 230 with a high-resistance phase to convert the cobalt silicide 230 with a high-resistance phase into cobalt silicide (CoSi2) 234 with a low-resistance phase. In one embodiment, the second heat treatment 20 can be, for example, rapid thermal annealing (RTA), the temperature of which is between 650 °C and 850 °C, and the time of which is between 30 seconds and 90 seconds. In this embodiment, the temperature of the second heat treatment 20 is higher than that of the first heat treatment 10, and the time of the second heat treatment 20 is longer than that of the first heat treatment 10.

[0030] In addition, when the second heat treatment 20 is performed, the first metal silicide material 230 covers the top surface and the upper sidewall of the third conductor layer 214. In this case, the upper part of the formed second metal silicide material 234 has a tapered shape. That is to say, the second metal silicide material 234 has a tapered sidewall in the upward extension direction (i.e., the extension direction from the substrate 100 to the metal silicide layer 234).

[0031] In summary, in the embodiment of the present invention, a barrier layer is formed between two polysilicon layers, and the barrier layer is used as a barrier layer in the metal silicidation process to completely metal-silicidize the upper polysilicon layer while preventing the lower polysilicon layer from being metal-silicidized. Therefore, the metal silicide layers of each word line structure can have substantially the same shape to improve the uniformity of the word line resistance value, thereby improving the reliability and yield.

[0032] Although the present invention has been disclosed above by way of examples, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to what is defined by the claims.

Claims

1. A memory element, comprising: a plurality of stacked structures disposed on a substrate, wherein each stacked structure comprises: a first conductor layer; a second conductor layer disposed on the first conductor layer; an inter-gate dielectric layer disposed between the first conductor layer and the second conductor layer; a metal silicide layer disposed on the second conductor layer; and a barrier layer disposed between the metal silicide layer and the second conductor layer; and a dielectric layer laterally surrounding a lower portion of the plurality of stacked structures to expose a portion of the metal silicide layer of the plurality of stacked structures; and a plurality of spacer walls respectively disposed between the plurality of stacked structures and the dielectric layer, wherein the metal silicide layer further extends to cover a top surface of the spacer wall and a partial top surface of the dielectric layer.

2. The memory element according to claim 1, wherein a top surface of the dielectric layer is higher than a top surface of the barrier layer, and wherein a material of the barrier layer comprises Ti, TiN, Ta, TaN, or a combination thereof.

3. The memory element according to claim 1, further comprising: a tunneling dielectric layer disposed between the substrate and the plurality of stacked structures and between the substrate and the dielectric layer, wherein the spacer wall covers the lower portion of the plurality of stacked structures.

4. The memory element according to claim 1, wherein the metal silicide layer is in direct contact with the barrier layer.

5. The memory element according to claim 1, wherein the plurality of stacked structures comprises a first stacked structure and a second stacked structure, a first metal silicide layer of the first stacked structure has a first bottom area, a second metal silicide layer of the second stacked structure has a second bottom area, and the first bottom area is substantially equal to the second bottom area.

6. The memory element according to claim 1, wherein the metal silicide layer has sidewalls tapered in a direction from the substrate towards the metal silicide layer.

7. The memory element according to claim 1, wherein materials of the first conductor layer and the second conductor layer comprise doped polysilicon, undoped polysilicon, or a combination thereof.

8. A method for forming a memory element, comprising: forming a plurality of stacked structures on a substrate, wherein each stacked structure sequentially comprises: a first conductor layer, an inter-gate dielectric layer, a second conductor layer, a barrier layer, and a third conductor layer; forming a dielectric layer on the substrate to laterally surround a lower portion of the plurality of stacked structures and expose a portion of the third conductor layer of the plurality of stacked structures; forming a plurality of spacer walls respectively between the plurality of stacked structures and the dielectric layer; forming a metal layer to cover the dielectric layer and the portion of the third conductor layer exposed from the dielectric layer; and performing a metal silicidation process to convert the third conductor layer into a metal silicide layer, wherein the third conductor layer is completely converted into the metal silicide layer, and the metal silicide layer is in direct contact with the barrier layer, wherein the metal silicide layer further extends to cover a top surface of the spacer wall and a partial top surface of the dielectric layer.

9. The method of forming a storage element according to claim 8, wherein the materials of the first conductor layer, the second conductor layer, and the third conductor layer include doped polysilicon, undoped polysilicon, or a combination thereof.

10. The method of forming a storage element according to claim 8, wherein forming the plurality of stacked structures includes: forming a stacked layer on the substrate; and performing a self-aligned double patterning process to pattern the stacked layer into the plurality of stacked structures.

11. The method of forming a storage element according to claim 8, further comprising: forming a tunneling dielectric layer between the substrate and the plurality of stacked structures and between the substrate and the dielectric layer.

12. The method of forming a storage element according to claim 11, wherein the spacer covers the lower portion of the plurality of stacked structures.

13. The method of forming a storage element according to claim 8, wherein performing the salicidation process includes: performing a first heat treatment to transform the metal layer and a first portion of the third conductor layer in contact therewith into a first metal silicide material; performing an etching process to remove the unreacted metal layer; and performing a second heat treatment to transform the first metal silicide material and a second portion of the third conductor layer in contact therewith into a second metal silicide material, wherein the resistance value of the second metal silicide material is lower than that of the first metal silicide material.

14. The method of forming a storage element according to claim 13, wherein the temperature of the second heat treatment is higher than that of the first heat treatment.

15. The method of forming a storage element according to claim 8, wherein the metal layer includes a single-layer structure, a double-layer structure, or a multi-layer structure.

16. The method of forming a storage element according to claim 15, wherein when the metal layer is the double-layer structure, the double-layer structure includes: a first metal material, contacting the third conductor layer, and including tungsten, titanium, cobalt, tantalum, nickel, platinum, palladium, molybdenum, or a combination thereof; and a second metal material, disposed on the first metal material, and including TiN, TaN, ZrN, WN, or a combination thereof.

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