Array substrate and manufacturing method thereof

Abstract

The application discloses an array substrate and a manufacturing method thereof. The array substrate comprises a scanning line, a gate and a gate insulating layer; a first semiconductor layer and a conductive connecting line formed above the gate insulating layer; an etching blocking part formed above the gate insulating layer, the etching blocking part being above the first semiconductor layer; a source, a drain and a data line formed above the gate insulating layer, the source, the drain and the etching blocking part collectively covering the first semiconductor layer; the data line comprising a plurality of first conductive sections and a plurality of second conductive sections, the first conductive sections being between two adjacent scanning lines, one end of the second conductive sections being electrically connected with the first conductive sections respectively, the other end of the second conductive sections being electrically connected with another first conductive section across the scanning line, and two adjacent second conductive sections being electrically connected with the conductive connecting line respectively. The array substrate has the function of automatically repairing the data line after the data line is broken.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a manufacturing method thereof. BACKGROUND

[0002] With the increasing requirement of product resolution specification, the transmittance requirement is also improved. When designing pixels of LCD products, the data line width is compressed. In the production process, due to the process influence, the space for manufacturing the data line is small, and the uniformity is poor. The data line is prone to breakage due to scratch and other reasons, resulting in yield loss.

[0003] At present, when designing the LCD product, a repair line is reserved on the panel. When the cell is lighted and the defect is found, the laser repair is performed. However, this method increases the laser repair process, resulting in the increase of product cost. In order to increase the stability of the repair line, an OP IC needs to be additionally placed, which increases the cost of the product. At the same time, the load of the repaired line is inconsistent with the adjacent line. Even if the OP IC is used, the weak line still exists in the heavy load picture. Most importantly, the number of broken lines that can be repaired in one panel is limited, generally 1-2, which increases the layout area of the line, and is not conducive to reducing the boundary of the product. SUMMARY

[0004] Therefore, the present application provides an array substrate with the function of automatically repairing the broken data line.

[0005] An array substrate, comprising:

[0006] a substrate;

[0007] a plurality of scan lines and a plurality of gates formed above the substrate, each scan line being electrically connected with each gate;

[0008] a gate insulating layer covering the scan lines and the gates;

[0009] a first semiconductor layer and a conductive connection line formed above the gate insulating layer, the first semiconductor layer being arranged corresponding to the gate;

[0010] an etching barrier layer formed above the gate insulating layer, the etching barrier layer covering the first semiconductor layer;

[0011] a source, a drain and a data line formed above the gate insulating layer, the source being connected with the first semiconductor layer, the drain being connected with the first semiconductor layer, the data line being electrically connected with the source, and the first semiconductor layer being located between the source and the drain;

[0012] The data line is located above the conductive connection line, and the data line comprises a plurality of first conductive segments and a plurality of second conductive segments, each first conductive segment is located between two adjacent scan lines, two ends of the first conductive segment are electrically connected with two adjacent second conductive segments respectively, each second conductive segment crosses the scan line, and each second conductive segment is electrically connected with the conductive connection line.

[0013] In the embodiment of the present application, the conductive connection line comprises a plurality of first conductive sections and a plurality of second conductive sections, the first conductive section is located between two adjacent scan lines, the second conductive section crosses the scan line, two ends of the second conductive section are electrically connected with two adjacent first conductive sections respectively, the first conductive section is electrically connected with the first conductive segment, and the second conductive section is electrically connected with the second conductive segment.

[0014] In the embodiment of the present application, the orthogonal projection of the data line on the substrate is located in the orthogonal projection of the conductive connection line on the substrate, or the orthogonal projection of the conductive connection line on the substrate is located in the orthogonal projection of the data line on the substrate.

[0015] In the embodiment of the present application, the etching barrier layer also covers the conductive connection line, the etching barrier layer is provided with a through hole corresponding to the conductive connection line, and the data line is filled into the through hole and electrically connected with the conductive connection line.

[0016] A manufacturing method of an array substrate, the manufacturing method comprises:

[0017] A substrate is provided;

[0018] A first metal layer is formed on the substrate, the first metal layer is patterned to form a plurality of scan lines and a plurality of gate electrodes, and each scan line is electrically connected with each gate electrode;

[0019] A gate insulating layer is formed on the substrate to cover the scan lines and the gate electrodes;

[0020] A first semiconductor layer, a conductive connection line and an etching barrier layer covering the first semiconductor layer are formed on the gate insulating layer;

[0021] A second metal layer is formed on the gate insulating layer, the second metal layer is patterned to form a source electrode, a drain electrode and a data line, the source electrode is connected with the first semiconductor layer, the drain electrode is connected with the first semiconductor layer, the data line is electrically connected with the source electrode, and the first semiconductor layer is located between the source electrode and the drain electrode;

[0022] The data line is located above the conductive connection lines, and the data line comprises a plurality of first conductive segments and a plurality of second conductive segments, each first conductive segment is located between two adjacent scan lines, and the two ends of the first conductive segment are electrically connected with two adjacent second conductive segments respectively, each second conductive segment crosses the scan lines, and each second conductive segment is electrically connected with the conductive connection lines.

[0023] In the embodiment of the present application, forming the first semiconductor layer and the conductive connection lines above the gate insulating layer comprises:

[0024] forming a full-face metal oxide layer above the gate insulating layer, performing a patterning process on the metal oxide layer, and making the metal oxide layer form the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer is arranged in correspondence with the gate above and below, and the second semiconductor layer is arranged in correspondence with the data line;

[0025] forming a passivation layer and a first photoresist layer above the gate insulating layer to cover the first semiconductor layer and the second semiconductor layer;

[0026] exposing the first photoresist layer by using a first half-tone mask plate, developing the first photoresist layer, removing the first photoresist layer corresponding to the second semiconductor layer to expose the corresponding passivation layer, etching the exposed passivation layer, making the second semiconductor layer exposed through the passivation layer, and performing a conductorization process on the exposed second semiconductor layer to make the second semiconductor layer form the conductive connection lines.

[0027] In the embodiment of the present application, forming the first semiconductor layer and the conductive connection lines above the gate insulating layer comprises:

[0028] forming a full-face metal oxide layer and a second photoresist layer above the gate insulating layer in sequence;

[0029] exposing the second photoresist layer by using a second half-tone mask plate, developing the second photoresist layer, retaining the second photoresist layer corresponding to the first semiconductor layer and the conductive connection lines, performing a patterning process on the metal oxide layer which is not covered by the second photoresist layer, and making the metal oxide layer form the first semiconductor layer and the second semiconductor layer;

[0030] removing the second photoresist layer above the second semiconductor layer to retain the second photoresist layer above the first semiconductor layer, and performing a conductorization process on the second semiconductor layer to make the second semiconductor layer form the conductive connection lines;

[0031] removing the remaining second photoresist layer to expose the first semiconductor layer;

[0032] In an embodiment of the present application, forming the first semiconductor layer and the conductive connection line above the gate insulating layer comprises:

[0033] forming a full-area metal oxide layer above the gate insulating layer, performing a patterning process on the metal oxide layer, so that the metal oxide layer forms the first semiconductor layer and the second semiconductor layer, the first semiconductor layer is directly above the gate, and the second semiconductor layer is arranged corresponding to the data line, the orthographic projection of the second semiconductor layer on the substrate does not coincide with the orthographic projection of the gate and the scan line on the substrate;

[0034] forming a third photoresist layer covering the gate insulating layer, the first semiconductor layer and the second semiconductor layer on the gate insulating layer; exposing the third photoresist layer using the gate as a mask plate or using a light-shielding mask plate for forming the gate and the scan line, developing the third photoresist layer, retaining the third photoresist layer above the first semiconductor layer, removing the third photoresist layer in other regions to expose the second semiconductor layer, and performing a conductorization process on the second semiconductor layer, so that the second semiconductor layer forms the conductive connection line.

[0035] In an embodiment of the present application, forming the etching stop layer covering the first semiconductor layer above the gate insulating layer comprises:

[0036] forming the passivation layer and a fourth photoresist layer covering the gate insulating layer, the first semiconductor layer and the conductive connection line on the gate insulating layer in sequence;

[0037] exposing the fourth photoresist layer, developing the fourth photoresist layer, retaining the fourth photoresist layer opposite to the first semiconductor layer, removing the fourth photoresist layer in other regions and exposing the corresponding passivation layer;

[0038] etching the exposed passivation layer, so that the passivation layer forms the etching stop layer.

[0039] In an embodiment of the present application, forming the etching stop layer covering the first semiconductor layer above the gate insulating layer comprises:

[0040] forming the passivation layer and a fifth photoresist layer covering the gate insulating layer, the first semiconductor layer and the conductive connection line on the gate insulating layer in sequence;

[0041] Exposing the fifth photoresist layer, developing the fifth photoresist layer, removing the fifth photoresist layer corresponding to the first contact hole and the second contact hole at the position above the first semiconductor layer, removing the fifth photoresist layer corresponding to the via hole at the position above the conductive connection line; leaving the fifth photoresist layer in other regions and exposing the corresponding passivation layer.

[0042] Etching the exposed passivation layer to form the etching stop layer, the source electrode and the drain electrode are respectively filled into the first contact hole and the second contact hole and electrically connected with the first semiconductor layer, and the data line is filled into the via hole and electrically connected with the conductive connection line.

[0043] The data line of the array substrate of the present application is located above the conductive connection line, and the data line comprises a plurality of first conductive segments and a plurality of second conductive segments, the first conductive segments are located between adjacent two scan lines, the second conductive segments cross the scan lines, the two ends of the first conductive segment are respectively electrically connected with adjacent two second conductive segments, and each second conductive segment is electrically connected with the conductive connection line. Therefore, at least when a break occurs on the first conductive segment of the data line, the corresponding second conductive segment and the first conductive segment can be electrically connected through the conductive connection line, and the electrical signal transmission of the data line can be realized. When the conductive connection line extends synchronously with the extension direction of the data line and is a continuous conductive connection line, the entire data line can be electrically connected through the conductive connection line when a break occurs at any position of the data line, and the electrical signal transmission of the entire data line can be realized. Therefore, no additional repair line design is needed, the line load is almost unchanged, the risk of weak line is reduced, the number of broken lines to be repaired is unlimited, and finally the data line has the function of automatically repairing after breaking. Finally, without additional repair line design, the overall boundary of the product can be reduced, and no repair OP IC needs to be configured, thereby saving cost. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figures 1 to 2 It is a cross-sectional manufacturing process schematic diagram of the array substrate of the first embodiment of the present application.

[0045] Figure 3 It is a partial planar structure schematic diagram of the array substrate of the first embodiment of the present application.

[0046] Figure 4 It is Figure 3 The array substrate shown in the figure is a cross-sectional manufacturing process schematic diagram along the direction A-A.

[0047] Figures 5 to 7 It is a cross-sectional manufacturing process schematic diagram of the array substrate of the first embodiment of the present application.

[0048] Figure 8This is a partial planar structure diagram of the array substrate according to the first embodiment of the present invention.

[0049] Figure 9 yes Figure 8 The diagram shows a schematic of the fabrication process of the array substrate along the BB direction.

[0050] Figures 10 to 12 This is a cross-sectional fabrication process diagram of the array substrate fabrication method according to the first embodiment of the present invention.

[0051] Figure 13 yes Figure 14 The diagram shows a schematic of the fabrication process of the array substrate along the CC direction.

[0052] Figure 14 This is a partial planar structure diagram of the array substrate according to the first embodiment of the present invention.

[0053] Figure 15 This is a partial planar structure diagram of the array substrate according to the first embodiment of the present invention.

[0054] Figure 16 yes Figure 15 The diagram shows a schematic of the fabrication process of the array substrate along the DD direction.

[0055] Figures 17 to 22 This is a cross-sectional fabrication process diagram of the array substrate fabrication method according to the second embodiment of the present invention.

[0056] Figures 23 to 29 This is a cross-sectional schematic diagram of the fabrication process of the array substrate fabrication method according to the third embodiment of the present invention.

[0057] Figure 30 This is a partial planar structure diagram of the array substrate according to the fourth embodiment of the present invention.

[0058] Figure 31 This is a partial planar structure diagram of the array substrate according to the fifth embodiment of the present invention.

[0059] Figure 32 This is a partial planar structure diagram of the array substrate according to the fifth embodiment of the present invention.

[0060] Figure 33 yes Figure 32 The diagram shows a schematic of the fabrication process of the array substrate along the EE direction.

[0061] Figure 34 This is a schematic cross-sectional view of the array substrate according to the fifth embodiment of the present invention.

[0062] Figure 35 This is a partial planar structure diagram of the array substrate according to the sixth embodiment of the present invention.

[0063] Figure 36 is Figure 35 A cross-sectional manufacturing process diagram of the array substrate along the F-F direction is shown. DETAILED DESCRIPTION

[0064] In order to facilitate the understanding of those skilled in the art, the specific implementation process of the technical solutions provided by the present application is described by the following examples.

[0065] First embodiment

[0066] As Figures 1 to 16 shown, the first embodiment of the present application provides an array substrate and a manufacturing method thereof.

[0067] The manufacturing method of the array substrate comprises:

[0068] S1: providing a substrate 11; the substrate 11 can be made of glass, quartz, acrylic or polycarbonate, etc.

[0069] S2: forming a full-surface first metal layer above the substrate 11, and performing a patterning process on the first metal layer to form a plurality of scan lines 121 and a plurality of gate electrodes 122, each scan line 121 being electrically connected to each gate electrode 122; the first metal layer can be made of copper and molybdenum niobium (Cu / MoNb), or copper and molybdenum (Cu / Mo), or aluminum and molybdenum (Al / Mo), etc.

[0070] S3: forming a gate insulating layer 13 covering the scan lines 121 and the gate electrodes 122 above the substrate 11; the gate insulating layer 13 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, for example.

[0071] S4: as Figures 2 to 11 shown, forming a first semiconductor layer 141, a conductive connection line 142a and an etching stop layer 151 above the gate insulating layer 13. In this embodiment, forming the first semiconductor layer 141, the conductive connection line 142a and the etching stop layer 151 above the gate insulating layer 13 comprises:

[0072] First, a full-surface metal oxide layer 14 is formed above the gate insulating layer 13, and a patterning process is performed on the metal oxide layer 14 to form a first semiconductor layer 141 and a second semiconductor layer 142, the first semiconductor layer 141 being arranged in a one-to-one correspondence with the gate electrodes 122, and the second semiconductor layer 142 being located below the data lines 173. The metal oxide layer 14 is indium gallium zinc oxide (IGZO), for example.

[0073] Second, a passivation layer 15 and a first photoresist layer 16 are formed on the gate insulating layer 13 to cover the first semiconductor layer 141 and the second semiconductor layer 142. The passivation layer 15 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0074] Then, the first photoresist layer 16 is exposed using the first half-tone mask plate 30, which includes a first semi-transparent region 31 corresponding to the first contact hole 101, a second semi-transparent region 32 corresponding to the second contact hole 102, a first full-transparent region 33 corresponding to the second semiconductor layer 142, and a first opaque region 34 corresponding to other regions. After developing the first photoresist layer 16, the corresponding first photoresist layer 16 above the second semiconductor layer 142 is removed to expose the corresponding passivation layer 15, and the remaining first photoresist layer 16 forms a first photoresist 161 and a second photoresist 162, where the thickness of the first photoresist 161 is less than that of the second photoresist 162, the first photoresist 161 is located above the first contact hole 101 and the second contact hole 102, respectively, and the second photoresist 162 is located in other regions.

[0075] Next, the passivation layer 15 is patterned. That is, the exposed passivation layer 15 is first subjected to dry etching to expose the second semiconductor layer 142 through the etching stop layer 151. The exposed second semiconductor layer 142 is then subjected to conductorization treatment to form a conductive connection line 142a. The conductorization treatment includes, for example, plasma treatment (using H2, Ar, or He gas treatment). In this embodiment, the metal oxide layer 14 is patterned to form the second semiconductor layer 142, which is composed of a plurality of spaced semiconductor connection portions. When the second semiconductor layer 142 is subjected to conductorization treatment, it should include conductorization treatment for each semiconductor connection portion to form a first conductive portion 1421. Moreover, the first conductive portion 1421 is located between two adjacent scan lines 121.

[0076] Finally, the first photoresist 161 and the second photoresist 162 are simultaneously subjected to a photoresist ashing and thinning treatment, the first photoresist 161 is removed to expose the passivation layer 15 corresponding to the first contact hole 101 and the second contact hole 102, and the second photoresist 162 after the ashing and thinning treatment is retained. The passivation layer 15 is again subjected to a dry etching treatment to form the first contact hole 101 and the second contact hole 102, and finally the passivation layer 15 forms the etching stop layer 151. The remaining second photoresist 162 is stripped to expose the entire etching stop layer 151. The etching stop layer 151 not only covers the first semiconductor layer 141, but also covers other areas except the conductive connection line 142a, so as to avoid the section of other metal lines from being corroded in subsequent processes.

[0077] S5: A second metal layer 17 is formed above the gate insulating layer 13, and the second metal layer 17 is subjected to a patterning treatment, so that the second metal layer 17 forms a source electrode 171, a drain electrode 172, and a data line 173. The source electrode 171 is connected with the first semiconductor layer 141, the drain electrode 172 is connected with the first semiconductor layer 141, the data line 173 is electrically connected with the source electrode 171, and the first semiconductor layer 141 is located between the source electrode 171 and the drain electrode 172 and is electrically connected with the source electrode 171 and the drain electrode 172. The second metal layer 17 can be made of metal materials such as copper and molybdenum niobium (Cu / MoNb), or copper and molybdenum (Cu / Mo), or aluminum and molybdenum (Al / Mo). In this embodiment, the drain electrode 172 and the source electrode 171 are respectively filled into the first contact hole 101 and the second contact hole 102 and are electrically connected with the first semiconductor layer 141, and the data line 173 directly covers the conductive connection line 142a and can be in contact with the surface of the conductive connection line 142a for electrical conduction.

[0078] The data line 173 includes a plurality of first conductive segments 1731 and a plurality of second conductive segments 1732. The first conductive segment 1731 is located between two adjacent scan lines 121, and the two ends of the first conductive segment 1731 are respectively electrically connected with two adjacent second conductive segments 1732. Each second conductive segment 1732 crosses the scan line 121. Finally, the first conductive segment 1731 and the second conductive segment 1732 are alternately formed to form a whole continuous data line 173. Each second conductive segment 1732 is electrically connected with the conductive connection line 142a. In this embodiment, one end of the first conductive part 1421 is electrically connected with the second conductive segment 1732, and the other end of the first conductive part 1421 is electrically connected with another second conductive segment 1732.

[0079] S6: Forming a first insulating layer 18 covering the source 171, the drain 172 and the data line 173 on the etching stop layer 151, wherein the first insulating layer 18 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx) or a combination of both. The first insulating layer 18 can be patterned at this time to form a part of the third contact hole for electrically connecting the pixel electrode 221 and the drain 172 at the position corresponding to the drain 172. Alternatively, the third contact hole can be formed by directly patterning the first insulating layer 18 in the subsequent process. In the present embodiment, the first insulating layer 18 is not patterned to form a part of the third contact hole.

[0080] S7: Forming a first transparent conductive layer on the first insulating layer 18 and patterning the first transparent conductive layer to form a common electrode 191. The common electrode 191 is electrically connected to a common signal line (not shown). The first transparent conductive layer is made of, for example, transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In the present embodiment, the first transparent conductive layer is made of indium tin oxide (ITO).

[0081] S8: Forming a second insulating layer 21 covering the common electrode 191 on the first insulating layer 18 and patterning the second insulating layer 21 to form the third contact hole penetrating through the second insulating layer 21 and the first insulating layer 18.

[0082] S9: Forming a second transparent conductive layer on the second insulating layer 21 and patterning the second transparent conductive layer to form a pixel electrode 221. The pixel electrode 221 is filled in the third contact hole and electrically connected to the drain 172. The second transparent conductive layer is made of, for example, transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In the present embodiment, the second transparent conductive layer is made of indium tin oxide (ITO).

[0083] The embodiment also provides an array substrate, comprising: a substrate 11; wherein the substrate 11 can be made of glass, quartz, acrylic or polycarbonate material. Further, the array substrate comprises: a plurality of scan lines 121 and a plurality of gate electrodes 122 formed above the substrate 11, each scan line 121 is electrically connected with each gate electrode 122; the scan line 121 and the gate electrode 122 can be made of copper and molybdenum niobium (Cu / MoNb), or copper and molybdenum (Cu / Mo), or aluminum and molybdenum (Al / Mo) and other metal materials. Further, the array substrate comprises: a gate insulating layer 13 covering the scan line 121 and the gate electrode 122; the gate insulating layer 13 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, for example. Further, the array substrate comprises: a first semiconductor layer 141 and a conductive connection line 142a formed above the gate insulating layer 13, the first semiconductor layer 141 is arranged corresponding to the gate electrode 122. In the embodiment, the first semiconductor layer 141 and the conductive connection line 142a are arranged in the same layer and are made of oxide, for example indium gallium zinc oxide (IGZO), and the conductive connection line 142a is obtained by conducting the oxide, wherein the conducting process includes plasma treatment (treatment with H2, Ar or He gas), for example. Further, the array substrate comprises: an etching stop layer 151 formed above the gate insulating layer 13; the etching stop layer 151 is located above the first semiconductor layer 141 to avoid the first semiconductor layer 141 from being affected by etching in subsequent processes. Wherein, the etching stop layer 151 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, for example.

[0084] Further, the etching stop layer 151 is provided with a first contact hole 101 and a second contact hole 102 penetrating the etching stop layer 151, the first contact hole 101 and the second contact hole 102 are arranged at left and right sides of each other, the first contact hole 101 is used for electrically connecting the source 171 and the first semiconductor layer 141, and the second contact hole 102 is used for electrically connecting the drain 172 and the first semiconductor layer 141. In the embodiment, the etching stop layer 151 not only covers the first semiconductor layer 141, but also covers other areas except the conductive connection line 142a, so as to avoid the section of other metal lines from being corroded in subsequent processes. Further, the array substrate comprises: a source 171, a drain 172 and a data line 173 formed above the gate insulating layer 13, the source 171 is connected with the first semiconductor layer 141, the drain 172 is connected with the first semiconductor layer 141, the data line 173 is electrically connected with the source 171, and the first semiconductor layer 141 is located between the source 171 and the drain 172 and is electrically connected with the source 171 and the drain 172. In the embodiment, after the etching stop layer 151 covers the first semiconductor layer 141, the first semiconductor layer 141 can only be exposed from the first contact hole 101 and the second contact hole 102, and when the source 171 and the drain 172 are filled in the first contact hole 101 and the second contact hole 102, the first semiconductor layer 141 is completely covered by the etching stop layer 151, the source 171 and the drain 172. The source 171, the drain 172 and the data line 173 are formed by the same layer of metal material, specifically, the source 171, the drain 172 and the data line 173 can be made of copper and molybdenum niobium (Cu / MoNb), or copper and molybdenum (Cu / Mo), or aluminum and molybdenum (Al / Mo) and the like. Further, the data line 173 is located above the conductive connection line 142a, the data line 173 comprises a plurality of first conductive segments 1731 and a plurality of second conductive segments 1732, the first conductive segments 1731 are located between adjacent two scan lines 121, the second conductive segments 1732 cross the scan lines 121, two ends of the first conductive segment 1731 are electrically connected with adjacent two second conductive segments 1732 respectively, and each second conductive segment 1732 is electrically connected with the conductive connection line 142a. The first conductive segments 1731 and the second conductive segments 1732 are arranged in a reciprocating cycle to form a continuous data line 173. In the embodiment, two ends of each first conductive segment 1731 extend to positions close to the adjacent two scan lines 121 (i.e., the length of the first conductive segment 1731 is equal to or slightly smaller than the interval between the adjacent two scan lines 121).

[0085] Further, the conductive connecting line 142a comprises a plurality of first conductive portions 1421, each of which is arranged at intervals, each of which extends along the extension direction of the data line 173, and each of which corresponds to a first conductive segment 1731. In this embodiment, the total number of the first conductive portions 1421 is equal to the total number of the first conductive segments 1731. Since the data line 173 (i.e., the first conductive segment 1731) between two adjacent scan lines 121 is most likely to form a weak line portion due to the process, the weak line risk can be solved by arranging the first conductive portion 1421 below the first conductive segment 1731 for reinforcement, without the need for additional repair of the circuit design. The orthographic projection of the first conductive segment 1731 on the substrate 11 is located within the orthographic projection of the first conductive portion 1421 on the substrate 11, or the orthographic projection of the first conductive portion 1421 on the substrate 11 is located within the orthographic projection of the first conductive segment 1731 on the substrate 11. At the same time, the bottom surface of the first conductive segment 1731 is in complete contact with the surface of the first conductive portion 1421, greatly avoiding the risk brought by the weak line portion. Further, the array substrate further comprises a first insulating layer 18 covering the source electrode 171, the drain electrode 172, the data line 173, and the etching stop layer 151, which is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. Further, the array substrate further comprises a common electrode 191 formed on the first insulating layer 18, which is electrically connected to a common signal line (not shown). The common electrode 191 is made of, for example, transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this embodiment, the common electrode 191 is made of indium tin oxide (ITO). Further, the array substrate further comprises a second insulating layer 21 covering the common electrode 191, which is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

[0086] Further, the array substrate further comprises a pixel electrode 221 formed on the second insulating layer 21, which is electrically connected to the drain electrode 172. The pixel electrode 221 is made of, for example, transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this embodiment, the pixel electrode 221 is made of indium tin oxide (ITO); and the second insulating layer 21 is provided with a third contact hole penetrating through the second insulating layer 21 and the first insulating layer 18, and the pixel electrode 221 is electrically connected to the drain electrode 172 by filling the third contact hole. Further, the array substrate further comprises a plurality of pixel regions surrounded by the plurality of scan lines 121 and the plurality of data lines 173, and the pixel electrode 221 is located in the pixel region. In this embodiment, the data line 173 and the conductive connecting line 142a correspond to each other, and the conductive connecting line 142a is arranged at intervals along the extension direction of the data line 173.

[0087] The data line 173 of the array substrate of the present application is located above the conductive connection line 142a, and the data line 173 comprises a plurality of first conductive segments 1731 and a plurality of second conductive segments 1732, the first conductive segments 1731 are located between two adjacent scan lines 121, the second conductive segments 1732 cross the scan lines 121, the two ends of the first conductive segment 1731 are electrically connected with two adjacent second conductive segments 1732 respectively, and each second conductive segment 1732 is electrically connected with the conductive connection line 142a. Therefore, at least when a break occurs on the first conductive segment 1731 of the data line 173, the corresponding second conductive segment 1732 and the first conductive segment 1731 can be electrically connected through the conductive connection line 142a, and the electrical signal transmission of the data line 173 can be realized. When the conductive connection line 142a extends synchronously with the extension direction of the data line 173 and is a continuous conductive connection line 142a, when a break occurs at any position of the data line 173, the whole data line 173 can be electrically connected through the conductive connection line 142a, and the electrical signal transmission of the whole data line 173 can be realized. Therefore, without additional repair line design, the line load is almost unchanged, the risk of weak line is reduced, the number of broken lines to be repaired is unlimited, and finally the data line 173 has the function of automatic repair after breakage. Finally, without additional repair line design, the overall boundary of the product can be reduced, and the repair OP IC does not need to be configured, thereby saving the cost.

[0088] Second embodiment

[0089] As shown in Figures 17 to 22 The structure of the array substrate provided by the second embodiment of the present application is completely the same as that of the array substrate in the first embodiment. However, the array substrate manufacturing method in the present embodiment is different from the array substrate manufacturing method in the first embodiment, specifically, the manufacturing method in S4 of the first embodiment is different, and other manufacturing method steps are the same

[0090] Specifically, S4 in the present embodiment comprises:

[0091] First, a full-area metal oxide layer 14 and a second photoresist layer 23 are formed in sequence above the gate insulating layer 13. The metal oxide layer 14 is, for example, indium gallium zinc oxide (IGZO). Then, the second photoresist layer 23 is exposed using a second half-tone mask 40, which includes a third semi-transparent region 41, a second fully-transparent region 42, and a second opaque region 43. The third semi-transparent region 41 corresponds to the conductive connection line 142a; the second opaque region 43 corresponds to the first semiconductor layer 141; and the second fully-transparent region 42 corresponds to other regions. The second photoresist layer 23 is developed, i.e., the second photoresist layer 23 corresponding to the first semiconductor layer 141 and the conductive connection line 142a is retained, and the second photoresist layer 23 in other regions is removed. At this time, the remaining part of the second photoresist layer 23 forms a third photoresist 231 and a fourth photoresist 232, the third photoresist 231 covers the surface of the second semiconductor layer 142, and the fourth photoresist 232 covers the surface of the first semiconductor layer 141. The thickness of the third photoresist 231 is less than that of the fourth photoresist 232, and the third photoresist 231 corresponds to covering the conductive connection line 142a, and the fourth photoresist 232 covers the first semiconductor layer 141. Next, the metal oxide layer 14 not covered by the third photoresist 231 and the fourth photoresist 232 is subjected to a patterning process, so that the metal oxide layer 14 forms the first semiconductor layer 141 and the second semiconductor layer 142. The third photoresist 231 and the fourth photoresist 232 are simultaneously subjected to a gray-scale thinning process, the third photoresist 231 is removed to expose the second semiconductor layer 142, and the fourth photoresist 232 after the gray-scale thinning process is retained. The exposed second semiconductor layer 142 is subjected to a conductorization process, so that the second semiconductor layer 142 forms the conductive connection line 142a, and then the fourth photoresist 232 is peeled off. The conductorization process includes, for example, plasma treatment (using H2, Ar, or He gas treatment). In this embodiment, the metal oxide layer 14 is subjected to a patterning process, so that the metal oxide layer 14 forms the second semiconductor layer 142, and the second semiconductor layer 142 is composed of a plurality of semiconductor connection portions arranged at intervals. When the second semiconductor layer 142 is subjected to a conductorization process, each semiconductor connection portion is subjected to a conductorization process to form a first conductive portion 1421. Moreover, the first conductive portion 1421 is located between two adjacent scan lines 121.

[0092] Finally, a passivation layer 15 is formed above the gate insulating layer 13, covering the gate insulating layer 13, the first semiconductor layer 141, and the conductive connection line 142a. The passivation layer 15 is, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. Then, the passivation layer 15 is patterned, i.e., dry-etched to form the first contact hole 101 and the second contact hole 102, ultimately forming the etch barrier layer 151. In this embodiment, the drain 172 and the source 171 are filled into the first contact hole 101 and the second contact hole 102, respectively, and electrically connected to the first semiconductor layer 141. After the drain 172 and the source 171 are filled into the first contact hole 101 and the second contact hole 102, they together with the etch barrier layer 151 cover the first semiconductor layer 141, preventing the first semiconductor layer 141 from being corroded in subsequent processes. Meanwhile, the etch barrier layer 151 not only covers the first semiconductor layer 141, but also covers other areas except for the conductive connection line 142a, preventing the cross-sections of other metal lines from being corroded in subsequent processes. The data line 173 directly covers the conductive connection line 142a and can contact the surface of the conductive connection line 142a to conduct electricity.

[0093] For details regarding the structure of the array substrate and other steps in the fabrication method of the array substrate, please refer to the first embodiment; they will not be repeated here.

[0094] Third Embodiment

[0095] like Figures 23 to 29 As shown, the structure of the array substrate provided in the third embodiment of the present invention is exactly the same as that of the array substrate in the first embodiment. However, the fabrication method of the array substrate in this embodiment is different from that in the first embodiment, specifically, it is different from the fabrication method in S4 of the first embodiment, while the other fabrication steps are the same.

[0096] Specifically, S4 in this embodiment includes:

[0097] First, a full-surface metal oxide layer 14 is formed above the gate insulating layer 13. The metal oxide layer 14 is patterned to form a first semiconductor layer 141 and a second semiconductor layer 142. The first semiconductor layer 141 is located directly above the gate 122, and the second semiconductor layer 142 is located directly below the data line 173. The orthogonal projection of the second semiconductor layer 142 onto the substrate 11 does not coincide with the orthogonal projections of the gate 122 and the scan line 121 onto the substrate 11. In this embodiment, the metal oxide layer 14 is, for example, indium gallium zinc oxide (IGZO).

[0098] Then, a third photoresist layer 24 is formed on the gate insulating layer 13 to cover the gate insulating layer 13, the first semiconductor layer 141 and the second semiconductor layer 142. The third photoresist layer 24 is exposed by using the gate 122 as a mask or by using the light-shielding mask plate 50 used for forming the gate 122 and the scan line 121, and then developed. The third photoresist layer 24 above the first semiconductor layer 141 is retained, and the third photoresist layer 24 in other regions is removed to expose the second semiconductor layer 142. The second semiconductor layer 142 is subjected to a conductorization treatment, and then the remaining third photoresist layer 24 is peeled off after the second semiconductor layer 142 forms the conductive connection line 142a. The conductorization treatment includes, for example, plasma treatment (treatment with H2, Ar or He gas).

[0099] Finally, a passivation layer 15 is formed on the gate insulating layer 13 to cover the gate insulating layer 13, the first semiconductor layer 141 and the conductive connection line 142a. The passivation layer 15 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx) or a combination of both. Then, the passivation layer 15 is subjected to a patterning treatment, i.e. dry etching of the passivation layer 15 to form the first contact hole 101 and the second contact hole 102, and finally an etching stop layer 151 is obtained. In this embodiment, the drain 172 and the source 171 are filled into the first contact hole 101 and the second contact hole 102, respectively, to be electrically connected to the first semiconductor layer 141. After the drain 172 and the source 171 are filled into the first contact hole 101 and the second contact hole 102, respectively, the drain 172 and the source 171 together with the etching stop layer 151 cover the first semiconductor layer 141 to avoid the first semiconductor layer 141 from being corroded in subsequent processes. Meanwhile, the etching stop layer 151 covers not only the top of the first semiconductor layer 141 but also other regions except the conductive connection line 142a to avoid the cross sections of other metal lines from being corroded in subsequent processes. The data line 173 directly covers the conductive connection line 142a and can be in contact with the surface of the conductive connection line 142a to conduct electricity.

[0100] The structure of the array substrate and other steps of the method for manufacturing the array substrate are the same as those of the first embodiment, and thus will not be described here.

[0101] Fourth Embodiment

[0102] As Figure 30As shown, the array substrate provided by the fourth embodiment of the present application has the same structure as the array substrate in the first embodiment, except that the conductive connection line in the present embodiment is different from the conductive connection line in the first embodiment.

[0103] Specifically, in the present embodiment, please refer to Figure 30 and Figure 31 As shown, the conductive connection line 142a includes a plurality of first conductive portions 1421 and a plurality of second conductive portions 1422. The first conductive portions 1421 are located between two adjacent scan lines 121, and the second conductive portions 1422 cross the scan lines 121. The two ends of each second conductive portion 1422 are electrically connected to two adjacent first conductive portions 1421, and the continuous conductive connection line 142a is formed by repeating the above-mentioned structure. The conductive connection line 142a extends synchronously with the data line 173. The first conductive portions 1421 are electrically connected to the first conductive segments 1731, and the second conductive portions 1422 are electrically connected to the second conductive segments 1732. The total number of the first conductive portions 1421 is equal to the total number of the first conductive segments 1731, and the total number of the second conductive portions 1422 is equal to the total number of the second conductive segments 1732.

[0104] In the present embodiment, the orthogonal projection of the first conductive portions 1421 on the substrate 11 is located within the orthogonal projection of the first conductive segments 1731 on the substrate 11, or the orthogonal projection of the first conductive segments 1731 on the substrate 11 is located within the orthogonal projection of the first conductive portions 1421 on the substrate 11. The orthogonal projection of the second conductive portions 1422 on the substrate 11 is located within the orthogonal projection of the second conductive segments 1732 on the substrate 11, or the orthogonal projection of the second conductive segments 1732 on the substrate 11 is located within the orthogonal projection of the second conductive portions 1422 on the substrate 11. In the present embodiment, the bottom surface of the first conductive segments 1731 is in complete contact with and electrically connected to the surface of the first conductive portions 1421, and the bottom surface of the second conductive segments 1732 is in complete contact with and electrically connected to the surface of the second conductive portions 1422. Therefore, compared with the arrangement of the conductive connection line 142a in the first embodiment, if the data line 173 is broken at any position, the electrical signal transmission of the data line 173 can be realized through the conductive connection line 142a, without additional repair line design, almost no change in line load, no weak line risk, no limit to the number of broken lines to be repaired, and thus the data line 173 has the function of automatically repairing after being broken. Since no additional repair line design is needed, the overall boundary of the product can be reduced, and no repair OP IC is needed, thereby saving cost.

[0105] For other structures of the array substrate, please refer to the first embodiment, and for the manufacturing method of the array substrate, please refer to the manufacturing method of the array substrate in the first embodiment and the second embodiment, which will not be described here.

[0106] Fifth embodiment

[0107] like Figures 31 to 34 As shown, the structure of the array substrate provided in the fifth embodiment of the present invention is basically the same as that of the array substrate in the fourth embodiment. The difference is that the conductive connection lines in this embodiment are different from those in the first embodiment, and the etch barrier layer is different from that in the first embodiment.

[0108] In this embodiment, the array substrate includes a first semiconductor layer 141 and conductive interconnects 142a formed above the gate insulating layer 13, with the first semiconductor layer 141 corresponding to the gate 122. In this embodiment, the first semiconductor layer 141 and the conductive interconnects 142a are disposed in the same layer and are both made of oxides such as indium gallium zinc oxide (IGZO). The conductive interconnects 142a are obtained after a conductor treatment, which may include, for example, plasma treatment (treatment with gases such as H2, Ar, or He). In this embodiment, the array substrate includes an etch barrier layer 151 formed above the gate insulating layer 13. The etch barrier layer 151 is located above the first semiconductor layer 141 and can prevent the first semiconductor layer 141 from being affected by etching in subsequent processes. The etch barrier layer 151 may be, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0109] In this embodiment, the etch stop layer 151 only covers the surface of the first semiconductor layer 141, and other areas are not covered by the etch stop layer 151. The source 171 and drain 172 are directly electrically connected to both ends of the first semiconductor layer 141. Finally, the source 171, drain 172, and etch stop layer 151 together completely cover the first semiconductor layer 141. This also prevents the first semiconductor layer 141 from being affected by subsequent etching processes. Most importantly, apart from the metal oxide layer 14 covered by the etch stop layer 151 forming the first semiconductor layer 141, the remaining parts of the metal oxide layer 14 can all serve as part of the conductive connection line 142a. This increases the area of ​​the conductive connection line 142a, ultimately allowing for better conductivity between the data line 173 and the conductive connection line 142a, further ensuring the automatic repair function of the data line 173. In this embodiment, the conductive connection line 142a is in contact with the first semiconductor layer 141.

[0110] This embodiment also provides a method for manufacturing an array substrate, and the method for manufacturing an array substrate in this embodiment is basically the same as the method for manufacturing an array substrate in the first embodiment, the second embodiment and the third embodiment, except that the method for manufacturing the etch barrier layer 151 is different.

[0111] Specifically: A passivation layer 15 and a fourth photoresist layer covering the gate insulating layer 13, the first semiconductor layer 141 and the conductive connection line 142a are sequentially formed above the gate insulating layer 13; then, the fourth photoresist layer is exposed and developed, the fourth photoresist layer opposite to the first semiconductor layer 141 is retained, the fourth photoresist layer in other areas is removed and the corresponding passivation layer 15 is exposed; finally, the exposed passivation layer 15 is etched to form an etch barrier layer 151.

[0112] For other structures of the array substrate, please refer to the first embodiment. For other fabrication methods and steps of the array substrate, please refer to the fabrication methods of the array substrate in the first, second and third embodiments, which will not be repeated here.

[0113] Sixth Embodiment

[0114] like Figures 35 to 36 As shown, the structure of the array substrate provided in the sixth embodiment of the present invention is basically the same as that of the array substrate in the first embodiment. The difference is that the etch barrier layer in this embodiment is different from that in the first embodiment.

[0115] Specifically, in this embodiment, the array substrate includes an etch barrier layer 151 covering the surfaces of the gate insulating layer 13, the first semiconductor layer 141, and the conductive connection line 142a. The etch barrier layer 151 covers the surfaces of the gate insulating layer 13, the first semiconductor layer 141, and the conductive connection line 142a, thus preventing the first semiconductor layer 141 and the conductive connection line 142a from being etched in subsequent processes. The etch barrier layer 151 may be, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0116] In the embodiment, the etching stop layer 151 is provided with a first contact hole 101 and a second contact hole 102 penetrating the etching stop layer 151, the first contact hole 101 and the second contact hole 102 are arranged at left and right sides of the etching stop layer 151, the first contact hole 101 is used for electrically connecting the source 171 and the first semiconductor layer 141, and the second contact hole 102 is used for electrically connecting the drain 172 and the first semiconductor layer 141. In the embodiment, the etching stop layer 151 covers not only the surfaces of the first semiconductor layer 141 and the conductive connection line 142a, but also other regions except the first semiconductor layer 141 and the conductive connection line 142a, so as to avoid the section of other metal lines from being corroded in subsequent processes. The etching stop layer 151 is further provided with a plurality of through holes 103, and the plurality of through holes 103 are arranged corresponding to the conductive connection line 142a. Accordingly, the data line 173 is filled into each through hole 103 and electrically connected with the conductive connection line 142a. In the embodiment, at least one through hole 103 is formed between the second conductive segment 1732 and the conductive connection line 142a, and at least one through hole 103 can also be formed between the first conductive segment 1731 and the conductive connection line 142a. Therefore, by covering the conductive connection line 142a with the etching stop layer 151 and electrically connecting the data line 173 and the conductive connection line 142a through the plurality of through holes 103, not only the conductive connection line 142a is prevented from being corroded in subsequent processes, but also the automatic repair function of the data line 173 is realized.

[0117] The embodiment further provides a manufacturing method of an array substrate, and the manufacturing method of the array substrate of the embodiment is basically the same as the manufacturing methods of the array substrates in the second embodiment and the third embodiment, and the difference lies in the manufacturing method of the etching stop layer 151.

[0118] Specifically, a passivation layer 15 and a fifth photoresist layer covering the gate insulating layer 13, the first semiconductor layer 141 and the conductive connection line 142a are sequentially formed above the gate insulating layer 13; the fifth photoresist layer is exposed and developed, the fifth photoresist layer corresponding to the first contact hole 101 and the second contact hole 102 is removed at a position above the first semiconductor layer 141, and the fifth photoresist layer corresponding to the through hole 103 is removed at a position above the conductive connection line 142a; the fifth photoresist layer in other regions is left and the corresponding passivation layer 15 is exposed; the exposed passivation layer 15 is etched, so that the passivation layer 15 forms the etching stop layer 151.

[0119] For other structures of the array substrate, refer to the first embodiment, the fourth embodiment or the fifth embodiment, and for other manufacturing method steps of the array substrate, refer to the manufacturing methods of the array substrates in the second embodiment and the third embodiment, which will not be described herein.

[0120] In this article, the orientation words such as up, down, left, right, front, back and the like are defined with the position of the structure in the drawing and the position of the structure relative to each other, just to express the technical solution clearly and conveniently. It should be understood that the use of orientation words should not limit the scope of the application claimed. It should also be understood that the terms "first" and "second" used herein are only used for name distinction and do not limit the quantity and order.

[0121] The above is only the preferred embodiment of the present application, not any form of limitation on the present application, although the present application has been disclosed as above with the preferred embodiment, however, it is not intended to limit the present application, any person skilled in the art, without departing from the technical solution range of the present application, can make some changes or modifications to the above disclosed technical content, as equivalent embodiments of equivalent changes, but as long as it does not deviate from the technical solution content of the present application, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, still belongs to the protection scope of the technical solution of the present application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate (11); a plurality of scan lines (121) and a plurality of gate electrodes (122) formed above the substrate (11), each of the scan lines (121) being electrically connected with each of the gate electrodes (122) respectively; a gate insulating layer (13) covering the scan lines (121) and the gate electrodes (122); a first semiconductor layer (141) and a conductive connecting line (142a) formed above the gate insulating layer (13), the first semiconductor layer (141) being arranged correspondingly to the gate electrodes (122); an etching stop layer (151) formed above the gate insulating layer (13), the etching stop layer (151) covering the first semiconductor layer (141); a source electrode (171), a drain electrode (172) and a data line (173) formed above the gate insulating layer (13), the source electrode (171) being connected with the first semiconductor layer (141), the drain electrode (172) being connected with the first semiconductor layer (141), the data line (173) being electrically connected with the source electrode (171), the first semiconductor layer (141) being located between the source electrode (171) and the drain electrode (172); the data line (173) being located above the conductive connecting line (142a), the data line (173) comprising a plurality of first conductive segments (1731) and a plurality of second conductive segments (1732), each of the first conductive segments (1731) being located between two adjacent scan lines (121), two ends of the first conductive segment (1731) being electrically connected with two adjacent second conductive segments (1732) respectively, each of the second conductive segments (1732) crossing the scan line (121), each of the second conductive segments (1732) being electrically connected with the conductive connecting line (142a).

2. The array substrate of claim 1, wherein, the conductive connecting line (142a) comprising a plurality of first conductive portions (1421) and a plurality of second conductive portions (1422), the first conductive portions (1421) being located between two adjacent scan lines (121), the second conductive portions (1422) crossing the scan line (121), two ends of the second conductive portion (1422) being electrically connected with two adjacent first conductive portions (1421) respectively, the first conductive portions (1421) being electrically connected with the first conductive segments (1731), the second conductive portions (1422) being electrically connected with the second conductive segments (1732).

3. The array substrate of claim 1, wherein, a projection of the data line (173) on the substrate (11) is located within a projection of the conductive connecting line (142a) on the substrate (11); or, a projection of the conductive connecting line (142a) on the substrate (11) is located within a projection of the data line (173) on the substrate (11).

4. The array substrate according to any one of claims 1 to 3, wherein, The etching barrier layer (151) also covers the conductive connecting line (142a), and the etching barrier layer (151) is provided with a through hole (103) corresponding to the conductive connecting line (142a), and the data line (173) is filled into the through hole (103) and electrically connected with the conductive connecting line (142a).

5. A manufacturing method of an array substrate, characterized by, The manufacturing method comprises: providing a substrate (11); forming a first metal layer on the substrate (11), and performing a patterning process on the first metal layer, so that the first metal layer forms a plurality of scan lines (121) and a plurality of gate electrodes (122), each of the scan lines (121) is electrically connected with each of the gate electrodes (122); forming a gate insulating layer (13) covering the scan lines (121) and the gate electrodes (122) on the substrate (11); forming a first semiconductor layer (141), a conductive connecting line (142a), and an etching barrier layer (151) covering the first semiconductor layer (141) on the gate insulating layer (13); forming a second metal layer (17) on the gate insulating layer (13), and performing a patterning process on the second metal layer (17), so that the second metal layer (17) forms a source electrode (171), a drain electrode (172), and a data line (173), the source electrode (171) is connected with the first semiconductor layer (141), the drain electrode (172) is connected with the first semiconductor layer (141), the data line (173) is electrically connected with the source electrode (171), and the first semiconductor layer (141) is located between the source electrode (171) and the drain electrode (172); the data line (173) is located above the conductive connecting line (142a), and the data line (173) comprises a plurality of first conductive segments (1731) and a plurality of second conductive segments (1732), each of the first conductive segments (1731) is located between two adjacent scan lines (121), two ends of the first conductive segment (1731) are respectively electrically connected with two adjacent second conductive segments (1732), each of the second conductive segments (1732) crosses the scan line (121), and each of the second conductive segments (1732) is electrically connected with the conductive connecting line (142a).

6. The method of manufacturing an array substrate according to claim 5, wherein forming the first semiconductor layer (141) and the conductive connecting line (142a) on the gate insulating layer (13) comprises: forming a metal oxide layer (14) on the gate insulating layer (13), and performing a patterning process on the metal oxide layer (14), so that the metal oxide layer (14) forms the first semiconductor layer (141) and a second semiconductor layer (142), the first semiconductor layer (141) is arranged in correspondence with the gate electrode (122) in an up-down direction, and the second semiconductor layer (142) is arranged in correspondence with the data line (173). Form a passivation layer (15) and a first photoresist layer (16) covering the first semiconductor layer (141) and the second semiconductor layer (142) on the gate insulating layer (13); Exposure is performed on the first photoresist layer (16) by using a first half-tone mask plate (30), the first photoresist layer (16) is developed, the first photoresist layer (16) corresponding to the second semiconductor layer (142) is removed to expose the corresponding passivation layer (15), the exposed passivation layer (15) is etched, the second semiconductor layer (142) is exposed through the passivation layer (15), and the exposed second semiconductor layer (142) is subjected to conductorization treatment, so that the second semiconductor layer (142) forms the conductive connection line (142a).

7. The method of manufacturing an array substrate according to claim 5, wherein The first semiconductor layer (141) and the conductive connection line (142a) are formed above the gate insulating layer (13), and the method comprises the following steps: forming a full-face metal oxide layer (14) and a second photoresist layer (23) above the gate insulating layer (13) in sequence; Exposure is performed on the second photoresist layer (23) by using a second half-tone mask plate (40), the second photoresist layer (23) is developed, the second photoresist layer (23) corresponding to the first semiconductor layer (141) and the conductive connection line (142a) is retained, the metal oxide layer (14) not covered by the second photoresist layer (23) is subjected to patterning treatment, and the metal oxide layer (14) forms the first semiconductor layer (141) and the second semiconductor layer (142); The second photoresist layer (23) covering the second semiconductor layer (142) is removed, the second photoresist layer (23) above the first semiconductor layer (141) is retained, the second semiconductor layer (142) is subjected to conductorization treatment, and the second semiconductor layer (142) forms the conductive connection line (142a); The remaining second photoresist layer (23) is removed to expose the first semiconductor layer (141).

8. The method of manufacturing an array substrate according to claim 5, wherein The first semiconductor layer (141) and the conductive connection line (142a) are formed above the gate insulating layer (13), and the method comprises the following steps: A full-face metal oxide layer (14) is formed above the gate insulating layer (13), the metal oxide layer (14) is subjected to patterning treatment, and the metal oxide layer (14) forms the first semiconductor layer (141) and the second semiconductor layer (142), the first semiconductor layer (141) is located directly above the gate (122), the second semiconductor layer (142) is arranged correspondingly to the data line (173), and the orthographic projection of the second semiconductor layer (142) on the substrate (11) does not coincide with the orthographic projection of the gate (122) and the scan line (121) on the substrate (11). A third photoresist layer (24) covering the gate insulating layer (13), the first semiconductor layer (141) and the second semiconductor layer (142) is formed on the gate insulating layer (13); the third photoresist layer (24) is exposed by using the gate (122) as a mask or by using a light shielding mask plate (50) for forming the gate (122) and the scanning line (121), the third photoresist layer (24) is developed, the third photoresist layer (24) above the first semiconductor layer (141) is reserved, the third photoresist layer (24) in other regions is removed to expose the second semiconductor layer (142), the second semiconductor layer (142) is subjected to a conductorization treatment, and the second semiconductor layer (142) forms the conductive connection line (142a).

9. The method of producing an array substrate according to any one of claims 5, wherein The etching stop layer (151) covering the first semiconductor layer (141) is formed above the gate insulating layer (13), and the etching stop layer (151) is formed by the following steps: A passivation layer (15) and a fourth photoresist layer covering the gate insulating layer (13), the first semiconductor layer (141) and the conductive connection line (142a) are sequentially formed above the gate insulating layer (13); The fourth photoresist layer is exposed and developed, the fourth photoresist layer opposite to the first semiconductor layer (141) is reserved, the fourth photoresist layer in other regions is removed and the corresponding passivation layer (15) is exposed; The exposed passivation layer (15) is etched, and the passivation layer (15) forms the etching stop layer (151).

10. The method of manufacturing an array substrate according to claim 5, wherein The etching stop layer (151) covering the first semiconductor layer (141) is formed above the gate insulating layer (13), and the etching stop layer (151) is formed by the following steps: A passivation layer (15) and a fifth photoresist layer covering the gate insulating layer (13), the first semiconductor layer (141) and the conductive connection line (142a) are sequentially formed above the gate insulating layer (13); The fifth photoresist layer is exposed and developed, the fifth photoresist layer corresponding to the first contact hole (101) and the second contact hole (102) is removed at a position above the first semiconductor layer (141), and the fifth photoresist layer corresponding to the through hole (103) is removed at a position above the conductive connection line (142a); the fifth photoresist layer in other regions is reserved and the corresponding passivation layer (15) is exposed; The exposed passivation layer (15) is etched, and the passivation layer (15) forms the etching stop layer (151), the source electrode (171) and the drain electrode (172) are respectively filled into the first contact hole (101) and the second contact hole (102) and electrically connected with the first semiconductor layer (141), and the data line (173) is filled into the through hole (103) and electrically connected with the conductive connection line (142a).

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