Display device

Abstract

A display device includes a substrate, a first data line, a scan line, a first sub-pixel, a passivation layer, and a common electrode. The first sub-pixel includes a first main driving element, a first sub-driving element, a first capacitive electrode, and a first pixel electrode. The first main driving element includes a first main gate, a first main channel layer, a first main source, and a first main drain. The first sub-driving element includes a first sub-gate, a first sub-channel layer, a first sub-source, and a first sub-drain. The first capacitive electrode is electrically connected to the first main drain and the first sub-source. The first pixel electrode is electrically connected to the first sub-drain. A first main capacitor is provided between the common electrode and the first capacitive electrode. A first sub-capacitor is provided between the common electrode and the first pixel electrode.

Description

[0001] This application is a divisional application. The filing date of the original application is June 21, 2019, and the priority dates are August 10, 2018 and February 20, 2019. The application number of the original application is 201910542067.0, and the invention title of the original application is "Display Device". Technical Field

[0002] The present invention relates to a display device, and more particularly to a display device in which a common electrode overlaps a capacitive electrode and a pixel electrode. Background Art

[0003] In recent years, with the continuous progress of display technology, viewers' requirements for the resolution of display devices have become increasingly high. To improve the resolution of a display device, the size of each sub-pixel in the display device must be reduced. However, sub-pixels with a small size usually have a relatively small storage capacitor, and problems such as a large feed-through voltage or crosstalk are likely to occur, and sometimes even leakage may occur.

[0004] Reducing the frame rate can reduce the power consumption of the display device, thereby increasing the usage time of the display device. However, if the storage capacitor in the display device is too small or the display device leaks electricity, it is easy to make it difficult to reduce the frame rate due to the insufficient ability of the storage capacitor to maintain the voltage. Therefore, in order to increase the usage time of high-resolution display devices, it is currently urgent to improve the problem of leakage in small-size sub-pixels. Summary of the Invention

[0005] The present invention provides a display device that can improve the problem of leakage.

[0006] An embodiment of the present invention provides a display device, including a substrate, a first data line, a scanning line, a first sub-pixel, a passivation layer, and a common electrode. The first data line and the scanning line are located on the substrate. The first sub-pixel is located on the substrate. The first sub-pixel includes a first main driving element, a first sub-driving element, a first capacitive electrode, and a first pixel electrode. The first main driving element includes a first main gate, a first main channel layer, a first main source, and a first main drain. The first main gate is electrically connected to the scanning line. The first main channel layer overlaps the first main gate. The first main source and the first main drain are electrically connected to the first main channel layer. The first main source is electrically connected to the first data line. The first sub-driving element includes a first sub-gate, a first sub-channel layer, a first sub-source, and a first sub-drain. The first sub-gate is electrically connected to the scanning line. The first sub-channel layer overlaps the first sub-gate. The first sub-source and the first sub-drain are electrically connected to the first sub-channel layer. The first main drain is electrically connected to the first sub-source. The first capacitive electrode is electrically connected to the first main drain and the first sub-source. The first pixel electrode is electrically connected to the first sub-drain. The passivation layer is located on the first main source, the first main drain, the first sub-source, and the first sub-drain. The first capacitive electrode and the first pixel electrode are located on the passivation layer. The common electrode overlaps the first capacitive electrode and the first pixel electrode. A first main capacitance exists between the common electrode and the first capacitive electrode. A first sub-capacitance exists between the common electrode and the first pixel electrode. The materials of the first capacitive electrode, the first pixel electrode, and the common electrode include transparent conductive materials.

[0007] Based on the above, the first sub-source of the first sub-driving element is electrically connected to the first capacitive electrode, and the first sub-drain is electrically connected to the first pixel electrode. Thus, the first main capacitance between the common electrode and the first capacitive electrode can reduce the voltage difference between the first sub-drain and the first sub-source and improve the problem of leakage. Even when the voltage applied to the scanning line is stopped (i.e., the first main driving element and the first sub-driving element are turned off), the voltage on the first pixel electrode can still be maintained for a period of time. In this way, the energy consumption can be reduced by reducing the frame rate of the display device.

[0008] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but it is not intended to limit the present invention. Description of the Drawings

[0009] Figure 1A is a top view schematic diagram of a display device according to an embodiment of the present invention.

[0010] Figure 1B is along Figure 1A a cross-sectional schematic diagram taken along line aa'.

[0011] Figure 1C is along Figure 1A a cross-sectional schematic diagram taken along line bb'.

[0012] Figure 2 is a top view schematic diagram of a display device according to an embodiment of the present invention.

[0013] Figure 3A is a top view schematic diagram of a display device according to an embodiment of the present invention.

[0014] Figure 3B is along Figure 3A a cross-sectional schematic diagram taken along line aa'.

[0015] Figure 3C is along Figure 3A a cross-sectional schematic diagram taken along line bb'.

[0016] Figure 4 is a top view schematic diagram of a display device according to an embodiment of the present invention.

[0017] Wherein, reference numerals:

[0018] 10, 20, 30, 40: display device

[0019] AA: display area

[0020] BM: black matrix

[0021] CE1: first capacitive electrode

[0022] CE2: second capacitive electrode

[0023] CE3: third capacitive electrode

[0024] CF: color conversion element

[0025] CM: common electrode

[0026] DD: source driver circuit

[0027] DL: data line

[0028] DL1: first data line

[0029] DL2: second data line

[0030] DL3: third data line

[0031] I1: first dielectric material layer

[0032] I2: second dielectric material layer

[0033] N: direction

[0034] M: display medium layer

[0035] MCH1: first main channel layer

[0036] MCH2: Second main channel layer

[0037] MCH3: third main channel layer

[0038] MD1: First main drain

[0039] MD2: Second main drain

[0040] MD3: Third main drain

[0041] MG1: First main gate

[0042] MG2: Second main gate

[0043] MG3: Third main gate

[0044] MS1: First main source

[0045] MS2: Second main source

[0046] MS3: The third main source

[0047] GD: Gate drive circuit

[0048] GI: Gate Insulator

[0049] O: Open

[0050] PE1: first pixel electrode

[0051] PE2: second pixel electrode

[0052] PE3: third pixel electrode

[0053] PV: Passivation layer

[0054] PX1: Second sub-pixel

[0055] PX2: First sub-pixel

[0056] PX3: third sub-pixel

[0057] SB1: Base board

[0058] SB2: Opposite substrate

[0059] SCH1: first sub-channel layer

[0060] SCH2: Second sub-channel layer

[0061] SCH3: third sub-channel layer

[0062] SD1: First secondary drain

[0063] SD2: Second drain

[0064] SD3: The third drain

[0065] SG1: The first auxiliary gate

[0066] SG2: The second auxiliary gate

[0067] SG3: The third auxiliary gate

[0068] SL: The scan line

[0069] SS1: The first auxiliary source

[0070] SS2: The second auxiliary source

[0071] SS3: The third auxiliary source

[0072] TH1: The first through hole

[0073] TH2: The second through hole

[0074] TH3: The third through hole

[0075] TH4: The fourth through hole

[0076] TH5: The fifth through hole

[0077] TH6: The sixth through hole

[0078] U: The insulating layer Detailed implementation manners

[0079] The structural principle and working principle of the present invention will be specifically described below with reference to the accompanying drawings:

[0080] Figure 1A is a top view schematic diagram of a display device according to an embodiment of the present invention. Figure 1B is along Figure 1A the sectional schematic diagram of line aa'. Figure 1C is along Figure 1A the sectional schematic diagram of line bb'. For the convenience of description, Figure 1A some components in the display device are omitted.

[0081] The display device 10 includes a substrate SB1, a first data line DL1, a scan line SL, a first main gate MG1, a first sub - gate SG1, a first main channel layer MCH1, a first sub - channel layer SCH1, a gate insulating layer GI, a first main source MS1, a first main drain MD1, a first sub - source SS1, a first sub - drain SD1, a passivation layer PV, a first capacitor electrode CE1, a first pixel electrode PE1, and a common electrode CM. In the present embodiment, the display device 10 further includes a second data line DL2, a third data line DL3, a second main gate MG2, a second sub - gate SG2, a second main channel layer MCH2, a second sub - channel layer SCH2, a second main source MS2, a second main drain MD2, a second sub - source SS2, a second sub - drain SD2, a second capacitor electrode CE2, a second pixel electrode PE2, a third main gate MG3, a third sub - gate SG3, a third main channel layer MCH3, a third sub - channel layer SCH3, a third main source MS3, a third main drain MD3, a third sub - source SS3, a third sub - drain SD3, a third capacitor electrode CE3, a third pixel electrode PE3, an insulating layer U, a first dielectric layer I1, a display medium layer M, a counter substrate SB2, a black matrix BM, and a color conversion element CF.

[0082] In the present embodiment, three sub - pixels of the display device 10 are taken as an example for illustration. Among them, a first sub - pixel PX1, a second sub - pixel PX2, and a third sub - pixel PX3 are located on the substrate SB1. The first sub - pixel PX1 includes a first main driving element MT1, a first sub - driving element ST1, a first capacitor electrode CE1, and a first pixel electrode PE1. The second sub - pixel PX2 includes a second main driving element MT2, a second sub - driving element ST2, a second capacitor electrode CE2, and a second pixel electrode PE2. And the third sub - pixel PX3 includes a third main driving element MT3, a third sub - driving element ST3, a third capacitor electrode CE3, and a third pixel electrode PE3.

[0083] The first main gate MG1, the first main channel layer MCH1, the first main source MS1, and the first main drain MD1 form the first main driving element MT1. The first sub-gate SG1, the first sub-channel layer SCH1, the first sub-source SS1, and the first sub-drain SD1 form the first sub-driving element ST1. The second main gate MG2, the second main channel layer MCH2, the second main source MS2, and the second main drain MD2 form the second main driving element MT2. The second sub-gate SG2, the second sub-channel layer SCH2, the second sub-source SS2, and the second sub-drain SD2 form the second sub-driving element ST2. The third main gate MG3, the third main channel layer MCH3, the third main source MS3, and the third main drain MD3 form the third main driving element MT3. The third sub-gate SG3, the third sub-channel layer SCH3, the third sub-source SS3, and the third sub-drain SD3 form the third sub-driving element ST3.

[0084] The first main driving element MT1, the first sub-driving element ST1, the second main driving element MT2, the second sub-driving element ST2, the third main driving element MT3, the third sub-driving element ST3, the first data line DL1, the second data line DL2, the third data line DL3, and the scan line SL are located on the substrate SB1.

[0085] The first main gate MG1 and the first sub-gate SG1 are electrically connected to the scan line SL. The first main channel layer MCH1 and the first sub-channel layer SCH1 overlap the first main gate MG1 and the first sub-gate SG1 respectively in the direction N perpendicular to the substrate SB1. The gate insulating layer GI is located between the first main gate MG1 and the first main channel layer MCH1 and between the first sub-gate SG1 and the first sub-channel layer SCH1. The first main source MS1 and the first main drain MD1 are electrically connected to the first main channel layer MCH1. The first main source MS1 is electrically connected to the first data line DL1. The first sub-source SS1 and the first sub-drain SD1 are electrically connected to the first sub-channel layer SCH1. The first main drain MD1 is electrically connected to the first sub-source SD1. In this embodiment, the first main drain MD1 and the first sub-source SD1 are substantially integrated.

[0086] The second main gate MG2 and the second sub - gate SG2 are electrically connected to the scan line SL. The second main channel layer MCH2 and the second sub - channel layer SCH2 overlap the second main gate MG2 and the second sub - gate SG2 respectively in the direction N perpendicular to the substrate SB1. The gate insulating layer GI is located between the second main gate MG2 and the second main channel layer MCH2 and between the second sub - gate SG2 and the second sub - channel layer SCH2. The second main source MS2 and the second main drain MD2 are electrically connected to the second main channel layer MCH2. The second main source MS2 is electrically connected to the second data line DL2. The second sub - source SS2 and the second sub - drain SD2 are electrically connected to the second sub - channel layer SCH2. The second main drain MD2 is electrically connected to the second sub - source SD2. In this embodiment, the second main drain MD2 and the second sub - source SD2 are substantially integrated into one body.

[0087] The third main gate MG3 and the third sub - gate SG3 are electrically connected to the scan line SL. The third main channel layer MCH3 and the third sub - channel layer SCH3 overlap the third main gate MG3 and the third sub - gate SG3 respectively in the direction N perpendicular to the substrate SB1. The gate insulating layer GI is located between the third main gate MG3 and the third main channel layer MCH3 and between the third sub - gate SG3 and the third sub - channel layer SCH3. The third main source MS3 and the third main drain MD3 are electrically connected to the third main channel layer MCH3. The third main source MS3 is electrically connected to the third data line DL3. The third sub - source SS3 and the third sub - drain SD3 are electrically connected to the third sub - channel layer SCH3. The third main drain MD3 is electrically connected to the third sub - source SD3. In this embodiment, the third main drain MD3 and the third sub - source SD3 are substantially integrated into one body.

[0088] The first main channel layer MCH1, the first sub - channel layer SCH1, the second main channel layer MCH2, the second sub - channel layer SCH2, the third main channel layer MCH3, and the third sub - channel layer SCH3 are each a single - layer or multi - layer structure, and their materials include, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single - crystal silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium gallium zinc oxide, or other suitable materials or combinations thereof), or other suitable materials, or contain dopants in the above materials or combinations thereof.

[0089] The first data line DL1, the second data line DL2, the third data line DL3, the scan line SL, the first main gate MG1, the first sub - gate SG1, the second main gate MG2, the second sub - gate SG2, the third main gate MG1, the third sub - gate SG3, the first main source MS1, the first main drain MD1, the first sub - source SS1, the first sub - drain SD1, the second main source MS2, the second main drain MD2, the second sub - source SS2, the second sub - drain SD2, the third main source MS3, the third main drain MD3, the third sub - source SS3, and the third sub - drain SD3 are each a single - layer or multi - layer structure, and their materials include, for example, metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, alloys of the above - mentioned metals, oxides of the above - mentioned metals, nitrides of the above - mentioned metals, combinations of the above - mentioned materials, or other conductive materials.

[0090] In this embodiment, the main driving element and the sub - driving element take the bottom - gate type thin - film transistor as an example, but the present invention is not limited thereto. In other embodiments, the main driving element and the sub - driving element are top - gate type thin - film transistors, double - gate type thin - film transistors, or other types of thin - film transistors. In other embodiments, each main driving element is not limited to a single thin - film transistor, and each main driving element can be formed by two or more thin - film transistors connected in series. Similarly, each sub - driving element is not limited to a single thin - film transistor, and each sub - driving element can be formed by two or more thin - film transistors connected in series.

[0091] The passivation layer PV is located on the first main source MS1, the first main drain MD1, the first sub - source SS1, the first sub - drain SD1, the second main source MS2, the second main drain MD2, the second sub - source SS2, the second sub - drain SD2, the third main source MS3, the third main drain MD3, the third sub - source SS3, and the third sub - drain SD3.

[0092] The insulating layer U is located on the passivation layer PV. The insulating layer U is, for example, an organic insulating layer, but the present invention is not limited thereto.

[0093] The common electrode CM is located on the insulating layer U. The common electrode CM has a plurality of openings O, and the openings O are arranged corresponding to the positions of the first main drain MD1, the first sub - source SS1, the first sub - drain SD1, the second main drain MD2, the second sub - source SS2, the second sub - drain SD2, the third main drain MD3, the third sub - source SS3, and the third sub - drain SD3.

[0094] The first dielectric material layer I1 is located on the common electrode CM. The first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, and the third pixel electrode PE3 are located on the passivation layer PV. In this embodiment, an insulating layer U, the first dielectric material layer I1, and the common electrode CM are also interposed between the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, and the third pixel electrode PE3 and the passivation layer PV. In this embodiment, the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, and the third pixel electrode PE3 belong to the same film layer, or can be said to be formed in the same mask process, thereby reducing the influence of process deviation on optical properties. In this embodiment, the materials of the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, the third pixel electrode PE3, and the common electrode CM include transparent conductive materials. For example, indium tin oxide, indium zinc oxide, or other metal oxides, or a combination of the above materials.

[0095] In this embodiment, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are located on one side of the scan line SL, and part of the first capacitor electrode CE1, part of the second capacitor electrode CE2, and part of the third capacitor electrode CE3 are located on the other side of the scan line SL.

[0096] The first capacitor electrode CE1 is electrically connected to the first main drain MD1 and the first sub-source SS1. For example, the first capacitor electrode CE1 is electrically connected to the first main drain MD1 and the first sub-source SS1 through the first through hole TH1. The first pixel electrode PE1 is electrically connected to the first sub-drain SD1. For example, the first pixel electrode PE1 is electrically connected to the first sub-drain SD1 through the second through hole TH2.

[0097] The second capacitor electrode CE2 is electrically connected to the second main drain MD2 and the second sub-source SS2. For example, the second capacitor electrode CE2 is electrically connected to the second main drain MD2 and the second sub-source SS2 through the third through hole TH3. The second pixel electrode PE2 is electrically connected to the second sub-drain SD2. For example, the second pixel electrode PE2 is electrically connected to the second sub-drain SD2 through the fourth through hole TH4.

[0098] The third capacitive electrode CE3 is electrically connected to the third main drain MD3 and the third sub-source SS3. For example, the third capacitive electrode CE3 is electrically connected to the third main drain MD3 and the third sub-source SS3 through a fifth via TH5. The third pixel electrode PE3 is electrically connected to the third sub-drain SD3. For example, the third pixel electrode PE3 is electrically connected to the third sub-drain SD3 through a sixth via TH6.

[0099] In the present embodiment, the first via TH1, the second via TH2, the third via TH3, the fourth via TH4, the fifth via TH5, and the sixth via TH6 penetrate through the passivation layer PV, the insulating layer U, and the first dielectric material layer I1. The first via TH1, the second via TH2, the third via TH3, the fourth via TH4, the fifth via TH5, and the sixth via TH6 are provided corresponding to a plurality of openings O of the common electrode CM. In the present embodiment, the first via TH1 and the second via TH2 are juxtaposed along the extending direction of the scanning line SL, the third via TH3 and the fourth via TH4 are juxtaposed along the extending direction of the scanning line SL, and the fifth via TH5 and the sixth via TH6 are juxtaposed along the extending direction of the scanning line SL, thereby reducing the influence of the foregoing vias on the aperture ratio.

[0100] In the present embodiment, the common electrode CM overlaps the first capacitive electrode CE1, the first pixel electrode PE1, the second capacitive electrode CE2, the second pixel electrode PE2, the third capacitive electrode CE3, and the third pixel electrode PE3 in the direction N perpendicular to the substrate SB1. A first main capacitance is provided between the common electrode CM and the first capacitive electrode CE1, and the capacitance value is M1. A first sub-capacitance is provided between the common electrode CM and the first pixel electrode PE1, and the capacitance value is S1. A second main capacitance is provided between the common electrode CM and the second capacitive electrode CE2, and the capacitance value is M2. A second sub-capacitance is provided between the common electrode CM and the second pixel electrode PE2, and the capacitance value is S2. A third main capacitance is provided between the common electrode CM and the third capacitive electrode CE3, and the capacitance value is M3. A third sub-capacitance is provided between the common electrode CM and the third pixel electrode PE3, and the capacitance value is S3. In the present embodiment, S1 = S2 = S3.

[0101] By providing the first main capacitance, the second main capacitance, and the third main capacitance, the voltage holding ability on the pixel electrode can be increased. For example, the first main capacitance between the common electrode CM and the first capacitive electrode CE1 can reduce the voltage difference between the first sub-drain SD1 and the first sub-source SS1 and improve the leakage problem, so that even if the voltage applied to the scanning line SL is stopped (i.e., the first main driving element MT1 and the first sub-driving element ST1 are turned off), the voltage on the first pixel electrode PE1 can still be maintained for a period of time. Therefore, the energy consumption can be reduced by reducing the frame rate of the display device 10.

[0102] In some embodiments, in order to take into account the anti-leakage effect, charging effect, and optical properties of the pixels simultaneously, S1, M1, S2, M2, S3, and M3 satisfy the following relational expressions: 10% of S1 < M1 ≤ 60% of S1, 10% of S2 < M2 ≤ 60% of S2, and 10% of S3 < M3 ≤ 60% of S3.

[0103] The counter substrate SB2 is disposed facing the substrate SB1. The black matrix BM and the color conversion element CF are located on the substrate SB1. The black matrix BM and the color conversion element CF are disposed on the counter substrate SB2. A display medium layer M is sandwiched between the counter substrate SB2 and the substrate SB1. The display medium layer M includes, for example, liquid crystal molecules.

[0104] In the present embodiment, the black matrix BM overlaps the scanning line SL, the first capacitor electrode CE1, the first data line DL1, the first main driving element MT1, the first sub-driving element ST1, the second capacitor electrode CE2, the second data line DL2, the second main driving element MT2, the second sub-driving element ST2, the third capacitor electrode CE3, the third data line DL3, the third main driving element MT3, and the third sub-driving element ST3 in the direction N perpendicular to the substrate SB1.

[0105] In the present embodiment, since some of the first capacitor electrodes CE1, some of the second capacitor electrodes CE2, and some of the third capacitor electrodes CE3 are parallel to the scanning line SL, and the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3 are disposed adjacent to the scanning line SL, the area of the black matrix BM does not need to be very large to cover the first capacitor electrode CE1, the second capacitor electrode CE2, the third capacitor electrode CE3, and the scanning line SL, thereby reducing the influence of the capacitor electrodes on the pixel aperture ratio. In the present embodiment, some of the first capacitor electrodes CE1, some of the second capacitor electrodes CE2, and some of the third capacitor electrodes CE3 parallel to the scanning line SL do not overlap the scanning line SL in the direction N perpendicular to the substrate SB1, but the present invention is not limited thereto. In other embodiments, some of the first capacitor electrodes CE1, some of the second capacitor electrodes CE2, and some of the third capacitor electrodes CE3 parallel to the scanning line SL may overlap the scanning line SL in the direction N perpendicular to the substrate SB1, thereby further reducing the influence of the capacitor electrodes on the aperture ratio. In the present embodiment, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are positioned corresponding to the openings of the black matrix BM.

[0106] The color conversion layer CF includes, for example, a variety of different colors. For example, it includes a red color conversion layer, a green color conversion layer, and a blue color conversion layer. In this embodiment, the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 respectively correspond to the red color conversion layer, the green color conversion layer, and the blue color conversion layer. In other words, the first sub-pixel PX1 is a red sub-pixel, the second sub-pixel PX2 is a green sub-pixel, and the third sub-pixel PX3 is a blue sub-pixel.

[0107] In this embodiment, by adjusting the capacitance value M1 of the first main capacitor, the capacitance value M2 of the second main capacitor, and the capacitance value M3 of the third main capacitor, sub-pixels of different colors have better optical properties. For example, the capacitance value M1 is not equal to the capacitance value M2 and the capacitance value M3, and the capacitance value M2 is not equal to the capacitance value M3. In this embodiment, among the first main capacitor, the second main capacitor, and the third main capacitor, the material of the dielectric layer (the first dielectric material layer I1) between the two electrodes (the capacitor electrode and the common electrode) is the same. The capacitance values M1, M2, and M3 can be adjusted by adjusting the areas of the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3, or by providing openings of different sizes on the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3. For example, the ratio of the capacitance values M1, M2, and M3 is equal to the area ratio of the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3, but the present invention is not limited thereto.

[0108] In some embodiments, since the brightness of the third sub-pixel PX3 (blue sub-pixel) is relatively low and the flicker is less obvious, by adjusting the capacitance value M3 of the third main capacitor to be less than the capacitance value M1 of the first main capacitor and the capacitance value M2 of the second main capacitor, the third sub-pixel PX3 can have a better charging rate. For example, S1, M1, S2, M2, S3, M3 can satisfy the following relationship: 12% of S1 < M1 ≤ 50% of S1, 12% of S2 < M2 ≤ 50% of S2, and 10% of S3 < M3 < 40% of S3.

[0109] In some embodiments, since the brightness of the second sub-pixel PX2 (green sub-pixel) is relatively high and the flicker is more significant, by adjusting the capacitance value M2 of the second main capacitor to be greater than the capacitance value M1 of the first main capacitor and the capacitance value M3 of the third main capacitor, the flicker problem of the second sub-pixel PX2 can be improved. For example, S1, M1, S2, M2, S3, M3 can satisfy the following relationship: 10% of S1 < M1 ≤ 50% of S1, 12% of S2 < M2 ≤ 60% of S2, and 10% of S3 < M3 ≤ 50% of S3.

[0110] Figure 2 is a top view schematic diagram of a display device according to an embodiment of the present invention. It should be noted here that Figure 2 The embodiment of Figures 1A to 1C adopts the component numbers and partial content of the embodiment of

[0111] Figure 2 The display device 20 and Figure 1A The main difference between the display device 10 is that: the first capacitive electrode CE1, the first pixel electrode PE1, the second capacitive electrode CE2, the second pixel electrode PE2, the third capacitive electrode CE3 and the third pixel electrode PE3 of the display device 20 are all located on the same side of the scan line.

[0112] In this embodiment, the first main capacitor and the first sub-capacitor are arranged in parallel along the extension direction of the scan line SL, the second main capacitor and the second sub-capacitor are arranged in parallel along the extension direction of the scan line SL, and the third main capacitor and the third sub-capacitor are arranged in parallel along the extension direction of the scan line SL.

[0113] In the display device 20, the adjustable space of the capacitance value M1 of the first main capacitor, the capacitance value S1 of the first sub-capacitor, the capacitance value M2 of the second main capacitor, the capacitance value S2 of the second sub-capacitor, the capacitance value M3 of the third main capacitor and the capacitance value S3 of the third sub-capacitor is larger than that of the display device 10. For the remaining parts, please refer to the foregoing embodiment, which will not be elaborated here.

[0114] Figure 3A is a top view schematic diagram of a display device according to an embodiment of the present invention. Figure 3B is along Figure 3A The cross-sectional schematic diagram of line aa'. Figure 3C is along Figure 3A The cross-sectional schematic diagram of line bb'. It should be noted here that Figures 3A to 3C The embodiment of Figures 1A to 1C adopts the component numbers and partial content of the embodiment of

[0115] Figures 3A to 3C The display device 30 and Figures 1A to 1C The main difference between the display device 10 is that: the display device 30 further includes a second dielectric material layer I2.

[0116] Please refer to Figures 3A to 3C, the first capacitive electrode CE1, the second capacitive electrode CE2, and the third capacitive electrode CE3 are located on the insulating layer U. The first dielectric material layer I1 is located on the first capacitive electrode CE1, the second capacitive electrode CE2, and the third capacitive electrode CE3. The common electrode CM is located on the first dielectric material layer I1. The second dielectric material layer I2 is located on the common electrode CM. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are located on the second dielectric material layer I2.

[0117] The first capacitive electrode CE1, the second capacitive electrode CE2, and the third capacitive electrode CE3 belong to the same film layer, or can be said to be formed in the same mask process. In this embodiment, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 belong to another film layer, or can be said to be formed in another mask process.

[0118] In this embodiment, the first capacitive electrode CE1 overlaps the common electrode CM and the first pixel electrode PE1 in the direction N perpendicular to the substrate SB1, the second capacitive electrode CE2 overlaps the common electrode CM and the second pixel electrode PE2 in the direction N perpendicular to the substrate SB1, and the third capacitive electrode CE3 overlaps the common electrode CM and the third pixel electrode PE3 in the direction N perpendicular to the substrate SB1. Thereby, the display device 30 has the advantage of a high aperture ratio. In this embodiment, the first capacitive electrode CE1, the second capacitive electrode CE2, and the third capacitive electrode CE3 do not easily affect the setting space of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. By increasing the areas of the first capacitive electrode CE1, the second capacitive electrode CE2, and the third capacitive electrode CE3 to increase the capacitance value M1 of the first main capacitor, the capacitance value M2 of the second main capacitor, and the capacitance value M3 of the third main capacitor, the leakage problem of the display device 30 is improved.

[0119] In this embodiment, the capacitance values M1 of the first main capacitor, the capacitance values S1 of the first sub-capacitor, the capacitance values M2 of the second main capacitor, the capacitance values S2 of the second sub-capacitor, the capacitance values M3 of the third main capacitor, and the capacitance values S3 of the third sub-capacitor can be adjusted by adjusting the materials and / or thicknesses of the first dielectric material layer I1 and the second dielectric material layer I2. The materials and / or thicknesses of the first dielectric material layer I1 and the second dielectric material layer I2 are the same as or different from each other. For the remaining parts, please refer to the foregoing embodiments and will not be elaborated here.

[0120] Figure 4 is a top view schematic diagram of a display device according to an embodiment of the present invention. It must be noted here that Figures 3A to 3C The embodiments of Figures 1A to 1CElement numbers and partial content of the embodiments, where the same or similar element numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to the foregoing embodiments and will not be elaborated herein.

[0121] Figure 4 The main difference between the display device 40 and Figures 1A to 1C the display device 10 is that: the display device 40 further includes a gate driving circuit GD and a source driving circuit DD.

[0122] The gate driving circuit GD is electrically connected to the scanning line SL. The source driving circuit DD is electrically connected to the data line DL (such as Figure 1A the first data line DL1, the second data line DL2, and the third data line DL3).

[0123] In this embodiment, the first sub-pixel PX1 is closer to the gate driving circuit GD than the second sub-pixel PX2. In other words, the first main driving element and the first sub-driving element of the first sub-pixel PX1 are closer to the gate driving circuit GD than the second main driving element and the second sub-driving element of the second sub-pixel PX2, and the loss of the control signal on the scanning line SL when reaching the first sub-pixel PX1 is less than that when reaching the second sub-pixel PX2. Generally speaking, in the prior art, due to the different positions relative to the gate driving circuit GD, the severity of the flicker problem of the first sub-pixel PX1 is different from that of the second sub-pixel PX2. For example, the flicker problem of the second sub-pixel PX2 may be less than that of the first sub-pixel PX1.

[0124] In this embodiment, even if the second sub-pixel PX2 is closer to the center of the display area AA, by making the capacitance value M1 of the first main capacitor greater than the capacitance value M2 of the second main capacitor, the problem of uneven brightness at different positions of the screen of the display device 40 is improved.

[0125] Although in this embodiment, the display device 40 takes gate bilateral driving as an example, the present invention is not limited thereto. In other embodiments, the display device can also be gate unilateral driving.

[0126] In summary, in the display device of the present invention, the sub-source of the sub-driving element is electrically connected to the capacitor electrode, and the sub-drain is electrically connected to the pixel electrode. Thus, the main capacitor between the common electrode and the capacitor electrode can reduce the voltage difference between the sub-drain and the sub-source and improve the leakage problem, so that even when the voltage applied to the scanning line is stopped (i.e., the main driving element and the sub-driving element are turned off), the voltage on the pixel electrode can still be maintained for a period of time. In this way, the energy consumption can be reduced by reducing the frame rate of the display device.

[0127] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention. However, these corresponding changes and modifications should all fall within the protection scope of the appended claims of the present invention.

Claims

1. A display device, characterized in that, Comprising: A substrate; A first data line and a scan line, located on the substrate; A first sub-pixel, located on the substrate, wherein the first sub-pixel includes a first main driving element, a first sub-driving element, a first capacitive electrode, and a first pixel electrode, where The first main driving element includes: A first main gate, electrically connected to the scan line; A first main channel layer, overlapping the first main gate; and A first main source and a first main drain, electrically connected to the first main channel layer, wherein the first main source is electrically connected to the first data line; The first sub-driving element includes: A first sub-gate, electrically connected to the scan line; A first sub-channel layer, overlapping the first sub-gate; and A first sub-source and a first sub-drain, electrically connected to the first sub-channel layer, wherein the first main drain is electrically connected to the first sub-source, the first capacitive electrode is electrically connected to the first main drain and the first sub-source, and the first pixel electrode is electrically connected to the first sub-drain; A passivation layer, located on the first main source, the first main drain, the first sub-source, and the first sub-drain, wherein the first capacitive electrode and the first pixel electrode are located on the passivation layer; A common electrode, overlapping the first capacitive electrode and the first pixel electrode, wherein there is a first main capacitance between the common electrode and the first capacitive electrode, and a first sub-capacitance between the common electrode and the first pixel electrode, and the materials of the first capacitive electrode, the first pixel electrode, and the common electrode include transparent conductive materials; The display device further includes: A second data line and a third data line, located on the substrate; A second sub-pixel and a third sub-pixel, located on the substrate, wherein the second sub-pixel includes: A second main driving element and a second sub-driving element, wherein a second main source of the second main driving element is electrically connected to the second data line, and a second main drain of the second main driving element is electrically connected to a second sub-source of the second sub-driving element; A second capacitive electrode, electrically connected to the second main drain and the second sub-source; A second pixel electrode, electrically connected to a second sub-drain, wherein there is a second main capacitance between the common electrode and the second capacitive electrode, and a second sub-capacitance between the common electrode and the second pixel electrode; The third sub-pixel includes: A third main driving element and a third sub-driving element, wherein a third main source of the third main driving element is electrically connected to the third data line, and a third main drain of the third main driving element is electrically connected to a third sub-source of the third sub-driving element; A third capacitive electrode, electrically connected to the third main drain and the third sub-source; and A third pixel electrode, electrically connected to a third sub-drain, wherein there is a third main capacitance between the common electrode and the third capacitive electrode, and a third sub-capacitance between the common electrode and the second pixel electrode; Among them, the first main capacitor and the first sub-capacitor are arranged in parallel along the extending direction of the scanning line, the second main capacitor and the second sub-capacitor are arranged in parallel along the extending direction of the scanning line, and the third main capacitor and the third sub-capacitor are arranged in parallel along the extending direction of the scanning line; The display device further includes a gate driving circuit and a source driving circuit. The gate driving circuit is electrically connected to the scanning line, and the source driving circuit is electrically connected to the first data line and the second data line. Moreover, the first main driving element and the first sub-driving element are closer to the gate driving circuit than the second main driving element and the second sub-driving element.

2. The display device according to claim 1, wherein Among them, part of the first capacitive electrodes are parallel to the scanning line.

3. The display device according to claim 1, characterized in that, Among them, the capacitance value of the first main capacitor is M1, the capacitance value of the first sub-capacitor is S1, and 10% of S1 < M1 ≦ 60% of S1.

4. The display device according to claim 1, wherein The capacitance value of the first main capacitor is M1, the capacitance value of the second main capacitor is M2, and the capacitance value of the third main capacitor is M3, and M1 is not equal to M2 and M3.

5. The display device according to claim 4, characterized in that, Among them, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, the third sub-pixel is a blue sub-pixel, the capacitance value of the first sub-capacitor is S1, the capacitance value of the second sub-capacitor is S2, and the capacitance value of the third sub-capacitor is S3, where 12% of S1 < M1 ≦ 50% of S1, 12% of S2 < M2 ≦ 50% of S2, and 10% of S3 < M3 < 40% of S3.

6. The display device according to claim 5, wherein Among them, M3 is less than M1 and M2.

7. The display device according to claim 4, characterized in that, Among them, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, the third sub-pixel is a blue sub-pixel, the capacitance value of the first sub-capacitor is S1, the capacitance value of the second sub-capacitor is S2, and the capacitance value of the third sub-capacitor is S3, where 10% of S1 < M1 ≦ 50% of S1, 12% of S2 < M2 ≦ 60% of S2, and 10% of S3 < M3 ≦ 50% of S3.

8. The display device according to claim 7, wherein Among them, M2 is greater than M1 and M3.

9. The display device according to claim 4, wherein Among them, the capacitance value of the first sub-capacitor is S1, the capacitance value of the second sub-capacitor is S2, and the capacitance value of the third sub-capacitor is S3, and S1 = S2 = S3.

10. The display device according to claim 4, characterized in that, Further includes: A gate driving circuit, electrically connected to the scanning line, where the first main driving element is closer to the gate driving circuit than the second main driving element, and M1 is greater than M2.

11. The display device according to claim 1, characterized in that, Among them, the first capacitive electrode and the first pixel electrode belong to different film layers.

12. The display device according to claim 11, wherein Further includes: A first dielectric material layer, located on the first capacitive electrode, and the common electrode is located on the first dielectric material layer; A second dielectric material layer, located on the common electrode, and the first pixel electrode is located on the second dielectric material layer.

13. The display device according to claim 1, characterized in that, Among them, the first capacitive electrode and the first pixel electrode belong to the same film layer.

14. The display device according to claim 13, characterized in that, Further includes: A black matrix, located on the substrate, where in the direction perpendicular to the substrate, the black matrix overlaps the scanning line and the first capacitive electrode.

15. The display device according to claim 1, wherein The first capacitive electrode is electrically connected to the first main drain electrode and the first sub-source electrode through a first via hole, and the first pixel electrode is electrically connected to the first sub-drain electrode through a second via hole. The first via hole and the second via hole penetrate through the passivation layer, and the first via hole and the second via hole are arranged side by side along the extending direction of the scanning line.

16. The display device according to claim 15, wherein the common electrode is located on the passivation layer; a first dielectric material layer is located on the common electrode, and the first capacitive electrode is located on the first dielectric material layer.

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