A method for preparing a vertical structure gallium nitride power transistor

Abstract

The present invention belongs to the field of semiconductor technology, and more specifically, relates to a method for preparing a vertical structure gallium nitride power transistor. By selectively performing regional epitaxy and simultaneously forming a deep trench p-well shielding layer and a groove structure, the electric field of the gate oxide layer can be effectively reduced, and the device reliability problem caused by the high oxide layer electric field can be avoided. At the same time, the damage to the groove and the interface state defects caused by dry etching can be avoided, thereby improving the voltage resistance and reliability of the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and more specifically, relates to a method for preparing a vertical structure gallium nitride power transistor. Background Art

[0002] Compared with lateral structure transistors, vertical structure power transistors are mainly supported by the drift layer, so the breakdown voltage can be increased by increasing the thickness of the drift layer, while keeping the device area unchanged, increasing wafer utilization, and improving device power density. In addition, the peak electric field is moved from the surface to the inside of the device, weakening the current collapse effect and improving reliability.

[0003] Among various vertical GaN field effect transistor structures, the groove MOSFET can reduce the leakage under the off-state withstand voltage through the p-type GaN current blocking layer and reduce the gate leakage through the insulating oxide layer. Compared with other structures, it has the advantages of good withstand voltage, small gate leakage, and easy to achieve normally off. However, the current blocking layer of the traditional groove MOSFET structure is a planar p-type GaN epitaxially grown together with the drift layer, such as Figure 1 As shown in (a), the groove is usually formed by dry etching the epitaxial layer. There are still some key issues in this structure and related processes that affect the electrical performance and reliability of the device:

[0004] (1) The electric field in the gate dielectric layer is too large, which reduces the reliability of the gate dielectric. Since GaN has a large bandgap width, GaN devices can operate at a larger voltage. When the groove MOSFET is in a larger off-state withstand voltage, a large electric field will exist in the gate dielectric layer. In addition, due to the difficulty in controlling the etching depth of dry etching, the bottom of the groove usually goes deep into the drift layer, further increasing the electric field of the gate dielectric layer. On the other hand, the grooves etched by dry etching will have sharper corners, and the smaller radius of curvature causes the electric field lines to gather here, such as Figure 2 (a) As shown. Under a large electric field in the gate dielectric layer, a large number of interface state defects caused by etching will lead to a decrease in the insulation ability of the gate dielectric layer, an increase in gate leakage current, and an increase in the capture of electrons by defect states, resulting in a serious decrease in device reliability and withstand voltage.

[0005] (2) There are difficulties in the process of forming pGaN by ion implantation. In traditional Si and SiC-based devices, in order to reduce the large electric field strength of the gate oxide layer, ion implantation is usually used to form deep pGaN wells on both sides of the groove to shield the electric field at the gate oxide layer. Figure 1 (b) and Figure 2(b) As shown. However, due to the high density and high hardness of GaN materials, the traditional p-type ion implantation process cannot be directly grafted into GaN vertical conduction devices. On the other hand, activating the acceptor impurity Mg implanted in GaN requires a high temperature of about 1300°C, which will cause GaN to decompose at high temperatures and produce nitrogen vacancies. In addition, ion implantation will also cause certain lattice damage and degrade device performance.

[0006] (3) Lattice damage to the groove sidewall introduced by dry etching further reduces the channel electron mobility. When the groove MOSFET is turned on, the current channel is formed by inverting the heavily doped p-type GaN. The ionized impurities of heavily doped p-type GaN have large scattering, resulting in a relatively small channel electron mobility of the groove MOSFET. The grooves of traditional groove MOSFETs are usually formed by dry etching, which will cause lattice damage on the groove surface, increase the surface roughness scattering, further reduce the channel electron mobility, and further increase the on-resistance of the device. Summary of the invention

[0007] In order to overcome the defects in the above-mentioned prior art, the present invention provides a method for preparing a vertical structure gallium nitride power transistor, which can effectively reduce the electric field of the gate oxide layer, reduce the etching damage and defects of the groove, and improve the voltage resistance and reliability of the device.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is: a method for preparing a vertical structure gallium nitride power transistor, comprising the following steps:

[0009] S1. epitaxially growing a device drift region on an n-type conductive substrate by MOCVD;

[0010] S2. Etching the mesa where the p-well needs to be grown by ICP;

[0011] S3. Depositing a mask layer SiO2 on the drift region of the device by PECVD, removing the SiO2 mask layer in the device region where the p-well region and the p-type channel layer need to be formed;

[0012] S4. epitaxially growing a p-type GaN region and an N-type GaN region by MOCVD, and removing the SiO2 mask layer;

[0013] S5. growing a gate dielectric layer on the device formed in step S4;

[0014] S6. Exposing the gate dielectric layer at the location where the source region needs to be evaporated by photolithography and development technology, and removing the gate dielectric layer using a buffered hydrofluoric acid solution;

[0015] S7. Etching an ohmic contact window of the source and p-type GaN region by ICP;

[0016] S8. Depositing Ni / Au metal on the p-type GaN region of the device by electron beam evaporation or magnetron sputtering, and forming a short-circuited ohmic contact by annealing;

[0017] S9. Depositing Ti / Al / Ni / Au metal on the n-type GaN region of the device by electron beam evaporation or magnetron sputtering, and forming an ohmic contact as a source by annealing;

[0018] S10. Ni / Au metal is deposited on the groove region of the device by electron beam evaporation or magnetron sputtering, and a gate electrode is formed by annealing;

[0019] S11. Ti / Al / Ni / Au metal is evaporated on the n-type conductive substrate by electron beam evaporation or magnetron sputtering, and an ohmic contact electrode is formed as a drain by annealing.

[0020] In one embodiment, the step S2 specifically includes:

[0021] S21. Coating a photoresist on the drift region of the device, and determining the p-well etching region by photolithography and development technology;

[0022] S22. Etch the area not covered by the photoresist by ICP to a depth of 0.5 μm to 5 μm.

[0023] In one embodiment, the step S3 specifically includes:

[0024] S31. Depositing a 0.1 μm to 10 μm thick SiO2 mask layer on the device drift region by PECVD;

[0025] S32. Opening a window by photolithography on the SiO2 mask layer where the p-well region and the channel layer are to be formed;

[0026] S33. The SiO2 mask layer not covered by the photoresist is removed by buffered hydrofluoric acid, and the remaining mask layer 3 is 0.05 to 5 μm wide.

[0027] In one embodiment, the step S4 specifically includes:

[0028] S41. Depositing 0.1 μm to 2 μm p-type GaN on the device drift region by MOCVD;

[0029] S42. Depositing 0.1 μm to 2 μm of n-type GaN on the device p-type GaN by MOCVD;

[0030] S43. Removing the SiO2 mask layer by buffered hydrofluoric acid;

[0031] S44. The groove structure formed by selective epitaxy is treated in a TMAH etching solution at 70 to 100°C for more than 1 hour.

[0032] In one of the embodiments, the n-type conductive substrate is an n-type GaN self-supporting substrate with a resistivity ranging from 0.005 Ω·cm to 0.1 Ω·cm and a thickness ranging from 100 μm to 500 μm.

[0033] In one embodiment, the device drift region is an unintentionally doped GaN epitaxial layer, a Si-doped epitaxial layer or an As-doped epitaxial layer with low dislocation density; the thickness of the device drift region is 1 μm to 50 μm, and the carrier concentration is 1×10 14 cm -3 ~5×10 17 cm -3 .

[0034] In one embodiment, the p-type GaN region has a p-type dopant of magnesium and a hole concentration of 1×10 17 cm -3 ~1×10 19 cm -3 , thickness is 0.1μm~5μm.

[0035] In one embodiment, the electron concentration of the source n-type GaN region is 1× 10 18 cm -3 ~3×10 19 cm -3 , thickness is 0.1μm~5μm.

[0036] In one of the embodiments, the gate dielectric layer is made of any one of Al2O3, SiN, and SiO2, and has a thickness of 10 nm to 100 nm.

[0037] In one embodiment, the short-circuit metal material is one of Ni, Au, Pt, Pd, Ir, Mo, Al, Ti or a stacked structure thereof.

[0038] In one embodiment, the material of the source metal and the drain metal is any one of Ti / Al / Ni / Au alloy, Ti / Al / Ti / Au alloy, Ti / Al / Mo / Au alloy, or Ti / Al / Ti / TiN alloy.

[0039] In one embodiment, the material of the gate metal is one of metals Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, TiN, Ta, TaN, ZrN, VN, NbN or a stacked structure thereof.

[0040] Compared with the prior art, the beneficial effects are as follows: the method for preparing a vertical structure gallium nitride power transistor provided by the present invention forms a deep well by etching, and then adopts selective area epitaxy of p-type GaN to prepare a p-well electric field shielding layer and a p-channel layer at the same time. The p-well can effectively reduce the electric field of the gate oxide layer under reverse bias, and alleviate the electric field concentration effect existing at the bottom corner of the oxide layer at the bottom of the device groove; while the groove structure formed by selective area epitaxy avoids the lattice damage and interface defects caused by dry etching, reduces surface roughness scattering, and improves the electron mobility of the channel. At the same time, reducing the interface state concentration is also conducive to improving the voltage resistance and reliability of the GaN groove MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 The following are schematic diagrams of three types of groove MOSFET structures: (a) is a traditional groove MOSFET structure; (b) is an ion-implanted dual p-well groove MOSFET; and (c) is the device structure of the present invention, a secondary epitaxial dual p-well groove MOSFET.

[0042] Figure 2 Schematic diagrams of simulated electric field distribution of three groove MOSFET structures, (a) is a traditional groove MOSFET structure; (b) is an ion-implanted dual p-well groove MOSFET; (c) is the device structure of the present invention, a secondary epitaxial dual p-well groove MOSFET.

[0043] Figures 3 to 10 is a schematic diagram of the device process flow of Example 2 of the present invention, wherein Fig.10 A schematic diagram showing the overall structure of the device prepared in Example 2.

[0044] Figures 11 to 16 is a schematic diagram of the process flow of the device of Example 3 of the present invention, wherein Fig.16 A schematic diagram showing the overall structure of the device prepared in Example 3.

[0045] Figure numerals: 1, substrate; 2, device drift region; 3, mask layer; 4, p-type GaN region; 5, source n-type GaN region; 6, gate dielectric layer; 7, short-circuit metal; 8, source metal; 9, gate metal; 10, drain metal; 11, passivation layer. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The present invention is described in one of the embodiments in combination with the specific implementation methods. Among them, the drawings are only used for exemplary descriptions, and only schematic diagrams are shown, not physical drawings, and cannot be understood as limitations on this patent; in order to better illustrate the embodiments of the present invention, some parts of the drawings will be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0047] In the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right" and the like indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the drawings are only used for exemplary explanations and cannot be understood as a limitation of this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances. In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" can explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing in the full text is to include three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or schemes that satisfy both A and B.

[0048] Embodiment 1:

[0049] This embodiment provides a vertical structure gallium nitride power transistor, such as Fig.10 The schematic diagram of the device structure of the present embodiment is shown, and its structure from bottom to top is: a drain metal 10 covering the device; a GaN self-supporting substrate 1; an n-type low carrier concentration region - a device drift region 2; a p-type GaN region 4; a source region heavily doped with n-type GaN 5; a gate dielectric layer 6; a source metal 7 forming an ohmic contact with the p-type GaN; a source electrode 8 forming an ohmic contact with the source region n-type GaN; and a gate metal 9 covering the recessed gate dielectric.

[0050] Example 2

[0051] like Figures 3 to 10 As shown, a method for preparing a vertical structure gallium nitride power transistor comprises the following steps:

[0052] Step 1.1 Formation of epitaxial structure

[0053] The n-type conductive device drift region 2 is epitaxially grown on the n-type conductive GaN self-supporting substrate 1 by MOCVD. After this step is completed, the material epitaxial structure is as follows: Figure 3 shown.

[0054] Step 1.2 Etching to form a deep well

[0055] S21. Coating a photoresist on the n-type conductive device drift region 2, and exposing and developing to expose the area to be etched;

[0056] S22. Etching the area not covered by the photoresist by ICP;

[0057] S23. Use acetone to remove the photoresist. After completion, the device structure is as follows Figure 4 shown.

[0058] Step 1.3 Preparation of mask layer 3

[0059] S31. Depositing SiO2 as a mask layer 3 on the device drift region 2;

[0060] S32. Coating a photoresist on the SiO2 mask layer 3, and exposing and developing to expose the location where the p-type GaN region 4 needs to be epitaxially grown;

[0061] S33. Use buffered hydrofluoric acid solution to selectively etch the mask layer 3 not covered by the photoresist. After completion, the device structure is as follows Figure 5 shown.

[0062] Step 1.4 Select the region for epitaxial growth of p-type GaN region 4 and source region n-type GaN region 5

[0063] S41. Place the device prepared in step 1.3 into a MOCVD chamber to epitaxially grow a p-type GaN region 4 and a source n-type GaN region 5 to form a p-type GaN region 4 and a source n-type GaN region 5;

[0064] S42. Using a buffered hydrofluoric acid solution to remove the SiO2 mask layer 3;

[0065] S43. Treat the device with TMAH hot solution and activate the acceptor impurity Mg by high temperature annealing. After completion, the device structure is as follows: Figure 6 shown.

[0066] Step 1.5 depositing a gate dielectric layer 6;

[0067] S51. Place the device prepared in step 1.4 into the ALD chamber to deposit the gate dielectric layer 6; after completion, the structure is as follows Figure 7 Shown

[0068] Step 1.6: removing part of the gate dielectric layer 6;

[0069] S61. Coating a photoresist on the gate dielectric layer 6, and exposing and developing to expose the region where the gate dielectric layer 6 needs to be removed;

[0070] S62. Selectively etch the dielectric layer 6 not covered by the photoresist using a buffered hydrofluoric acid solution;

[0071] S63. Use acetone to remove the photoresist. After completion, the structure is as follows Figure 8 shown.

[0072] Step 1.7 Etching out the pGaN shorting window

[0073] S71. Coating a photoresist, exposing and developing to expose the p-type GaN region 4 to be removed;

[0074] S72. Etching the area not covered by the photoresist by ICP;

[0075] S23. Use acetone to remove the photoresist. After completion, the device structure is as follows Fig. 9 shown.

[0076] Step 1.8 Evaporation electrode

[0077] S81. Vapor-depositing Ni / Au on the exposed p-type GaN region 4 of the device prepared in step S1.7 to form an ohmic contact as the pGaN shorting metal 7;

[0078] S82. Evaporating Ti / Al / Ni / Au on the n-type GaN region 5 and the shorting metal 7 of the device to form an ohmic contact as the source 8;

[0079] S83. Vapor depositing Ni / Au on the gate dielectric layer 6 in the device groove forms a gate electrode 9;

[0080] S84. Vapor-depositing Ti / Al / Ni / Au on the back of the epitaxial wafer forms an ohmic contact as the drain 10;

[0081] S85. The process described in Example 1 is completed, and the final device structure is as follows Fig.10 shown.

[0082] Example 3

[0083] The final device structure of this embodiment is as follows Fig.16As shown, the difference is that in Example 2, after the p-type GaN region 4 and the source n-type GaN region 5 are selectively epitaxially grown, the gate dielectric layer 6 is directly deposited, while in this embodiment, after the selective epitaxy, part of the p-type GaN region 4 and the source n-type GaN region 5 are first etched to form a window for the source short-circuiting pGaN, and then a passivation layer 11 is deposited to reduce the punch-through leakage caused by the low doping concentration of the p-type GaN on the sidewall. After the p-type GaN region 4 and the source n-type GaN region 5 are selectively epitaxially grown in Example 1 and the mask 3 is removed, the following process flow is performed:

[0084] Step 2.1 Etching to form a source shorting pGaN window

[0085] S11. After the selective epitaxial growth of the p-type GaN region 4 and the source n-type GaN region 5 in Example 1 is completed, a photoresist is coated on the device, and the p-type GaN region 4 and the n-type GaN region 5 to be removed are exposed after exposure and development;

[0086] S12. Etching the area not covered by the photoresist by ICP;

[0087] S13. Remove the photoresist using acetone;

[0088] S14. Treat the device with TMAH hot solution and activate the acceptor impurity Mg by high temperature annealing. After completion, the device structure is as follows: Fig.11 shown.

[0089] Step 2.2 Deposition of passivation layer 11

[0090] S21. SiO2 or Si3N4 is deposited as a passivation layer 11 by PECVD. After completion, the device structure is shown in FIG12 .

[0091] Step 2.3: Removing part of the passivation layer 11

[0092] S31. A photoresist is coated on the passivation layer 11, and after exposure and development, the area where the passivation layer 11 needs to be removed is exposed;

[0093] S32. Selectively etch the passivation layer 11 not covered by the photoresist using a buffered hydrofluoric acid solution;

[0094] S33. Use acetone to remove the photoresist. After completion, the structure is as follows Fig.13 shown.

[0095] Step 2.4 Deposition of gate dielectric layer 6

[0096] S41. Deposit the gate dielectric layer 6 by ALD. After completion, the device structure is as follows Fig.14 shown.

[0097] Step 2.5: removing part of the passivation layer 11 and the gate dielectric layer 6

[0098] S51. A photoresist is coated on the gate dielectric layer 6, and after exposure and development, the gate dielectric layer 6 and the passivation layer 11 region to be removed are exposed;

[0099] S52. Selectively etch the gate dielectric layer 6 and the passivation layer 11 not covered by the photoresist using a buffered hydrofluoric acid solution;

[0100] S53. Use acetone to remove the photoresist. After completion, the structure is as follows Fig.15 shown.

[0101] Step 2.6 Evaporation of electrodes

[0102] S61. Vapor-depositing Ni / Au on the exposed pGaN of the device prepared in step S2.5 forms an ohmic contact as the pGaN shorting metal 7;

[0103] S62. Evaporating Ti / Al / Ni / Au on the n-type GaN region 5 and the shorting metal 7 of the device to form an ohmic contact as a source 8;

[0104] S63. Vapor-depositing Ni / Au on the gate dielectric layer 6 in the device groove forms a gate electrode 9;

[0105] S64. Vapor-depositing Ti / Al / Ni / Au on the back of the epitaxial wafer forms an ohmic contact as the drain 10;

[0106] S65. The process described in Example 2 is completed, and the final device structure is as follows Fig.16 shown.

[0107] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A method for preparing a vertical structure gallium nitride power transistor, characterized in that: The following steps are involved: S1. epitaxially growing a device drift region (2) on an n-type conductive substrate (1) by MOCVD; S2. Etching the mesa where the p-well needs to be grown by ICP; S3. Depositing a SiO2 mask layer (3) on the device drift region (2) by PECVD, removing the SiO2 mask layer (3) in the device region where a p-well region and a p-type channel layer are to be formed; S4. epitaxially growing a p-type GaN region (4) and an N-type GaN region (5) by MOCVD, and removing the SiO2 mask layer (3); S5. growing a gate dielectric layer (6) on the device formed in step S4; S6. Exposing the gate dielectric layer (6) at the location where the source region needs to be evaporated by photolithography and development technology, and removing the gate dielectric layer (6) using a buffered hydrofluoric acid solution; S7. Etching an ohmic contact window of the source and p-type GaN region (4) by ICP; S8. Depositing metal on the p-type GaN region (4) of the device by electron beam evaporation or magnetron sputtering, and forming a short-circuited ohmic contact (7) by annealing; S9. Depositing metal on the n-type GaN region (5) of the device by electron beam evaporation or magnetron sputtering, and forming an ohmic contact as a source (8) by annealing; S10. Depositing metal on the groove region of the device by electron beam evaporation or magnetron sputtering, and forming a gate electrode (9) by annealing; S11. Depositing metal on an n-type conductive substrate (1) by electron beam evaporation or magnetron sputtering, and forming an ohmic contact electrode as a drain (10) by annealing.

2. The method for preparing a vertical structure gallium nitride power transistor according to claim 1, characterized in that: The step S2 specifically includes: S21. Coating a photoresist on the device drift region (2), and determining the p-well etching region by photolithography and development technology; S22. Etch the area not covered by the photoresist by ICP to a depth of 0.5 μm to 5 μm.

3. The method for preparing a vertical structure gallium nitride power transistor according to claim 1, characterized in that: The step S3 specifically includes: S31. Depositing a 0.1 μm to 10 μm thick SiO2 mask layer (3) on the device drift region (2) by PECVD; S32. Opening a window by photolithography on the SiO2 mask layer (3) where the p-well region and the channel layer are to be formed; S33. The SiO2 mask layer (3) not covered by the photoresist is removed by using buffered hydrofluoric acid, and the remaining SiO2 mask layer (3) has a width of 0.05 to 5 μm.

4. The method for preparing a vertical structure gallium nitride power transistor according to claim 1, characterized in that: The step S4 specifically includes: S41. Depositing 0.1 μm to 2 μm p-type GaN (4) on the device drift region (2) by MOCVD; S42. Depositing 0.1 μm to 2 μm of n-type GaN (5) on the device p-type GaN (4) by MOCVD; S43. Removing the SiO2 mask layer (3) by buffered hydrofluoric acid; S44. The groove structure formed by selective epitaxy is treated in a TMAH etching solution at 70 to 100°C for more than 1 hour.

5. The method for preparing a vertical structure gallium nitride power transistor according to any one of claims 1 to 4, characterized in that: The n-type conductive substrate (1) is an n-type GaN self-supporting substrate with a resistivity range of 0.005 Ω·cm to 0.1 Ω·cm and a thickness of 100 μm to 500 μm.

6. The method for preparing a vertical structure gallium nitride power transistor according to any one of claims 1 to 4, characterized in that: The device drift region (2) is an unintentionally doped GaN epitaxial layer, a Si-doped epitaxial layer or an As-doped epitaxial layer with a low dislocation density; the thickness of the device drift region (2) is 1 μm to 50 μm, and the carrier concentration is 1×10 14 cm -3 ~5×10 17 cm -3 .

7. The method for preparing a vertical structure gallium nitride power transistor according to any one of claims 1 to 4, characterized in that: The p-type GaN region (4) has a p-type dopant of magnesium and a hole concentration of 1×10 17 cm -3 ~1×10 19 cm -3 , thickness is 0.1μm~5μm.

8. The method for preparing a vertical structure gallium nitride power transistor according to any one of claims 1 to 4, characterized in that: The n-type GaN region (5) has an electron concentration of 1×10 18 cm -3 ~3×10 19 cm -3 , thickness is 0.1μm~5μm.

9. The method for preparing a vertical structure gallium nitride power transistor according to any one of claims 1 to 4, characterized in that: The material of the gate dielectric layer (6) is any one of Al2O3, SiN and SiO2, and has a thickness of 10nm to 100nm.

10. The method for preparing a vertical structure gallium nitride power transistor according to any one of claims 1 to 4, characterized in that: The short-circuit ohmic contact (7) material is one of Ni, Au, Pt, Pd, Ir, Mo, Al, Ti or a stacked structure thereof; the source (8) and drain (10) materials are any of Ti / Al / Ni / Au alloy, Ti / Al / Ti / Au alloy, Ti / Al / Mo / Au alloy, or Ti / Al / Ti / TiN alloy; The material of the gate electrode (9) is one of the metals Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, TiN, Ta, TaN, ZrN, VN, NbN or a stacked structure thereof.

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