Shielded gate trench field effect transistor, transistor module and method of manufacturing the same

Abstract

The application relates to a shielded gate trench field effect transistor, which comprises a substrate region, a drift region, a base region, a source region, a trench region, a drain and a source; the source region is composed of a first N-type source region, a second N-type source region and a P-type source region; the P-type source region is arranged at a corner of the source region away from the trench region, and the first N-type source region and the second N-type source region are arranged and connected at two sides adjacent to the P-type source region; and the area surrounded by the sides of the first N-type source region and the second N-type source region is the trench region. The channel in the base region is formed along the connected side of the trench region and the source region, the channel area is increased, and thus the channel resistance of the device is reduced. The increase of the channel area can reduce the hole current density below the N-type source region, reduce the voltage drop of the parasitic transistor emission junction, inhibit the opening of the parasitic transistor, and improve the avalanche resistance of the transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a split gate trench field effect transistor, a transistor module and a preparation method thereof. BACKGROUND

[0002] Split Gate Trench (SGT) has been widely used in important low-voltage fields such as power management. SGT has high channel density and good charge compensation effect. In addition, the split gate structure effectively isolates the coupling between the control gate and the drain, thereby significantly reducing the transmission capacitance.

[0003] Therefore, SGT has lower specific on-resistance, smaller on-resistance and switching loss, and higher working frequency.

[0004] However, the avalanche tolerance in the traditional SGT device limits the maximum current of the device in inductive load applications. Since the base region is short-circuited to the N-type source region connected to the channel through the heavily doped P-type source region, when the transistor generates holes due to avalanche effect, a hole current can be formed through the base region channel to turn on the parasitic transistor. The hole current flows through the base region channel, causing the parasitic transistor to turn on, which will cause the transistor to fail due to avalanche effect.

[0005] Therefore, in order to inhibit the opening of the parasitic transistor in the SGT before the SGT fails due to avalanche effect, a new type of split gate trench field effect transistor needs to be designed. SUMMARY

[0006] In order to overcome the problems in the related art, the present application provides a split gate trench field effect transistor, comprising:

[0007] a substrate region 1, a drift region 2, a base region 3, a source region 4, a trench region 5, a drain 6 and a source;

[0008] The drift region 2 is connected to the substrate region 1, and the direction of the substrate region 1 pointing to the drift region 2 is upward,

[0009] The base region 3 and the source region 4 are sequentially arranged above the drift region 2;

[0010] The trench region 5 is arranged on the side of the base region 3 and is connected to the drift region 2, the base region 3 and the source region 4, respectively;

[0011] The source region 4 is composed of a first N-type source region 41, a second N-type source region 42 and a P-type source region 43;

[0012] The P-type source region 43 is arranged at a corner of the source region 4 away from the trench region 5 in the cross section of the source region 4, and two side edges adjacent to the P-type source region 43 are connected to the first N-type source region 41 and the second N-type source region 42 respectively;

[0013] The area surrounded by the side edges of the first N-type source region 41 and the second N-type source region 42 is the trench region 5;

[0014] The trench region 5 comprises a shield gate 51, a control gate 52, an insulating layer 53 and a metal gate; the control gate 52 and the shield gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the substrate region 3 and the source region 4 through the insulating layer 53 respectively, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;

[0015] The source electrode is arranged above the source region 4; the drain electrode 6 is arranged below the substrate region 1; and the metal gate is arranged above the control gate 52.

[0016] In an embodiment, the trench region 5 is provided with a boss region 54:

[0017] The boss region 54 is arranged at the side edges of the first N-type source region 41, the substrate region 3 and the drift region 2;

[0018] On the first N-type source region 41, the other side edge opposite to the side edge connected to the P-type source region 43 is connected to the boss region 54 of the trench region 5.

[0019] In an embodiment, the doping concentration of the P-type source region 43, the first N-type source region 41 and the second N-type source region 42 is a heavy doping concentration.

[0020] In an embodiment, the substrate region 1 is N-type doped, and the doping concentration of the substrate region 1 is a heavy doping concentration;

[0021] The drift region 2 is N-type doped, and the doping concentration of the drift region 2 is a light doping concentration;

[0022] The substrate region 3 is P-type doped, and the doping concentration of the substrate region 3 is a medium doping concentration;

[0023] The doping concentration of the source region 4 is a heavy doping concentration; and the doping concentration of the control gate 52 is a heavy doping concentration.

[0024] The second aspect of the present application provides a preparation method of a shield gate trench field effect transistor, which is used for preparing the shield gate trench field effect transistor of any one of the first aspect of the present application, comprising:

[0025] forming a substrate region with a semiconductor material;

[0026] forming a drift region on the substrate region by epitaxy;

[0027] forming a base region on the drift region by ion implantation or diffusion;

[0028] forming a source region on the base region with a P-type doped semiconductor material and an N-type doped semiconductor material respectively; the source region comprises a first N-type source region, a second N-type source region and a P-type source region;

[0029] etching a trench on one side of the drift region, the base region and the source region;

[0030] depositing oxide, polysilicon, oxide and polysilicon in the trench in sequence to form a shield gate, an insulating layer and a control gate;

[0031] forming a source electrode above the source region; and forming a metal gate above the trench;

[0032] forming a drain electrode below the substrate region.

[0033] In one embodiment, the etching of the trench on one side of the drift region, the base region and the source region comprises:

[0034] etching the trench on one side of the first N-type source region at a first depth; and etching the trench on one side of the second N-type source region at a second depth.

[0035] In one embodiment, the forming of the source region on the base region with a P-type doped semiconductor material and an N-type doped semiconductor material respectively comprises:

[0036] the P-type source region is arranged at a corner of the source region away from the trench, and two adjacent sides of the P-type source region are connected to the first N-type source region and the second N-type source region respectively.

[0037] The third aspect of the present application provides a shield gate trench field effect transistor module, which is composed of the shield gate trench field effect transistor according to any one of the first aspect of the present application.

[0038] In the transistor module, transistors are arranged and combined in a 2x2 manner to form the transistor module; wherein the P-type source regions of different transistors are arranged in a 2x2 manner at the center of the top surface of the transistor module.

[0039] The fourth aspect of the present application provides a preparation method of a shield gate trench field effect transistor module, which is used to prepare the shield gate trench field effect transistor module according to the third aspect of the present application, and comprises:

[0040] The transistors are arranged in a 2×2 configuration; wherein the P-type source regions of different transistors are located at the center above the transistor module, and the P-type source regions are arranged in a 2×2 configuration.

[0041] The packaged and arranged transistors are assembled into transistor modules.

[0042] The technical solution provided in this application may include the following beneficial effects:

[0043] This application provides a shielded gate trench field-effect transistor, the source region of which is composed of a first N-type source region, a second N-type source region and a P-type source region; the P-type source region is disposed at a corner of the source region away from the trench region, and the first N-type source region and the second N-type source region are respectively disposed and connected on two adjacent sides of the P-type source region; the trench region is disposed in the area surrounded by the sides of the first N-type source region and the second N-type source region; when forward conducting, a channel is formed in the substrate region corresponding to the first N-type source region and the second N-type source region, and electrons reach the drift region through the channel. Since the trench region is surrounded by the first N-type source region and the second N-type source region, correspondingly, during forward conduction, the channel in the substrate region is formed along the side connecting the trench region and the source region, which increases the channel area and thus reduces the channel resistance of the device. At the same time, under the same current conditions, the increase in channel area can reduce the hole current density below the N-type source region, thereby reducing the voltage drop of the emitter junction of the parasitic transistor, which can effectively suppress the turn-on of the parasitic transistor and improve the avalanche capability during forward blocking or forward conduction.

[0044] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0045] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0046] Figure 1 This is a schematic diagram of the structure of a shielded gate trench field-effect transistor shown in an embodiment of this application;

[0047] Figure 2 This is a schematic flowchart illustrating the fabrication method of a shielded gate trench field-effect transistor according to an embodiment of this application;

[0048] Figure 3 This is a schematic diagram of the shielded gate trench field-effect transistor module shown in Embodiment 3;

[0049] Figure 4This is a schematic flowchart illustrating the fabrication method of the shielded gate trench field-effect transistor module shown in Example 4. Detailed Implementation

[0050] Preferred embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0051] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0052] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0053] Example 1

[0054] When a traditional SGT is blocked by a forward high voltage or turned on by a forward high voltage, the SGT is prone to generating hole current due to the avalanche effect. This hole current flowing through the substrate channel will cause the parasitic transistor to turn on, and the turning on of the parasitic transistor will cause the transistor to fail due to avalanche.

[0055] To address the aforementioned problems, this application provides a shielded gate trench field-effect transistor. The technical solution of this application embodiment is described in detail below with reference to the accompanying drawings.

[0056] Figure 1 This is a schematic diagram of the structure of a shielded gate trench field-effect transistor as shown in an embodiment of this application.

[0057] See Figure 1 It includes: substrate region 1, drift region 2, base region 3, source region 4, trench region 5, drain 6, and source.

[0058] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 defined as upward.

[0059] The matrix region 3 and the source region 4 are sequentially disposed above the drift region 2;

[0060] The trench region 5 is disposed on the side of the substrate region 3 and is connected to the drift region 2, the substrate region 3 and the source region 4 respectively;

[0061] The source region 4 is composed of a first N-type source region 41, a second N-type source region 42, and a P-type source region 43;

[0062] On the cross-section of the source region 4, the P-type source region 43 is disposed at a corner of the source region 4 away from the trench region 5, and the first N-type source region 41 and the second N-type source region 42 are respectively connected to the two adjacent sides of the P-type source region 43.

[0063] The trench region 5 is provided in the area surrounded by the sides of the first N-type source region 41 and the second N-type source region 42;

[0064] The trench region 5 includes a shielding gate 51, a control gate 52, an insulating layer 53, and a metal gate; the control gate 52 and the shielding gate 51 are arranged sequentially from top to bottom in the trench region 5 and are separated by the insulating layer 53; the control gate 52 is connected to the substrate region 3 and the source region 4 respectively through the insulating layer 53, and the shielding gate 51 is connected to the drift region 2 through the insulating layer 53;

[0065] The source electrode is disposed above the source region 4; the drain electrode 6 is disposed below the substrate region 1; and the metal gate electrode is disposed above the control gate 52.

[0066] In this embodiment, the substrate region 1 is doped with N-type doping and has a heavy doping concentration; the drift region 2 is doped with N-type doping and has a light doping concentration; the substrate region 3 is doped with P-type doping and has a medium doping concentration; the source region 4 has a heavy doping concentration; and the control gate 52 has a heavy doping concentration.

[0067] In this embodiment, the light doping concentration ranges from 1×10⁻⁶. 15 cm -3 Up to 5×10 16 cm -3 The doping concentration ranges from 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3The range of heavily doped concentration is 1×10. 19 cm -3 Up to 5×10 20 cm -3 .

[0068] In this embodiment, the doping type of the P-type source region 43 is P-type doping, and the doping concentration of the P-type source region is medium doping concentration or heavy doping concentration.

[0069] Furthermore, the doping concentration of the shielding gate 51 can be either heavily doped or moderately doped.

[0070] Preferably, the P-type source region 43, the first N-type source region 41, and the second N-type source region 42 are all set with the same doping concentration. For example, all are medium doping concentration or all are heavy doping concentration, so that the P-type source region 43 can more easily receive hole current and achieve better shunting effect.

[0071] In the shielded gate trench field-effect transistor described in this application embodiment, the source region 4 is composed of a first N-type source region 41, a second N-type source region 42, and a P-type source region 43; the P-type source region 43 is disposed at a corner of the source region 4 away from the trench region 5, and the first N-type source region 41 and the second N-type source region 42 are respectively disposed and connected on two adjacent sides of the P-type source region 43; the trench region 5 is disposed in the area surrounded by the sides of the first N-type source region 41 and the second N-type source region 42; during forward conduction, a channel is formed in the substrate region 3 corresponding to the first N-type source region 41 and the second N-type source region 42, and electrons reach the drift region 2 through the channel. Since the trench region 5 is surrounded by the first N-type source region 41 and the second N-type source region 42, correspondingly, during forward conduction, the channel in the substrate region 3 is formed along the side connecting the trench region 5 and the source region 4, increasing the channel area and thus reducing the channel resistance of the device. At the same time, under the same current conditions, the increase in channel area can reduce the hole current density below the N-type source region, thereby reducing the voltage drop of the emitter junction of the parasitic transistor, effectively suppressing the turn-on of the parasitic transistor, and improving the avalanche capability during forward blocking or forward conduction.

[0072] Example 2

[0073] Based on Embodiment 1, when the transistor is forward-biased, a forward voltage is applied to the control gate, attracting electrons in the substrate region to drift towards the control gate and form a P-type channel, thus turning on the transistor. Therefore, increasing the contact area between the control gate and the substrate region can effectively increase the channel area.

[0074] Since increasing the channel area can reduce the channel resistance of the transistor, this application embodiment also provides a shielded gate trench field-effect transistor, which can further reduce the channel area of ​​the transistor, such as... Figure 1 As shown, it includes:

[0075] Substrate region 1, drift region 2, substrate region 3, source region 4, trench region 5, drain 6, and source;

[0076] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 defined as upward.

[0077] The matrix region 3 and the source region 4 are sequentially disposed above the drift region 2;

[0078] The trench region 5 is disposed on the side of the substrate region 3 and is connected to the drift region 2, the substrate region 3 and the source region 4 respectively;

[0079] The source region 4 is composed of a first N-type source region 41, a second N-type source region 42, and a P-type source region 43;

[0080] On the cross-section of the source region 4, the P-type source region 43 is disposed at a corner of the source region 4 away from the trench region 5, and the first N-type source region 41 and the second N-type source region 42 are respectively connected to the two adjacent sides of the P-type source region 43.

[0081] The trench region 5 is provided in the area surrounded by the sides of the first N-type source region 41 and the second N-type source region 42;

[0082] The trench region 5 includes a shielding gate 51, a control gate 52, an insulating layer 53, and a metal gate; the control gate 52 and the shielding gate 51 are arranged sequentially from top to bottom in the trench region 5 and are separated by the insulating layer 53; the control gate 52 is connected to the substrate region 3 and the source region 4 respectively through the insulating layer 53, and the shielding gate 51 is connected to the drift region 2 through the insulating layer 53;

[0083] The source electrode is disposed above the source region 4; the drain electrode 6 is disposed below the substrate region 1; and the metal gate electrode is disposed above the control gate 52.

[0084] In this embodiment of the application, the trench area 5 is provided with a boss area 54:

[0085] The boss area 54 is disposed on the side of the first N-type source area 41, the substrate area 3 and the drift area 2; on the first N-type source area 41, the boss area 54 of the groove area 5 is connected to the other side opposite to the side connected to the P-type source area 43.

[0086] like Figure 1As shown, along the length of the first N-type source region 41, one end is connected to the P-type source region, and the other end is connected to the protrusion region of the trench region. Correspondingly, on the cross-section of the transistor, the side of the substrate region is also connected to the protrusion region of the trench region. When the transistor is forward-biased, a P-type channel is formed in the substrate region below the first and second N-type source regions, and electrons drift to the substrate region adjacent to the protrusion region of the trench region, increasing the area of ​​the P-type channel and thus reducing the channel resistance of the device. At the same time, under the same current conditions, the increase in channel area can reduce the hole current density below the N-type source region, thereby reducing the voltage drop of the emitter junction of the parasitic transistor, effectively suppressing the turn-on of the parasitic transistor, and improving the avalanche capability of the transistor during forward blocking or forward conduction.

[0087] Example 3

[0088] Corresponding to the aforementioned shielded gate trench field-effect transistor and its embodiments, this application also provides a method for fabricating a shielded gate trench field-effect transistor and corresponding embodiments.

[0089] Figure 2 This is a schematic flowchart illustrating the fabrication method of a shielded gate trench field-effect transistor according to an embodiment of this application.

[0090] See Figure 2 The fabrication method of the shielded gate trench field-effect transistor, such as... Figure 2 As shown, it includes:

[0091] 201. Fabrication of substrate regions using semiconductor materials;

[0092] 202. A drift region is epitaxially formed on the substrate region;

[0093] In the embodiments of this application, different epitaxial processes can be used according to actual needs, including but not limited to: vapor phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0094] 203. A matrix region is formed on the drift region by ion implantation or diffusion;

[0095] Ion implantation is a process of doping silicon materials. In practical applications, the power device is placed at one end of the ion implanter, and the dopant ion source is placed at the other end. At the dopant ion source, the dopant atoms are ionized, thus acquiring a certain charge. They are then accelerated to ultra-high speed by an electric field, penetrating the product surface and using their momentum to implant the dopant atoms into the power device, forming a doped region.

[0096] Diffusion is a process of incorporating pure impurity atoms into the surface of silicon materials. In practical applications, diborane or phosphine are usually used as ion sources, and pure impurity atoms are incorporated into the surface of silicon materials through intermittent diffusion or substitutional diffusion.

[0097] It should be noted that the embodiments of this application do not have strict limitations on the preparation method of the substrate region. In actual process, different processes described above can be selected to complete the preparation of the substrate region according to actual needs.

[0098] 204. On the substrate region, a source region is formed using P-type doped semiconductor material and N-type doped semiconductor material, respectively;

[0099] Furthermore, the source region includes a first N-type source region, a second N-type source region, and a P-type source region;

[0100] In this embodiment, the P-type source region and the N-type source region are connected. An N-type source region, a second N-type source region, and a P-type source region are formed above the substrate region using P-type and N-type doped semiconductor materials. The P-type source region short-circuits the substrate region with the N-type source region connecting the trench region, suppressing the substrate floating effect of the power semiconductor device and ensuring stable device performance.

[0101] Above the matrix region, such as Figure 1 As shown, the P-type source region is located at a corner of the source region away from the trench, and the first N-type source region and the second N-type source region are respectively connected to the two adjacent sides of the P-type source region.

[0102] In the embodiments of this application, preferably, the doping concentrations of the above-mentioned P-type doped semiconductor material and N-type doped semiconductor material are both heavily doped to form an ohmic contact, thereby ensuring that no significant additional impedance is generated in the device.

[0103] 205. Etch trenches on one side of the drift region, the substrate region, and the source region;

[0104] Furthermore, the trench is etched to a first depth on one side of the first N-type source region; and the trench is etched to a second depth on one side of the second N-type source region.

[0105] Furthermore, the directions of the first depth and the second depth are the etching directions.

[0106] Specifically, the first depth is less than the second depth.

[0107] In this embodiment, a trench is etched to a first depth on one side of the first N-type source region, the drift region, and the substrate region to form a boss region of the trench region. The boss region is disposed on the side of the first N-type source region, the substrate region, and the drift region; on the first N-type source region, the boss region of the trench is connected to the other side opposite to the side connected to the P-type source region.

[0108] In this embodiment, along the length of the first N-type source region, one end is connected to the first N-type source region, and the other end is connected to the protrusion region of the trench. Correspondingly, on the cross-section of the transistor, the side of the substrate region is also connected to the protrusion region of the trench. When the transistor is forward-biased, a P-type channel is formed in the substrate region below the first and second N-type source regions, and electrons drift to the substrate region adjacent to the protrusion region of the trench, increasing the area of ​​the P-type channel.

[0109] 206. P-type doped semiconductor material, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form a shielding gate, an insulating layer and a control gate;

[0110] Preferably, in this embodiment of the application, oxide, polysilicon, and oxide and heavily doped polysilicon are sequentially deposited in the trench to form the shielding gate, insulating layer and control gate.

[0111] 207. A source electrode is formed above the source region;

[0112] 208. A metal gate is formed above the trench;

[0113] 209. Fabricate the drain below the substrate region.

[0114] During forward conduction, a channel is formed in the substrate region corresponding to the first and second N-type source regions, allowing electrons to reach the drift region through the channel. Since the trench region is surrounded by the first and second N-type source regions, correspondingly, during forward conduction, the channel in the substrate region forms along the side connecting the trench region and the source region, increasing the channel area and thus reducing the channel resistance of the device. Simultaneously, under the same current conditions, the increased channel area reduces the hole current density below the N-type source region, thereby reducing the voltage drop across the emitter junction of the parasitic transistor, effectively suppressing the turn-on of the parasitic transistor, and improving the avalanche capability during forward blocking or forward conduction.

[0115] Example 4

[0116] Based on the shielded gate trench field-effect transistor described in Embodiment 1 or Embodiment 2 of this application, in order to better protect the transistor when hole current occurs, this application also provides a shielded gate trench field-effect transistor module, such as... Figure 3 As shown, it includes: the transistor described in Embodiment 1 or Embodiment 2;

[0117] In a transistor module, transistors are arranged in a 2×2 configuration to form the transistor module.

[0118] Furthermore, the P-type source regions of the different transistors are arranged in a 2×2 configuration at the center of the top surface of the transistor module.

[0119] In a transistor module, when a hole current occurs, it is generated in the drift region and flows to the source region along the interface between the trench region and the substrate region. Since the P-type source region is located at the center of the cross-section of the transistor module and is formed by combining the P-type source regions of four transistors, the P-type source region can better receive the hole current, thereby improving the avalanche withstand capability of the shielded gate trench field-effect transistor.

[0120] Example 5

[0121] Corresponding to the aforementioned shielded gate trench type field-effect transistor module and its embodiments, this application also provides a method for fabricating a shielded gate trench type field-effect transistor module and corresponding embodiments.

[0122] Figure 4 This is a schematic flowchart illustrating a method for fabricating a shielded gate trench field-effect transistor module according to an embodiment of this application.

[0123] See Figure 4 This includes the following steps:

[0124] 401. Arrange the transistors in a 2×2 configuration;

[0125] Furthermore, the P-type source regions of different transistors are arranged in a 2×2 configuration at the center of the top surface of the transistor module.

[0126] 402. The packaged transistors are assembled into a transistor module.

[0127] In the embodiments of this application, a transistor module is fabricated by assembling and combining the transistors described in Embodiment 1 or Embodiment 2. This transistor module has a larger P-type source region area, which allows the P-type source region to better receive hole current and improves the avalanche withstand capability of the shielded gate trench field-effect transistor.

[0128] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated further here.

[0129] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different emphases; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application embodiment can be combined, divided, and deleted according to actual needs.

[0130] Furthermore, the method according to this application can also be implemented as a computer program or computer program product, which includes computer program code instructions for performing some or all of the steps in the method described above.

[0131] Alternatively, this application may be implemented as a non-transitory machine-readable storage medium or computer-readable storage medium, or a machine-readable storage medium storing executable code or computer program or computer instruction code thereon, which, when executed by an electronic device or processor of an electronic device, server, etc., causes the processor to perform part or all of the steps of the methods described above according to this application.

[0132] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the present application can be implemented as electronic hardware, computer software, or a combination of both.

[0133] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0134] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A shielded gate trench field-effect transistor, characterized in that, include: Substrate region (1), drift region (2), substrate region (3), source region (4), trench region (5), drain (6), and source; The drift region (2) is connected to the substrate region (1), with the direction from the substrate region (1) to the drift region (2) as the top, and the substrate region (3) and the source region (4) are sequentially disposed above the drift region (2); The trench area (5) is located on the side of the substrate area (3) and is connected to the drift area (2), the substrate area (3) and the source area (4) respectively; The source region (4) is composed of a first N-type source region (41), a second N-type source region (42), and a P-type source region (43); On the cross-section of the source region (4), the P-type source region (43) is located at a corner of the source region (4) away from the trench region (5), and the first N-type source region (41) and the second N-type source region (42) are connected to the two adjacent sides of the P-type source region (43), respectively. The trench region (5) is provided in the area surrounded by the sides of the first N-type source region (41) and the second N-type source region (42); The trench region (5) includes a shielding gate (51), a control gate (52), an insulating layer (53), and a metal gate; the control gate (52) and the shielding gate (51) are arranged sequentially from top to bottom in the trench region (5) and separated by the insulating layer (53); the control gate (52) is connected to the substrate region (3) and the source region (4) respectively through the insulating layer (53), and the shielding gate (51) is connected to the drift region (2) through the insulating layer (53); The source electrode is disposed above the source region (4); the drain electrode (6) is disposed below the substrate region (1); and the metal gate electrode is disposed above the control gate (52). The groove area (5) is provided with a boss area (54): The boss area (54) is disposed on the side of the first N-type source area (41), the substrate area (3) and the drift area (2); On the first N-type source region (41), the side opposite to the side connected to the P-type source region (43) is connected to the boss region (54) of the trench region (5).

2. The shielded gate trench field-effect transistor according to claim 1, characterized in that, The doping concentrations of the P-type source region (43), the first N-type source region (41), and the second N-type source region (42) are all heavily doped.

3. The shielded gate trench field-effect transistor according to claim 1, characterized in that, The substrate region (1) is N-type doped, and the doping concentration of the substrate region (1) is a heavily doped concentration. The drift region (2) is N-type doped, and the doping concentration of the drift region (2) is light doping concentration; The substrate region (3) is P-type doped, and the doping concentration of the substrate region (3) is medium. The doping concentration of the source region (4) is a heavily doped concentration; the doping concentration of the control gate (52) is a heavily doped concentration.

4. A method for fabricating a shielded gate trench field-effect transistor, characterized in that, The method for fabricating a shielded gate trench field-effect transistor as described in any one of claims 1 to 3 includes: The substrate region is prepared using semiconductor materials; A drift region is epitaxially formed on the substrate region; A matrix region is formed on the drift region by ion implantation or diffusion. On the substrate region, source regions are formed using P-type doped semiconductor materials and N-type doped semiconductor materials, respectively; the source regions include a first N-type source region, a second N-type source region, and a P-type source region. Etch trenches on one side of the drift region, the substrate region, and the source region; Oxide, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form a shielding gate, an insulating layer and a control gate; A source electrode is formed above the source region; a metal gate electrode is formed above the trench. The drain is fabricated below the substrate region.

5. The method for fabricating a shielded gate trench field-effect transistor according to claim 4, characterized in that, The etching trench on one side of the drift region, the substrate region, and the source region includes: The trench is etched to a first depth on one side of the first N-type source region; The trench is etched to a second depth on one side of the second N-type source region.

6. The method for fabricating a shielded gate trench field-effect transistor according to claim 4, characterized in that, The step of forming a source region on the substrate region using P-type doped semiconductor material and N-type doped semiconductor material, respectively, includes: The P-type source region is located at a corner of the source region away from the trench, and the first N-type source region and the second N-type source region are respectively connected to the two adjacent sides of the P-type source region.

7. A shielded gate trench type field-effect transistor module, characterized in that, Composed of the shielded gate trench field-effect transistor as described in any one of claims 1-3: In the transistor module, transistors are arranged in a 2×2 configuration to form the transistor module; wherein, the P-type source regions of different transistors are arranged in a 2×2 configuration at the center of the top surface of the transistor module.

8. A method for fabricating a shielded gate trench type field-effect transistor module, characterized in that, For fabricating the shielded gate trench field-effect transistor module as described in claim 7, comprising: The transistors are arranged in a 2×2 configuration; wherein the P-type source regions of different transistors are located at the center above the transistor module, and the P-type source regions are arranged in a 2×2 configuration. The packaged and arranged transistors are assembled into transistor modules.

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