A power supply controller and direct grid-connected control method

Abstract

The present invention provides a power supply controller and a direct grid-connected control method. The power supply controller includes an S3R, a BCDR, and a bus error amplifier. The S3R is connected to a first bus error amplifier, and the BCDR is connected to a second bus error amplifier. The present invention has the following beneficial effects: the BCDR and S3R each have independent bus error amplifiers, achieving decoupling of their loop designs, making the design more flexible, facilitating improved bus dynamic characteristics and stability, and enhancing power scalability. Furthermore, the power scalability of the power supply controller is further improved through a direct grid-connected control method using dual power supply controllers. This grid-connected method does not require the addition of a separate grid-connected controller, thus enabling power expansion without increasing the weight of the entire satellite. Furthermore, this method can be extended to grid-connected control with multiple power supply controllers.

Description

Technical Field

[0001] The present invention relates to the field of aerospace technology, and in particular to a power supply controller and a direct grid-connected control method. Background Art

[0002] The power controller PCU is the only source of power for the satellite. Regardless of whether the satellite is in the illuminated area or the shadow area, the power regulation system keeps the bus voltage constant at a certain value. Figure 1 This is the PCU functional block diagram. The bus error amplifier M provides unified power management. S3R is a shunt regulator, and the charge-discharge regulator BCDR is a bidirectional power converter. When the output power of the solar array SA fails to meet the load, the bus voltage is regulated by the charge-discharge regulator BCDR using the discharge current to provide power to the output bus. When the solar array's output power exceeds the load but fails to meet the preset battery pack charging current, the bus voltage is regulated by the charge-discharge regulator BCDR using the charging current to charge the battery BAT. When the solar array's output power exceeds both the load and the charging current requirements, the bus voltage is regulated by the shunt regulator S3R. The bus error amplifier M coordinates the BCDR and S3R to stabilize the bus voltage.

[0003] The working principle of the bus error amplifier M is as follows Figure 2 As shown:

[0004] (1) The M unit collects the error between the bus voltage and the reference value, and forms the VMEA signal through PID operation, such as Figure 4 As shown, the VMEA signal is mapped into three domains to adjust the bus voltage, and VMEA decreases as the load current I_Load increases;

[0005] (2) When I_Load is small, VMEA is in the SUN domain, the output power of SA is greater than the load and charging current requirements, BCDR is in charging mode, charging the battery with the maximum current, and S3R regulates the bus voltage.

[0006] (3) As I_Load increases, when the output power of SA is greater than the load requirement but cannot meet the preset maximum charging current requirement of the battery pack, VMEA enters the BCR domain, and BCDR regulates the bus voltage through the charging current.

[0007] (4) As I_Load continues to increase, when the output power of SA cannot meet the load requirements, VMEA enters the BDR domain, and BCDR regulates the bus voltage through the discharge current.

[0008] Figure 2In the example, each BCDR module and S3R unit can be equivalent to a voltage-controlled current source. Multiple BCDR modules are connected in parallel to adjust the bus voltage, while multiple S3R units are connected in sequence to adjust the bus voltage:

[0009] (1) Assuming that there are N S3R units, VMEA is set in the SUN domain with equal intervals. The N reference voltages from LREF_1 to LREF_N correspond to the N S3R units respectively.

[0010] (2) Each S3R unit adopts hysteresis control. Taking the i-th S3R as an example, when VMEA is greater than LREF_i+ΔV, the S1 switch is turned on to shunt SA_i to the ground; when VMEA is less than LREF_i-ΔV, the S1 switch is turned off to allow SA_i to supply power to the bus.

[0011] (3) When VMEA is in the SUN domain, the reference voltage is higher than the S3R unit of VMEA

[0012] In the power supply state, the S3R unit with a reference voltage lower than VMEA is in the shunt state. Due to the hysteresis range design and load current, the SUN domain generally has only one S3R unit in the switching regulation state.

[0013] As satellite payloads increase, the power demand for satellite platforms continues to rise. However, due to component limitations, the power of a single module cannot be further increased. Power expansion can only be achieved by increasing the number of S3R units and BCDR units. If the three-domain division remains unchanged, the problems caused by the increase in the number of units include:

[0014] (1) The difficulty of BCDR in ensuring full-range loop stability increases with the number of modules configured;

[0015] (2) The design of the S3R hysteresis control range is limited, and the double-stage and multi-stage regulation phenomena are aggravated, resulting in a decrease in dynamic performance and an increase in heat consumption. Summary of the Invention

[0016] The present invention provides a power supply controller, including an S3R, a BCDR, and a bus error amplifier. The bus error amplifier includes a first bus error amplifier and a second bus error amplifier. The S3R represents a shunt regulator, and the BCDR represents a charge and discharge regulation unit. The S3R is connected to the first bus error amplifier, and the BCDR is connected to the second bus error amplifier. The first bus error amplifier is an analog controller, and the first bus error amplifier is used to control the S3R to achieve SUN domain bus regulation. The second bus error amplifier is a digital controller, and the second bus error amplifier controls the BCDR to achieve BCR domain and BDR domain bus regulation.

[0017] As a further improvement of the present invention, the first bus error amplifier (M_A) and the second bus error amplifier (M_D) collect the error between the bus voltage and the reference value, and form VMEA_A signal and VMEA_D signal respectively after PID operation. The VMEA_A signal is mapped to the SUN domain, corresponding to multiple S3Rs, and sequential shunt regulation is performed. The VMEA_D signal is mapped to the BCR domain and the BDR domain. Multiple BCDRs are connected in parallel to adjust the bus voltage. VMEA_A and VMEA_D decrease as the load current I_Load increases.

[0018] As a further improvement of the present invention, when I_Load is less than the set value, VMEA_A is in the SUN domain, the output power of SA is greater than the load and charging current requirements, VMEA_D is in a high saturation state, BCDR is in charging mode, charging the battery with the maximum current, and S3R regulates the bus voltage;

[0019] As I_Load increases, when the SA's output power exceeds the load requirement but cannot meet the preset maximum battery pack charging current, VMEA_A enters a low-saturation state, all S3Rs supply power to the bus, and VMEA_D enters the BCR domain, where the BCDR regulates the bus voltage through the charging current.

[0020] As I_Load continues to increase, when the output power of SA cannot meet the load requirements, VMEA_D enters the BDR domain. At this time, VMEA_A is still in a low saturation state, and the bus voltage is regulated by BCDR through the discharge current.

[0021] As a further improvement of the present invention, the power controller also includes a first digital control unit (PMU1A), a second digital control unit (PMU1B), a third digital control unit (PMU2A), a fourth digital control unit (PMU2B), a fifth digital control unit (PMU3A), and a sixth digital control unit (PMU3B). The first to sixth digital control units are respectively responsible for a BCDR power regulation. The BCDRs corresponding to the first digital control unit (PMU1A), the third digital control unit (PMU2A), and the fifth digital control unit (PMU3A) are connected to the first battery, and the BCDRs corresponding to the second digital control unit (PMU1B), the fourth digital control unit (PMU2B), and the sixth digital control unit (PMU3B) are connected to the second battery. The first digital control unit (PMU1A), the second digital control unit (PMU1B), the third digital control unit (PMU2A), and the fourth digital control unit (PMU2B) participate in voting and voting to achieve a quad-redundant design.

[0022] As a further improvement of the present invention, the power controller also includes a control system, which includes an analog control system and a digital control system. The digital control system is used to implement BCDR digital control, and the analog control system is used to implement S3R control.

[0023] As a further improvement of the present invention, the BCR function: the single BCR current sampling signal IBUS_BCR is subjected to ADC linear transformation K1 and the value after VBCM_D is subjected to linear transformation 1 is subtracted to form an error signal, which is then subjected to BCR compensator digital PID operation and then to DPWM unit to produce PWM signal, and control the BCR unit to realize BCR domain bus regulation function;

[0024] BDR function: The single BDR current sampling signal IBUS_BDR undergoes ADC linear transformation K2, and the value after VMEA_D undergoes linear transformation 2 is subtracted to form an error signal, which is then processed by the BDR compensator digital PID operation and then produced by the DPWM unit to generate a PWM signal, controlling the BDR unit to realize the BDR domain bus regulation function.

[0025] The present invention also provides a direct grid-connected control method for a power controller, comprising the power controller, wherein there are two power controllers, the two power controllers being PCU_X and PCU_Y, PCU_X representing the first power controller, PCU_Y representing the second power controller, PCU_X and PCU_Y directly short-circuit the output bus, SA_X_i is connected to S3R of PCU_X, B_X1 and B_X2 are respectively connected to the two BCDRs of PCU_X, RL_X1 and RL_X2 are respectively connected to the two BCDRs of PCU_X, and RL_X1 and RL_X2 are respectively connected to the two BCDRs of PCU_X. RL_X2 is connected to the PCU_X, SA_X_i is the solar cell array connected to PCU_X, B_X1 and B_X2 are batteries connected to PCU_X, RL_X1 and RL_X2 are loads connected to PCU_X; SA_Y_i is connected to S3R of PCU_Y, B_Y1 and B_Y2 are connected to the two BCDRs of PCU_Y respectively, RL_Y1 and RL_Y2 are connected to the PCU_Y, SA_Y_i is the solar cell array connected to PCU_Y, B_Y1 and B_Y2 are connected to the PCU_Y respectively, B_Y2 is the battery connected to PCU_Y, RL_Y1 and RL_Y2 are the loads connected to PCU_Y; the reference voltage of the bus error amplifier is REF_A_X>REF_A_Y, REF_A_Y>REF_D_X, REF_A_Y>REF_D_Y, and the relationship between REF_D_X and REF_D_Y can be changed through software configuration. After direct parallel connection, as the load current increases from 0 to the full load maximum current of two power controllers in parallel, the current of PCU_X is first increased. The S3R stabilizes the bus, followed by the S3R of PCU_Y, and then the BCDR of PCU_X or PCU_Y stabilizes the bus according to the size relationship between REF_D_X and REF_D_Y. According to the battery voltage and the working status of PCU_X and PCU_Y, the working status of PCU_X and PCU_Y are alternately changed by changing the bus voltage regulation value of the BCDR unit of PCU_X and the bus voltage regulation value of the BCDR unit of PCU_Y, thereby ensuring balanced charging and discharging of the battery.

[0026] As a further improvement of the present invention, when REF_D_X>REF_D_Y:

[0027] When the load power demand is less than the maximum output power of the S3R of PCU_X minus the charging power of all batteries, the bus voltage is regulated by the S3R of PCU_X, and the remaining power units are in the output cut-off state;

[0028] When the load power demand is greater than the maximum output power of PCU_X's S3R minus the charging power of all batteries but less than the sum of the maximum output power of PCU_X's S3R and PCU_Y's S3R minus the charging power of all batteries, the bus voltage is regulated by PCU_Y's S3R. At this time, PCU_X's S3R unit is in the maximum power output state, and the other power units are in the output cutoff state.

[0029] When the load power demand is greater than the sum of the maximum output powers of S3R of PCU_X and S3R of PCU_Y minus all battery charging powers, but less than the sum of the maximum output powers of S3R of PCU_X, S3R of PCU_Y, and BCDR of PCU_X minus the battery charging power of PCU_Y, the bus voltage is regulated by BCDR of PCU_X. At this time, S3R of PCU_X and S3R of PCU_Y are in the maximum power output state, and BCDR of PCU_Y is in the output cut-off state;

[0030] When the load power demand is greater than the sum of the maximum output powers of S3R of PCU_X, S3R of PCU_Y, and BCDR of PCU_X minus the battery charging power of PCU_Y, the bus voltage is regulated by BCDR of PCU_Y, and the remaining power units are in the maximum power output state.

[0031] As a further improvement of the present invention, when REF_D_X < REF_D_Y:

[0032] When the load power demand is less than the maximum output power of S3R of PCU_X minus all battery charging powers, the bus voltage is regulated by S3R of PCU_X, and the remaining power units are in the output cut-off state;

[0033] When the load power demand is greater than the maximum output power of S3R of PCU_X minus all battery charging powers, but less than the sum of the maximum output powers of S3R of PCU_X and S3R of PCU_Y minus all battery charging powers, the bus voltage is regulated by S3R of PCU_Y. At this time, the S3R unit of PCU_X is in the maximum power output state, and the remaining power units are in the output cut-off state;

[0034] When the load power demand is greater than the sum of the maximum output powers of S3R of PCU_X and S3R of PCU_Y minus all battery charging powers, but less than the sum of the maximum output powers of S3R of PCU_X, S3R of PCU_Y, and BCDR of PCU_Y minus the battery charging power of PCU_X, the bus voltage is regulated by BCDR of PCU_Y. At this time, S3R of PCU_X and S3R of PCU_Y are in the maximum power output state, and BCDR of PCU_X is in the output cut-off state;

[0035] When the load power demand is greater than the sum of the maximum output powers of S3R of PCU_X, S3R of PCU_Y, and BCDR of PCU_Y minus the battery charging power of PCU_X, the bus voltage is regulated by BCDR of PCU_X, and the remaining power units are in the maximum power output state.

[0036] As a further improvement of the present invention, to ensure balanced charging and discharging of the battery packs connected to PCU_X and PCU_Y, the following steps are performed:

[0037] Step 1: Initialize REF_A_X=VREF, REF_A_Y=VREF-ΔV, REF_D_X=VREF-2*ΔV, REF_D_Y=VREF-3*ΔV;

[0038] Step 2: Determine whether (VBAT_X1+VBAT_X2) / 2<(VBAT_Y1+VBAT_Y2) / 2-ΔVB and REF_D_X>REF_D_Y. If so, the BCDR of PCU_X takes priority and the battery voltage connected to PCU_X is lower than the battery voltage connected to PCU_Y. Slowly decrease REF_D_X to VREF-3*ΔV and slowly increase REF_D_Y to VREF-2*ΔV. The working state is changed to PCU_Y's BCDR unit taking priority, and then return to step 2. Otherwise, go to step 3.

[0039] Step 3: Determine whether (VBAT_Y1+VBAT_Y2) / 2<(VBAT_X1+VBAT_X2) / 2-ΔVB and REF_D_Y>REF_D_X. If so, the BCDR of PCU_Y takes priority and the battery voltage connected to PCU_Y is lower than the battery voltage connected to PCU_X. Slowly decrease REF_D_Y to VREF-3*ΔV and slowly increase REF_D_X to VREF-2*ΔV. The operating state is changed to PCU_X's BCDR unit taking priority, and then return to step 2. Otherwise, execute step 2.

[0040] The present invention has the following beneficial effects: Because the BCDR and S3R each have independent bus error amplifiers, their loop designs are decoupled, making the design more flexible, facilitating improved bus dynamic characteristics and stability, and enhancing power scalability. A control system that combines analog and digital control ensures both high reliability of the power controller S3R circuit and high flexibility of the BCDR control system. The power scalability of the power controller is further enhanced through a direct grid-connected control method using dual power controllers. This grid-connected method eliminates the need for a separate grid-connected controller, enabling power expansion without increasing the weight of the entire satellite. This method can also be extended to grid-connected control with multiple power controllers. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is the PCU functional block diagram;

[0042] Figure 2 This is the working principle diagram of the bus error amplifier;

[0043] Figure 3 is the functional block diagram of the PCU of the present invention;

[0044] Figure 4 is the control schematic diagram based on the three-domain control of dual error amplifiers;

[0045] Figure 5 is the schematic diagram of an embodiment of the present invention;

[0046] Figure 6 is the schematic diagram of the control system;

[0047] Figure 7 is the schematic diagram of directly parallel use of two power controllers PCU_X and PCU_Y; [[ID=2"]]

[0048] Figure 8 is the schematic diagram of the system control working principle when REF_D_X > REF_D_Y;

[0049] Figure 9 is the schematic diagram of the system control working principle when REF_D_X < REF_D_Y;

[0050] Figure 10 is the control flow chart. Detailed implementation manners [[ID=]]

[0051] To solve the problems in the background art, the present invention is implemented by improving the design of the bus error amplifier.

[0052] Figure 3 shows the solution proposed for the present invention. Based on the principle block diagram shown in Figure 1 , the bus error amplifier becomes two (the first bus error amplifier M_A and the second bus error amplifier M_D). The first bus error amplifier M_A is an analog controller, which controls the S3R circuit to achieve the bus regulation in the SUN domain. The second bus error amplifier M_D is a digital controller, which controls the BCDR circuit to achieve the bus regulation in the BCR domain and the BDR domain. The S3R and BCDR units can be equivalent to voltage-controlled current sources, and perform bus regulation under the control of M_A and M_D. Figure 3 In

[0053] The above specific control principle based on the three-domain control of dual error amplifiers is as shown in Figure 4 [[ID=]]<o000131>

[0054] ​(1) The first bus error amplifier M_A and the second bus error amplifier M_D collect the error between the bus voltage and the reference value, and form VMEA_A signal and VMEA_D signal respectively after PID operation. The VMEA_A signal is mapped to the SUN domain, corresponding to multiple S3Rs, and performs sequential shunt regulation. The VMEA_D signal is mapped to the BCR domain and BDR domain. Multiple BCDRs are connected in parallel to regulate the bus voltage. VMEA_A and VMEA_D decrease as the load current I_Load increases.

[0055] (2) When I_Load is less than the set value (i.e., when I_Load is small), VMEA_A is in the SUN domain, the output power of SA is greater than the load and charging current requirements, VMEA_D is in a high saturation state, BCDR is in charging mode, charging the battery with the maximum current, and the bus voltage is regulated by S3R.

[0056] (3) As I_Load increases, when the SA's output power exceeds the load requirement but cannot meet the preset maximum battery pack charging current, VMEA_A enters a low saturation state, and all S3Rs supply power to the bus. VMEA_D enters the BCR domain, and the BCDR regulates the bus voltage through the charging current.

[0057] (4) As I_Load continues to increase, when the output power of SA cannot meet the load requirements, VMEA_D enters the BDR domain. At this time, VMEA_A is still in a low saturation state, and the bus voltage is regulated by BCDR through the discharge current.

[0058] Since BCDR and S3R have their own independent bus error amplifiers, the loop design of the two is decoupled, the design is more flexible, which is conducive to improving the dynamic characteristics and stability of the bus and enhancing the power expansion capability. Figure 4 As shown in the schematic, the bus voltage decreases slightly when transitioning from the SUN domain to the BCR domain; conversely, the bus voltage increases slightly when transitioning from the BCR domain to the SUN domain. The difference between the REF_A and REF_D regulated voltages should be controlled to keep the bus voltage change caused by the cross-domain transition within an acceptable range.

[0059] BCDR uses full digital control to achieve bus regulation (BUS and RTN represent bus and power ground), such as Figure 5As shown, PMU1A, PMU1B, PMU2A, PMU2B, PMU3A, and PMU3B are digital control units, each responsible for a BCDR power regulation. The BCDRs corresponding to PMU1A, PMU2A, and PMU3A are connected to the first battery (BAT1), while the BCDRs corresponding to PMU1B, PMU2B, and PMU3B are connected to the second battery (BAT2). PMU1A, PMU1B, PMU2A, and PMU2B participate in voting and voting, implementing a quad-redundant design to ensure the reliability of the outer voltage control loop. Simultaneously, the inner current control loop is implemented through the BCDR digital controller. Other digital control units, such as PMU3A and PMU3B, only implement the inner current control loop. A quad-redundant bus design, HRBUS_V0, HRBUS_V1, HRBUS_V2, and HRBUS_V3, is used to achieve highly reliable voting and voting in the digital system.

[0060] The design of the whole machine digital control system and digital control unit is as follows Figure 6 As shown in the figure, VBAT_D is the battery voltage, and VBUS_D is the bus voltage sample. VMEA_D and VBCM_D are obtained through quad-redundant digital voting; VMEA_D_O and VBCM_D_O are calculated and output for multiprocessor digital voting. HRBUS is the high-speed data transmission bus used for multiprocessor voting.

[0061] Figure 6 The control system shown is a combination of analog and digital control. The dotted box contains the digital control system, which is used to implement BCDR digital control. The controlled object and the analog control system are outside the dotted box. The analog control system is a quad-redundant design, which is used to implement S3R control. The controlled object consists of the SUN module (multi-channel S3R), BCR unit (BCDR charging mode), BDR unit (BCDR discharge mode), capacitor array C bus , load R. The working principle of the control system is described as follows:

[0062] (1) VMEA_A generation process: The controller adopts a quad-redundant design. Taking the first channel as an example, the bus voltage VBUS is linearly transformed into V0_K0 and then subtracted from the voltage reference value V0_REF_A to form an error signal. The error signal is then PID-operated with V0_M_A and the results of the other three channels are input into the median voter to generate the VMEA_A signal to control the SUN module, i.e., the multi-channel S3R, thereby realizing the SUN domain bus regulation function.

[0063] (2) VMEA_D generation process: The bus voltage sampling signal VBUS_D is linearly converted by ADC K4 and subtracted from the voltage reference value REF_D to form an error signal, which is then digitally PID-operated by M_D to obtain the VMEA_D_O digital quantity. This digital quantity is input to the bus interface and the other three digital controllers participating in the voting to enter the median voter to generate the VMEA_D control quantity.

[0064] (3) VBCM_D Generation Process: The battery voltage sampling signal VBAT_D undergoes ADC linear transformation K3, which is then subtracted from the voltage range setting value to form an error signal. This error signal is then processed through the BEA digital PID operation to obtain D1. VMEA_D is subtracted from the VMEA_TH threshold and linearly transformed 3 to obtain D2. The BCM_LIMIT high limit unit outputs D0. The current range setting unit outputs D3. D0, D1, D2, and D3 are processed through the low-value voter to generate VBCM_D.

[0065] (4) BCR function: The single BCR current sampling signal IBUS_BCR undergoes ADC linear transformation K1 and is subtracted from the value of VBCM_D after linear transformation 1 to form an error signal. The error signal is then processed by the BCR compensator digital PID operation and then passes through the DPWM unit to generate a PWM signal to control the BCR unit to achieve the BCR domain bus regulation function.

[0066] (5) BDR function: The single BDR current sampling signal IBUS_BDR is converted by ADC linear transformation K2 and the value after VMEA_D is converted by linear transformation 2 is subtracted to form an error signal, which is then processed by the BDR compensator digital PID operation and then produced by the DPWM unit to control the BDR unit to realize the BDR domain bus regulation function.

[0067] (6) IBUS is equal to multiple IBUS_SUN plus multiple IBUS_BDR minus multiple IBUS_BCR. IBUS acts on the capacitance array C of the controlled object. bus , load R, forming a stable bus voltage VBUS.

[0068] As spacecraft systems become more complex and power demands increase, multiple power controllers sometimes need to be connected to the grid to meet power requirements. This typically requires adding a grid controller to each power controller, which inevitably increases the weight of the entire spacecraft. This paper proposes a method for directly connecting two power controllers to the grid without requiring a grid controller. This method can also be expanded to directly connect multiple power controllers to the grid. Figure 7The figure shows a schematic diagram of two power controllers, PCU_X and PCU_Y, connected in parallel. This method directly short-circuits the output busbars, eliminating the need for internal signal exchange between the two power controllers. The equivalent resistance of the shorting cable is RT. SA_X_i represents the solar array connected to PCU_X, B_X1 and B_X2 represent the batteries connected to PCU_X, and RL_X1, RL_X2, and so on represent the loads connected to PCU_X. SA_Y_i represents the solar array connected to PCU_Y, B_Y1 and B_Y2 represent the batteries connected to PCU_Y, and RL_Y1, RL_Y2, and so on represent the loads connected to PCU_Y.

[0069] To ensure reliability and safety, isolation diodes are installed at the output ends of the BCDR circuit and S3R circuit of PCU_X and PCU_Y. Figure 7 In the figure, the four main error amplifier reference voltages REF_A_X>REF_A_Y, REF_A_Y>REF_D_X, REF_A_Y>REF_D_Y. The size relationship between REF_D_X and REF_D_Y can be changed through software configuration.

[0070] To ensure reliability and safety, isolation diodes are installed at the output ends of the BCDR circuit and S3R circuit of PCU_X and PCU_Y. Figure 7 In the figure, the four main error amplifier reference voltages REF_A_X>REF_A_Y, REF_A_Y>REF_D_X, REF_A_Y>REF_D_Y. The size relationship between REF_D_X and REF_D_Y can be changed through software configuration.

[0071] After direct parallel connection, as the load current increases from 0 to the full-load maximum current of two power controllers in parallel, the bus is stabilized first by the S3R unit of PCU_X, followed by the S3R unit of PCU_Y. Then, according to the size relationship between REF_D_X and REF_D_Y, the bus is stabilized by the BCDR unit of PCU_X or PCU_Y respectively (the one with a higher voltage regulation value stabilizes the bus first, and the one with a lower voltage regulation value stabilizes the bus last).

[0072] Power units with higher voltage stabilization values ​​than the power unit currently stabilizing the bus voltage output current at maximum power, while power units with lower voltage stabilization values ​​have their output cut off. From the perspective of a single unit, charge and discharge balance between BAT_X1 and BAT_X2 is ensured by the current sharing of the BCDR module of PCU_X. Similarly, charge and discharge balance between BAT_Y1 and BAT_Y2 is ensured by the current sharing of the BCDR module of PCU_Y. When two units are used in parallel, it is necessary to ensure balanced charge and discharge of the battery packs connected to PCU_X and PCU_Y. This is achieved by alternating the bus voltage stabilization values ​​of the BCDR units of PCU_X and PCU_Y, based on the battery voltage and the operating status of PCU_X and PCU_Y, thereby ensuring balanced battery charge and discharge.

[0073] When REF_D_X>REF_D_Y, the entire system control works as follows Figure 8 As shown:

[0074] (1) When the load power demand is less than the maximum output power of the S3R unit of PCU_X minus the charging power of all batteries, the bus voltage is regulated by the S3R unit of PCU_X, and the remaining power units are in the output cut-off state.

[0075] (2) When the load power demand is greater than the maximum output power of PCU_X's S3R unit minus the total battery charging power, but less than the sum of the maximum output power of PCU_X's S3R unit and PCU_Y's S3R unit minus the total battery charging power, the bus voltage is regulated by PCU_Y's S3R unit. At this time, PCU_X's S3R unit is in the maximum power output state, and the remaining power units are in the output cutoff state.

[0076] (3) When the load power demand is greater than the sum of the maximum output power of PCU_X's S3R unit and PCU_Y's S3R unit minus the charging power of all batteries, but less than the sum of the maximum output power of PCU_X's S3R unit, PCU_Y's S3R unit, and PCU_X's BCDR unit minus the charging power of PCU_Y's batteries, the bus voltage is regulated by PCU_X's BCDR unit. At this time, PCU_X's S3R unit and PCU_Y's S3R unit are in the maximum power output state, and PCU_Y's BCDR unit is in the output cutoff state.

[0077] (4) When the load power demand is greater than the sum of the maximum output power of PCU_X's S3R unit, PCU_Y's S3R unit, and PCU_X's BCDR unit minus PCU_Y's battery charging power, the bus voltage is regulated by PCU_Y's BCDR unit. The remaining power units are in the maximum power output state.

[0078] When REF_D_X < REF_D_Y, the working principle of the entire system control is as follows Figure 9 shown:

[0079] (1) When the load power demand is less than the maximum output power of the S3R unit of PCU_X minus all battery charging powers, the bus voltage is regulated by the S3R unit of PCU_X, and the remaining power units are in the output cut-off state.

[0080] (2) When the load power demand is greater than the maximum output power of the S3R unit of PCU_X minus all battery charging powers but less than the sum of the maximum output powers of the S3R units of PCU_X and PCU_Y minus all battery charging powers, the bus voltage is regulated by the S3R unit of PCU_Y. At this time, the S3R unit of PCU_X is in the maximum power output state, and the remaining power units are in the output cut-off state.

[0081] (3) When the load power demand is greater than the sum of the maximum output powers of the S3R units of PCU_X and PCU_Y minus all battery charging powers but less than the sum of the maximum output powers of the S3R units of PCU_X, PCU_Y, and the BCDR unit of PCU_Y minus the battery charging power of PCU_X, the bus voltage is regulated by the BCDR unit of PCU_Y. At this time, the S3R units of PCU_X and PCU_Y are in the maximum power output state, and the BCDR unit of PCU_X is in the output cut-off state.

[0082] (4) When the load power demand is greater than the sum of the maximum output powers of the S3R units of PCU_X, PCU_Y, and the BCDR unit of PCU_Y minus the battery charging power of PCU_X, the bus voltage is regulated by the BCDR unit of PCU_X. The remaining power units are in the maximum power output state.

[0083] To ensure the charge and discharge balance of the battery packs connected to PCU_X and PCU_Y respectively, the control flow is designed as follows Figure 10 shown:

[0084] (1) Initialize REF_A_X = VREF, REF_A_Y = VREF - ΔV, REF_D_X = VREF - 2*ΔV, REF_D_Y = VREF - 3*ΔV, and the working process of the entire system follows Figure 8 operation;

[0085] (2) If (VBAT_X1+VBAT_X2) / 2<(VBAT_Y1+VBAT_Y2) / 2-ΔVB and REF_D_X>REF_D_Y, then the BCDR unit of PCU_X will work first and the battery voltage connected to PCU_X is lower than the battery voltage connected to PCU_Y. Slowly reduce REF_D_X to VREF-3*ΔV and slowly increase REF_D_Y to VREF-2*ΔV. The working state is changed to that the BCDR unit of PCU_Y works first, and the working process of the whole system starts to follow Figure 9 run;

[0086] (3) If (VBAT_Y1+VBAT_Y2) / 2<(VBAT_X1+VBAT_X2) / 2-ΔVB and REF_D_Y>REF_D_X, then the BCDR unit of PCU_Y will work first and the battery voltage connected to PCU_Y is lower than the battery voltage connected to PCU_X. Slowly reduce REF_D_Y to VREF-3*ΔV and slowly increase REF_D_X to VREF-2*ΔV. The working state is changed to that the BCDR unit of PCU_X works first, and the working process of the whole system starts to follow Figure 8 run.

[0087] In the above steps, the REF_D_X and REF_D_Y reference values ​​are slowly changed based on digital control technology to ensure smooth changes in the output current of PCU_X and PCU_Y, and smooth switching of operating states. This process ensures balanced charge and discharge of the battery packs connected to PCU_X and PCU_Y.

[0088] In summary, the present invention has the following technical features:

[0089] (1) A three-domain control system with dual error amplifiers (M_A and M_D) is invented. M_A controls the S3R circuit to achieve SUN domain bus regulation. M_D controls the BCDR circuit to achieve BCR domain and BDR domain bus regulation. The M_D reference value REF_D is slightly lower than the M_A reference value REF_A.

[0090] (2) The control system implementation method is disclosed. The system is a control system that combines analog control and digital control. The M_A outer loop and the S3R inner loop use analog controllers, and the M_D outer loop and the BCDR inner loop use digital controllers. When the power controller operates in the SUN domain, M_A controls S3R to implement the busbar regulation function, M_D operates in a high saturation state, and the BCDR unit charges the battery at the maximum set current. When the power controller operates in the BCR domain, M_D controls the BCDR charging current to implement the busbar regulation function, M_A operates in a low saturation state, and S3R operates in a full power supply state. When the power controller operates in the BDR domain, M_D controls the BCDR discharge current to implement the busbar regulation function, M_A operates in a low saturation state, and S3R operates in a full power supply state.

[0091] (3) Based on the flexibility of digital control, a direct grid-connected control method for dual power supply controllers was invented. The reference voltages of the four main error amplifiers of the two power supply controllers are designed to be REF_A_X>REF_A_Y, REF_A_Y>REF_D_X, and REF_A_Y>REF_D_Y. The magnitude relationship between REF_D_X and REF_D_Y can be changed through software configuration. According to the battery voltage and the operating status of PCU_X and PCU_Y, the busbar voltage regulation value of the BCDR unit of PCU_X and the busbar voltage regulation value of the BCDR unit of PCU_Y are changed by changing the above parameters, so that the operating status of PCU_X and PCU_Y changes alternately, thereby ensuring balanced battery charging and discharging. This method can be extended to the grid-connected control of multiple power supply controllers.

[0092] The beneficial effects of the present invention are as follows:

[0093] (1) Since the BCDR unit and S3R unit have their own independent bus error amplifiers, the loop design of the two is decoupled, the design is more flexible, which is conducive to improving the dynamic characteristics and stability of the bus and enhancing the power expansion capability.

[0094] (2) The S3R control circuit is simple, and analog control makes it easy to achieve independent control of each S3R. The BCDR control circuit is complex, and digital control can improve circuit integration and design flexibility. A control system that combines analog and digital control can ensure high reliability of the power controller S3R circuit and achieve high flexibility of the BCDR control system.

[0095] (3) The power expansion capability of the power controller is further improved by the direct grid-connected control method of the dual power controller. This grid-connected method does not require the addition of a separate grid-connected controller, so that power expansion can be performed without increasing the weight of the entire satellite. This method can also be extended to the grid-connected control of multiple power controllers.

[0096] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A power controller, characterized in that: It includes an S3R, a BCDR, and a bus error amplifier. The bus error amplifier includes a first bus error amplifier (M_A) and a second bus error amplifier (M_D). The S3R represents a shunt regulator, and the BCDR represents a charge and discharge regulation unit. The S3R is connected to the first bus error amplifier (M_A), and the BCDR is connected to the second bus error amplifier (M_D). The first bus error amplifier (M_A) is an analog controller, and the first bus error amplifier (M_A) is used to control the S3R to implement SUN domain bus regulation. The second bus error amplifier (M_D) is a digital controller, and the second bus error amplifier (M_D) controls the BCDR to implement BCR domain and BDR domain bus regulation. The first bus error amplifier (M_A) and the second bus error amplifier (M_D) collect the error between the bus voltage and the reference value, and form the VMEA_A signal and VMEA_D signal respectively through PID calculation. The VMEA_A signal is mapped to the SUN domain, corresponding to multiple S3Rs, and performs sequential shunt regulation. The VMEA_D signal is mapped to the BCR domain and BDR domain. Multiple BCDRs are connected in parallel to regulate the bus voltage. VMEA_A and VMEA_D decrease as the load current I_Load increases. When I_Load is less than the set value, VMEA_A is in the SUN domain, the output power of the SA is greater than the load and charging current requirements, VMEA_D is in a high saturation state, and the BCDR is in charging mode, charging the battery with the maximum current. The bus voltage is regulated by the S3R. As I_Load increases, when the SA's output power exceeds the load requirement but cannot meet the preset maximum battery pack charging current, VMEA_A enters a low-saturation state, all S3Rs supply power to the bus, and VMEA_D enters the BCR domain, where the BCDR regulates the bus voltage through the charging current. As I_Load continues to increase, when the output power of SA cannot meet the load requirements, VMEA_D enters the BDR domain. At this time, VMEA_A is still in a low saturation state, and the bus voltage is regulated by BCDR through the discharge current.

2. The power controller according to claim 1, wherein: The power controller also includes a first digital control unit (PMU1A), a second digital control unit (PMU1B), a third digital control unit (PMU2A), a fourth digital control unit (PMU2B), a fifth digital control unit (PMU3A), and a sixth digital control unit (PMU3B). The first to sixth digital control units are respectively responsible for a BCDR power regulation. The BCDRs corresponding to the first digital control unit (PMU1A), the third digital control unit (PMU2A), and the fifth digital control unit (PMU3A) are connected to a first battery, and the BCDRs corresponding to the second digital control unit (PMU1B), the fourth digital control unit (PMU2B), and the sixth digital control unit (PMU3B) are connected to a second battery. The first digital control unit (PMU1A), the second digital control unit (PMU1B), the third digital control unit (PMU2A), and the fourth digital control unit (PMU2B) participate in voting and voting to achieve a quad-redundant design.

3. The power controller according to claim 1, wherein: The power controller also includes a control system, which includes an analog control system and a digital control system. The digital control system is used to implement BCDR digital control, and the analog control system is used to implement S3R control.

4. The power controller according to claim 3, wherein: BCR function: The single BCR current sampling signal IBUS_BCR undergoes ADC linear transformation K1, and the value after VBCM_D undergoes linear transformation 1 is subtracted to form an error signal. The error signal is then processed by the BCR compensator digital PID operation, and then the DPWM unit generates a PWM signal to control the BCR unit to achieve BCR domain bus regulation function. BDR function: The single BDR current sampling signal IBUS_BDR undergoes ADC linear transformation K2, and the value after VMEA_D undergoes linear transformation 2 is subtracted to form an error signal, which is then processed by the BDR compensator digital PID operation and then produced by the DPWM unit to generate a PWM signal, controlling the BDR unit to realize the BDR domain bus regulation function.

5. A direct grid-connected control method for a power supply controller, characterized in that: The power supply controller includes any one of claims 1 to 4, wherein the power supply controller is 2, and the 2 power supply controllers are PCU_X and PCU_Y respectively, PCU_X represents the first power supply controller, PCU_Y represents the second power supply controller, PCU_X and PCU_Y directly short-circuit the output bus, SA_X_i is connected to S3R of PCU_X, B_X1 and B_X2 are respectively connected to the 2 BCDRs of PCU_X, RL_X1 and RL_X2 are connected to the PC U_X is connected, SA_X_i is the solar cell array connected to PCU_X, B_X1 and B_X2 are batteries connected to PCU_X, RL_X1 and RL_X2 are loads connected to PCU_X; SA_Y_i is connected to S3R of PCU_Y, B_Y1 and B_Y2 are connected to the two BCDRs of PCU_Y respectively, RL_Y1 and RL_Y2 are connected to the PCU_Y, SA_Y_i is the solar cell array connected to PCU_Y, B_Y1 and B_Y2 are batteries connected to PCU_X, RL_X1 and RL_X2 are loads connected to PCU_X; SA_Y_i is connected to S3R of PCU_Y, B_Y1 and B_Y2 are connected to the two BCDRs of PCU_Y respectively, RL_Y1 and RL_Y2 are connected to the PCU_Y U_Y is connected to the battery, RL_Y1 and RL_Y2 are the loads connected to PCU_Y; the reference voltage of the bus error amplifier is REF_A_X>REF_A_Y, REF_A_Y>REF_D_X, REF_A_Y>REF_D_Y, and the size relationship between REF_D_X and REF_D_Y can be changed through software configuration. After direct parallel connection, as the load current increases from 0 to the full load maximum current of two power controllers in parallel, first the S3R of PCU_X is used. Stabilize the bus, followed by the S3R of PCU_Y, and then the BCDR of PCU_X or PCU_Y stabilizes the bus according to the size relationship between REF_D_X and REF_D_Y; according to the battery voltage and the working status of PCU_X and PCU_Y, by changing the bus voltage regulation value of the BCDR unit of PCU_X and the bus voltage regulation value of the BCDR unit of PCU_Y, the working status of PCU_X and PCU_Y changes alternately, thereby ensuring balanced charging and discharging of the battery.

6. The direct grid connection control method according to claim 5, characterized in that: When REF_D_X>REF_D_Y: When the load power demand is less than the maximum output power of PCU_X's S3R minus the charging power of all batteries, PCU_X's S3R regulates the bus voltage, and the remaining power units are in the output cutoff state. When the load power demand is greater than PCU_X's S3R maximum output power minus the charging power of all batteries but less than the sum of the maximum output power of PCU_X's S3R and PCU_Y's S3R minus the charging power of all batteries, PCU_Y's S3R regulates the bus voltage. At this time, PCU_X's S3R unit is in the maximum power output state, and the remaining power units are in the output cutoff state. When the load power demand is greater than the sum of the maximum output powers of S3R of PCU_X and S3R of PCU_Y minus all battery charging powers but less than the sum of the maximum output powers of S3R of PCU_X, S3R of PCU_Y, and BCDR of PCU_X minus the battery charging power of PCU_Y, the bus voltage is regulated by BCDR of PCU_X. At this time, S3R of PCU_X and S3R of PCU_Y are in the maximum power output state, and BCDR of PCU_Y is in the output cut-off state; When the load power demand is greater than the sum of the maximum output powers of S3R of PCU_X, S3R of PCU_Y, and BCDR of PCU_X minus the battery charging power of PCU_Y, the bus voltage is regulated by BCDR of PCU_Y, and the remaining power units are in the maximum power output state.

7. The direct grid connection control method according to claim 5, characterized in that: When REF_D_X < REF_D_Y: When the load power demand is less than the maximum output power of S3R of PCU_X minus all battery charging powers, the bus voltage is regulated by S3R of PCU_X, and the remaining power units are in the output cut-off state; when the load power demand is greater than the maximum output power of S3R of PCU_X minus all battery charging powers but less than the sum of the maximum output powers of S3R of PCU_X and S3R of PCU_Y minus all battery charging powers, the bus voltage is regulated by S3R of PCU_Y. At this time, the S3R unit of PCU_X is in the maximum power output state, and the remaining power units are in the output cut-off state; When the load power demand is greater than the sum of the maximum output powers of S3R of PCU_X and S3R of PCU_Y minus all battery charging powers but less than the sum of the maximum output powers of S3R of PCU_X, S3R of PCU_Y, and BCDR of PCU_Y minus the battery charging power of PCU_X, the bus voltage is regulated by BCDR of PCU_Y. At this time, S3R of PCU_X and S3R of PCU_Y are in the maximum power output state, and BCDR of PCU_X is in the output cut-off state; When the load power demand is greater than the sum of the maximum output powers of S3R of PCU_X, S3R of PCU_Y, and BCDR of PCU_Y minus the battery charging power of PCU_X, the bus voltage is regulated by BCDR of PCU_X, and the remaining power units are in the maximum power output state.

8. The direct grid connection control method according to claim 5, characterized in that: To ensure the charge-discharge balance of the battery packs connected to PCU_X and PCU_Y respectively, the following steps are executed: Step 1: Initialize REF_A_X = VREF, REF_A_Y = VREF - ΔV, REF_D_X = VREF - 2 * ΔV, REF_D_Y = VREF - 3 * ΔV; Step 2: Determine whether (VBAT_X1+VBAT_X2) / 2<(VBAT_Y1+VBAT_Y2) / 2-ΔVB and REF_D_X>REF_D_Y. If so, the BCDR of PCU_X takes priority and the battery voltage connected to PCU_X is lower than the battery voltage connected to PCU_Y. Slowly decrease REF_D_X to VREF-3*ΔV and slowly increase REF_D_Y to VREF-2*ΔV. The working state is changed to PCU_Y's BCDR unit taking priority, and then return to step 2. Otherwise, go to step 3. Step 3: Determine whether (VBAT_Y1+VBAT_Y2) / 2<(VBAT_X1+VBAT_X2) / 2-ΔVB and REF_D_Y>REF_D_X. If so, the BCDR of PCU_Y takes priority and the battery voltage connected to PCU_Y is lower than the battery voltage connected to PCU_X. Slowly decrease REF_D_Y to VREF-3*ΔV and slowly increase REF_D_X to VREF-2*ΔV. The operating state is changed to PCU_X's BCDR unit taking priority, and then return to step 2. Otherwise, execute step 2.

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