An automatic / manual control signal switching circuit for unmanned surface vessels

Abstract

This invention discloses an automatic / manual control signal switching circuit for unmanned surface vessels (USVs). Its main purpose is to solve the problem of manually switching between automatic and manual control signals for remotely operated USVs, ensuring that in the event of autopilot failure, the propeller control signal can be manually taken over, achieving manual operation of the USV. The circuit comprises three parts: a level conversion unit, a logic processing unit, and a logic level trigger switch. Digital signals output from external devices such as local radios are converted into LVTTL logic signals recognizable by the circuit through the level conversion unit. Upon receiving this signal, the logic processing unit immediately performs a corresponding level conversion response and maintains it, triggering and maintaining the on / off state of the subsequent level trigger switch. The control signal switching circuit disclosed in this invention is simple in structure, low in cost, small in size, and easy to operate. By avoiding the use of programmable control units such as microcontrollers for signal switching, it greatly improves the circuit switching efficiency and stability.

Description

Technical Field

[0001] This invention belongs to the field of unmanned surface vessel circuit design, specifically relating to an automatic / manual control signal switching circuit for unmanned surface vessels. Background Technology

[0002] With social development and continuous advancements in science and technology, unmanned, intelligent, and information-based weapon systems have become a development trend in modern weaponry. Unmanned surface vessels (USVs) are special unmanned surface platforms with autonomous navigation, obstacle avoidance, and detection capabilities. They possess advantages such as strong ocean adaptability, a large operating radius, good stealth, high speed, long endurance, good economy, small size, low draft, and unmanned and intelligent operation. Whether for military applications like covert reconnaissance and mine detection, or civilian applications like marine surveying and hydrological investigation, USVs have broad application value and market demand.

[0003] Unmanned surface vessels (USVs) equipped with various sensors possess strong autonomous operation capabilities. Software algorithms are crucial for achieving this autonomy, especially under high-maneuverability conditions, where the reliability of the control program is paramount. However, in external environments with high-frequency electromagnetic signals, the main control chip may malfunction, or vulnerabilities in the program itself may lead to decreased system reliability. These issues could result in the USV losing control and causing irreparable damage. If timely human intervention is implemented upon detecting a problem, cutting off the signal input to the automatic control system and allowing a manually operated remote controller to take over control of the propulsion system, potential losses due to the USV losing control can be avoided. Summary of the Invention

[0004] To address the aforementioned issues, this invention discloses a signal switching circuit that avoids the use of programmable control units such as microcontrollers, which can be used for automatic / manual control signal switching of unmanned surface vessels.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] An automatic / manual control signal switching circuit for unmanned surface vessels (USVs) comprises three parts: a level conversion unit, a logic processing unit, and a logic level trigger switch. Digital signals output from external devices such as local radios are converted into LVTTL logic signals recognizable by the circuit through the level conversion unit. Upon receiving this signal, the logic processing unit immediately performs a corresponding level conversion response and maintains it, thereby triggering and maintaining the on / off state of the subsequent level trigger switch.

[0007] Furthermore, the level conversion unit includes, but is not limited to, level conversion circuits such as "RS232-LVTTL", "RS485-LVTTL" and "RS422-LVTTL" that can convert input signals into LVTTL signals.

[0008] Furthermore, the logic processing unit comprises three parts: an XOR set chip, a latch chip, and an initial set circuit. During a brief period after power-on, the initial set circuit performs logic initialization on the XOR set chip and the latch chip. After initialization, under the coupling effect of the XOR set chip and the latch chip, the logic processing unit maintains a fixed level signal output until a valid signal is obtained from the level conversion unit, at which point a corresponding level conversion is performed.

[0009] Furthermore, there are two initial set circuits, each consisting of a P-channel MOSFET, three resistors, and a capacitor. Taking the initial set circuit of MOSFET Q11 as an example, the source of Q11 is connected to a high level, the bias resistor R21 connects the source and gate of Q11, the bypass capacitor C1 connects the source of Q11 and ground, the current limiting resistor R23 connects from the drain of Q11 to ground, and the current limiting resistor R22 connects to the drain of Q11 and outputs the level signal to the XOR set chip and the latch chip.

[0010] Furthermore, in the initial set circuit, the initial set circuit to which the field-effect transistor Q12 belongs also includes resistors R25, R26, R27 and capacitor C2, and its structure is the same as that of the initial set circuit to which Q11 belongs.

[0011] Furthermore, the XOR setter chip is an integrated chip with two inputs and a single output.

[0012] Furthermore, the latch chip is a single-channel D-type latch.

[0013] Furthermore, the logic processing unit is characterized in that: the " / OE" pin of the latch chip is grounded; the "LE" pin is connected to the output terminal of R22 of the initial set circuit described in Q11; the "D" pin is connected to R26 of the initial set circuit of Q12, the signal output port of the level conversion unit, and the "B" pin of the XOR set chip; the "Q" pin is connected to the "A" pin of the XOR set chip and the input terminal of the logic level trigger switch. The "Y" pin of the XOR set chip is connected to the output terminal of R22 through the current limiting resistor R24.

[0014] Furthermore, the logic level triggered switch includes two sub-switches with and two without a set circuit.

[0015] Furthermore, each of the two sub-switches consists of one P-channel MOSFET, one N-channel MOSFET, and four resistors. Taking the sub-switch belonging to MOSFET Q1 as an example, the bias resistor R1 is connected to the source and gate of the P-channel MOSFET Q1, the current-limiting resistor R2 is connected to the gate of Q1 and the drain of the N-channel MOSFET Q2, the source of Q2 is grounded, the bias resistor R6 is connected to the gate and source of Q2, and the gate of Q2 is connected to the "Q" pin of the latch in the logic processing unit through the current-limiting resistor R5.

[0016] Furthermore, in the two sub-switching circuits, the sub-switching circuit to which the P-channel MOSFET Q4 belongs also includes resistors R7, R8, R11, R12 and an N-channel MOSFET Q5, and its structure is the same as that of the sub-switching circuit to which Q1 belongs.

[0017] Furthermore, in the sub-switch with set circuits, both set circuits consist of one N-channel MOSFET and two resistors. Taking the set circuit of N-channel MOSFET Q3 as an example, voltage divider resistor R3 is connected to the drain of Q1 and the drain of Q3, voltage divider resistor R4 is connected to the drain of Q3 to a high level, the source of Q3 is grounded, and the gate of Q3 is connected to the "Q" pin of the latch in the logic processing unit through current limiting resistor R5.

[0018] Furthermore, in the two set circuits, the set circuit belonging to the N-channel MOSFET Q6 also includes resistors R9 and R10, and its structure is the same as that of the set circuit belonging to Q3.

[0019] Furthermore, in the sub-switch without a set circuit, both sub-switches consist of one P-channel MOSFET, one N-channel MOSFET, and four resistors. Taking the sub-switch belonging to MOSFET Q7 as an example, the bias resistor R13 is connected to the source and gate of the N-channel MOSFET Q7, the current-limiting resistor R14 is connected to the gate of Q7 and the drain of the P-channel MOSFET Q8, the source of Q8 is connected to a high level, the bias resistor R16 is connected to the gate and source of Q8, and the gate of Q8 is connected to the "Q" pin of the latch in the logic processing unit through the current-limiting resistor R15.

[0020] Furthermore, among the two sub-switches, the sub-switch circuit to which the N-channel MOSFET Q9 belongs also includes resistors R17, R18, R19, R20 and a P-channel MOSFET Q10, and its structure is the same as that of the sub-switch circuit to which Q7 belongs.

[0021] The beneficial effects of this invention are:

[0022] This invention discloses an automatic / manual control signal switching circuit for unmanned surface vessels (USVs). It features a simple structure, low cost, small size, and ease of operation, allowing for immediate intervention by the operator to cut off or restore control of the autopilot system at the signal source level. This can avert potential losses due to unmanned vessel loss of control in emergencies. Because this invention avoids the use of programmable control units such as microcontrollers, it is not affected by high-frequency electromagnetic interference and does not need to consider functional failures caused by program malfunctions. Compared to the traditional method of using a microcontroller to capture external control signals and copy them to the thruster, this invention eliminates the signal capture and copying steps, significantly improving circuit switching efficiency and stability, and possesses significant application value. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the signal switching circuit disclosed in Embodiment 1 of the present invention;

[0024] Figure 2 This is a schematic diagram of the usage method of the signal switching circuit disclosed in Embodiment 1 of the present invention; Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] Example 1, as Figure 1 As shown in the figure, this embodiment discloses an automatic / manual control signal switching circuit for unmanned surface vessels. The circuit includes three parts: a level conversion unit, a logic processing unit, and a logic level trigger switch.

[0027] Specifically, the level conversion unit includes, but is not limited to, level conversion circuits such as "RS232-LVTTL", "RS485-LVTTL" and "RS422-LVTTL" that can convert input signals into LVTTL signals.

[0028] The logic processing unit comprises three parts: an XOR set chip, a latch chip, and an initial set circuit. The XOR set chip is a two-input, single-output integrated chip. The latch chip is a single-channel D-type latch. There are two initial set circuits, each consisting of a P-channel MOSFET, three resistors, and a capacitor. Taking the initial set circuit for MOSFET Q11 as an example, the source of Q11 is connected to a high level, the bias resistor R21 connects the source and gate of Q11, the bypass capacitor C1 connects the source and ground of Q11, the current-limiting resistor R23 connects from the drain of Q11 to ground, and the current-limiting resistor R22 connects to the drain of Q11 and outputs the level signal to the XOR set chip and the latch chip. The initial set circuit for MOSFET Q12 also includes resistors R25, R26, R27, and capacitor C2, and its structure is the same as that of the initial set circuit for Q11. The latch chip's " / OE" pin is grounded, the "LE" pin is connected to the output of R22 in the initial set circuit described in Q11, the "D" pin is connected to R26 in the initial set circuit of Q12, the signal output port of the level conversion unit, and the "B" pin of the XOR set chip, respectively, and the "Q" pin is connected to the "A" pin of the XOR set chip and the input of the logic level trigger switch. The "Y" pin of the XOR set chip is connected to the output of R22 through the current limiting resistor R24.

[0029] The logic level trigger switches include two sub-switches with and two without set circuits. Each of the two sub-switches with set circuits consists of one P-channel MOSFET, one N-channel MOSFET, and four resistors. Taking the sub-switch belonging to MOSFET Q1 as an example, bias resistor R1 is connected to the source and gate of P-channel MOSFET Q1, current-limiting resistor R2 is connected to the gate of Q1 and the drain of N-channel MOSFET Q2, the source of Q2 is grounded, bias resistor R6 is connected to the gate and source of Q2, and the gate of Q2 is connected to the "Q" pin of the latch in the logic processing unit via current-limiting resistor R5. The sub-switch circuit belonging to P-channel MOSFET Q4 also includes resistors R7, R8, R11, R12 and N-channel MOSFET Q5, and its structure is the same as that of the sub-switch belonging to Q1. Each of the two set circuits consists of one N-channel MOSFET and two resistors. Taking the set circuit of N-channel MOSFET Q3 as an example, voltage divider resistor R3 is connected to the drain of Q1 and the drain of Q3, voltage divider resistor R4 is connected to the drain of Q3 to a high level, the source of Q3 is grounded, and the gate of Q3 is connected to the "Q" pin of the latch in the logic processing unit through current limiting resistor R5. The set circuit of N-channel MOSFET Q6 also includes resistors R9 and R10, and its structure is the same as that of the set circuit of Q3. Both sub-switches without a set circuit consist of one P-channel MOSFET, one N-channel MOSFET, and four resistors. Taking the sub-switch belonging to MOSFET Q7 as an example, bias resistor R13 connects the source and gate of N-channel MOSFET Q7, current-limiting resistor R14 connects the gate of Q7 and the drain of P-channel MOSFET Q8, the source of Q8 is connected to a high level, bias resistor R16 connects the gate and source of Q8, and the gate of Q8 is connected to the "Q" pin of the latch in the logic processing unit through current-limiting resistor R15. The sub-switch circuit belonging to N-channel MOSFET Q9 also includes resistors R17, R18, R19, R20 and P-channel MOSFET Q10, and its structure is the same as that of the sub-switch belonging to Q7.

[0030] The operation of the automatic / manual control signal switching circuit for unmanned surface vessels disclosed in this embodiment is as follows: Upon power-up, the P3 interface receives no signal, therefore the level conversion unit has no signal input or output; the XOR set chip and latch chip in the logic processing unit power on, and the two initial set circuits power on. Taking the initial set circuit to which Q11 belongs as an example, after power-up, current flows through R21 to charge C1. The gate of Q11 is grounded through the charging C1. At this time, the voltage between the gate and source of Q11 is less than the turn-on voltage, and the source and drain are connected. R23 is grounded, limiting current and dividing voltage. The high-level signal at the drain is current-limited. Resistor R22 outputs to the "LE" pin of the latch. Similarly, the initial set circuit to which Q12 belongs outputs a high-level signal via R26 to the "D" pin of the latch and the "B" pin of the XOR set chip. Because the latch's " / OE" is grounded and both the "LE" and "D" pins are high, the "Q" pin outputs a high level. The "A" pin of the XOR set chip is connected to the "Q" pin of the latch and thus inputs a high level. Both the "A" and "B" pins of the XOR set chip are high, and its "Y" pin outputs a low-level signal to the "LE" pin of the latch. Therefore, the latch latches the currently output high-level signal. When capacitors C1 and C2 are nearly fully charged, they are approximately open-circuited. The gates of Q11 and Q12 are connected to a high-level signal via R21 and R25 respectively. The gate-source voltage cannot meet the conduction condition, so Q11 and Q12 are disconnected. The "LE" pin of the latch is grounded via R22 and R23, and remains locked. In the logic level trigger switch, in the sub-switch to which Q1 belongs, after the gate of Q2 receives a high-level signal from the logic processing unit transmitted via the current-limiting resistor R5, under the action of the bias resistor R6, the source and drain are connected because the gate-source voltage is greater than the power-on power supply. The gate of Q1 is grounded via R2 and Q2. Under the action of the bias resistor R1, as long as a high-level signal is input to the source of Q1, the source and drain are connected, and the high-level signal is transmitted to the drain of Q1. If a low-level signal is input to the source of Q1, the source and drain of Q1 are disconnected. Meanwhile, in the set circuit of Q3, after the gate receives a high-level signal from the logic processing unit transmitted via the current-limiting resistor R5, the gate-source voltage is greater than the turn-on voltage, and the drain and source are connected. One end of R3 is grounded through Q3, and the other end is connected to the drain of Q1. When the drain of Q1 outputs a high level, under the voltage division effect of R3, the drain of Q1 still outputs a high level. When the drain and source of Q1 are disconnected, R3 is grounded, causing the drain port of Q1 to output a low level. The circuit structure of the sub-switch of Q4 is the same as that of the sub-switch of Q1. Thus, after receiving a high-level trigger signal from the logic processing unit, the drains of the sub-switches of Q1 and Q4 can output PWM signals from the source.Of the two sub-switches belonging to Q7 and Q9, taking the sub-switch belonging to Q7 as an example, the high-level signal of the logic processing unit is transmitted to the gate of Q8 through R15. Since the source is connected to a high level, the gate-source voltage of Q8 cannot meet the turn-on condition, so the source and drain of Q8 are disconnected, and consequently the source and drain of Q7 are disconnected. Because the circuit structure of the sub-switch belonging to Q9 is the same, both sub-switches are in the off state.

[0031] Furthermore, after power-on stabilization, when the level conversion unit receives a signal from an external circuit, it immediately converts it into an LVTTL signal applicable to this invention and outputs it to the logic processing unit. When the output signal of the level conversion unit is high, the "B" pin of the XOR set chip receives a high level, and the "A" pin receives a high level because it is connected to the "Q" pin of the latch. At this time, the "Y" pin outputs a low-level signal to the "LE" pin of the latch after the XOR operation. Therefore, the latch maintains the previous output as high, and the on / off state of the logic level trigger switch remains unchanged. When the output signal of the level conversion unit is low, the "B" pin of the XOR set chip receives a low level, and the "A" pin receives a high level because it is connected to the "Q" pin of the latch. At this time, the "Y" pin outputs a high-level signal to the "LE" pin of the latch after the XOR operation. Simultaneously, the "D" pin of the latch receives the low-level signal output by the level conversion unit and begins writing to the latch. The "Q" pin of the latch outputs a low level, and the "A" pin of the XOR set chip also receives a low level. With the "B" pin still low, the "Y" pin of the XOR set chip outputs a low-level signal to the "LE" pin of the latch after the XOR operation, and the latch locks the current output state. After the logic level trigger switch receives the low-level signal from the logic processing unit, the sub-switches to which Q1 and Q4 belong remain open because the gate-source voltages of Q2 and Q5 do not meet the turn-on condition. Taking the sub-switch belonging to Q7 as an example, when the gate of Q8 receives a low-level signal via R15, the gate-source voltage meets the turn-on condition, and the drain and source of Q8 are connected. A high-level signal is transmitted to the gate of Q7 through Q8 and the current-limiting resistor R14. If a low-level signal is input to the source of Q7, then the source and drain of Q7 are connected, and the drain port outputs a low-level signal. If a high-level signal is input to the source of Q7, then the source and drain of Q7 are disconnected. Since the drain of Q7 is connected to the drain of Q1, the drain of Q7 is connected to a high level via R3 and R4, and the drain port of Q7 outputs a high level. The conduction principle of the sub-switch belonging to Q9 is the same as that of the sub-switch belonging to Q7. Therefore, after receiving a low-level trigger signal from the logic processing unit, the drains of the sub-switches belonging to Q7 and Q9 can output PWM signals from the source.At this time, if the logic processing unit receives a high-level signal from the level conversion unit again, the "A" and "B" pins of the XOR set chip will input low-level and high-level signals respectively. The "Y" pin will output a high level after XOR operation and send it to the "LE" pin of the latch to enable the write function of the latch. After writing the high-level signal to the "D" pin, "Q" will output a high level to the "A" pin of the XOR set chip. At this time, the "B" pin will also be high. The "Y" pin will output a low level after XOR operation and send it to the "LE" pin of the latch, so that the latch locks the current output. The logic processing unit will continue to output a high level until the logic level triggers the switch. The sub-switches to which Q1 and Q4 belong will remain on, and the sub-switches to which Q7 and Q9 belong will be off, completing one circuit switch.

[0032] This invention assumes that the thruster has two control signal input ports. Assume that the two control signals from the manual remote control are connected to the sources of Q1 and Q4 respectively, and the two control signals from the automatic driving system are connected to the sources of Q7 and Q9 respectively. The drains of Q1 and Q7 are connected to the first control signal input of the thruster, and the drains of Q4 and Q9 are connected to the second control signal input of the thruster. Only a high-level or low-level signal from the remote control or other device needs to be sent to the level conversion unit. After level conversion, it is transmitted to the logic processing unit. The logic processing unit uses a latch to continuously output the level signal to the logic level trigger switch. The high-level or low-level signal can continuously control the two on and two off states of the four signals, realizing the instantaneous switching of the thruster signal source. A schematic diagram of its functional implementation is shown below. Figure 2 As shown.

[0033] It should be noted that the above embodiments are merely preferred embodiments of the present invention and are not within the scope of protection of the present invention. Equivalent substitutions or replacements made based on the above technical solutions shall all fall within the scope of protection of the present invention.

Claims

1. An automatic / manual control signal switching circuit for a water surface unmanned vehicle, characterized in that: The circuit comprises three parts of a level conversion unit, a logic processing unit and a logic level trigger switch, the digital signal output by the external equipment of the local radio station is converted into the LVTTL logic signal recognizable by the circuit after the level conversion unit, the logic processing unit receives the signal and immediately makes the corresponding level conversion response and keeps to trigger and keep the on-off of the post-level trigger switch; the logic processing unit comprises three parts of an exclusive or setting chip, a latch chip and an initial setting circuit, after power-on, the initial setting circuit starts to make the logic initialization of the exclusive or setting chip and the latch chip, the initialization time depends on the RC time constant of the initial setting circuit, after the initialization, under the coupling of the exclusive or setting chip and the latch chip, the logic processing unit keeps the fixed level signal output, until the valid signal is obtained from the level conversion unit, the corresponding level conversion is made. The initial setting circuit is 2, each initial setting circuit is composed of a P-channel field effect transistor, three resistors and a capacitor. The initial setting circuit comprises the initial setting circuit of the field effect transistor Q11 and the initial setting circuit of the field effect transistor Q12, wherein the initial setting circuit of the field effect transistor Q11 comprises the field effect transistor Q11, resistors R21, R22, R23 and a capacitor C1; the source of the field effect transistor Q11 is connected to high level, the bias resistor R21 is connected to the source and the gate of Q11, the bypass capacitor C1 is connected to the gate of Q11 and the ground, the current limiting resistor R23 is connected from the drain of Q11 to the ground, and the current limiting resistor R22 is connected to the drain of Q11 and outputs the level signal to the exclusive or setting chip and the latch chip; the initial setting circuit of the field effect transistor Q12 comprises the field effect transistor Q12, resistors R25, R26, R27 and a capacitor C2, the source of Q12 is connected to high level, the bias resistor R25 is connected to the source and the gate of Q12, the bypass capacitor C2 is connected to the gate of Q12 and the ground, the current limiting resistor R27 is connected from the drain of Q12 to the ground, and the current limiting resistor R26 is connected to the drain of Q12 and outputs the level signal to the latch chip. The exclusive or setting chip is a two-way input and single-way output integrated chip, and the latch chip is a single-way D-type latch. The " / OE" pin of the latch chip is connected to the ground, the "LE" pin is connected to the output end of R22 of the initial setting circuit of Q11, the "D" pin is connected to R26 of the initial setting circuit of Q12, the signal output port of the level conversion unit and the "B" pin of the exclusive or setting chip respectively, the "Q" pin is connected to the "A" pin of the exclusive or setting chip and the input end of the logic level trigger switch, and the "Y" pin of the exclusive or setting chip is connected to the output end of R22 through the current limiting resistor R24.

2. An automatic / manual control signal switching circuit for an unmanned surface vehicle according to claim 1, characterized in that: The level conversion unit is at least one of "RS232-LVTTL", "RS485-LVTTL", "RS422-LVTTL" or other level conversion circuits capable of outputting LVTTL signal.

3. The automatic / manual control signal switching circuit for the unmanned surface vehicle according to claim 1, wherein: The logic level trigger switch comprises two sub-switches with and without setting circuit respectively.

4. The automatic / manual control signal switching circuit for the unmanned surface vehicle according to claim 3, wherein the sub-switch with the set circuit is composed of one P-channel field effect transistor, one N-channel field effect transistor and four resistors, in the sub-switch of the field effect transistor Q1, the bias resistor R1 connects the source and the gate of the P-channel field effect transistor Q1, the current-limiting resistor R2 connects the gate of Q1 and the drain of the N-channel field effect transistor Q2, the source of Q2 is grounded, the bias resistor R6 connects the gate and the source of Q2, the gate of Q2 is connected to the "Q" pin of the latch in the logic processing unit through the current-limiting resistor R5, in the sub-switch of the field effect transistor Q4, the sub-switch circuit of the P-channel field effect transistor Q4 further comprises resistors R7, R8, R11, R12 and the N-channel field effect transistor Q5, the bias resistor R7 connects the source and the gate of Q4, the current-limiting resistor R8 connects the gate of Q4 and the drain of Q5, the source of Q5 is grounded, the bias resistor R12 connects the gate and the source of Q5, the gate of Q5 is connected to the "Q" pin of the latch in the logic processing unit through the current-limiting resistor R11.

5. An automatic / manual control signal switching circuit for an unmanned surface vehicle according to claim 4, characterized in that: The sub-switch with the set circuit is composed of one N-channel field effect transistor and two resistors, in the set circuit of the N-channel field effect transistor Q3, the voltage-dividing resistor R3 connects the drain of Q1 and the drain of Q3, the voltage-dividing resistor R4 connects the drain of Q3 to the high level, the source of Q3 is grounded, the gate of Q3 is connected to the "Q" pin of the latch in the logic processing unit through the current-limiting resistor R5.

6. An automatic / manual control signal switching circuit for an unmanned surface vehicle according to claim 5, characterized in that: In the two set circuits of the sub-switch with the set circuit, the set circuit of the N-channel field effect transistor Q6 further comprises resistors R9 and R10, the voltage-dividing resistor R9 connects the drain of Q4 and the drain of Q6, the voltage-dividing resistor R10 connects the drain of Q6 to the high level, the source of Q6 is grounded, the gate of Q6 is connected to the "Q" pin of the latch in the logic processing unit through the current-limiting resistor R11.

7. An automatic / manual control signal switching circuit for an unmanned surface vehicle according to claim 6, characterized in that: In the sub-switch without the set circuit, the two sub-switches are composed of one P-channel field effect transistor, one N-channel field effect transistor and four resistors, in the sub-switch of the field effect transistor Q7 without the set circuit, the bias resistor R13 connects the source and the gate of the N-channel field effect transistor Q7, the current-limiting resistor R14 connects the gate of Q7 and the drain of the P-channel field effect transistor Q8, the source of Q8 is connected to the high level, the bias resistor R16 connects the gate and the source of Q8, the gate of Q8 is connected to the "Q" pin of the latch in the logic processing unit through the current-limiting resistor R15; in the sub-switch of the field effect transistor Q9 without the set circuit, the sub-switch circuit of the N-channel field effect transistor Q9 further comprises resistors R17, R18, R19, R20 and the P-channel field effect transistor Q10, the bias resistor R17 connects the source and the gate of Q9, the current-limiting resistor R18 connects the gate of Q9 and the drain of Q10, the source of Q10 is connected to the high level, the bias resistor R20 connects the gate and the source of Q10, the gate of Q10 is connected to the "Q" pin of the latch in the logic processing unit through the current-limiting resistor R19.

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