Suppressing outlier drift coefficients when programming phase-change memory synapses

Abstract

A computer-implemented method for suppressing abnormal value drift in a phase-change memory (PCM) device includes programming, by a controller, the conductance of the PCM device, wherein the programming includes configuring the conductance of the PCM device to a first conductance value at a first time point, the first time point being a programming time point. The programming also includes determining, at a first pre-compensation time point, that the conductance of the PCM device has changed to a second conductance value, the second conductance value differing from a target conductance value by no more than a predetermined threshold. Furthermore, the programming includes reprogramming the PCM device to the first conductance value at a second time point based on the determination, including again measuring the pre-compensation, but at the second pre-compensation time point.

Description

Background Art

[0001] The present invention relates generally to computer technology, and more particularly to programming phase change memory (PCM), and to a method of suppressing outlier drift when programming PCM.

[0002] PCMs exploit the properties of materials that can switch between two phases with different electrical properties. For example, these materials can switch between an amorphous, disordered phase and a crystalline or polycrystalline, ordered phase. These two phases are associated with distinct values of resistivity. Furthermore, intermediate configurations, in which the material only partially switches to either the amorphous or crystalline phase, can be associated with intermediate values of resistivity. Summary of the Invention

[0003] According to one or more embodiments of the present invention, a computer-implemented method for suppressing abnormal value drift in a phase-change memory (PCM) device includes programming, by a controller, the conductance of the PCM device, wherein the programming includes configuring the conductance of the PCM device to a first conductance value at a first point in time, the first point in time being a programming point in time. The programming also includes determining, at a first pre-compensation point in time, that the conductance of the PCM device has changed to a second conductance value, the second conductance value differing from a target conductance value by no more than a predetermined threshold. Furthermore, the programming includes reprogramming the PCM device to the first conductance value at a second point in time based on the determination, including again measuring the pre-compensation, but at the second pre-compensation point in time. Due to conductance drift, the conductance of the PCM device changes to the second conductance value.

[0004] In one or more examples, the pre-compensation time point is a predetermined duration after the programming time point. Further, in one or more examples, the target conductance value at the first pre-compensation time point is determined based on a target time window that is a second predetermined duration after the programming time point. The conductance of the PCM device is maintained within a specific range during the target time window.

[0005] In one or more examples, programming continues until a difference between (i) the second conductance value at the pre-compensation time point and (ii) the target conductance value is less than a predetermined threshold.

[0006] If, at the pre-compensation time point, the difference between the second conductance value at the pre-compensation time point and the target conductance value is less than a predetermined threshold, the method further includes determining, at a first checkpoint, that the conductance of the PCM device has changed to a third conductance value that differs from the second conductance value by no more than the predetermined threshold. The method also includes programming the PCM device to the first conductance value at a third time point, including measuring the pre-compensation again.

[0007] In one or more examples, the first checkpoint is a second predetermined duration after the programming time point. The second target conductance value at the first checkpoint is determined based on a target time window, the target time window being the second predetermined duration since the programming time point, during which the conductance of the PCM device is maintained within a specific range.

[0008] In one or more examples, the PCM device is used as a synapse in an artificial neural network system, and the conductance is the weight assigned to the synapse.

[0009] In one or more examples, the PCM device includes a plurality of PCM devices, each PCM device being associated with a corresponding target conductance value.

[0010] The features described above may also be provided at least by a system, a computer program product, and a machine.

[0011] According to one or more embodiments of the present invention, a computer-implemented method includes configuring a conductance value of a phase-change memory (PCM) device from a plurality of PCM devices in a cross-bar array by receiving a signal at a first time point to configure the conductance of the PCM device to a first conductance value, the first time point being a programming time point. The method further includes determining, at a pre-compensation time point, that the conductance of the PCM device has changed to a second conductance value, the second conductance value not differing from a target conductance value by more than a predetermined threshold. The method further includes receiving another signal at a second time point to configure the conductance of the PCM device to the first conductance value, including measuring the pre-compensation again but at a second pre-compensation time point.

[0012] The features described above may also be provided at least by a system, a computer program product, and a machine.

[0013] Thus, one or more embodiments of the present invention facilitate practical applications and improvements to computer technology, particularly for programming PCM devices and suppressing outlier drift. Embodiments of the present invention can be applied when it is known what the weights of a PCM device should be, and the PCM device is programmed so that it reaches the correct weight values at the correct time in the future. Because the evolution of the PCM device is on a logarithmic scale, the realization is that even after a relatively small (compared to when weights are used) duration (e.g., 1 second, 1 minute, etc.), the measured value of the PCM device's weight can be used to predict whether the PCM device will have the desired target weight within a desired target time window (e.g., 6 months, 1 year, etc.).

[0014] The pre-compensation time point is a predetermined duration after the programmed time point. A target conductance value at the pre-compensation time point is determined based on a target time window, the target time window being a second predetermined duration after the programmed time point. The conductance of the PCM device is to be maintained within a specified range during the target time window.

[0015] Additional technical features and advantages are achieved through the technology of the present invention. Embodiments and aspects of the present invention are described in detail herein, and these embodiments and aspects are considered to be part of the claimed subject matter. For a better understanding, reference is made to the detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The details of the exclusive rights claimed herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 Depicts a block diagram of a deep neural network;

[0018] Figure 2A 、 Figure 2B and Figure 2C depicts a block diagram of a deep neural network using a crossbar array of analog memory in accordance with one or more embodiments of the present invention;

[0019] Figure 3 depicts a block diagram of a phase change memory array device according to one or more embodiments of the present invention;

[0020] Figure 4 depicts the structure of a neuromorphic system implemented using a crossbar array coupled to a plurality of neurons as a network in accordance with one or more embodiments of the present invention;

[0021] Figure 5 depicts example drifts in resistance / conductance values of a phase change memory device according to one or more embodiments of the present invention;

[0022] Figure 6 shows coefficients for an exemplary apparatus according to one or more embodiments of the present invention;

[0023] Figure 7 A flow chart depicting a method for suppressing outlier drift coefficients when programming a phase change memory device according to one or more embodiments of the present invention is depicted;

[0024] Figure 8 depicts an example phase change memory device being programmed according to one or more embodiments of the present invention; and

[0025] Figure 9 A system for programming a phase change memory device that suppresses anomalous value drift according to one or more embodiments of the present invention is described.

[0026] The figures depicted herein are illustrative. Many variations of the figures or operations described herein are possible without departing from the spirit of the present invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Furthermore, the term "coupled" and its variations describe the presence of a communication path between two elements and do not imply a direct connection between the elements, with no intervening elements / connections between them. All such variations are considered part of this specification.

[0027] In the drawings and the detailed description of the disclosed embodiments below, various elements shown in the drawings are provided with two or three reference numerals. With few exceptions, the leftmost digit of each reference numeral corresponds to the drawing in which its element is first shown. DETAILED DESCRIPTION

[0028] Various embodiments of the present invention are described herein with reference to the accompanying drawings. Without departing from the scope of the present invention, alternative embodiments of the present invention may be designed. In the following description and accompanying drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) are described between elements. Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and the present invention is restrictive in this respect and in the schematic diagram. Therefore, the connection of an entity may refer to a direct or indirect connection, and the positional relationship between the entity may be a direct or indirect positional relationship. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive program or process with additional steps or functions not described in detail herein.

[0029] The following definitions and abbreviations will be used to interpret the claims and specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing" or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0030] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" may be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include both indirect and direct connections.

[0031] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on the equipment available at the time the application is filed. For example, "about" may include a range of ±8%, or 5%, or 2% of a given value.

[0032] For the sake of brevity, conventional techniques related to making and using aspects of the present invention may or may not be described in detail herein. In particular, various aspects of the computing systems and specific computer programs used to implement the various technical features described herein are well known. Thus, for the sake of brevity, many conventional implementation details are only briefly mentioned herein or omitted entirely, without providing well-known system and / or process details.

[0033] As previously mentioned, phase change memory (PCM) elements utilize the properties of materials that can switch between two phases with different electrical properties. Currently, alloys from Group VI of the periodic table, such as Te or Se, known as chalcogenides or chalcogenide materials, are advantageously used in phase change cells. In chalcogenides, the resistivity changes by two or more orders of magnitude when the material transitions from an amorphous phase (higher resistance) to a crystalline phase (lower resistance), or vice versa.

[0034] Such properties make PCM elements well suited for providing memory cells and arrays for digital and analog data storage. In particular, in phase change memory, a portion of the chalcogenide material acts as a programmable resistor that can be electrically heated by a controlled current so as to switch between a high resistance condition and a low resistance condition, and vice versa, with associated therewith a first logic value and a second logic value, respectively. The state of the chalcogenide can be read by applying a voltage low enough not to cause heating and by measuring the current passing through it. Since the current is proportional to the conductivity of the chalcogenide material, the two states can be distinguished. For example, chalcogenides formed from an alloy of Ge, Sb, and Te (Ge2Sb2Te5, GST) are widely used to store information in rewritable memory devices, such as in computers and other types of digital storage devices.

[0035] The phase transition between the highly resistive amorphous state and the highly conductive crystalline state can be electrically induced by a current pulse of appropriate amplitude and duration. Specifically, the transition to the amorphous state ("reset") is achieved by applying a current pulse with an amplitude sufficient to heat the chalcogenide above its melting point via the Joule effect. The current pulse used has sharp edges so that the cooling of the chalcogenide is rapid enough to prevent crystallization, such as a rectangular current pulse. Different techniques can be used to induce the transition to the crystalline state ("freezing"). Thus, because the conductivity of the phases of the PCM device is different, this phenomenon can be used to store bits. The internal temperature and its temporal evolution can also be controlled so that the bit enters a state with an intermediate conductivity. In addition to storing bits, this can be used to perform calculations, because a predetermined group (or set) of predetermined threshold phase transitions can be gradually added up to achieve a bit flip.

[0036] The advantages of performing computations in this way are twofold: since the operations occur in memory, it avoids jumping back and forth to memory, and the operations can be done in parallel. Those differences have a natural parallelism with the behavior of a group of neurons, which makes PCM devices suitable for use in artificial neural networks (ANNs) such as deep neural networks (DNNs).

[0037] PCM is further applicable to DNNs (or other types of neural networks). This is because neuronal activity is not binary, all-or-nothing stateful—it can take on a range of intermediate behaviors between on and off. Therefore, the ability of PCM devices to take on states between 1 and 0 allows them to directly model the behavior of neurons.

[0038] To use this for training, a grid (or array) of PCM devices (bits) can be mapped to each layer of the DNN. A communication network consisting of wiring allows neurons to communicate among themselves. The intensity of this communication is set by the state of the memory, which is on a spectrum between fully on and fully off. This state is in turn set by all the bits fed into it. The communication hardware converts the variable intensity signal from the phase-changing bits into signals of varying durations that are compatible with the digital communication network.

[0039] Typically, for implementing a DNN, forward reasoning computations can be slow and energy-intensive due to the need to transfer the network's weight data between conventional digital memory chips and processor chips, as well as the need to maintain the weights constantly in memory. As described above, PCM-based analog non-volatile memory can accelerate forward reasoning and reduce energy consumption by performing parallel multiplication-accumulation operations in the analog domain at the location of the weight data, thereby reducing the need to refresh the weight data stored in memory. The practical applications of such DNNs are not limited and may include real-time sensor data processing and inference for IoT devices, among others.

[0040] The accuracy of forward extrapolation depends strongly on the accuracy of weight programming. However, programming an analog memory (e.g., PCM) to a desired analog conductance value is not trivial, especially given the variability in the analog memory array. After a PCM device is programmed to a particular resistance state (e.g., a low resistance or set state, a high resistance or reset state, or some intermediate state between the set / reset states, such as R1, R2, or R3), the particular resistance value of the resistance state can drift over time. For example, resistance drift is a physical process whereby a PCM device continues to exhibit a steady linear increase in LOG(resistance) as a function of LOG(time) (equivalent to a decrease in LOG(conductance)). While this means that the conductance initially decreases rapidly as a linear function of time and then appears to saturate (as a linear function of time), the conductance continues to decrease over a time interval of at least a predetermined duration (e.g., 6 weeks, 3 months, 1 year, etc.). Such drift can cause problems in distinguishing one resistance state from another, especially when the memory device is operating in a multi-state mode. This may cause a system using a PCM device (e.g., an ANN) to be forced to repeatedly reprogram the PCM device or produce unexpected results (due to different values from the PCM device). Hereinafter, in this document, the minimum duration after which drift causes the conductance value of the PCM device to change by at least a predetermined value is referred to as the "drift duration."

[0041] For forward inference of ANNs implemented using PCM devices that have been programmed at least in the past, while the average loss of conductance can be partially compensated by scaling the read current, the spread of conductance caused by random cycle-to-cycle variations in the drift coefficient "nu" cannot be easily corrected in this way. A way to avoid encoding synaptic weight data into PCM-based synaptic weights that would be poorly corrected by the average scaling factor is still needed.

[0042] The techniques described herein using one or more embodiments of the present invention overcome such technical challenges. Thus, one or more embodiments of the present invention contribute to the practical application and improvement of computer technology, particularly for programming PCM devices and suppressing abnormal value drift. Based on the description herein, other advantages and practical applications provided by one or more embodiments of the present invention will be apparent to those skilled in the art.

[0043] One or more embodiments of the present invention address the technical challenges described herein based on the conductance first falling and then saturating. However, once a PCM device is programmed (programming event), the conductance variation is always a straight line on a LOG(conductance) vs. LOG(time) graph, as long as time is the time since the programming event. Using some other t=0 origin results in data points that violate causality or in a curve that is flat for the first order of magnitude in the time axis and only later matches the actual underlying nu coefficient.

[0044] A description of one or more embodiments of the present invention is now provided, which includes using PCM devices as synapses in an ANN and addresses technical challenges by integrating techniques for suppressing outlier drift coefficients while programming synapses in the ANN.

[0045] Figure 1 A block diagram of a deep neural network is depicted. The depicted DNN 100 has an input layer 110, a hidden layer 120, and an output layer 130, each layer comprising neurons 105. DNNs are loosely inspired by biological neural networks. Neurons 105 act as parallel processing units interconnected by plastic synapses. By tuning the weights of the interconnections, DNN 100 can efficiently solve certain problems, such as classification problems. The training of DNN 100 is generally based on a global supervised learning algorithm commonly referred to as backpropagation. During training, input data is forward propagated through neuron layers 110, 120, and 130, while the synaptic network performs multiple multiplication and accumulation operations. The final layer (output layer 130) response is compared with the input data label, and the error is backpropagated. Both the forward propagation step and the backpropagation step involve a sequence of matrix-vector multiplications. Subsequently, the synaptic weights are updated to reduce the error. Because these operations need to be performed repeatedly using very large data sets (multi-gigabytes) to very large neural networks, this brute force optimization approach can take days or weeks to train a state-of-the-art network on a von Neumann machine. Therefore, in one or more embodiments of the present invention, a coprocessor is used that includes multiple crossbar arrays of PCM devices and other analog communication links and peripheral circuits to accelerate such deep learning steps.

[0046] Figure 2A 、 Figure 2B and Figure 2C A block diagram of a deep neural network using a crossbar array of analog memory is depicted in accordance with one or more embodiments of the present invention. The synaptic weights associated with each layer (110, 120, and 130) of the DNN 100 are in terms of the conductivity values of non-volatile memory (NVM) devices 210 organized in a crossbar array 200. The NVM devices 210 may be PCM devices, resistive random access memory (RRAM) devices, etc. Figure 2A 、 2Band 2C, depicting the various stages of implementing DNN 100 - Figure 2A The forward propagation in Figure 2B Backpropagation in Figure 2C The weight update in .

[0047] In one or more examples, there are multiple such crossbar arrays corresponding to each of the multiple layers (110, 120, and 130) of the DNN 100. According to one or more embodiments of the present invention, the coprocessor / chip / system includes such a crossbar array 200 together with additional peripheral circuits to implement neuron activation functions and communication between the crossbar arrays 200.

[0048] Figure 3 A block diagram of a phase change memory array device according to one or more embodiments of the present invention is depicted. The architecture depicts multiple identical array blocks 310 connected by a flexible routing network on a chip / system 300. Each array block 310 represents a crossbar array 200 of NVM devices 210. The flexible routing network has at least three tasks: (1) passing chip inputs (such as sample data, sample labels, and sample coverage) from the edge of the chip 300 to the device array 310, (2) passing chip outputs (such as inferred classifications and updated weights) from the array 310 to the edge of the chip 300, and (3) interconnecting different arrays 310 to implement a multi-layer neural network. Each array 310 has input neurons 110 (shown here on the "west" side of each array) and output neurons 130 ("south" side), which are connected to a dense grid of synaptic connections 115. The peripheral circuitry is divided into circuits assigned to individual rows (row circuits 320) and columns (column circuits 330), with circuits shared between multiple adjacent rows and columns.

[0049] According to one or more embodiments of the present invention, NVM devices 210 (e.g., PCM devices) in crossbar array 200 are programmed according to pre-trained weights. The pre-trained weights are the weights that NVM devices 210 should implement within neural network calculations, despite any uncertainty / distribution in drift that NVM devices 210 will experience between the time of programming and a future point (the time of actual inference use).

[0050] Figure 4The structure of a neuromorphic system implemented using a crossbar array coupled to a plurality of neurons as a network according to one or more embodiments of the present invention is depicted. The depicted neuromorphic system 400 includes a plurality of neurons 414, 416, 418, and 420 interconnected using a crossbar array 200. In one example, the crossbar array 200 has a pitch in the range of approximately 0.1 nm to 10 μm. The system 400 also includes a synaptic device 422, which includes an NVM device 210 that acts as a variable state resistor at the intersection of the crossbar array 412. The synaptic device 422 is connected to an axon path 424, a dendrite path 426, and a membrane path 427 such that the axon path 424 and the membrane path 427 are orthogonal to the dendrite 426. The terms "axon path," "dendrite path," and "membrane path" are sometimes referred to as "axon," "dendrite," and "membrane," respectively.

[0051] The crossbar array 200 can be a nanoscale crossbar array including NVM devices 210 at the crosspoints, which are used to achieve arbitrary and plastic connectivity between the electronic neurons. Each synaptic device 422 further includes an access or control device 425, which can include a field effect transistor (FET) that is not wired as a diode at each crossbar junction to prevent crosstalk during signal communication (neuron firing events) and minimize leakage and power consumption. It should be noted that in other embodiments, other types of circuits can be used as control devices 425, and FETs are used as one possible example in the description herein.

[0052] Electronic neurons 414, 416, 418, and 420 are configured as circuits on the periphery of the crossbar array 200. In addition to being simple to design and manufacture, the crossbar architecture provides efficient use of available space. The full neuronal connectivity inherent in a full crossbar array can be converted to any arbitrary connectivity by electrical initialization or by omitting shielding steps at undesirable locations during manufacturing. The crossbar array 200 can be configured to customize communication between neurons (e.g., a neuron never communicates with another neuron). Arbitrary connectivity can be achieved by blocking certain synapses at the manufacturing level. Thus, the architectural principles of system 400 can mimic all direct wiring combinations observed in biological neuronal morphological networks.

[0053] The crossbar array 200 further includes driver devices X2, X3, and X4, such as Figure 4. Devices X2, X3, and X4 may include interface driver devices. Specifically, dendrite 426 has a driver device X2 on one side of the cross-bar array 200 and a level shifter device (e.g., sense amplifier) X4 on the other side of the cross-bar array. Axon 424 has a driver device X3 on one side of the cross-bar array 200. The driver devices may include CMOS logic circuits that implement the functions described herein, such as the "west" side and the "south" side ( Figure 3 ).

[0054] These signaling techniques are used to use Figure 2A 、 Figure 2B and Figure 2C The crossbar array 200 depicted in FIG. 1 implements the operation of DNN 100. Figure 2A , forward propagation includes processing data through the neuron layers (110, 120, and 130), where the synaptic network performs a multi-accumulation operation. The matrix-vector multiplication associated with the forward pass can be implemented with O(1) complexity using the depicted crossbar array 200. For example, to perform Ax=b, where A is a matrix and x and b are vectors, the elements of A are linearly mapped to the conductance values of the PCM devices 210 organized in the crossbar array 200. The x value is encoded as the amplitude or duration of the read voltage applied along the row. The positive and negative elements of A are encoded on separate devices along with the subtraction circuit. Alternatively, in one or more examples, the negative vector elements are applied as negative voltages. The resulting current along the column is proportional to the result b. If the input is encoded as a duration, the result b is the total charge (e.g., the current integrated over time). The properties of the NVM device 210 used are multi-level storage capability and Kirchhoff's circuit laws: Ohm's law and Kirchhoff's current law.

[0055] It should be noted that the description of the crossbar array 210 and the neuromorphic system 400 is one possible example implementation, and that one or more embodiments of the present invention may be used in other types of implementations.

[0056] Typically, programming the NVM device 210 (updating the weights) is accomplished by iteratively applying SET pulses with a steadily increasing compliance current. Unlike a RESET pulse (which can cause an abrupt transition to a lower conductance value), continuously applying partial set pulses is believed to result in a more gradual increase in the conductance value of the NVM device 210. Therefore, for the neuromorphic system 400 using the NVM device 210, in existing solutions, partial set pulses are used to tune the PCM device to the desired synaptic weights.

[0057] For example, a typical programming strategy for analog conductance tuning of NVM device 210 is to iteratively apply SET pulses with steadily increasing compliance current (while also potentially increasing pulse duration) to reach a target analog conductance value. NVM device 210 is corrected by an average scaling factor. However, encoding synaptic weight data into PCM-based synaptic weights is not corrected for drift over time by such an average scaling factor.

[0058] Figure 5 Depicted are example drifts of resistance / conductance values for NVM devices according to one or more embodiments of the present invention. It should be understood that the depictions are exemplary values, and that any other resistance / conductance values and drifts are possible in other examples. Figure 5 The drift of the resistance / conductance of individual NVM devices 210 over time is shown. It can be seen that these devices can drift differently from one another. The different drift of each device can be expressed as a drift coefficient ("ν" (nu) coefficient) for the corresponding NVM device 210. The ν coefficient of an NVM device 210 indicates the trajectory of the conductance variation of the NVM device 210 and represents the slope of a straight line on a logarithmic (log) (conductance) vs. logarithmic (time) graph.

[0059] Figure 6 The coefficient ν is shown for an exemplary device according to one or more embodiments of the present invention. Figure 6 The graph in Figure 2 shows the conductance of individual NVM devices 210 over time. Also shown are the coefficients ν for each NVM device. Both the conductance and the time at which the conductance was last read are plotted using a logarithmic scale. The coefficients ν are not values that can be assigned to NVM devices 210. Instead, the coefficients ν appear to be randomly adopted by NVM devices 210 as the devices are programmed. These phenomena are attributed to the random distribution of polycrystalline grains within the NVM devices after each programming event. Consequently, the drift of NVM devices 210 is unpredictable, leading to the technical challenges discussed herein.

[0060] One or more embodiments of the present invention address these technical challenges by programming weight values in NVM device 210 (synapse) and checking the changed weight values in NVM device 210 after a predetermined duration. For example, the changed weight values are checked after waiting 1-60 seconds until the trajectory due to coefficient v is clear. If the changed weight values differ from the target value by at least a predetermined threshold after the predetermined duration (e.g., 1-60 seconds), the NVM device 210 is reprogrammed.

[0061] This loop continues until NVM device 210 selects a coefficient ν that is sufficiently close to the median of the desired coefficient ν distribution. This can be checked at reasonable intervals of 1 second to 1 minute by checking that the device's conductance at that time is within a given bounding box that is related to the original bounding box by a ratio corresponding to the change in conductance of a device with the median coefficient ν drifting over that time interval. Because each check takes less than 1 minute per attempt, multiple programming attempts can be reasonably implemented to protect the neural network from "outlier" nu coefficients over long periods of time into the future. In other words, taking "extra" time to program NVM device 210 multiple times is acceptable, given that this results in NVM device 210 being programmed in a manner that inhibits weight values from drifting beyond a predetermined threshold. This is because drift may require NVM device 210 to be reprogrammed or result in erroneous results from NVM device 210.

[0062] Figure 7 A flow chart of a method for suppressing outlier drift coefficients when programming an NVM device according to one or more embodiments of the present invention is depicted. Figure 8 Describes the Figure 7 Method 700 is shown for programming an example NVM device.

[0063] Method 700 includes determining, at 702, a conductance target for NVM device 210 at a pre-compensation time point 810 (e.g., 20 ns) that pre-compensates for an average expected drift between time point 810 after programming NVM device 210 and a desired target window 850 (e.g., 7 hours, 2 weeks, 6 months, etc.) after programming time point 805. Pre-compensation time point 810 represents a predetermined duration (e.g., 20 ns) for which changes in conductance value of NVM device 210 are examined.

[0064] refer to Figure 8 , NVM device 210 is programmed at time point 805. A desired (target) time window 850 is depicted at approximately 6 hours to 6 months from programming time point 805. It should be understood that in other examples, desired time window 850 may be different. Desired time window 850 represents the duration of time during which the conductance value programmed into NVM device 210 does not change by more than a predetermined threshold due to a median drift coefficient outside of a predetermined interval around the expected drift at that duration, as described herein. Pre-compensation time point 810 is depicted as a predetermined duration of 20 ns from programming time point 805. It should be understood that in other examples, pre-compensation time point 810 may be at a different duration.

[0065] Thus, determining the conductance target for NVM device 210 at pre-compensation time point 810 includes calculating the conductance value that NVM device 210 should have after a predetermined duration. If the conductance value of NVM device 210 is within a predetermined threshold from the conductance target, coefficient v is considered to be within an acceptable range, such that the conductance value of NVM device 210 will not drift beyond the predetermined threshold during target window 850. If the conductance value of NVM device 210 is not within the predetermined threshold from the conductance target at pre-compensation time point 810, coefficient v is considered to be outside the acceptable range. In other words, the conductance of NVM device 210 is predicted to drift beyond the predetermined threshold during target window 850.

[0066] In one or more examples, method 700 includes determining multiple conductance target values at different time points. For example, a first target conductance value is calculated for a pre-compensation time point 805, a second target conductance value is calculated for a checkpoint 815, and so on. From a practical implementation perspective, the number of conductance target values that can be checked must be limited to, for example, two, four, or any other such number that can facilitate multiple programming and checking of the NVM device within a limited time (such as 1 minute, 5 minutes, or any other such programming time).

[0067] Now refer to Figure 7 At 704, NVM device 210 is programmed with a conductance value corresponding to the weight stored in the synapse represented by NVM device 210. Programming occurs at time point 805, as previously described. Method 700 also includes measuring the conductance value of the NVM device at the pre-compensation time point at 706 (810). At 708, the measured conductance value is compared to the target conductance value. If the conductance value measured at the pre-compensation time point 810 is not within a first predetermined threshold corresponding to the conductance target value at the pre-compensation time point 810, then NVM device 210 is reprogrammed, and the checking continues (704, 706, 708).

[0068] If the measured conductance value is within the first predetermined threshold of the target conductance value, the method 700 measures the conductance value again at 710 at a second checkpoint 815. Figure 8 In the example shown, the checkpoint 815 is shown as one second from the programming time point 805; however, it should be understood that in other examples, other checkpoints may be used.

[0069] At 712, the second measured conductance value is compared to the second target conductance value corresponding to checkpoint 815. If the second measured conductance value at checkpoint 815 is not within a predetermined threshold value corresponding to the second conductance target value at checkpoint 815, then the NVM device 210 is reprogrammed and the method operations (704, 706, 708, 710) are repeated. If the second measured conductance value is within a predetermined threshold value of the second target conductance value, then the NVM device 210 is deemed to be programmed with suppressed anomalous value drift.

[0070] Figure 8 Different situations are depicted in which the coefficient ν is varied such that the conductance value drifts by different amounts at the precompensation point 810 and / or the check point 815 . Figure 8 Traces 860 and 865 in FIG. 8 represent NVM devices being programmed so that the conductance values are desired in target window 850. Other traces are depicted to illustrate that measured conductance values that do not meet the target conductance values result in NVM device 210 having conductance values different from those desired in target window 850.

[0071] Because the coefficients have randomness associated with them when programming an NVM device, for most programming events, the conductance will be within the calculated target range, corresponding to the center region of the random distribution of the coefficients. If the measured conductance value is within the target value threshold, the NVM device is most likely to have the expected conductance value at the time span of interest for the application (here, 6 hours to 6 months), represented by the target time window 850. Conversely, if the conductance that was successfully within the first target range at the pre-compensation time point 810 (20 ns) after programming is known to be outside the second target conductance range at the checkpoint 815, this indicates that the coefficient is an outlier. Thus, in this case, the expected conductance at the time span of interest for the application can be predicted to be higher or lower than the expected value.

[0072] This method of reprogramming the NVM device 210 and checking the conductance measurement at a checkpoint after programming can be performed within practically acceptable programming time limits. Thus, after multiple attempts to program the NVM device with an acceptable "average" coefficient v, it can be assumed that abnormal value drift of the NVM device is suppressed and the conductance value is predicted to be within the expected range during the target time window.

[0073] Figure 9A system for programming NVM devices for suppressing outlier drift according to one or more embodiments of the present invention is depicted. The depicted system 900 includes a controller 910 and an NVM device system 920, such as a neural network system including one or more NVM devices 210. The controller 910 can be a computing device including one or more processing units capable of executing one or more computer-executable instructions stored on a memory device. For example, the controller 910 can be a desktop computer, a tablet computer, a phone, a server computer, or any other computing device. The controller 910 and the NVM device system 920 are coupled to each other so that the controller 910 can configure the resistance / conductance (i.e., weights) of the NVM devices 210 in the NVM device system 920. The controller 910 can also read / measure the resistance / conductance of the NVM devices 210. In one or more examples, the controller 910 implements one or more methods described herein. Although the controller 910 and the NVM device system 920 are coupled to each other, the controller 910 can also read / measure the resistance / conductance of the NVM devices 210. Figure 9 2. Although shown as separate blocks in FIG. 2, in one or more embodiments of the present invention, controller 910 and NVM device 210 may be integrated as part of a single block.

[0074] The present invention may be a system, method and / or computer program product of any possible degree of technical detail integration. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon for causing a processor to execute various aspects of the present invention.

[0075] Computer-readable storage media can be a tangible device that can retain and store instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device (for example, a convex structure with instructions recorded thereon in a punch card or a slot), and any suitable combination thereof. Computer-readable storage media as used herein should not be interpreted as a temporary signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission media (for example, a light pulse passing through an optical fiber cable), or an electrical signal emitted by a wire.

[0076] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or downloaded to an external computer or external storage device. The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0077] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of integrated circuits or source code or object code written in any combination of one or more programming languages, these programming languages include object-oriented programming languages (such as Smalltalk, C++ etc.) and process programming languages (such as " C " programming languages or similar programming languages). The computer-readable program instructions can be performed completely on the user's computer, partly on the user's computer, performed as an independent software package, partly on the user's computer, partly on a remote computer or fully on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer by any type of network (including local area network (LAN) or wide area network (WAN)), or can be connected to an external computer (for example, using an internet service provider through the internet). In certain embodiments, the electronic circuit comprising for example programmable logic circuit, field programmable gate array (FPGA) or programmable logic array (PLA) can be personalized to perform the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to perform the electronic circuit, so as to perform various aspects of the present invention.

[0078] The present invention will be described below with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0079] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in the flowchart and / or block diagram or multiple blocks. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture containing instructions that implement aspects of the functions / actions specified in the flowchart and / or block diagram or multiple blocks.

[0080] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other device, so that a series of operational steps are performed on the computer, other programmable device, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable device, or other device implement the functions / actions specified in the flowchart and / or block diagram or multiple boxes.

[0081] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functions and operations of possible implementations of the systems, methods and computer program products according to different embodiments of the present invention. To this end, each box in the flowchart or block diagram may represent a module, segment or portion of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions annotated in the box may not occur in the order annotated in the figure. For example, depending on the functions involved, two blocks shown in succession may actually be executed substantially simultaneously, or the blocks may sometimes be executed in the opposite order. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0082] The description of various embodiments of the present invention has been presented for the purpose of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments described herein.

[0083] In a preferred embodiment of the present invention described herein, a crossbar array is provided, comprising: a plurality of phase change memory (PCM) devices at each of a plurality of crosspoints in the crossbar array, wherein one or more PCM devices represent simulated synapses in an artificial neural network, wherein programming the conductance of the PCM devices from the crossbar array comprises: receiving a signal for configuring the conductance of the PCM device to a first conductance value at a first time point, the first time point being a programming time point; determining, at a precompensation time point, that the conductance of the PCM device has changed to a second conductance value, the second conductance value differing from a target conductance value by no more than a predetermined threshold; and receiving another signal at a second time point to configure the conductance of the PCM device to the first conductance value, including measuring the precompensation again but at a second precompensation time point. Preferably, the precompensation time point is a predetermined duration after the programming time point, and wherein the target conductance value at the precompensation time point is determined based on a target time window, the target time window being the second predetermined duration after the programming time point, wherein the conductance of the PCM device is within a specified range during the target time window.

[0084] In another preferred embodiment of the present invention described herein, a computer-implemented method is provided, comprising: configuring conductance values of phase change memory (PCM) devices from a plurality of PCM devices in a crossbar array by: receiving a signal for configuring the conductance of the PCM device to a first conductance value at a first point in time, the first point in time being a programming point in time; determining at a pre-compensation point in time that the conductance of the PCM device has changed to a second conductance value, the second conductance value not differing from a target conductance value by more than a predetermined threshold; and receiving another signal at a second point in time to configure the conductance of the PCM device to the first conductance value, including measuring the pre-compensation again but at a second pre-compensation point in time.

Claims

1. A computer-implemented method for suppressing abnormal value drift of a phase change memory (PCM) device, the method comprising: The conductance of the PCM device is programmed by a controller, the programming comprising: configuring the conductance of the PCM device to a first conductance value at a first time point, the first time point being a programming time point; At a first pre-compensation time point, determining that the conductance of the PCM device has changed to a second conductance value, the second conductance value differing from a target conductance value by no more than a predetermined threshold; and Reprogramming the PCM device to the first conductance value at a second point in time includes again measuring the precompensation, but at a second precompensation point in time.

2. The method according to claim 1, wherein The first pre-compensation time point is a predetermined duration after the programming time point.

3. The method according to claim 2, wherein: The target conductance value at the first pre-compensation time point is determined based on a target time window having a second predetermined duration after the programming time point, wherein the conductance of the PCM device is expected to be within a specific range during the target time window.

4. The method according to claim 2, wherein: Programming continues until a difference between (i) the second conductance value at the pre-compensation time point and (ii) the target conductance value is less than the predetermined threshold.

5. The method according to claim 1, wherein The programming further comprises: determining, at the first pre-compensation time point, that a difference between the second conductance value at the pre-compensation time point and the target conductance value is less than a predetermined threshold; determining at a first checkpoint that the conductance of the PCM device has changed to a third conductance value, the third conductance value differing from a second target conductance value by no more than the predetermined threshold; and Programming the PCM device to the first conductance value at a third point in time includes again measuring the precompensation.

6. The method according to claim 5, wherein: The first checkpoint is a second predetermined duration after the programming time point.

7. The method according to claim 5, wherein: The second target conductance value at the first checkpoint is determined based on a target time window at a second predetermined duration from the programming time point, wherein the conductance of the PCM device remains within a specific range during the target time window.

8. The method according to claim 1, wherein The PCM device is used as a synapse in an artificial neural network system, and the conductance is the weight assigned to the synapse.

9. The method according to claim 1, wherein The PCM device includes a plurality of PCM devices, each of the PCM devices being associated with a corresponding target conductance value.

10. The method according to claim 1, wherein Due to conductance drift, the conductance of the PCM device becomes the second conductance value.

11. A system comprising: Controller; and a coprocessor comprising one or more crossbar arrays; and wherein the controller is configured to implement the artificial neural network using the coprocessor by mapping layers of the artificial neural network to the crossbar arrays, wherein implementing the artificial neural network comprises the method of any one of claims 1 to 10.

12. A computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a processing circuit to perform a method for suppressing abnormal value drift of a phase change memory (PCM) device, the method according to any one of claims 1 to 10.

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