Quantum State Classifier Using Reservoir Computing

Abstract

A quantum state classifier includes: a reservoir computing circuit for post-processing qubits to obtain a readout signal; and a readout circuit coupled to the reservoir computing circuit for discriminating the quantum state of the qubits from the readout signal among a plurality of possible quantum states. The readout circuit is trained during a calibration process activated by a specific quantum state in each of the plurality of quantum states, such that the weights within the linear readout circuit are updated by mini-batch learning for each of a plurality of measurement sequences for the calibration process. The readout circuit generates a binary output after a plurality of measurement sequences during a post-calibration classification process for test qubits. The quantum state classifier further includes a controller that is coupled to the readout circuit and is selectively triggerable to output a control pulse in response to the quantum state of the test qubits indicated by the binary output.

Description

Background Art

[0001] The present invention generally relates to quantum computing, and more particularly to a quantum state classifier using reservoir computing. Deploying machine learning algorithms requires expensive digital electronics (e.g., FPGAs) and tuning of hyperparameters for each qubit, which is not feasible for large-scale quantum computers. In addition, short-time measurements require fast analog-to-digital converters (ADCs), which consume power and cannot be integrated into cryogenic electronics due to cooling power limitations. Therefore, there is a need for a quantum state classifier that can overcome the above limitations. Summary of the Invention

[0002] According to one aspect of the present invention, a quantum state classifier is provided. The quantum state classifier includes a reservoir computing circuit for post-processing qubits to obtain a readout signal. The quantum state classifier further includes a linear readout circuit operably coupled to the reservoir computing circuit for discriminating the quantum state of the qubits from the readout signal among a plurality of possible quantum states. The linear readout circuit is trained during a calibration process activated by a specific quantum state in each of the plurality of quantum states, such that the weights within the linear readout circuit are updated by mini-batch learning for each measurement sequence of the calibration process. The linear readout circuit generates a binary output after a plurality of measurement sequences during a post-calibration classification process for a test qubit. The quantum state classifier further includes a controller operably coupled to the linear readout circuit, selectively triggerable to output a control pulse in response to the quantum state of the test qubit indicated by the binary output.

[0003] According to another aspect of the present invention, a method for quantum state classification is provided. The method includes post-processing qubits by a reservoir computing circuit to obtain a readout signal. The method further includes discriminating the quantum state of the qubits from the readout signal among a plurality of possible quantum states by a linear readout circuit operably coupled to the reservoir computing circuit, while training the linear readout circuit during a calibration process activated by a specific quantum state in each of the plurality of quantum states. The training process updates the weights within the linear readout circuit by mini-batch learning for each measurement sequence of the calibration process. The method further includes generating a binary output by the linear readout circuit after a plurality of measurement sequences during a post-calibration classification process for a test qubit. The method further includes selectively triggering a controller operably coupled to the linear readout circuit to output a control pulse in response to the quantum state of the test qubit indicated by the binary output.

[0004] According to another aspect of the present invention, a quantum state classifier is provided. The quantum state classifier includes an analog reservoir computing circuit for post-processing qubits using an echo state network (ESN), at least one delay feedback device, and a non-linear amplifier to obtain a readout signal. The quantum state classifier further includes a linear readout circuit operatively coupled to the reservoir computing circuit for discriminating the quantum state of the qubits from the readout signal among a plurality of possible quantum states. The linear readout circuit is trained during a calibration process activated by a specific quantum state among each of the plurality of quantum states, such that the weights within the linear readout circuit are updated by mini-batch learning for each measurement sequence of the calibration process. The linear readout circuit generates a binary output after a plurality of measurement sequences during a post-calibration classification process for a test qubit. The quantum state classifier further includes a controller operatively coupled to the linear readout circuit, selectively triggerable to output a control pulse in response to the quantum state of the test qubit indicated by the binary output.

[0005] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following description will provide details of the preferred embodiments with reference to the following drawings, wherein:

[0007] Figure 1 is a block diagram showing an exemplary quantum state classifier according to an embodiment of the present invention;

[0008] Figure 2 is a flowchart showing an exemplary method for quantum classification according to an embodiment of the present invention;

[0009] Figures 3 - 4 is a flowchart showing an exemplary method for training and using a quantum classifier according to an embodiment of the present invention;

[0010] Figure 5 is a block diagram showing another exemplary quantum state classifier according to an embodiment of the present invention; and

[0011] Figure 6 is a block diagram showing yet another exemplary quantum state classifier according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] Embodiments of the present invention relate to a quantum state classifier using reservoir computing.

[0013] In an embodiment, a readout signal from a qubit is post - processed by a reservoir computing circuit. In an embodiment, the reservoir computing circuit is followed by a linear readout circuit for discriminating quantum states. In an embodiment, these circuits may be implemented by analog hardware (such as one or corresponding microwave circuits for each of the reservoir computing circuit and the linear readout circuit).

[0014] In an embodiment, the linear readout circuit is trained to be activated by a specific quantum state. The output weights within the linear readout circuit are updated by mini - batch learning for each measurement sequence. This process corresponds to calibration.

[0015] In an embodiment, the linear readout circuit generates a binary output after a measurement sequence such that a controller can be triggered by the quantum state. This process corresponds to classification.

[0016] Figure 1 is a block diagram showing an exemplary quantum state classifier 100 according to an embodiment of the present invention.

[0017] The quantum state classifier 100 includes a cryostat 110, a reservoir computing circuit 120, a linear readout circuit 130, a quantum controller 140, an IQ mixer 150, an IQ mixer 160, and a combiner 170. The cryostat 110 includes a quantum chip 110A for processing quantum information.

[0018] The IQ mixer 150 receives a gate pulse 181 and a local oscillator (LO) output 182. The IQ mixer 160 receives a measurement tone 191 and an LO output 192.

[0019] In an embodiment, a readout signal from a qubit is post - processed by the reservoir computing circuit 120. Such post - processing may include, for example, filtering, delaying, amplifying. The linear readout circuit 130 discriminates the quantum state of the qubit. These circuits 120 and 130 may be implemented by analog hardware. In an embodiment, the analog hardware includes microwave circuits. For a physical implementation, the microwave circuit may include non - linear and delay feedback components. Additionally, the microwave circuit may include other physical components with fast dynamics, such as, for example but not limited to, optical systems. Moreover, the microwave circuit may be implemented in whole or in part by one or more field - programmable gate arrays (FPGAs) and / or one or more application - specific integrated circuits (ASICs). For a method - based implementation, an echo state network (ESN) or its derivatives (e.g., leaky integrate - and - fire ESN), a liquid machine, or similar techniques may be used to classify time - domain signals. In an embodiment, the reservoir computing circuit 120 includes a set of recurrently connected units. Thus, in an embodiment, the reservoir computing circuit 120 is implemented by an echo state network (ESN) (see Figure 6)Implementation. The behavior of the ESN is non - linear, and the only weights modified during training are those of the synapses connecting the hidden neurons to the output neurons.

[0020] The linear readout circuit 130 is trained to be activated by specific quantum states. The output weights within the linear readout circuit 130 are updated by mini - batch learning for each of a plurality of measurement sequences. This process corresponds to a calibration process.

[0021] The linear readout circuit 130 generates a binary output after a measurement sequence, such that the controller 140 can be triggered by the quantum state. This process corresponds to a post - calibration (classification) process.

[0022] Thus, the dynamics of the reservoir computing circuit 120 map the input to a higher dimension. Then, the linear readout circuit 130 is trained to read the state of the reservoir and map that state to the desired output. The main benefit is that the training is only performed in the readout phase, and the reservoir 120 is fixed.

[0023] It should be understood that although in one or more embodiments, the reservoir computing circuit 120 is described herein with respect to an ESN, in other embodiments, other types of reservoir computing circuits may be used, including but not limited to, for example, context reverberation networks, backpropagation - decorrelation networks, liquid machines, etc.

[0024] Figure 2 is a flowchart showing an exemplary method 200 for quantum classification according to an embodiment of the present invention.

[0025] In block 210, qubits are post - processed by a reservoir computing circuit to obtain a readout signal.

[0026] In block 220, the quantum state of the qubits from the readout signal is discriminated from a plurality of possible quantum states by a linear readout circuit operably coupled to the reservoir computing circuit. The linear readout circuit is trained during a calibration process activated by a specific quantum state among each of the plurality of quantum states, such that the weights within the linear readout circuit are updated by mini - batch learning for each of a plurality of measurement sequences for the calibration process.

[0027] In block 230, the linear readout circuit generates a binary output after a plurality of measurement sequences during a post - calibration classification process for testing the qubits.

[0028] In block 240, in response to the quantum state of the test qubits indicated by the binary output, a controller operably coupled to the linear readout circuit is selectively triggered to output a control pulse.

[0029] Figures 3 - 4is a flowchart showing an exemplary method 300 for training and using a quantum classifier according to an embodiment of the present invention. Method 300 includes a calibration section 301 and a classification section 302. The calibration section 301 includes blocks 305 to 350. The classification section 302 includes blocks 355 to 380.

[0030] At block 305, activate the calibration path.

[0031] At block 310, set teacher-0 on and teacher-1 off. This block corresponds to implementing calibration with respect to the quantum state prepared by block 315.

[0032] At block 315, prepare the quantum state |0>.

[0033] At block 320, read out the quantum state.

[0034] At block 325, measure <x0 e0> and <x0 e1> via an analog-to-digital converter (ADC).

[0035] At block 330, set teacher-0 off and teacher-1 on. This block corresponds to implementing calibration with respect to the quantum state prepared by block 335.

[0036] At block 335, prepare another quantum state |1>.

[0037] At block 340, read out the other quantum state.

[0038] At block 345, measure <x1 e0> and <x1 e1> via the ADC.

[0039] At block 350, update the linear readout circuit.

[0040] At block 355, determine whether n > NCAL. If so, proceed to block 360. Otherwise, return to block 310. In block 355, n is a variable representing the current iteration number, and NCAL is a threshold iteration number. Thus, once the threshold is exceeded, the calibration section 301 is terminated, and the classification section 302 can be started.

[0041] At block 360, activate the classification path.

[0042] At block 365, set teacher-0 off and teacher-1 off. This block corresponds to implementing quantum state classification.

[0043] At block 370, run the target quantum circuit. This block corresponds to inputting the test qubit whose quantum state is to be discriminated.

[0044] At block 375, the comparator output is measured. The comparator output includes a binary value indicative of the quantum state of the test qubit. According to an embodiment of the present invention, the value of the quantum state can be used to cause an action to be performed in a computer processing system or another system coupled to or receiving output from the quantum classifier.

[0045] Figure 5 is a block diagram showing another exemplary quantum state classifier 500 according to an embodiment of the present invention.

[0046] The following variable definitions and abbreviations apply:

[0047] NL Amp Nonlinear amplifier

[0048] W0 OUT Gain of the readout amplifier

[0049] LO Local oscillator

[0050] I-Q mixer In-phase quadrature mixer

[0051] Q / C Quantum chip

[0052] V ref Reference voltage for the comparator

[0053] The quantum state classifier 500 includes a physical reservoir 510, a set of readout amplifiers 520, an adder 530, a quantum state '1' detector 540, an I-Q mixer 550, a microwave switch 560, and a field programmable gate array (FPGA) 570. The I-Q mixer 550 receives a gate pulse 591 and a local oscillator (LO) output 592.

[0054] The physical reservoir 510 corresponding to and implementing the reservoir computing circuit 520 includes an analog circuit 510A having a delay feedback (implemented by a buffer) 510B, a non-linear (NL) amplifier 510C, and a combiner 510D.

[0055] Each output weight W o can be represented by the gain of the readout amplifier 520, which is determined according to the application of calibration data from the FGPA 570, and the calibration data of the FGPA 570 is in turn obtained from the compiler 583.

[0056] The comparator (e.g., an OP-amp) 540A of the detector 540 is used to binaryize the preprocessed signal of the physical reservoir 510.

[0057] The output weights of the readout amplifier 520 are configured to switch the target quantum state to be detected. Thus, the detector 540 can generate a trigger for any quantum state. The weight information is stored and appropriately configured for a given conditional pulse.

[0058] The conditional pulse is controlled by the fast microwave switch 560 using the gate signal 581 from the comparator 540A.

[0059] Figure 6 FIG. is a block diagram showing yet another exemplary quantum state classifier 600 according to an embodiment of the present invention.

[0060] The following variable definitions and abbreviations apply:

[0061] |0> quantum state

[0062] |1> another quantum state

[0063] x(t) signal from the reservoir unit 602

[0064] W out,0 output weight corresponding to the |0> quantum state

[0065] y0(t) activate the output neuron to detect the |0> quantum state

[0066] ‘H’ high voltage state of the digital circuit

[0067] d0(t) reference signal for the |0> quantum state

[0068] <y0>Average activation of the output neuron to detect the |0> quantum state

[0069] <xe0>Output weight update for the |0> quantum state

[0070] MW Microwave

[0071] LO Local oscillator

[0072] LPF Low-pass filter

[0073] LI-ESN Leaky integrator echo state network

[0074] W out,1 Output weight corresponding to the |1> quantum state

[0075] y1(t) Activate the output neuron to detect the |1> quantum state

[0076] d1(t) Reference signal for the |1> quantum state

[0077] <y1>Average activation of the output neuron to detect the |1> quantum state

[0078] <xe1>Output weight update for |1> quantum state

[0079] Q / C quantum controller

[0080] IQ mixer In-phase quadrature mixer

[0081] ADC Analog-to-Digital Converter

[0082] DAC Digital-to-Analog Converter

[0083] RTC Room temperature electronic device (e.g., personal computer)

[0084] The quantum state classifier 600 includes an LPF 601, an L1-ESN (e.g., microwave circuit) 602, a readout amplifier 603, a switch 604, an adder 605, an analog integrator sub-circuit 606 (formed by a resistor 606A, a capacitor 606B, and an amplifier 606C), an op-amp based comparator (hereinafter referred to as "comparator") 607, a mixer 608, an analog integrator sub-circuit 609 (formed by a resistor 609A, a capacitor 609B, and an amplifier 609C), an ADC 610, a switch 611, a readout amplifier 612, an adder 613, an analog integrator sub-circuit 614 (formed by a resistor 614A, a capacitor 614B, and an amplifier 614C), a mixer 615, an analog integrator sub-circuit 616 (formed by a resistor 616A, a capacitor 616B, and an amplifier 616C), an ADC 617, a field programmable gate array (FPGA) 618, a DAC 619, an I-Q mixer 622, and a microwave (MW) switch 623. The IQ mixer 622 receives a gate pulse 621 and a local oscillator (LO) output 620.

[0085] The switch 604 controls the input 'H' to the adder 605 in response to the quantum state |0>. The switch 611 controls the input 'H' to the adder 605 in response to the quantum state |1>.

[0086] In an embodiment, the reservoir computing circuit 120 may be considered to include the following: an LPF 601; and an L1-ESN 602.

[0087] In an embodiment, the linear readout circuit 130 may be considered to include the following: a readout amplifier 603; a switch 604; an adder 605; an analog integrator sub-circuit 606; a comparator 607; a mixer 608; an analog integrator sub-circuit 609; an ADC 610; a switch 611; a readout amplifier 612; an adder 613; an analog integrator sub-circuit 614; a mixer 615; an analog integrator sub-circuit 616; an ADC 617; a field programmable gate array (FPGA) 618; and a DAC 619.

[0088] In an embodiment, the reservoir computing circuit 120 includes an analog circuit with a delay feedback and a non-linear amplifier.

[0089] Each output weight W out can be represented by the gain of a readout amplifier.

[0090] The output signal is integrated by an analog integrator (sub-circuit) to output the average activation of each neuron, which avoids the need for a fast ADC.

[0091] The linear readout circuit 130 has different paths for quantum state classification and calibration. In an embodiment, the calibration path can output the cost function of an adaptive filter. The classification path 692 is shown with a thicker line compared to the non-classification (i.e., the calibration path). The dashed line represents the digital communication path. The adaptive filter is implemented by the FPGA 618.

[0092] In an implementation, the comparator 607 is used to binaryize the pre-processed signal of the reservoir computing circuit 120.

[0093] The conditional pulse 691 is controlled by a fast microwave switch 623 triggered by a signal from the comparator 607.

[0094] In an embodiment, the reservoir computing circuit 120 can be mounted at the 50K or 4K flange of the cryostat 110 because no power-consuming elements (ADC / DAC) are required.

[0095] It should be understood that the present invention can be applied to any type of quantum state.

[0096] The present invention can be a system, method, and / or computer program product with any possible degree of integration of technical details. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the present invention.

[0097] A computer-readable storage medium can be a tangible device that is capable of retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punched card or raised structures in a groove having instructions recorded thereon, and any appropriate combination of the foregoing. As used herein, a computer-readable storage medium should not be construed to be a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0098] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or an external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include a copper transmission cable, an optical transmission fiber, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the corresponding computing / processing device.

[0099] The computer-readable program instructions for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network connection, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of the present invention, an electronic circuit, including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit.

[0100] Aspects of the present invention are described herein with reference to the flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0101] These computer-readable program instructions can be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions executed via the processor of the computer or other programmable data processing apparatus create means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium, which can direct a computer, a programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored comprises an article of manufacture including instructions for implementing aspects of the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0102] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0103] References in the specification to "an embodiment" or "embodiments" of the present invention and other variations thereof mean that the specific features, structures, characteristics, etc. described in connection with that embodiment are included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in an embodiment" or "in embodiments" and any other variations thereof throughout the specification do not necessarily all refer to the same embodiment.

[0104] It should be understood that, for example, in the cases of "A / B", "A and / or B", and "at least one of A and B", the use of any one of the following " / ", "and / or", and "at least one of" is intended to cover the selection of only the first-listed option (A), or only the second-listed option (B), or the selection of both options (A and B). As a further example, in the cases of "A, B, and / or C" and "at least one of A, B, and C", such wording is intended to include the selection of only the first-listed option (A), or only the second-listed option (B), or only the third-listed option (C), or the selection of only the first and second-listed options (A and B), or only the first and third-listed options (A and C), or only the second and third-listed options (B and C), or the selection of all three options (A and B and C). This can be extended to any number of items listed.

[0105] The flowcharts and block diagrams in the figures illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of an instruction, which includes one or more executable instructions for implementing the specified logical function. In some alternative embodiments, the functions noted in the block may not occur in the order noted in the figures. For example, two consecutive blocks shown may actually be implemented as one step, executed simultaneously, substantially simultaneously, in a partially or fully time-overlapped manner, or these blocks may sometimes be executed in the reverse order, depending on the functions involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified functions or actions or a combination of dedicated hardware and computer instructions.

[0106] Preferred embodiments of the system and method have been described (which are intended to be illustrative and not restrictive), noting that those skilled in the art can make modifications and variations based on the above teachings. Thus, it should be understood that changes can be made in the specific embodiments disclosed, and such changes are within the scope of the present invention as defined by the appended claims. Thus, the aspects of the present invention have been described with the details and characteristics required by patent law, and what is claimed and desired to be protected by letters patent is set forth in the appended claims.

Claims

1. A quantum state classifier, comprising: A reservoir computing circuit for post-processing qubits to obtain a readout signal; A linear readout circuit operatively coupled to the reservoir computing circuit for discerning the quantum state of the qubits from the readout signal among a plurality of possible quantum states, the linear readout circuit being trained during a calibration process activated by a specific quantum state among each of the plurality of quantum states such that the weights within the linear readout circuit are updated by mini-batch learning for each measurement sequence among a plurality of measurement sequences for the calibration process, wherein the linear readout circuit generates a binary output after the plurality of measurement sequences during a post-calibration classification process for test qubits; And A controller operatively coupled to the linear readout circuit, selectively triggerable to output a control pulse in response to the quantum state of the test qubits indicated by the binary output, Wherein the linear readout circuit includes an analog integrator circuit for outputting the average activation of each of a plurality of neurons.

2. The quantum state classifier according to claim 1, wherein the reservoir computing circuit and the linear readout circuit include at least one analog hardware circuit.

3. The quantum state classifier according to claim 2, wherein the at least one hardware circuit includes at least one microwave circuit.

4. The quantum state classifier according to any one of claims 1-3, wherein the reservoir computing circuit includes a non-linear amplifier that uses delayed feedback to amplify the readout signal.

5. The quantum state classifier according to any one of claims 1-3, wherein each of the weights is determined as a function of the gain of at least one readout amplifier included in the linear readout circuit.

6. The quantum state classifier according to any one of claims 1-3, wherein the linear readout circuit includes at least some different circuit paths for the calibration process and the post-calibration classification process.

7. The quantum state classifier according to claim 6, wherein a corresponding one of the different circuit paths for the calibration process outputs a cost function of an adaptive filter.

8. The quantum state classifier according to any one of claims 1-3, wherein the reservoir computing circuit includes a comparator for binaryizing a pre-processing signal representing the qubits before the post-processing.

9. The quantum state classifier according to claim 8, further comprising a microwave switch triggerable by the output of the comparator.

10. The quantum state classifier according to any one of claims 1-3, wherein the linear readout circuit is included in a cryostat.

11. The quantum state classifier according to claim 10, wherein the reservoir computing circuit is included in the cryostat.

12. The quantum state classifier according to any one of claims 1-3, wherein the linear readout circuit is tuned by adjustment of the weights.

13. The quantum state classifier according to any one of claims 1-3, wherein the reservoir computing circuit comprises a leaky integrator echo state network LI-ESN.

14. The quantum state classifier according to any one of claims 1-3, wherein each of the plurality of measurement sequences corresponds to a respective one of the plurality of possible quantum states.

15. A method for quantum state classification, comprising: post-processing qubits by a reservoir computing circuit to obtain a readout signal; discriminating, by a linear readout circuit operably coupled to the reservoir computing circuit, the quantum state of the qubits from the readout signal among a plurality of possible quantum states, while training the linear readout circuit during a calibration process activated by a specific quantum state in each of the plurality of quantum states, wherein the training process updates weights within the linear readout circuit by mini-batch learning for each of the plurality of measurement sequences for the calibration process; generating, by the linear readout circuit, a binary output after the plurality of measurement sequences during a post-calibration classification process for test qubits; and selectively triggering, in response to the quantum state of the test qubits indicated by the binary output, a controller operably coupled to the linear readout circuit to output a control pulse, wherein the linear readout circuit comprises an analog integrator circuit for outputting the average activation of each of a plurality of neurons.

16. The method for quantum state classification according to claim 15, wherein the calibration process sequentially updates the weights for each of the plurality of possible quantum states.

17. The method for quantum state classification according to any one of claims 15-16, wherein the calibration process comprises switching between calibration modes for each of the plurality of possible quantum states.

18. The method for quantum state classification according to any one of claims 15-16, further comprising determining each of the weights as a function of the gain of at least one readout amplifier included in the linear readout circuit.

19. The method for quantum state classification according to any one of claims 15-16, further comprising tuning the linear readout circuit by adjustment of the weights.

20. The method for quantum state classification according to any one of claims 15-16, wherein the post-processing comprises binaryizing a pre-processing signal representing the qubits by a comparator prior to the post-processing.

21. A quantum state classifier, comprising: an analog reservoir computing circuit for post-processing qubits using an echo state network (ESN), at least one delay feedback device, and a non-linear amplifier to obtain a readout signal; A linear readout circuit, operably coupled to the reservoir computing circuit, for discerning the quantum state of the qubit from the readout signal among a plurality of possible quantum states, the linear readout circuit being trained during a calibration process activated by a specific quantum state among each of the plurality of quantum states, such that the weights within the linear readout circuit are updated by mini-batch learning for each of a plurality of measurement sequences for the calibration process, wherein the linear readout circuit generates a binary output after the plurality of measurement sequences during a post-calibration classification process for a test qubit; and a controller, operably coupled to the linear readout circuit, selectively triggerable to output a control pulse in response to the quantum state of the test qubit indicated by the binary output, wherein the linear readout circuit includes an analog integrator circuit for outputting the average activation of each of a plurality of neurons.

22. The quantum state classifier according to claim 21, wherein the linear readout circuit and the reservoir computing circuit are included in a cryostat.

23. The quantum state classifier according to any one of claims 21 to 22, wherein the echo state network is a leaky integrator echo state network LI-ESN.

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