Display substrate and display device

Abstract

A display substrate includes: a substrate (9) including a display area (99) and a peripheral area surrounding the display area (99); a plurality of sub-pixels (1) located in the display area (99); a plurality of data lines (81) located in the display area (99) and electrically connected with the plurality of sub-pixels (1), the plurality of data lines (81) being configured to provide data signals to the plurality of sub-pixels (1); a plurality of pads (71) located in the peripheral area, at least part of the plurality of pads (71) being configured to provide data signals to the plurality of data lines (81); at least one test data signal line (8531) located in the peripheral area; at least one test control signal line (8532) located in the peripheral area; a plurality of test units (3) located in the peripheral area, and the plurality of test units (3) being located on a side of the plurality of pads (71) away from the display area (99), at least one of the plurality of test units (3) being electrically connected with at least one of the test data signal line (8531), the test control signal line (8532), and at least one of the plurality of data lines (81), and being configured to transmit a signal provided by the at least one test data signal line (8531) to the at least one data line (81) according to a signal provided by the at least one test control signal line (8532).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] To simplify the structure of driver chips, detection devices, etc., some of the units or circuits used to drive the display can be directly placed on the display substrate. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a display substrate, comprising:

[0004] The substrate includes a display area and a peripheral area surrounding the display area;

[0005] Multiple sub-pixels are located in the display area;

[0006] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, and the multiple data lines are configured to provide data signals to the multiple sub-pixels;

[0007] Multiple pads are located in the peripheral area, and at least a portion of the multiple pads are configured to provide data signals to the multiple data lines;

[0008] At least one test data signal line is located in the surrounding area;

[0009] At least one test control signal line is located in the surrounding area;

[0010] Multiple test units are located in the peripheral area, and the multiple test units are located on the side of the multiple pads away from the display area. At least one of the multiple test units is electrically connected to at least one of the test data signal lines, at least one of the test control signal lines, and at least one of the multiple data lines, and is configured to transmit a signal provided by at least one of the test data signal lines to the at least one data line according to a signal provided by the at least one of the test control signal lines.

[0011] In some embodiments, the display area includes: a first boundary and a second boundary extending substantially along a first direction, a third boundary and a fourth boundary extending substantially along a second direction, the first boundary and the second boundary being located on opposite sides of the display area, the third boundary and the fourth boundary being located on opposite sides of the display area, a first arc angle connecting the first boundary and the third boundary, a second arc angle connecting the first boundary and the fourth boundary, a third arc angle connecting the second boundary and the third boundary, and a fourth arc angle connecting the second boundary and the fourth boundary;

[0012] The first direction and the second direction intersect each other;

[0013] The surrounding area includes: a first edge area located outside the first boundary, a second edge area located outside the second boundary, a third edge area located outside the third boundary, a fourth edge area located outside the fourth boundary, a first corner area connecting the first edge area and the third edge area, a second corner area connecting the first edge area and the fourth edge area, a third corner area connecting the second edge area and the third edge area, and a fourth corner area connecting the second edge area and the fourth edge area.

[0014] In some embodiments, the first boundary and the second boundary are parallel to the first direction;

[0015] The third boundary and the fourth boundary are parallel to the second direction.

[0016] In some embodiments, the first direction is perpendicular to the second direction;

[0017] The first arc angle, the second arc angle, the third arc angle, and the fourth arc angle are convex arc angles.

[0018] In some embodiments, at least a portion of the plurality of test units are located in the second edge region.

[0019] In some embodiments, all of the test units are located in the second edge region.

[0020] In some embodiments, the display substrate further includes a plurality of multiplexing units, a plurality of multiplexed data signal lines, and a plurality of multiplexed control signal lines located in the peripheral area;

[0021] At least a portion of the plurality of multiplexing units are located in the first edge region;

[0022] The plurality of pads are located on the side of the at least part of the multiplexing unit away from the display area;

[0023] At least one of the plurality of multiplexing units is electrically connected to one of the plurality of multiplexed data signal lines, at least two of the plurality of multiplexed control signal lines, and at least two of the plurality of data lines, and is configured to provide a signal provided by one multiplexed data signal line to the at least two data lines in a time-division manner according to a signal provided by the at least two multiplexed control signal lines.

[0024] In some embodiments, at least two of the plurality of multiplexing units are electrically connected to the same multiplexed data signal line via different sub-lines.

[0025] In some embodiments, the plurality of multiplexed control signal lines are located between the at least one test data signal line and the display area;

[0026] The multiple multiplexed control signal lines are located between the at least one test control signal line and the display area.

[0027] In some embodiments, all of the multiplexing units are located in the first edge region.

[0028] In some embodiments, each of the multiplexed data signal lines is electrically connected to at least one of the plurality of pads;

[0029] Each of the multiplexed control signal lines is electrically connected to at least one of the plurality of pads.

[0030] In some embodiments, the display substrate further includes a plurality of connectors located in the peripheral area;

[0031] The plurality of connectors are located on the side of the plurality of multiplexing units away from the display area;

[0032] At least a portion of the plurality of joints are located on one side of the plurality of pads along the first direction;

[0033] Each of the test data signal lines is electrically connected to at least one of the plurality of connectors;

[0034] Each of the test control signal lines is electrically connected to at least one of the plurality of connectors.

[0035] In some embodiments, along the first direction, the plurality of connectors are respectively located on both sides of the plurality of pads.

[0036] In some embodiments, the display substrate further includes a plurality of first signal lead-in lines located in the peripheral area;

[0037] The plurality of first signal input lines are electrically connected to at least a portion of the plurality of pads, as well as at least one of the plurality of multiplexed control signal lines, the at least one test data signal line, and the at least one test control signal line.

[0038] In some embodiments, the display substrate further includes a plurality of second signal lead-in lines;

[0039] The plurality of second signal lead wires are electrically connected to at least one of the plurality of connectors and at least one of the plurality of first signal lead wires.

[0040] In some embodiments, at least one of the plurality of multiplexing units includes m multiplexing transistors;

[0041] In at least one of the plurality of multiplexing units, the gate of each multiplexing transistor is electrically connected to one of the plurality of multiplexing control signal lines, the first electrode of each multiplexing transistor is electrically connected to one of the plurality of data lines, and the second electrode of the m multiplexing transistors is electrically connected to one of the plurality of multiplexing data signal lines.

[0042] In some embodiments, the plurality of multiplexing units are arranged in a row along the first direction;

[0043] The m multiplexing transistors of at least one of the plurality of multiplexing units are arranged in a row along the first direction, and the first electrode and the second electrode of each multiplexing transistor are respectively located on both sides of the active layer of the multiplexing transistor along the first direction.

[0044] In some embodiments, the at least one test data signal line is located in the peripheral area and is a closed trace surrounding the display area;

[0045] The at least one test control signal line is located in the peripheral area and is a closed trace surrounding the display area.

[0046] In some embodiments, the total number of the at least one test data signal line is n, and the total number of the at least one test control signal line is one, where n is an integer greater than or equal to 2;

[0047] At least one of the plurality of test units includes n test transistors;

[0048] In the same test unit, among the n test transistors, the gates of the n test transistors are electrically connected to the test control signal line, the first electrode of each test transistor is electrically connected to one of the multiple data lines, and the second electrode of each test transistor is electrically connected to one of the n test data signal lines.

[0049] In some embodiments, the plurality of test units are arranged in a row along the first direction;

[0050] At least one of the plurality of test units has n test transistors arranged in a row along a direction that is inclined relative to both the first direction and the second direction. The gates of the n test transistors are a stepped integral structure. The first electrode and the second electrode of each test transistor are located on both sides of the source layer of its multiplexed transistor along the first direction.

[0051] In a second aspect, embodiments of this disclosure provide a display device, which includes:

[0052] Any of the above-mentioned display substrates. Attached Figure Description

[0053] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0054] Figure 1 A schematic diagram illustrating the region division of a substrate in a display substrate according to an embodiment of this disclosure;

[0055] Figure 2 A schematic diagram of the circuit structure of a pixel circuit in a display substrate provided in an embodiment of this disclosure;

[0056] Figure 3 A partial cross-sectional schematic diagram showing the location of the driving transistor of a sub-pixel in a display substrate according to an embodiment of this disclosure;

[0057] Figure 4 This is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0058] Figure 5 A schematic diagram of the circuit structure of a multiplexing unit in a display substrate provided in an embodiment of this disclosure;

[0059] Figure 6 A schematic diagram of the structure of a multiplexing unit in a display substrate provided in an embodiment of this disclosure;

[0060] Figure 7 for Figure 6 A schematic diagram of the structure of the layer containing the active layer of the multiplexed transistor;

[0061] Figure 8 for Figure 6 A schematic diagram of the structure of the layer containing the gate of the multiplexed transistor;

[0062] Figure 9 for Figure 6 A schematic diagram of the structure of another conductive layer in the middle;

[0063] Figure 10 for Figure 6 Schematic diagram of the via locations in the middle insulating layer;

[0064] Figure 11 for Figure 6 A schematic diagram of the structure of the layer containing the first and second electrodes of a multiplexed transistor;

[0065] Figure 12 A schematic diagram of the circuit structure of a test unit in a display substrate provided in an embodiment of this disclosure;

[0066] Figure 13 A schematic diagram of the structure of a test unit in a display substrate provided in an embodiment of this disclosure;

[0067] Figure 14 for Figure 13 A schematic diagram of the structure of the active layer of the transistor being tested;

[0068] Figure 15 for Figure 13 A schematic diagram of the structure of the layer containing the gate of the transistor being tested;

[0069] Figure 16 for Figure 13 A schematic diagram of the structure of another conductive layer in the middle;

[0070] Figure 17 for Figure 13 Schematic diagram of the via locations in the middle insulating layer;

[0071] Figure 18 for Figure 13 A schematic diagram of the structure of the layer containing the first and second electrodes of the multiplexed transistor. Detailed Implementation

[0072] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the display substrate and display device provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0073] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0074] Embodiments of this disclosure can be described with reference to plan views and / or cross-sectional views, taking into account the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0075] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0076] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0077] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0078] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0079] In some related technologies, in order to simplify the structure of driver chips, detection devices, etc., some of the units or circuits used to drive the display can be directly placed on the display substrate.

[0080] To avoid affecting the display, these units or circuits are usually located in the peripheral area of ​​the display substrate. However, these units or circuits occupy a large area, which leads to an excessively wide peripheral area and a wider bezel for the display device, making it difficult to achieve a narrow bezel design.

[0081] Firstly, referring to Figures 1 to 18 This disclosure provides a display substrate.

[0082] Reference Figure 1 , Figure 4 The display substrate in this embodiment is a substrate used in a display device (or display panel).

[0083] The display substrate of this disclosure includes:

[0084] The substrate 9 includes a display area 99 and a peripheral area surrounding the display area 99;

[0085] Multiple sub-pixels 1 are located in display area 99;

[0086] Multiple data lines 81 are located in the display area 99 and electrically connected to multiple sub-pixels 1. The multiple data lines 81 are configured to provide data signals to the multiple sub-pixels 1.

[0087] Multiple pads 71 ​​are located in the peripheral area, and at least some of the multiple pads 71 ​​are configured to provide data signals to multiple data lines 81;

[0088] At least one test data signal line 8531 is located in the surrounding area;

[0089] At least one test control signal line 8532 is located in the surrounding area;

[0090] Multiple test units 3 are located in the peripheral area and on the side of multiple pads 71 ​​away from the display area 99. At least one of the multiple test units 3 is electrically connected to at least one of at least one test data signal line 8531, at least one test control signal line 8532, and multiple data lines 81, and is configured to transmit the signal provided by at least one test data signal line 8531 to at least one data line 81 according to the signal provided by at least one test control signal line 8532.

[0091] Reference Figure 1 , Figure 4 In this embodiment of the present disclosure, the substrate 9 of the display substrate can be a flexible substrate or a rigid substrate. The center of the substrate 9 is a display area 99 for display, and the periphery of the display area 99 is a peripheral area with other structures.

[0092] "A certain structure is located in a certain region" means that the orthographic projection of the structure on the base 9 is located within the range of that region.

[0093] In the display area 99 of the substrate 9, there are multiple sub-pixels 1 for display. Each sub-pixel 1 is the smallest point that can independently emit light with the required brightness and color. Usually, multiple sub-pixels 1 can form a "pixel" that can display light of any color and brightness. Each "pixel" is a "point" in the image to be displayed.

[0094] The display area 99 is also provided with leads for providing driving signals to sub-pixel 1, such as data line 81 for providing data signals (data voltage) to sub-pixel 1.

[0095] Reference Figure 4 In some embodiments, the display area 99 is also provided with other leads such as gate line 82 and control line 83.

[0096] Reference Figure 4In some embodiments, the sub-pixels 1 in the display area 99 are arranged in a matrix, that is, in multiple rows and columns. The data lines 81 are all parallel to the column direction, and each data line 81 is electrically connected to one column of sub-pixels 1; the gate lines 82 are all parallel to the row direction, and each gate line 82 is electrically connected to one row of sub-pixels 1; the control lines 83 are all parallel to the row direction, and each control line 83 is electrically connected to one row of sub-pixels 1.

[0097] Therefore, when displaying each frame, conduction signals (signals that enable transistors to conduct) can be sequentially (time-divisionally) supplied to each gate line 82. When a conduction signal is supplied to each gate line 82, each data line 81 writes data signals to each sub-pixel 1 (e.g., a row of sub-pixels 1) electrically connected to that gate line 82, and stores the data signals in the storage capacitor Cst, so that the sub-pixel 1 can be displayed according to the stored data signals for the remaining time of the frame. The control line 83 is used to control whether the sub-pixel 1 can emit light.

[0098] Here, "row" and "column" are two opposing directions that can be perpendicular to each other. In some of the attached drawings, the row direction is taken as horizontal (left-right) and the column direction as vertical (up-down). However, it should be understood that horizontal and vertical are not restrictions on "row" and "column", and "row" and "column" are not necessarily related to the placement of the display substrate.

[0099] In the peripheral area of ​​the substrate 9, there are also multiple test units 3 (CT) and multiple pads 71. The multiple test units 3 are located on the side of the multiple pads 71 ​​away from the display area 99. In other words, the multiple test units 3 and the multiple pads 71 ​​are located on two opposite sides of the display area 99, that is, they are opposite each other across the display area 99.

[0100] The test unit 3 is electrically connected to the test data signal line 8531 and the test control signal line 8532. Each test unit 3 is used to provide the signal (data signal) of the test data signal line 8531 to (simultaneously or separately) multiple data lines 81 electrically connected to it according to the control of the test control signal line 8532, so as to determine whether the sub-pixel 1 electrically connected to these data lines 81 can be lit, and whether there are bad or bright pixels.

[0101] The pad 71 is a structure provided on the substrate 9 for obtaining signals, and can be a sheet-like layer or multiple layers of metal provided on the substrate 9.

[0102] For example, pad 71 may be a structure (such as a pin) for bonding to a flexible printed circuit board (FPC) or driver chip (IC) to receive signals from the FPC or driver chip.

[0103] Furthermore, at least a portion of the pads 71 ​​are used to provide data signals to the data line 81, that is, at least a portion of the pads 71 ​​are used to provide data signals to the data line 81 during display to control the sub-pixel 1 connected to the data line 81 to display the required content.

[0104] In this embodiment, the test unit 3 is located on the side away from the pad 71, thereby making full and uniform use of the layout area, which helps to reduce the bezel of the display device, realize a narrow bezel design, and improve the screen occupancy ratio.

[0105] In some embodiments, each sub-pixel 1 is provided with a pixel circuit for emitting light.

[0106] For example, the structure of the pixel circuit can be referred to Figure 2 It has a 7T1C structure, which includes a first transistor T1, a second transistor T2, a driving transistor T3 (third transistor), a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, an organic light-emitting diode OLED, a first reset terminal Reset, a second reset terminal Reset', an initialization terminal Vinit, a gate terminal Gate, a data terminal Data, a control terminal EM, a positive terminal VDD, and a negative terminal VSS. Each transistor can be a P-type transistor (such as PMOS) or an N-type transistor (such as NMOS).

[0107] In the pixel circuit described above, by writing a suitable data signal to the gate (first gate 112) of the driving transistor T3, the current flowing through the driving transistor T3 can be controlled, thereby controlling the organic light-emitting diode OLED to emit light at a corresponding brightness, thus realizing the display of sub-pixel 1.

[0108] The positive terminal VDD is electrically connected to the positive signal source (e.g., via a positive wire), and the negative terminal VSS is electrically connected to the negative signal source (e.g., the cathode layer 153 of an organic light-emitting diode OLED). Figure 3 (As shown) Directly connected to the negative signal source, the control electrode EM is connected to the control electrode 83, the gate electrode Gate is connected to the gate electrode 82, and the data electrode Data is connected to the data electrode 81; all other terminals are also electrically connected to the corresponding signal sources.

[0109] Of course, the specific structure of sub-pixel 1 and the pixel circuit is not limited to the above methods.

[0110] Reference Figure 3 In some embodiments, each sub-pixel 1 includes a driving transistor T3 and a storage capacitor Cst; wherein,

[0111] The driving transistor T3 includes:

[0112] The first active layer 11 is located on one side of the substrate 9;

[0113] A gate insulating layer 190 is located on the side of the first active layer 11 away from the substrate 9;

[0114] The first gate 112 is located on the side of the gate insulating layer 190 away from the substrate 9;

[0115] The first insulating layer 191 is located on the side of the first gate 112 away from the substrate 9;

[0116] The second insulating layer 192 (interlayer insulation layer ILD) is located on the side of the first insulating layer 191 away from the substrate 9;

[0117] The first source 113 and the first drain 114 of the first active layer 11 are electrically connected on the side of the second insulating layer 192 away from the substrate 9.

[0118] Storage capacitor Cst includes:

[0119] The first electrode 121 is disposed in the same layer as the first gate 112;

[0120] The second electrode 122 is located between the first insulating layer 191 and the second insulating layer 192.

[0121] When the pixel circuit of each sub-pixel 1 includes a driving transistor T3 and a storage capacitor Cst, the stacking relationship of some structures in sub-pixel 1 can be referred to Figure 3 .

[0122] Of course, subpixel 1 may also include other structures.

[0123] For example, refer to Figure 3 Between the first gate 112 and the substrate 9, a buffer layer 193 (Buffrt) may be provided to improve the contact performance between the first gate 112 and the substrate 9. On the side of the first source 113 and the first drain 114 away from the substrate 9, a planarization layer 194 (PLN) may also be provided. On the side of the planarization layer 194 away from the substrate 9, the above-mentioned organic light-emitting diode (OLED) may also be provided. The OLED may include an anode layer 151 connected to the first drain 114, and a light-emitting layer 152 and a cathode layer 153 provided on the side of the anode layer 151 away from the substrate 99. Thus, the anode layer 151, the light-emitting layer 152, and the cathode layer 153 stacked together constitute an OLED. The OLED may be defined by a pixel defining layer 154 (PDL), and the cathode layer 153 away from the substrate 9 may also be provided with a structure such as an encapsulation layer 155.

[0124] Of course, the structure of sub-pixel 1 can be changed.

[0125] For example, the encapsulation layer 155 can be further divided into an organic encapsulation layer, an inorganic encapsulation layer, etc., and may even include a stacked structure of organic encapsulation layer and inorganic encapsulation layer; and the sub-pixel 1 may also have other structures such as a reflective layer and a color filter film.

[0126] It should be understood that the layer structure of each other transistor in sub-pixel 1 can be set on the same layer as the corresponding structure of driving transistor T3.

[0127] In the following description, some other structures are illustrated by way of example based on this stacking method.

[0128] Reference Figure 4 In some embodiments, at least one test data signal line 8531 is located in the peripheral area and is a closed trace around the display area 99;

[0129] At least one test control signal line 8532 is located in the peripheral area and is a closed trace around the display area 99.

[0130] Reference Figure 4 The surrounding area may be provided with test data signal lines 8531 and test control signal lines 8532 surrounding the display area 99, for example, three test data signal lines 8531 and one test control signal line 8532; moreover, the test data signal lines 8531 and the test control signal lines 8532 respectively form closed loops.

[0131] As can be seen, the above-mentioned leads surrounding the display area 99 (but located in the peripheral area) enable the driving of the test unit 3, simplifying the product structure and reducing the bezel width of the display device.

[0132] Reference Figure 1 In some embodiments, the display area 99 includes: a first boundary 991 and a second boundary 992 extending substantially along a first direction 9991, a third boundary 993 and a fourth boundary 994 extending substantially along a second direction 9992, the first boundary 991 and the second boundary 992 being located on opposite sides of the display area 99, the third boundary 993 and the fourth boundary 994 being located on opposite sides of the display area 99, a first arc angle 9913 connecting the first boundary 991 and the third boundary 993, a second arc angle 9914 connecting the first boundary 991 and the fourth boundary 994, a third arc angle 9923 connecting the second boundary 992 and the third boundary 993, and a fourth arc angle 9924 connecting the second boundary 992 and the fourth boundary 994;

[0133] The first direction 9991 and the second direction 9992 intersect each other;

[0134] The surrounding area includes: a first edge area 91 located outside the first boundary 991, a second edge area 92 located outside the second boundary 992, a third edge area 93 located outside the third boundary 993, a fourth edge area 94 located outside the fourth boundary 994, a first corner area 913 connecting the first edge area 91 and the third edge area 93, a second corner area 914 connecting the first edge area 91 and the fourth edge area 94, a third corner area 923 connecting the second edge area 92 and the third edge area 93, and a fourth corner area 924 connecting the second edge area 92 and the fourth edge area 94.

[0135] Reference Figure 1 As one embodiment of this disclosure, the display area 99 can be basically quadrilateral in shape, that is, the display area 99 has four boundaries, and the boundaries of the display area 99 generally extend along the first direction 9991 or the second direction 9992, but each boundary can specifically be an arc with a small curvature, a broken line with a small bend, etc.; and the adjacent boundaries of the display area 99 are connected by arc-shaped corners (arc angles); correspondingly, the peripheral area includes four edge areas opposite to the four boundaries of the display area 99, and four corner areas opposite to the four arc angles of the display area 99.

[0136] Reference Figure 1 In some embodiments, the first boundary 991 and the second boundary 992 are parallel to the first direction 9991;

[0137] The third boundary 993 and the fourth boundary 994 are parallel to the second direction 9992.

[0138] In some embodiments, the first direction 9991 is perpendicular to the second direction 9992;

[0139] The first arc angle 9913, the second arc angle 9914, the third arc angle 9923, and the fourth arc angle 9924 are convex arc angles.

[0140] Furthermore, refer to Figure 1 The relative boundaries of display area 99 can be parallel straight lines, that is, display area 99 is a quadrilateral with rounded corners.

[0141] Furthermore, refer to Figure 4 The adjacent boundaries of the display area 99 can be perpendicular to each other, and its arc angle is a convex arc angle that bulges outward relative to the display area 99, that is, the display area 99 can be a "convex arc angle rectangle"; correspondingly, the first direction 9991 can also be called the "row direction (horizontal in each figure)" and the second direction 9992 can also be called the "column direction (vertical in each figure)", that is, the data line 81 can extend along the second direction 9992 and the gate line 82 can extend along the first direction 9991.

[0142] Reference Figure 4In some embodiments, at least a portion of the plurality of test units 3 are located in the second edge region 92.

[0143] Reference Figure 4 As one embodiment of this disclosure, at least a portion of the test units 3 are located in the second edge region 92 (test units 3 may also be located in the third corner region 923 and the fourth corner region 924).

[0144] As before, in the first direction 9991, most of the data lines 81 are located at the corresponding second edge area 92 (or in other words, most of the data lines 81 along the extension of the second direction 9992 intersect with the second edge area 92). Therefore, the test unit 3 is located in the second edge area 92 to facilitate electrical connection with the corresponding data lines 81 nearby.

[0145] Reference Figure 4 In some embodiments, all test units 3 are located in the second edge region 92.

[0146] Reference Figure 4 All test units 3 can be located in the second edge area 92, thereby freeing up the third corner area 923 and the fourth corner area 924 to set up other structures.

[0147] Reference Figure 4 In some embodiments, the data line 81 extends along the second direction 9992; the data line 81 located at the corresponding third corner area 923 and fourth corner area 924 on the first direction 9991 is electrically connected to the corresponding test unit 3 through the test connection line 843.

[0148] Reference Figure 4 As before, for the display area 99 with arc corners, some data lines 81 must correspond to the third corner area 923 or the fourth corner area 924 (or in other words, some data lines 81 intersect the third corner area 923 or the fourth corner area 924 along the extension of the second direction 9992). Since there are no test units 3 in the third corner area 923 and the fourth corner area 924, these data lines 81 need to be electrically connected to the corresponding test units 3 located in the second edge area 92 through the obliquely extending test connection lines 843.

[0149] Of course, even if the data line 81 corresponding to the second edge area 92 on the first direction 9991 is not directly aligned with the corresponding test unit 3, it can still be electrically connected to the corresponding test unit 3 through the test connection line 843.

[0150] Reference Figure 4 In some embodiments, the display substrate of this disclosure further includes a plurality of multiplexing units 2, a plurality of multiplexed data signal lines 8521, and a plurality of multiplexed control signal lines 8522 located in the peripheral area;

[0151] At least a portion of the multiplexed units 2 are located in the first edge region 91;

[0152] Multiple pads 71 ​​are located on at least part of the multiplexing unit 2 on the side away from the display area 99;

[0153] At least one of the multiplexed units 2 is electrically connected to one of the multiplexed data signal lines 8521, at least two of the multiplexed control signal lines 8522, and at least two of the multiplexed data lines 81, and is configured to provide a signal provided by one multiplexed data signal line 8521 to at least two data lines 81 in a time-division manner based on the signals provided by at least two multiplexed control signal lines 8522.

[0154] Reference Figure 4 On the opposite side of the location of the test unit 3, multiple multiplexing units 2 (MUX) are also provided. Each multiplexing unit 2 is used to provide the signal (data signal) of a multiplexed data signal line 8521 to multiple data lines 81 electrically connected to it in a time-division manner according to the control of multiple multiplexing control signal lines 8522; that is, the multiplexing unit 2 is used to provide data signals to multiple data lines 81 with a single signal source (e.g., a pin of a driver chip) during the display process, thereby greatly reducing the actual number of signal sources and simplifying the product structure.

[0155] Furthermore, the pad 71 and the multiplexing unit 2 are located on the same side of the display area 99, and are farther away from the display area 99 than the multiplexing unit 2, thus facilitating the provision of signals to the multiplexing unit 2 from the outside.

[0156] Reference Figure 4 At least some of the multiplexing units 2 are located in the first edge region 91 (but multiplexing units 2 may also be located in the first corner region 913 and the second corner region 914).

[0157] As before, the data line 81 can extend along the second direction 9992. Therefore, most of the data lines 81 in the first direction 9991 are located at the corresponding first edge area 91 (or in other words, the extension of most of the data lines 81 along the second direction 9992 intersects with the first edge area 91). Thus, the multiplexing unit 2 is located in the first edge area 91 to facilitate electrical connection with the corresponding data line 81 nearby.

[0158] Reference Figure 4 In some embodiments, all multiplexing units 2 are located in the first edge region 91.

[0159] Reference Figure 4 All multiplexing units 2 can be located only in the first edge region 91, thereby freeing up the first corner region 913 and the second corner region 914 to set up other structures.

[0160] Reference Figure 4 In some embodiments, the data line 81 extends along the second direction 9992; the data line 81 located at the position corresponding to the first corner area 913 or the second corner area 914 on the first direction 9991 is electrically connected to the corresponding multiplexing unit 2 through the multiplexing connection line 842.

[0161] Reference Figure 4 As before, for the display area 99 with arc corners, some data lines 81 must correspond to the first corner area 913 or the second corner area 914 (or in other words, some data lines 81 intersect the first corner area 913 and the second corner area 914 along the extension of the second direction 9992). When there is no multiplexing unit 2 in the first corner area 913 and the second corner area 914, these data lines 81 need to be electrically connected to the corresponding multiplexing unit 2 located in the first edge area 91 through the diagonally extended multiplexing connection line 842.

[0162] Of course, even if the data line 81 corresponding to the first edge region 91 in the first direction 9991 is not directly opposite to the corresponding multiplexing unit 2, it can still be electrically connected to the corresponding multiplexing unit 2 through the multiplexing connection line 842.

[0163] In the display substrate of this embodiment, the multiplexing unit 2 and the test unit 3 are located on two opposite sides of the display area 99, which makes the distribution of different units uniform, which helps to reduce the width of the peripheral area and realize the narrow bezel design of the display device.

[0164] Reference Figure 4 In some embodiments, the display substrate of this disclosure further includes:

[0165] Multiple gate lines 82 are located in the display area 99 and extend along the first direction 9991; the multiple gate lines 82 are electrically connected to multiple sub-pixels 11 and are configured to provide gate drive signals to the multiple sub-pixels 1;

[0166] The gate drive circuit 4 is located in the third edge region 93, the first corner region 913, and the third corner region 923. The gate drive circuit 4 is electrically connected to multiple gate lines 82 and is configured to provide gate drive signals to the multiple gate lines 82.

[0167] As before, refer to Figure 4The display area 99 may also be provided with multiple gate lines 82 extending along the first direction 9991 (row direction) for providing gate drive signals to the gate line terminals of the pixel circuits of each sub-pixel 1; and the gate drive signals of these gate lines 82 can be provided by the gate drive circuit 4 located in the third edge area 93, the first corner area 913, and the third corner area 923; since the gate drive circuit 4 is located in the third edge area 93, the first corner area 913, and the third corner area 923 (i.e., occupying the peripheral area on the left side of the figure), most of the gate lines 82 can be connected to it nearby.

[0168] Specifically, the gate drive circuit 4 may include multiple cascaded gate shift registers, each gate shift register being electrically connected to one or more gate lines 82 to provide a gate drive signal for the corresponding gate line 82; moreover, the output of each gate shift register is also electrically connected to a gate shift register below it to trigger the operation of the corresponding gate shift register.

[0169] The specific forms of gate shift registers vary and will not be described in detail here.

[0170] In terms of position, each gate shift register can be arranged sequentially along the second direction 9992 in the first corner region 913, the third edge region 93, and the third corner region 923.

[0171] Of course, when the gate line 82 and its corresponding gate shift register are not aligned, they can also be electrically connected to the gate shift register through the gate drive connection line.

[0172] Of course, the gate drive circuit 4 also needs to be electrically connected to some other signal sources to obtain the drive signals required for operation. For example, the gate drive circuit 4 can also be electrically connected to a high-level signal source, a low-level signal source, one or more clock signal sources, etc.

[0173] Reference Figure 4 In some embodiments, the display substrate of this disclosure further includes:

[0174] Multiple control electrode lines 83 are located in the display area 99 and extend along the first direction 9991; the multiple control electrode lines 83 are electrically connected to multiple sub-pixels 1 and are configured to provide control electrode drive signals to the multiple sub-pixels 1;

[0175] The control electrode drive circuit 5 is located in the fourth edge region 94, the second corner region 914, and the fourth corner region 924. The control electrode drive circuit 5 is electrically connected to multiple control electrode lines 83 and is configured to provide control electrode drive signals to the multiple control electrode lines 83.

[0176] As before, refer to Figure 4The display area 99 may also be provided with multiple control lines 83 for providing control drive signals to the control line terminals EM of the pixel circuit of each sub-pixel 1; and the control drive signals of these control lines 83 can be provided by the control drive circuit 5 located in the fourth edge area 94, the second corner area 914, and the fourth corner area 924; since the control drive circuit 5 is located in the fourth edge area 94, the second corner area 914, and the fourth corner area 924 (i.e., occupying the peripheral area on the right side of the figure), most of the control lines 83 can be connected to it nearby.

[0177] Specifically, the control pole drive circuit 5 may include multiple cascaded control pole shift registers, each control pole shift register being electrically connected to one or more control pole lines 83 to provide control pole drive signals to the corresponding control pole line 83; moreover, the output of each control pole shift register is also electrically connected to a certain control pole shift register below it to trigger the operation of the corresponding control pole shift register.

[0178] The specific forms of the control pole shift register vary, and will not be described in detail here.

[0179] In terms of position, each control pole shift register can be arranged sequentially along the second direction 9992 in the second corner region 914, the fourth edge region 94, and the fourth corner region 924.

[0180] Of course, when the control pole line 83 and its corresponding control pole shift register are not aligned, it can also be electrically connected to the control pole shift register through the control pole drive connection line.

[0181] Of course, the control electrode drive circuit 5 also needs to be electrically connected to some other signal sources to obtain the drive signals required for operation. For example, the control electrode drive circuit 5 can also be electrically connected to a high-level signal source, a low-level signal source, one or more clock signal sources, etc.

[0182] As before, when the multiplexing unit 2 is only located in the first edge region 91 and the test unit 3 is only located in the second edge region 92, the multiplexing unit 2 and the test unit 3 are not located in the third edge region 93, the fourth edge region 94, and the four corner regions. For this purpose, gate drive circuits 4 and control electrode drive circuits 5 for driving gate lines 82 and control electrode lines 83 can be respectively provided in the peripheral regions on both sides opposite to each other along the first direction 9991 (third edge region 93, first corner region 913, third corner region 923, fourth edge region 94, second corner region 914, and fourth corner region 924) to facilitate providing signals for the corresponding gate lines 82 and control electrode lines 83.

[0183] As can be seen, according to the above method, the gate drive circuit 4 or control electrode drive circuit 5 in each corner area can be easily connected to the corresponding gate line 82 and control electrode line 83 nearby; moreover, each corner area is provided with only one type of circuit, so there is no situation where different circuit structures (such as cells and shift registers) are mixed. The circuit layout design is convenient, and the width of the corner area can be further reduced to achieve the narrow bezel design of the display device.

[0184] Of course, the circuit configuration in the peripheral areas on both sides opposite to each other along the first direction 9991 is not limited to this. For example, a gate drive circuit 4 can be provided in the peripheral areas on both sides opposite to each other along the first direction 9991 to provide power to the gate line 82 on both sides, or to provide power to the gate lines 82 corresponding to different rows respectively; or a control electrode drive circuit 5 can be provided in the peripheral areas on both sides opposite to each other along the first direction 9991 to provide power to the control electrode line 83 on both sides, or to provide power to the control electrode lines 83 corresponding to different rows respectively.

[0185] Reference Figure 4 Each multiplexed data signal line 8521 is electrically connected to at least one of multiple pads 71;

[0186] Each multiplexed control signal line 8522 is electrically connected to at least one of a plurality of pads 71.

[0187] The multiplexed data signal line 8521 and multiplexed control signal line 8522 used to control the multiplexing unit 2 can be connected to the corresponding pad 71 to obtain the required signal from the pad 71.

[0188] Typically, most different multiplexing units 2 require different multiplexed data signal lines 8521, while many (or even all) test units 3 can correspond to the same test signal lines and test control signal lines 8532. Therefore, the number of multiplexed data signal lines 8521 is usually far greater than the total number of test signal lines and test control signal lines 8532. Since the pads 71 ​​and the multiplexing units 2 are located on the same side of the display area 99, the multiplexing units 2 can be connected to the pads 71 ​​nearby via leads, thereby reducing the total length of the leads, reducing their occupied area, reducing the bezel of the display device, and simplifying the product structure.

[0189] Reference Figure 4 In some embodiments, the display substrate of this disclosure further includes a plurality of connectors 72 located in the peripheral area;

[0190] Multiple connectors 72 are located on the side of multiple multiplexing units 2 away from the display area 99;

[0191] At least a portion of the plurality of connectors 72 are located on one side of the plurality of pads 71 ​​along the first direction 9991;

[0192] Each test data signal line 8531 is electrically connected to at least one of multiple connectors 72;

[0193] Each test control signal line 8532 is electrically connected to at least one of multiple connectors 72.

[0194] Reference Figure 4 The display substrate also includes multiple connectors 72 (Pads), which are structures disposed on the substrate 9 for obtaining signals. Specifically, they may be sheet-like layers or multiple layers of metal disposed on the substrate 9. For example, the connectors 72 may be used to contact test probes during testing to obtain signals from the test probes.

[0195] Among them, the test data signal line 8531 and the test control signal line 8532 are electrically connected to the connector 72, that is, the connector 72 is at least used to provide signals to the test unit 3.

[0196] The connector 72 is also located on the side of the multiplexing unit 2 away from the display area 99, and can be located on one or both sides of the pad 71 along the first direction 9991.

[0197] Reference Figure 4 In some embodiments, along the first direction 9991, a plurality of connectors 72 are located on both sides of a plurality of pads 71.

[0198] Reference Figure 4 The pads 71 ​​can be concentrated together to facilitate bonding and connection with flexible circuit boards or driver chips; while multiple connectors 72 are distributed on both sides of the pads 71 ​​along the first direction 9991 to achieve uniform distribution of the connectors 72.

[0199] In some embodiments, along the first direction 9991, except for the pad 711 corresponding to the multiplexed data signal line 8521, the other pads 712 are located in the middle, and the pads 711 corresponding to the multiplexed data signal line 8521 are located on both sides of the other pads 712.

[0200] As mentioned earlier, there are a large number of multiplexed data signal lines 8521 in the display substrate, and a large number of corresponding pads 711. However, there are relatively few other pads 712 (pads 712 corresponding to test data signal lines 8531, test control signal lines 8532, multiplexed control signal lines 8522, positive signal source, negative signal source, clock signal source, etc.). Therefore, from the perspective of uniform layout and simple structure, the other pads 712 except for the pads 711 corresponding to multiplexed data signal lines 8521 can be concentrated in the middle, while a large number of pads 711 corresponding to multiplexed data signal lines 8521 can be placed on both sides to achieve uniform distribution of leads.

[0201] Of course, due to size limitations, therefore... Figure 4The diagram only shows a portion of the multiplexing unit 2, multiplexed data signal line 8521, and corresponding pads 711, but this is not a limitation on the position or number of the actual structure in the embodiments of this disclosure.

[0202] Reference Figure 4 In some embodiments, at least two of the multiplexing units 2 are electrically connected to the same multiplexed data signal line 8521 via different sub-lines 85211.

[0203] Reference Figure 4 In this embodiment of the disclosure, multiple (two in the figure are used as an example) multiplexing units 2 can be electrically connected to a multiplexed data signal line 8521 through their respective sub-lines 85211, so as to minimize the number of data signal lines.

[0204] Of course, in order to achieve individual control of each data line 81, the multiplexing unit 2, which is electrically connected to a multiplexed data signal line 8521, should be electrically connected to different multiplexed control signal lines 8522.

[0205] Reference Figure 4 In some embodiments, multiple multiplexed control signal lines 8522 are located between multiple test data signal lines 8531 and the display area 99;

[0206] Multiple multiplexed control signal lines 8522 are located between multiple test control signal lines 8532 and display area 99.

[0207] Obviously, the multiplexing control signal line 8522 is to be electrically connected to the multiplexing unit 2, so it should be closer to the display area 99 (and of course closer to the multiplexing unit 2) than the leads of the corresponding test unit 3 (test data signal line 8531 and test control signal line 8532).

[0208] For example, when the test data signal line 8531 and the test control signal line 8532 are closed-loop traces, the multiplexing control signal line 8522 may be a lead that extends substantially along the first direction 9991 and is located between the test data signal line 8531 / test control signal line 8532 and the multiplexing unit 2.

[0209] Reference Figure 4 In some embodiments, the display substrate of this disclosure further includes a plurality of first signal introduction lines 871 located in the peripheral area;

[0210] Multiple first signal input lines 871 are electrically connected to at least a portion of multiple pads 71, and at least one of multiple multiplexed control signal lines 8522, at least one of multiple test data signal lines 8531, and at least one of multiple test control signal lines 8532.

[0211] Reference Figure 4 As previously stated, pad 71 is located on the side of multiplexing unit 2 away from display area 99, meaning that pad 71 is at a certain distance from multiplexing unit 2 and test unit 3. Therefore, a first signal input line 871 can be provided to achieve electrical connection between pad 71 and multiplexing control signal line 8522, test data signal line 8531, and test control signal line 8532. For example, each first signal input line 871 can be connected (physically connected; since the first signal input line 871 is obviously conductive, an electrical connection can also be achieved) between the pad 71 and the multiplexed control signal line 8522 (as the line located between the display area 99 and the test data signal line 8531 / test control signal line 8532), or the test data signal line 8531 (as the closed trace above), or the test control signal line 8532 (as the closed trace above), thereby using the first signal input line 871 to achieve an electrical connection between the multiplexed control signal line 8522, the test data signal line 8531, the test control signal line 8532 and the pad 71, thereby enabling the control of the multiplexing unit 2 and the test unit 3 using the pad 71.

[0212] In some embodiments, the substrate 9 is made of a flexible material.

[0213] As one embodiment of this disclosure, the substrate 9 is made of a flexible material (such as polyimide) and has a bendable and deformable structure.

[0214] Therefore, in the display device product, by bending the base 9, the area where the solder pads 71 ​​and connectors 72 are located can be bent to the "back side" of the display area 99, so as to further reduce the width of the bezel of the display device.

[0215] In order to avoid damaging the complex structure such as the multiplexing unit 2, the area where the bending occurs can be located between the area where the multiplexing unit 2 is located and the area where the pad 71 and connector 72 are located, such as the area where the first signal lead-in line 871 is located.

[0216] Reference Figure 4 In some embodiments, the display substrate of this disclosure further includes a plurality of second signal introduction lines 872;

[0217] Multiple second signal lead-in lines 872 are electrically connected to at least one of multiple connectors 72 and at least one of multiple first signal lead-in lines 871.

[0218] Reference Figure 4The connector 72 (e.g., located on the side of pad 71 along the first direction 9991) can be electrically connected to the first signal input line 871 via the second signal input line 872. For example, each second signal input line 872 can be connected (physically connected, since the second signal input line 872 is obviously conductive, so electrical connection can also be achieved) between the connector 72 and the first signal input line 871, so that the signal in the connector 72 can first enter the first signal input line 871, and then enter the multiplexing control signal line 8522, test data signal line 8531, test control signal line 8532, etc. via the first signal input line 871, so as to realize the control of multiplexing unit 2, test unit 3, etc. by the connector 72.

[0219] With the above structure, the signals from connector 72 and pad 71 are ultimately introduced through the first signal lead-in line 871, thereby reducing the number and total length of leads, saving layout area, simplifying product structure, and reducing the bezel of the display device.

[0220] Of course, it should be understood that when there is a gate drive circuit 4 and a control electrode drive circuit 5, corresponding leads, pads 71, connectors 72, etc. can also be provided to provide signals, which will not be described in detail here.

[0221] In the accompanying drawings, due to space limitations, the gate drive circuit 4 and the control electrode drive circuit 5 each correspond to only one pad 71 (or connector 72). However, it should be understood that this does not represent the actual number of pads 71 ​​(or connectors 72) corresponding to the gate drive circuit 4 and the control electrode drive circuit 5.

[0222] Of course, it should be understood that other structures in sub-pixel 1 (such as the positive end VDD, the negative end VSS, etc.) may also have corresponding leads, pads 71, connectors 72, etc. to provide signals, which will not be described in detail here.

[0223] Reference Figure 5 , Figure 6 In some embodiments, at least one of the multiplexing units 2 includes m multiplexing transistors 21;

[0224] In at least one of the multiplexed units 2, among the m multiplexed transistors 21, the gate 211 of each multiplexed transistor 21 is electrically connected to one of the multiple multiplexed control signal lines 8522, the first electrode 213 of each multiplexed transistor 21 is electrically connected to one of the multiple data lines 81, and the second electrode 214 of the m multiplexed transistors 21 is electrically connected to one of the multiple multiplexed data signal lines 8521.

[0225] Reference Figure 5 , Figure 6Each multiplexing unit 2 may include m (m is at least 2) multiplexing transistors 21, the gates 211 of the m multiplexing transistors 21 are electrically connected to different multiplexing control signal lines 8522, the first poles 213 (such as drains) are electrically connected to different data lines 81, and the second poles 214 (such as sources) are electrically connected to the same multiplexing data signal line 8521 (such as connected through sub-line 85211).

[0226] As can be seen, during the display process, when a conduction signal is provided to any gate line 82, a conduction signal can be provided to each control signal line in a time-division manner so that each multiplexing transistor 21 in each multiplexing unit 2 is turned on in a time-division manner. When any multiplexing transistor 21 is turned on, the data signal required by the data line 81 electrically connected to the multiplexing transistor 21 is provided through the multiplexed data signal line 8521 so as to write the data signal into the corresponding sub-pixel 1.

[0227] For example, refer to Figure 5 m is 3, meaning that each multiplexing unit 2 can control 3 data lines 81 (one to three).

[0228] Clearly, based on the above method, the number of data lines 81 can be equal to m * the number of multiplexing units 2; while the number of multiplexing control signal lines 8522 cannot be less than m, for example, referring to... Figure 4 , Figure 5 When every two multiplexing units 2 are electrically connected to a multiplexed data signal line 8521, the number of multiplexed control signal lines 8522 can be 2m (e.g., 6).

[0229] In some embodiments, refer to Figure 4 , Figure 6 Multiple multiplexing units 2 are arranged in a row along the first direction 9991;

[0230] At least one of the multiplexed units 2 has m multiplexed transistors 21 arranged in a row along the first direction 9991, and the first electrode 213 and the second electrode 214 of each multiplexed transistor 21 are located on both sides of the active layer 212 of the multiplexed transistor 21 along the first direction 9991.

[0231] Reference Figure 4 , Figure 6 As one embodiment of this disclosure, each multiplexing unit 2 can be arranged in a row along the first direction 9991 in the first edge region 91; and the m multiplexing transistors 21 in each multiplexing unit 2 are also arranged in a row along the first direction 9991; moreover, the first electrode 213 and the second electrode 214 of each multiplexing transistor 21 are also located on both sides of its active layer 212 along the first direction 9991.

[0232] As before, the data line 81 extends along the second direction 9992, that is, multiple data lines 81 are arranged sequentially along the first direction 9991. Therefore, each multiplexing unit 2 and the transistors therein are arranged along the first direction 9991, which is beneficial for connection with the corresponding data line 81 and makes the structure regular and easy for layout design.

[0233] The specific layer distribution of each structure in the multiplexing unit 2 can be varied.

[0234] For example, refer to Figure 3 , Figures 6 to 11 The active layer 212 of each multiplexed transistor 21 Figure 7 The multiplexed transistor 21 can be disposed on the same layer as the first active layer 11 and arranged at intervals along the first direction 9991, and is covered by the gate insulating layer 190; while the gate 211 of each multiplexed transistor 21 ( Figure 8 The first gate 112 can be disposed on the same layer as the second gate 112, and the same layer also has a structure (or a part of the data line 81) for electrically connecting the first electrode of the partial multiplexed transistor 21 to the corresponding data line 81; while the second electrode 122 can be disposed on the same layer as the second electrode 122. Figure 9 ), and a structure that electrically connects the first electrode 213 of another part of the multiplexed transistor 21 to the corresponding data line 81 (or a part of the data line 81); on the same layer as the first source 113 and the first drain 114, the first electrode 213 and the second electrode 214 of the multiplexed transistor 21 can be provided. Figure 11 In the same multiplexing unit 2, the second terminals 214 of each multiplexing transistor 21 are connected together at one end; and the vias in the second insulating layer 192 ( Figure 10 This allows for the electrical connection of the corresponding structure.

[0235] Reference Figure 12 , Figure 13 In some embodiments, the total number of at least one test data signal line 8531 is n, and the total number of at least one test control signal line 8532 is one, where n is an integer greater than or equal to 2;

[0236] At least one of the multiple test units 3 includes n test transistors 31;

[0237] In the same test unit 3, among the n test transistors 31, the gates 311 of the n test transistors 31 are electrically connected to a test control signal line 8532, the first terminal 313 of each test transistor 31 is electrically connected to one of the multiple data lines 81, and the second terminal 314 of each test transistor 31 is electrically connected to one of the n test data signal lines 8531.

[0238] Reference Figure 12As one embodiment of this disclosure, the number of test data signal lines 8531 is n (n should be at least 2), while there is only one test control signal line 8532; each test unit 3 also includes n test transistors 31, the gates 311 of the n test transistors 31 are all electrically connected to the test control signal line 8532, and the first poles 313 (such as drains) are electrically connected to different data lines 81 respectively; the second poles 314 (such as sources) of the n test transistors 31 are electrically connected to the n test data signal lines 8531 respectively (that is, the second poles of different test transistors 31 are electrically connected to different test data signal lines 8531).

[0239] As can be seen, the test control signal line 8532 can control whether the test transistor 31 in each test unit 3 is turned on, and can control the signal of each test data signal line 8531 to be written to different data lines 81, that is, control "whether to perform test"; when test is to be performed, a turn-on signal can be provided to the test control signal line 8532, and the required signal can be provided to each of the n test data signal lines 8531, so that each data line 81 obtains the required signal to realize detection.

[0240] Therefore, in some embodiments, the number of data lines 81 may be equal to n * the number of test units 3.

[0241] In some embodiments, n is 3.

[0242] In some embodiments, each data line 81 is electrically connected to sub-pixels 1 of the same color, for example, sub-pixels 1 in the same column of the same color, for example, columns of red, green and blue sub-pixels 1 are arranged along the first direction 9991.

[0243] Therefore, during testing, the same signal can be provided to the data line 81 corresponding to the sub-pixel 1 of the same color so that these sub-pixels 1 can be displayed in the same way (e.g., lit or not lit) so as to determine whether there is a faulty sub-pixel 1 by the color of the displayed screen, and to locate the faulty sub-pixel 1.

[0244] Reference Figure 4 , Figure 13 In some embodiments, multiple test units 3 are arranged in a row along the first direction 9991;

[0245] At least one of the multiple test units 3 has n test transistors 31 arranged in a row along a direction that is inclined relative to both the first direction 9991 and the second direction 9992. The gates 311 of the n test transistors 31 are connected in a stepped integral structure. The first electrode 313 and the second electrode 314 of each test transistor 31 are located on both sides of the active layer 312 of the test transistor 31 along the first direction 9991.

[0246] Reference Figure 4, Figure 13 As one embodiment of this disclosure, each test unit 3 can be arranged in a row along the first direction 9991 in the second edge region 92, and the arrangement direction of the n test transistors 31 of the same test unit 3 is inclined relative to both the first direction 9991 and the second direction 9992 (for example, as a reference). Figure 13 (From the upper left to the lower right direction); Thus, the gates 311 of the n test transistors 31 in the same test unit 3 are connected as one unit and present a "stepped shape"; however, the first electrode 313 and the second electrode 314 of each test transistor 31 are located on both sides of its active layer 312 along the first direction 9991.

[0247] As can be seen, the space occupied by each test unit 3 in the first direction 9991 is reduced by the above method, which is conducive to the uniform distribution of the structure and the full utilization of space.

[0248] The specific layer distribution of each structure in test unit 3 can be varied.

[0249] For example, refer to Figure 3 , Figures 13 to 18 The active layer 312 of each test transistor 31 ( Figure 14 The test transistors are arranged at intervals along directions inclined to both the first direction 9991 and the second direction 9992 (and can be disposed on the same layer as the first active layer 11), and are covered by the gate insulating layer 190; while the gate 311 of each test transistor ( Figure 15 The first electrode 313 of the test transistor 31 can be disposed on the same layer as the first gate 112, and the same layer also has a structure for electrically connecting the first electrode of a portion of the test transistor 31 to the corresponding data line 81 (or regarded as part of the data line 81); while the second electrode 313 can be disposed on the same layer as the second electrode 122 for electrically connecting the first electrode 313 of another portion of the test transistor 31 to the corresponding data line 81 (or regarded as part of the data line 81). Figure 16 ), and a structure for electrically connecting the second terminal of the test transistor 31 to the corresponding test data signal line 8531; on the same layer as the first source 113 and the first drain 114, the first terminal 313 and the second terminal 314 of the test transistor 31 can be provided. Figure 18 ); and through the vias in the second insulating layer 192 ( Figure 17 This allows for the electrical connection of the corresponding structure.

[0250] Of course, it should be understood that the specific forms of the multiplexing unit 2 and the test unit 3, as well as the distribution of each structure in the specific layer, are merely exemplary and not a limitation on the embodiments of this disclosure, and therefore will not be described in detail here.

[0251] In a second aspect, embodiments of this disclosure provide a display device, which includes:

[0252] The display substrate of any of the above.

[0253] As one embodiment of this disclosure, the above-mentioned display substrate can be combined with other devices (such as a cell substrate, power supply, flexible circuit board, driver chip, housing, etc.) to form a display device with display function.

[0254] In some embodiments, the display device is a wearable display device.

[0255] The display device in this disclosure can be a display device that can be worn on the human body in some way, such as a smartwatch or smart bracelet.

[0256] When the substrate is made of a flexible material, the display device can be further made into a deformable flexible display device, such as a flexible wearable display device.

[0257] Of course, the display device in the embodiments of this disclosure may also be a liquid crystal display panel (LCD), an organic light-emitting diode (OLED) display panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with display function.

[0258] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A display substrate, wherein, The display substrate comprises: a substrate comprising a display area and a peripheral area surrounding the display area; the display area comprises: a first boundary extending substantially along a first direction and a second boundary extending substantially along a first direction, a third boundary extending substantially along a second direction and a fourth boundary extending substantially along a second direction, the first boundary and the second boundary are located on opposite sides of the display area respectively, and the third boundary and the fourth boundary are located on opposite sides of the display area respectively; the first direction and the second direction intersect each other; the peripheral area comprises: a first edge area located outside the first boundary, a second edge area located outside the second boundary, a third edge area located outside the third boundary, and a fourth edge area located outside the fourth boundary; a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of data lines are configured to provide data signals to the plurality of sub-pixels; a plurality of multiplexing units located in the peripheral area; at least part of the plurality of multiplexing units are located in the first edge area; a plurality of pads located in the peripheral area, at least part of the plurality of pads are configured to provide data signals to the plurality of data lines; the plurality of pads are located on a side of at least part of the multiplexing units away from the display area; at least one test data signal line located in the peripheral area and being a closed trace around the display area; at least one test control signal line located in the peripheral area and being a closed trace around the display area; a plurality of test units located in the peripheral area, and the plurality of test units are located on a side of the plurality of pads away from the display area, at least one of the plurality of test units is electrically connected to at least one of the test data signal line, at least one of the test control signal line, and at least one of the data line, and is configured to transmit a signal provided by at least one of the test data signal line to at least one of the data line according to a signal provided by at least one of the test control signal line; a plurality of joints located in the peripheral area; the plurality of joints are located on a side of the plurality of multiplexing units away from the display area; at least part of the plurality of joints are located on a side of the plurality of pads along the first direction; each of the test data signal line is electrically connected to at least one of the plurality of joints; each of the test control signal line is electrically connected to at least one of the plurality of joints.

2. The display substrate according to claim 1, wherein the display area further comprises: a first arc corner connecting the first boundary and the third boundary, a second arc corner connecting the first boundary and the fourth boundary, a third arc corner connecting the second boundary and the third boundary, and a fourth arc corner connecting the second boundary and the fourth boundary; the peripheral area further comprises: a first corner area connecting the first edge area and the third edge area, a second corner area connecting the first edge area and the fourth edge area, a third corner area connecting the second edge area and the third edge area, and a fourth corner area connecting the second edge area and the fourth edge area.

3. The display substrate according to claim 2, wherein The first boundary and the second boundary are parallel to the first direction; The third boundary and the fourth boundary are parallel to the second direction.

4. The display substrate of claim 3, wherein, The first direction is perpendicular to the second direction; The first arc angle, the second arc angle, the third arc angle and the fourth arc angle are convex arc angles.

5. The display substrate of any one of claims 2 to 4, wherein, At least part of the plurality of test units are located in the second edge area.

6. The display substrate of any one of claims 2 to 4, wherein, All of the test units are located in the second edge area.

7. The display substrate of claim 2, further comprising a plurality of multiplexed data signal lines and a plurality of multiplexed control signal lines located in the peripheral area; At least one of the plurality of multiplexing units is electrically connected to one of the plurality of multiplexed data signal lines, at least two of the plurality of multiplexed control signal lines and at least two of the plurality of data lines, and is configured to provide signals provided by one of the multiplexed data signal lines to at least two of the data lines in time according to signals provided by the at least two multiplexed control signal lines.

8. The display substrate of claim 7, wherein, At least two of the plurality of multiplexing units are electrically connected to the same one of the multiplexed data signal lines through different sub-lines.

9. The display substrate of claim 7 or 8, wherein, The plurality of multiplexed control signal lines are located between the at least one test data signal line and the display area; The plurality of multiplexed control signal lines are located between the at least one test control signal line and the display area.

10. The display substrate of claim 7 or 8, wherein, All of the multiplexing units are located in the first edge area.

11. The display substrate of claim 7 or 8, wherein, Each of the multiplexed data signal lines is electrically connected to at least one of the plurality of pads; Each of the multiplexed control signal lines is electrically connected to at least one of the plurality of pads.

12. The display substrate of claim 7 or 8, wherein, Along the first direction, the plurality of joints are respectively located on both sides of the plurality of pads.

13. The display substrate of claim 12, further comprising a plurality of first signal introduction lines located in the peripheral area; The plurality of first signal introduction lines are electrically connected to at least part of the plurality of pads, at least one of the plurality of multiplexed control signal lines, the at least one test data signal line and the at least one test control signal line.

14. The display substrate of claim 13, further comprising a plurality of second signal introduction lines; The plurality of second signal introduction lines are electrically connected to at least one of the plurality of joints and at least one of the plurality of first signal introduction lines.

15. The display substrate of claim 7 or 8, wherein, At least one of the plurality of multiplexing units comprises m multiplexing transistors; The gate of each of the m multiplexing transistors of at least one of the plurality of multiplexing units is electrically connected to one of the plurality of multiplexing control signal lines, the first electrode of each of the m multiplexing transistors is electrically connected to one of the plurality of data lines, and the second electrode of the m multiplexing transistors is electrically connected to one of the plurality of multiplexing data signal lines.

16. The display substrate of claim 15, wherein, The plurality of multiplexing units are arranged in a row along the first direction. The m multiplexing transistors of at least one of the plurality of multiplexing units are arranged in a row along the first direction, and the first electrode and the second electrode of each of the m multiplexing transistors are respectively located on both sides of the active layer of the multiplexing transistor along the first direction.

17. The display substrate of claim 1, wherein, The total number of the at least one test data signal line is n, the total number of the at least one test control signal line is one, and n is an integer greater than or equal to 2; At least one of the plurality of test units includes n test transistors; The gate of the n test transistors of the same test unit is electrically connected to one of the test control signal lines, the first electrode of each of the n test transistors is electrically connected to one of the plurality of data lines, and the second electrode of each of the n test transistors is electrically connected to one of the n test data signal lines.

18. The display substrate of claim 17, wherein, The plurality of test units are arranged in a row along the first direction. The n test transistors of at least one of the plurality of test units are arranged in a row along a direction inclined with respect to both the first direction and the second direction, the gate of the n test transistors is a one-piece stepped structure, and the first electrode and the second electrode of each of the n test transistors are respectively located on both sides of the source layer of the test transistor along the first direction.

19. A display device, comprising: The display substrate of any one of claims 1 to 18.

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