Semiconductor structure and method for forming the same

Abstract

The present application discloses a semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, wherein a conductive area is formed on the surface of the substrate; forming a first dielectric layer on the conductive area, wherein the first dielectric layer at least exposes a portion of the surface of the conductive area; forming a first conductive layer on the surface of the first dielectric layer, wherein the first conductive layer conformally covers the first dielectric layer and also covers the exposed surface of the conductive area; forming a second dielectric layer on the substrate, wherein the second dielectric layer covers the substrate and the other surfaces of the first conductive layer except the top surface, and the surface of the second dielectric layer is flush with the top surface of the first conductive layer; forming a second conductive layer on the second dielectric layer, wherein the second conductive layer at least covers a portion of the top surface of the first conductive layer. This can reduce the difficulty of subsequent processes; the entire top surface of the second conductive layer is used as the subsequent interconnection area, thereby increasing the interconnection area and improving the interconnection capability of the corresponding semiconductor structure.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] MEMS (Micro Electromechanical System) has developed rapidly in recent years. It is a technology for designing, processing, manufacturing, measuring and controlling micron and / or nano materials, including mechanical components, optical systems, drive components and electronic control systems. It is widely used in intelligent systems, consumer electronics, wearable devices, smart homes, synthetic biology and microfluidics in systems biotechnology. MEMS devices are mainly divided into four categories: sensor MEMS devices, biological MEMS devices, optical MEMS devices and radio frequency MEMS devices. MEMS technology is developing into a huge industry. The leading products in the current MEMS market are microactuators, pressure sensors, accelerometers, micro-gyroscopes, ink nozzles and hard disk drive heads.

[0003] MEMS devices often include multiple semiconductor structures, which need to be interconnected to help realize various functions of the corresponding MEMS devices. Traditional interconnection solutions easily increase the process difficulty of MEMS devices. Summary of the invention

[0004] In view of this, the present application provides a semiconductor structure and a method for forming the same to solve the problem that traditional interconnection solutions easily increase the difficulty of MEMS device processing.

[0005] The present application provides a method for forming a semiconductor structure, comprising:

[0006] Providing a substrate, wherein a conductive area is formed on a surface of the substrate;

[0007] forming a first dielectric layer on the conductive area, wherein the first dielectric layer at least exposes a portion of the surface of the conductive area;

[0008] forming a first conductive layer on the surface of the first dielectric layer, wherein the first conductive layer conformally covers the first dielectric layer and also covers the surface of the exposed conductive area;

[0009] forming a second dielectric layer on the substrate, wherein the second dielectric layer covers the substrate and other surfaces of the first conductive layer except the top surface, and the surface of the second dielectric layer is flush with the top surface of the first conductive layer;

[0010] A second conductive layer is formed on the second dielectric layer, wherein the second conductive layer at least covers a portion of a top surface of the first conductive layer.

[0011] Optionally, the method of forming the first conductive layer on the surface of the first dielectric layer includes:

[0012] A first conductive material layer is deposited to cover the entire conductive area and the first dielectric layer, and the first conductive material layer is patterned to form the first conductive layer.

[0013] Optionally, the method of forming a second dielectric layer on the substrate includes:

[0014] A second dielectric material layer is deposited to cover the substrate and the first conductive layer, and the top surface of the first conductive layer is used as a stop layer to planarize the second dielectric material layer to obtain a second dielectric layer flush with the first conductive layer.

[0015] Optionally, the method of forming the second conductive layer on the second dielectric layer includes:

[0016] A second conductive material layer is deposited to cover the top surface of the first conductive layer, and the second conductive material layer is patterned to form a second conductive layer with each end extending to each side of the first conductive layer.

[0017] Optionally, the method of forming a first dielectric layer on the conductive area includes:

[0018] A dielectric block is formed on the conductive area, and the dielectric block is etched to obtain the first dielectric layer with rounded corners and at least a portion of the surface of the conductive area is exposed.

[0019] Optionally, the forming method further comprises:

[0020] A third dielectric layer is formed on the second dielectric layer, wherein the third dielectric layer covers the second dielectric layer, and a surface of the third dielectric layer is flush with a surface of the second conductive layer.

[0021] Optionally, the method of forming a third dielectric layer on the second dielectric layer includes:

[0022] A third dielectric material layer is deposited to cover the second dielectric layer, and the third dielectric material layer is planarized using the second conductive layer as a stop layer to obtain a third dielectric layer flush with the second conductive layer.

[0023] Optionally, after forming the second dielectric layer on the substrate, the forming method further comprises: forming a third dielectric layer on the second dielectric layer, wherein the third dielectric layer covers the second dielectric layer; etching the third dielectric layer to form an opening, wherein the bottom of the opening at least exposes a portion of the surface of the first conductive layer;

[0024] The method for forming the second conductive layer on the second dielectric layer includes: forming the second conductive layer in the opening, wherein a surface of the second conductive layer is flush with a surface of the third dielectric layer.

[0025] The present application also provides a semiconductor structure, comprising:

[0026] A substrate, wherein a conductive area is provided on a surface of the substrate;

[0027] A first dielectric layer located above the conductive area, wherein the first dielectric layer at least exposes a portion of the surface of the conductive area;

[0028] a first conductive layer conformally covering the first dielectric layer, the first conductive layer also covering the surface of the exposed conductive area;

[0029] a second dielectric layer located above the substrate, the second dielectric layer covering the substrate and other surfaces of the first conductive layer except the top surface, and the surface of the second dielectric layer is flush with the top surface of the first conductive layer;

[0030] A second conductive layer is located above the second dielectric layer, and the second conductive layer at least covers a portion of a top surface of the first conductive layer.

[0031] Optionally, the semiconductor structure further includes:

[0032] A third dielectric layer is located above the second dielectric layer, the third dielectric layer covers the second dielectric layer, and a surface of the third dielectric layer is flush with a surface of the second conductive layer.

[0033] The semiconductor structure and its formation method form a first dielectric layer on the conductive area of ​​the substrate, form a first conductive layer on the surface of the first dielectric layer, raise the interconnection position of the first conductive layer, and then form a second dielectric layer. Planarize the surfaces of the second dielectric layer and the first conductive layer to ensure that the metal layer and the dielectric layer are flat before the subsequent structure is formed, and then form a second conductive layer on the second dielectric layer to raise the interconnection surface and reduce the difficulty of subsequent related processes, and form a third dielectric layer on both sides of the second conductive layer to make the second conductive layer and the third dielectric layer flush, further reducing the difficulty of subsequent processes; wherein the entire top surface of the second conductive layer is used as the subsequent interconnection area, so that the interconnection area is increased, and the interconnection capacity of the corresponding semiconductor structure is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 Schematic diagram of the interconnection structure of the traditional solution;

[0036] Figure 2 This is a flow chart of a method for forming a semiconductor structure in one embodiment of the present application;

[0037] Figure 3a , Figure 3b , Figure 3c , Figure 3d and Figure 3e They are schematic diagrams of structures obtained in each step in an embodiment of the present application;

[0038] Figure 4 Schematic diagram of the interconnection structure of the traditional solution;

[0039] Figure 5 A schematic diagram of a semiconductor structure according to an embodiment of the present application;

[0040] Figure 6a and Figure 6b They are schematic diagrams of structures obtained by some steps in an embodiment of the present application;

[0041] Figure 7 A schematic diagram of a semiconductor structure according to an embodiment of the present application;

[0042] Figure 8a , Figure 8b and Figure 8c They are schematic diagrams of connections between a semiconductor structure and other objects in one embodiment of the present application;

[0043] Fig. 9 A schematic structural diagram of a microactuator according to an embodiment of the present application;

[0044] Fig.10 yes Fig. 9 Schematic diagram of the structure of the mid-displacement module. DETAILED DESCRIPTION

[0045] In sensing MEMS devices or optical MEMS devices, such as microactuators, the interconnection between semiconductor structures usually adopts metal interconnection and other interconnection processes. Metal interconnection is an important process in integrated circuit technology, and its process characteristics have a significant impact on the subsequent process of the integrated circuit, the performance of the resulting circuit, etc. In the traditional interconnection process, in order to ensure the interconnection between two conductive layers, it is usually necessary to set up larger through holes. For example, for a semiconductor structure such as a metal interconnection structure, it is necessary to interconnect the second layer of metal with the first layer of metal by setting up larger through holes. After the second conductive layer is filled with the above-mentioned larger through holes, the following will appear. Figure 1If the pit shown is used directly for subsequent interconnection, the pit has too many turns, which affects the difficulty of the subsequent interconnection process. If the pit is filled, the pit requires additional processing such as alignment of specific materials for filling and the like in subsequent interconnection processes, which easily increases the complexity and difficulty of the subsequent process; at the same time, because the inside of the pit is filled, only part of the second metal layer on the surface of the dielectric layer can be used as interconnection, so the effective area for interconnection is small, which affects the accuracy of other subsequent interconnections and increases the difficulty of the process.

[0046] In view of the above problems, the present application provides a semiconductor structure and a method for forming the same, wherein a first dielectric layer is formed on a conductive area of ​​a substrate, a first conductive layer is formed on a surface of the first dielectric layer, an interconnection position of the first conductive layer is raised, and a second dielectric layer is formed, and the surfaces of the second dielectric layer and the first conductive layer are planarized to ensure that the metal layer and the dielectric layer are flat before subsequent structure formation, and then a second conductive layer is formed on the second dielectric layer to raise the interconnection surface and reduce the difficulty of various subsequent interconnection processes, and a third dielectric layer is formed on both sides of the second conductive layer to make the second conductive layer and the third dielectric layer flush, thereby further reducing the complexity and difficulty of various subsequent processes.

[0047] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0048] In a first aspect, the present application provides a method for forming a semiconductor structure, referring to Figure 2 As shown, the forming method includes:

[0049] S110, such as Figure 3a As shown, a substrate 310 is provided, and a conductive area 312 is formed on the surface of the substrate 310 .

[0050] refer to Figure 3a As shown, the substrate may include a substrate layer 311 and a conductive area 312 disposed on the top surface of the substrate layer, and the conductive area 312 may include at least one electrical connection terminal. In some semiconductor structures, the substrate layer 311 may include at least one electronic component such as a transistor, and each electronic component may be connected to form a corresponding working circuit, and the external pins of the working circuit may be connected to the electrical connection terminals of the conductive area 312, so that the working circuit may be connected to an external connection object such as an external circuit and / or an external power source through the conductive area 312. The conductive area 312 may be covered with a conductive layer such as a metal film to ensure good electrical contact with the outside.

[0051] S120, such as Figure 3b As shown, a first dielectric layer 321 is formed on the conductive area 312 , and the first dielectric layer 321 at least exposes a portion of the surface of the conductive area 312 .

[0052] The above steps form a first dielectric layer 321 above the conductive area 312, which can raise the corresponding interconnection part. The first dielectric layer 321 exposes at least a portion of the surface of the conductive area 312, so that the first conductive layer 330 formed subsequently maintains electrical contact with the exposed portion of the surface of the conductive area 312. The size of the portion of the surface can be set according to factors such as the contact requirements between the first conductive layer and the conductive area 312 and / or the relevant size of the first conductive layer.

[0053] The thickness of the first dielectric layer 321 can be set according to factors such as the size of the corresponding semiconductor structure, the size requirements of the subsequent first conductive layer and / or related process requirements. It is usually within a reasonable thickness range, such as a thickness range of 1 / 4 to 2 / 3 of the entire semiconductor structure, which can prevent the thickness of the first dielectric layer 321 from being too large, resulting in a large thickness of the semiconductor structure, which is not conducive to the subsequent integration of the semiconductor structure, and will not make the thickness of the first dielectric layer 321 too small, making it difficult to control the thickness of the subsequent second dielectric layer, and increasing the difficulty of subsequent surface planarization processes such as chemical mechanical polishing; it can also be 0.1 micron to 5 microns, so as to fully raise the interconnection surface (such as the subsequent second conductive layer) on the basis of ensuring the insulation effect, and further improve the interconnection capability; in some semiconductor structures, the thickness of the first dielectric layer 321 can also be set to other thickness ranges.

[0054] Specifically, in this step, a dielectric material can be formed on the conductive area 312 by various deposition processes, and then the dielectric material is rounded, etched and / or patterned according to the shape and / or size requirements of the first dielectric layer 321 to form the first dielectric layer 321, so that the first dielectric layer 321 exposes the corresponding surface of the conductive area 312, and has a shape or other features that reduce the difficulty of subsequent processes. The above-mentioned conductive area 312 can be rectangular or circular, etc., which is suitable for setting the first dielectric layer 321 and the subsequent first conductive layer. The length of each side of the conductive area 312 can be set according to the shape characteristics and the interconnection capability to be provided. It is usually necessary to make the area of ​​the conductive area 312 greater than a certain area threshold to ensure sufficient conductive contact area. The bottom surface shape and side wall shape of the first dielectric layer 321 can be determined according to relevant structural features and process requirements. In one example, the bottom surface shape of the first dielectric layer 321 can be the same or similar to the shape of the conductive area 312, so as to control the process parameters such as the distance parameter between the bottom surface boundary of the first dielectric layer 321 and the boundary of the conductive area 312, and reduce the corresponding process difficulty.

[0055] Specifically, the process of processing the above-mentioned dielectric material may include: rounding the above-mentioned dielectric material to reduce the difficulty of subsequently forming the first conductive layer due to the corner features of the first dielectric layer 321; graphic processing the above-mentioned dielectric material into a side wall with an inclined side wall and a right trapezoidal cross-section to reduce the difficulty of subsequently depositing the first conductive layer on the surface of the first dielectric layer 321; and / or etching the first dielectric layer 321 to expose the surface of the conductive area on both sides of the first dielectric layer 321, thereby reserving a sufficiently large conductive area contact area for the first conductive layer and improving the interconnection reliability.

[0056] In one example, the method for forming the first dielectric layer 321 on the conductive area 312 specifically includes: forming a dielectric block on the conductive area 312, etching the dielectric block, and obtaining the first dielectric layer 321 with rounded corners at the connection between the top and the sidewall and exposing at least part of the surface of the conductive area, so as to reduce the difficulty of the corner features of the first dielectric layer 321 for the subsequent formation of the first conductive layer, and reserve the required conductive area contact area for the first conductive layer to ensure the interconnection reliability.

[0057] In one example, the method for forming the first dielectric layer 321 on the conductive area 312 may also include: forming a dielectric block on the conductive area 312, etching the dielectric block according to the position characteristics of the conductive area 312, and obtaining the first dielectric layer 321 with the surface of the conductive area 312 exposed on both sides, so that the surface of the conductive area 312 is connected to the first conductive layer 330 on both sides of the first dielectric layer 321, thereby improving the connection stability. Figure 3b As shown, the surface areas of the conductive regions 312 respectively exposed on both sides of the first dielectric layer 321 are equal, so as to improve the regularity of the corresponding interconnection structure and further enhance the interconnection capability.

[0058] S130, such as Figure 3c As shown, a first conductive layer 330 is formed on the surface of the first dielectric layer 321 , and the first conductive layer 330 conformally covers the first dielectric layer 321 and also covers the surface of the exposed conductive region 312 .

[0059] The first conductive layer 330 may include a conductive structure with good conductive properties such as a metal layer. The process for forming the first conductive layer 330 may include a deposition process such as a coating process. In an example, the first conductive layer 330 may be formed by a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, so as to achieve precise control of the formation process of the first conductive layer 330, thereby ensuring that the formed first conductive layer 330 covers the top surface of the first dielectric layer 321, each sidewall, and the exposed surface of the conductive region 312.

[0060] In one example, the method for forming the first conductive layer 330 on the surface of the first dielectric layer 321 specifically includes: depositing a first conductive material layer covering the entire conductive area 312 and the first dielectric layer 321, and patterning the first conductive material layer using an etching process to remove a portion exceeding the conductive area 312 and / or a portion of the conductive material that is too thick on the side wall of the first conductive layer 330 to form the first conductive layer 330, so that the surface of the obtained first conductive layer 330 is flat and the thickness is convenient for subsequent processes, and the corresponding interconnection performance is guaranteed. The various parameters used in the above-mentioned etching process can be determined based on factors such as the conductive properties of the first conductive material layer, the size of the first dielectric layer 321 and / or the size of the conductive area 312. For example, the shape of the top surface of the first conductive layer 330 can match the shape of the top surface of the first dielectric layer 321 to reduce the difficulty of the deposition process. The size is larger than the top surface of the first dielectric layer 321 and smaller than the corresponding size of the conductive area 312, so as to reduce the size as much as possible on the basis of ensuring the interconnection performance, thereby reducing the size of the corresponding semiconductor structure and facilitating the subsequent integration of the semiconductor structure. The sidewall thickness can be set according to the surface size of the exposed conductive area, and can be smaller than the surface size of the conductive area to reduce the occupied space. The bottom end of the first conductive layer 330 can also include an extension end that exceeds the sidewall, and the extension end covers the entire conductive area 312 to effectively utilize the conductive contact area of ​​the conductive area 312, so that the first conductive layer 330 is in full contact with the conductive area 312, and the interconnection reliability is improved.

[0061] S140, such as Figure 3d As shown, a second dielectric layer 322 is formed on the substrate 310 , and the second dielectric layer 322 covers the substrate 310 and other surfaces of the first conductive layer 330 except the top surface, and the surface of the second dielectric layer 322 is flush with the top surface of the first conductive layer 330 .

[0062] The second dielectric layer 322 includes a first dielectric body 322a on one side of the first conductive layer 330 and a second dielectric body 322b on the other side of the first conductive layer 330, wherein the first dielectric body 322a covers a surface located on one side of the first conductive layer 330, and the second dielectric body 322b covers a surface located on the other side of the first conductive layer 330. Specifically, the above steps may form the second dielectric layer 322 by a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, so as to achieve precise control of the formation process of the second dielectric layer 322, thereby ensuring the accuracy of the formed second dielectric layer 322.

[0063] In one example, the method of forming the second dielectric layer 322 on the substrate 310 specifically includes: depositing a second dielectric material layer covering the substrate 310 and the first conductive layer 330, using the top surface of the first conductive layer as a stop layer, and performing a planarization process such as chemical mechanical polishing on the second dielectric material layer to make the surfaces of the second dielectric layer 322 and the first conductive layer 330 flat, thereby obtaining a second dielectric layer 322 flush with the first conductive layer 330.

[0064] S150, such as Figure 3e As shown, a second conductive layer 340 is formed on the second dielectric layer 322 , and the second conductive layer 340 at least covers a portion of the top surface of the first conductive layer 330 .

[0065] The second conductive layer 340 may include a conductive structure with good conductive properties such as a metal layer, so as to be interconnected with other semiconductor structures such as interconnection structures through the conductive structure.

[0066] The above steps can form a semiconductor structure of non-hole through-hole interconnection, which pre-raises the interconnection part of the non-contact hole design process, and can achieve reliable interconnection with other semiconductor structures through the second conductive layer 340, and can eliminate the metal pits that are formed by the opening of the interconnection part, that is, there are no pits and other features that increase the difficulty of subsequent processes, which can reduce the difficulty of various subsequent processes required for the semiconductor structure and improve the practicality of the semiconductor structure. Specifically, the above steps can form the second conductive layer 340 by a deposition process such as a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, so as to achieve precise control of the formation process of the second conductive layer 340, thereby ensuring the accuracy of the formed second conductive layer 340. In some examples, the second conductive layer 340 can cover the entire top surface of the first conductive layer 330 to ensure full contact between the two and improve the interconnection performance.

[0067] refer to Figure 4 As shown, for Figure 1 In some examples of the interconnection structure shown, insulating materials are filled in the pits, so that subsequent interconnection can only be performed on the exposed wing metal part (the interconnection part shown in the figure), and the effective area of ​​the interconnection is small. To address this problem, in one embodiment of the present application, the method of forming the second conductive layer 340 on the second dielectric layer 322 further includes: depositing a second conductive material layer covering the top surface of the first conductive layer 330, and patterning the second conductive material layer to form a second conductive layer 340 with each end extending to each side of the first conductive layer 330.

[0068] In this embodiment, each end of the second conductive layer 340 extends along the top surface of the second dielectric layer 322 toward each side of the first conductive layer 330, that is, the second conductive layer 340 covers the top surface of the first conductive layer 330, and each end exceeds the top surface, so that the entire top surface of the second conductive layer 340 can be used as a subsequent interconnection area, the interconnection area is increased, and the interconnection reliability is improved. Specifically, the two ends of the second conductive layer 340 can extend along the top surface of the second dielectric layer 322 toward both sides of the first conductive layer 330 to the boundary line aligned with the conductive area 312, so that the interconnection area provided by the second conductive layer 340 is the same as the area of ​​the conductive area 312, which can further ensure the interconnection reliability of the corresponding semiconductor structure.

[0069] In one embodiment, the forming method may further include: referring to Figure 5 As shown, a third dielectric layer 323 is formed on the second dielectric layer 322 . The third dielectric layer 323 covers the second dielectric layer 322 , and a surface of the third dielectric layer 323 is flush with a surface of the second conductive layer 340 .

[0070] The third dielectric layer 323 includes a third dielectric body 323a on one side of the second conductive layer 340 and a fourth dielectric body 323b on the other side of the second conductive layer 340. The third dielectric body 323a covers the surface of the second dielectric layer 322 on one side of the second conductive layer 340, and the fourth dielectric body 323b covers the surface of the second dielectric layer 322 on the other side of the second conductive layer 340. Specifically, in this embodiment, the third dielectric layer 323 may be formed by a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, so as to achieve precise control of the formation process of the third dielectric layer 323, thereby ensuring the accuracy of the formed third dielectric layer 323.

[0071] In one example, the method for forming the third dielectric layer 323 on the second dielectric layer 322 specifically includes: depositing a third dielectric material layer covering the second dielectric layer 322, using the second conductive layer 340 as a stop layer, and performing a planarization process such as chemical mechanical polishing on the third dielectric material layer to make the surfaces of the third dielectric layer 323 and the second conductive layer 340 flat, thereby obtaining a third dielectric layer flush with the second conductive layer 340.

[0072] In another embodiment, after forming the second dielectric layer 322 on the substrate 310, the forming method further includes: Figure 6aAs shown, a third dielectric layer 323 is formed on the second dielectric layer 322, and the third dielectric layer 323 covers the second dielectric layer 322; the third dielectric layer 323 is etched to form an opening, and a third dielectric body 323a and a fourth dielectric body 323b on both sides of the opening, and the bottom of the opening at least exposes a portion of the surface of the first conductive layer 330, so that the second conductive layer 340 formed subsequently can contact the portion of the surface, so that the two maintain good electrical contact. Here, the size of the exposed area formed by etching the third dielectric layer 323 can be set according to the interconnection requirements provided by the second conductive layer 340. The larger the size of the exposed area, the larger the surface area of ​​the second conductive layer 340 in the corresponding semiconductor structure, that is, the larger the interconnection area, and the higher the corresponding interconnection reliability.

[0073] The method of forming the second conductive layer 340 on the second dielectric layer 322 specifically includes: forming the second conductive layer 340 in the opening, wherein the surface of the second conductive layer 340 is flush with the surface of the third dielectric layer to reduce the difficulty of various processes required for subsequent corresponding semiconductor structures.

[0074] In the above method for forming a semiconductor structure, a first dielectric layer 321 is formed above the conductive area 312 of the substrate 310 to raise the interconnection position of the conductive area 312. The first dielectric layer 321 at least exposes part of the surface of the conductive area 312, so that a first conductive layer 330 is formed on the surface of the first dielectric layer 321. The first conductive layer 330 conformally covers the first dielectric layer 321 and also covers the exposed surface of the conductive area; a second dielectric layer 322 is formed on the substrate 310 to be flush with the first conductive layer 330, and then a second conductive layer 340 is formed on the second dielectric layer 322 to cover at least part of the top surface of the first conductive layer 330, thereby ensuring good interconnection performance and reducing the difficulty of subsequent processes of the corresponding semiconductor structure. In addition, a third dielectric layer 323 is formed on both sides of the second conductive layer 340 to make the second conductive layer 340 and the third dielectric layer 323 flush, further increasing the difficulty of related processes; wherein the entire top surface of the second conductive layer 340 is used as the subsequent interconnection area, so that the interconnection area is increased and the interconnection capacity is improved.

[0075] A second aspect of the present application provides a semiconductor structure, which can be formed by using the method for forming a semiconductor structure provided by any of the above embodiments, referring to Figure 7 As shown, the semiconductor structure includes:

[0076] A substrate 310, wherein a conductive area 312 is provided on a surface of the substrate 310;

[0077] A first dielectric layer 321 located above the conductive area 312 , wherein the first dielectric layer 321 at least exposes a portion of the surface of the conductive area 312 ;

[0078] A first conductive layer 330 conformally covering the first dielectric layer 321, wherein the first conductive layer 330 also covers the surface of the exposed conductive area 312;

[0079] A second dielectric layer 322 located above the substrate 310, the second dielectric layer 322 covers the substrate 310 and other surfaces of the first conductive layer 330 except the top surface, and the surface of the second dielectric layer 322 is flush with the top surface of the first conductive layer 330;

[0080] The second conductive layer 340 is located above the second dielectric layer 321 , and the second conductive layer 340 at least covers a portion of the top surface of the first conductive layer 330 .

[0081] Among them, the conductive area 312 of the substrate 310 is provided with at least one electrical connection end, and at least one electronic component such as a transistor may be included inside. Each electronic component is connected to form a corresponding working circuit, and the external pins of the working circuit are correspondingly connected to the electrical connection end of the conductive area 312, so that the working circuit can be connected to an external connection object such as an external circuit and / or an external power supply through the conductive area 312. The above-mentioned conductive area 312 may be covered with a conductive layer such as a metal film to ensure good electrical contact with the outside. The conductive area 312 may be rectangular or circular, etc., which is suitable for setting the first dielectric layer 321 and the subsequent first conductive layer. The length of each side of the conductive area 312 can be set according to the shape characteristics and the interconnection capability to be provided. It is usually necessary to make the area of ​​the conductive area 312 greater than a certain area threshold to ensure sufficient conductive contact area. The bottom surface shape and side wall shape of the first dielectric layer 321 can be determined according to relevant structural characteristics and process requirements. In one example, the bottom shape of the first dielectric layer 321 may be the same as or similar to the shape of the conductive region 312 to facilitate control of process parameters such as the distance parameter between the bottom boundary of the first dielectric layer 321 and the boundary of the conductive region 312 and reduce the corresponding process difficulty.

[0082] The shape, size and / or specific position of the first dielectric layer 321 in the conductive area 312 can be set according to the contact requirements between the first conductive layer 330 and the conductive area 312 and / or the relevant size of the first conductive layer. Specifically, the first dielectric layer 321 can include a rectangular shape that is easy to etch, which reduces the difficulty of forming the first dielectric layer 321; it can also include a trapezoidal shape that helps to form the required deposition layer on the surface later. Each corner can be a right angle, or a rounded corner or other shape that is convenient for forming the deposition layer later. Its size, such as the bottom size of the contact conductive area 312, can be set according to the subsequent contact requirements between the first conductive layer 330 and the conductive area 312, and its bottom surface usually does not exceed a certain proportion of the area of ​​the conductive area 312, so as to reserve sufficient conductive area contact area for the first conductive layer 330; the thickness can be set according to the size of the corresponding semiconductor structure, the size requirements of the subsequent first conductive layer and / or the relevant process requirements, and it is usually in a reasonable thickness range, such as the thickness range of 1 / 4 to 2 / 3 of the entire semiconductor structure or other thickness ranges, so as to prevent the thickness of the first dielectric layer 321 from being too large, resulting in the thickness of the semiconductor structure reaching , which is not conducive to the subsequent integration of the semiconductor structure, and the thickness of the first dielectric layer 321 is not too small, making it difficult to control the thickness of the subsequent second dielectric layer, and increasing the difficulty of the subsequent surface planarization process such as chemical mechanical polishing. It can be set in the central area of ​​the conductive area 312, and the surface size of the conductive area 312 exposed on each side is equal, so that the size of the first conductive layer 330 formed on the surface of the subsequent first dielectric layer 321 matches each other, further reducing the difficulty of the corresponding formation process.

[0083] In one embodiment, the sidewall of the first dielectric layer 321 is inclined and the cross section is a positive trapezoid, so as to reduce the difficulty of the subsequent process of depositing the first conductive layer 330 on the surface of the first dielectric layer 321, and also ensure that the bottom surface is in full contact with the conductive area 312;

[0084] The ratio of the bottom surface of the first dielectric layer to the area of ​​the conductive area is less than or equal to 2 / 3, so as to reserve a sufficiently large contact area of ​​the conductive area for the first conductive layer 330 to improve the interconnection reliability between the two;

[0085] And / or, both sides of the first dielectric layer 330 expose the surface of the conductive area 312 , so that the bottom surfaces of each side of the first conductive layer 330 are in contact with the conductive area 312 , further improving the contact reliability.

[0086] In one embodiment, the bottom boundary line of the first conductive layer 330 is aligned with the boundary line of the conductive area 312 to effectively utilize the conductive contact area of ​​the conductive area 312 so that the first conductive layer 330 is in full contact with the conductive area 312 .

[0087] Specifically, Figure 7As described above, the bottom end of the first conductive layer 330 can extend along the conductive area 312 toward the outside of the first dielectric layer 330 to ensure that the bottom surface of the first conductive layer 330 is in full contact with the conductive area 312; the bottom end can extend to the boundary line of the conductive area 312 to ensure the effectiveness of contact at all locations on its bottom surface. Further, the characteristics and parameters of each part of the first conductive layer 33 can be set according to factors such as the conductive performance of the first conductive material layer, the size of the first dielectric layer 321 and / or the size of the conductive area 312. For example, the shape of the top surface of the first conductive layer 330 can match the shape of the top surface of the first dielectric layer 321 to reduce the difficulty of the deposition process. The size of the top surface is larger than the corresponding size of the top surface of the first dielectric layer 321 and smaller than the corresponding size of the conductive area 312, so as to reduce the size as much as possible on the basis of ensuring the interconnection performance, thereby reducing the size of the corresponding semiconductor structure and facilitating the subsequent integration of the semiconductor structure. The sidewall thickness can be set according to the exposed surface size of the conductive area and can be smaller than the surface size of the conductive area to reduce the occupied space. The bottom end of the first conductive layer 330 can also include an extension end that exceeds the sidewall, and the extension end covers the entire conductive area 312 to effectively utilize the conductive contact area of ​​the conductive area 312, so that the first conductive layer 330 is in full contact with the conductive area 312, and the interconnection reliability is improved.

[0088] In one embodiment, the second conductive layer covers the entire top surface of the first conductive layer to ensure sufficient contact between the two and improve interconnection performance.

[0089] Specifically, the two ends of the second conductive layer 340 extend along the surface of the second dielectric layer to the two sides of the top surface of the first conductive layer 330 to increase the interconnection area provided by the second conductive layer 340, and further improve the reliability of the corresponding semiconductor structure. Specifically, the two ends of the second conductive layer 340 can extend to the boundary line of the conductive area 312, so that the interconnection area provided by the second conductive layer 340 is the same as the area of ​​the conductive area 312, and the corresponding interconnection performance is maintained.

[0090] In one embodiment, Figure 5 As shown, the semiconductor structure further includes: a third dielectric layer 323 located above the second dielectric layer, the third dielectric layer 323 covers the second dielectric layer 322, and the surface is flush with the surface of the second conductive layer 340, so that the surface of the corresponding semiconductor structure is flat, which can further reduce the difficulty of subsequent processes.

[0091] Figure 5The semiconductor structure shown can be provided in a semiconductor device to provide a port for the corresponding semiconductor device to be electrically connected to an external circuit and / or device. The port for the semiconductor device to be electrically connected to the external circuit and / or device is the surface of the second conductive layer 340, and the surface of the second conductive layer 340 can provide a large interconnection area and has a high interconnection reliability.

[0092] In one example, reference Figure 8a As shown, the semiconductor structure provided in the semiconductor device can be connected to other circuits 410, so that the semiconductor device is electrically connected to the other circuits 410 through the semiconductor structure, and responds to various requirements of the other circuits 410. Specifically, the other circuits 410 include electrical connection terminals 411, and the electrical connection terminals 411 are electrically connected to the second conductive layer 340, so as to realize the electrical connection between the corresponding semiconductor device and the other circuits 410, so that the two can assist each other in the operation process and realize various functions.

[0093] In one example, a semiconductor device having the above semiconductor structure may also be interconnected with other semiconductor devices having the above semiconductor structure. Figure 8b As shown, the semiconductor structures located in the two semiconductor devices are interconnected, that is, the second conductive layer 340 in the lower semiconductor device contacts the second conductive layer 340 in the upper semiconductor device to realize the interconnection between the upper and lower semiconductor devices, so that the two semiconductor devices can assist each other in the working process and realize the corresponding functions. Optionally, the second conductive layers 340 in the upper and lower semiconductor devices can be interconnected by a relatively simple process such as bonding to simplify the process flow corresponding to the interconnection. In addition, the two bonded second conductive layers 340 have a large interconnection area, which can improve the reliability of the bonded electrical connection.

[0094] Optionally, when a semiconductor device having the above semiconductor structure is located at the upper part, the upper semiconductor device can also be interconnected with the second conductive layer 340 in the lower semiconductor device through other interconnection parts, so that the second conductive layer 340 in the upper semiconductor structure provides interconnection terminals corresponding to other circuits and / or devices, which can further improve the interconnection performance and the flexibility in the interconnection process. Figure 8c As shown, the upper semiconductor device is interconnected with the second conductive layer 340 in the lower semiconductor device through the bottom of the first conductive layer 330. At this time, the second conductive layer 340 in the lower semiconductor device has a larger interconnection area, which makes it easier to interconnect with the bottom of the first conductive layer 330, and can also improve the corresponding interconnection reliability; the second conductive layer 340 in the upper semiconductor structure can provide a reliable interconnection terminal for other circuits and / or devices, so that on the basis of improving the interconnection reliability, the interconnection flexibility between multiple devices is improved.

[0095] In one embodiment, the first conductive layer 330 and / or the second conductive layer 340 includes a metal layer or other structure with good conductivity to ensure interconnection performance.

[0096] Optionally, the material of the metal layer is copper, aluminum, tungsten or other metal materials.

[0097] In one embodiment, reference Fig. 9 and Fig.10 , Fig. 9 It is a schematic diagram of the structure of a micro actuator. Fig.10 yes Fig. 9 The specific structural diagram of the displacement module in the embodiment. Specifically, the semiconductor structure is a microactuator, and the microactuator has a fixed platform 10; at least one displacement module is located on the fixed platform 10, and the displacement module 70 includes: a transverse driving electrode group, located on the fixed platform 10, and the transverse driving electrode group includes two separate and oppositely arranged transverse driving electrodes 721, and the arrangement direction of the transverse driving electrodes is the same as the moving direction, and along the moving direction, any of the transverse driving electrodes includes a first side surface opposite to the other transverse driving electrode; a "X"-shaped movable electrode 71, suspended on the transverse driving electrode group and the fixed platform 10, and corresponding to the transverse driving electrode group, the movable electrode 71 includes a top electrode arranged opposite to the top surface of the transverse driving electrode group, a side electrode arranged opposite to the first side surface of the transverse driving electrode, and a bottom electrode arranged opposite to the fixed platform 10, and there is a first preset spacing between the side electrode and the corresponding transverse driving electrode, and the first preset spacing is equal to the preset moving step length;

[0098] A fixed electrode 50 is located on the fixed platform 10, and the fixed electrode 50 is located on both sides of the movable electrode 71 along the moving direction; a spring wire 51 is located between the bottom electrode and the fixed electrode 50, one end of the spring wire 51 is connected to the bottom electrode, and the other end is connected to the fixed electrode 50, and the spring wire 51 is used to support the movable electrode 71;

[0099] A first longitudinal driving electrode, located on the fixed platform 10 below the bottom electrode;

[0100] A movable platform 74, used for supporting the moved component, the movable platform 74 is located above the top of the displacement module, and the movable platform 74 is arranged parallel to the fixed platform 10;

[0101] The movable platform 74 can be meshed or electrostatically attracted with the top electrode through the electrode plate 73 located at the bottom of the movable platform 74, thereby driving the movable platform 74 to move, and further driving the moved component to move.

[0102] refer to Fig.10 It can be seen that the fixed electrode 50 and the lateral driving electrode 721 provide electrical signals through the interconnection structure located in the fixed platform 10. Since the mobile module needs to drive the movable part to move, the movable part has a certain weight, and the mobile module needs a large driving force, the magnitude of the driving force is related to the voltage drop, and the mobile modules are all formed of semiconductor silicon, the current borne by the TSV method is small, and the area of ​​the metal used for the upper layer connection is small by using the recessed setting. Therefore, the use of any structure in the above embodiment for the interconnection between the fixed platform 10 and the fixed electrode 50 and the lateral driving electrode 721 can improve the performance and reliability of the device.

[0103] The application of the semiconductor structure provided in the above embodiment is not limited thereto, but can also be applied to the packaging of other large-size or high-voltage devices, such as MEMS actuators, pressure sensors, accelerometers, gyroscopes, radio frequency switches and other devices.

[0104] The semiconductor structure provided by each of the above-mentioned embodiments can be formed by the semiconductor structure forming method provided by any of the above-mentioned embodiments, which has all the beneficial effects of the above-mentioned semiconductor structure forming method. The semiconductor structure can reduce the difficulty of subsequent related processes, has high interconnection reliability, and is suitable for various semiconductor products.

[0105] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on reading and understanding of this specification and the accompanying drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the functions in the exemplary implementation of this specification shown herein.

[0106] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0107] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0108] In this application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the present application provides the above description. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: The forming method comprises: Providing a substrate, wherein a conductive area is formed on a surface of the substrate; forming a first dielectric layer on the conductive area, wherein the first dielectric layer at least exposes a portion of the surface of the conductive area; forming a first conductive layer on the surface of the first dielectric layer, wherein the first conductive layer conformally covers the first dielectric layer and also covers the surface of the exposed conductive area; forming a second dielectric layer on the substrate, wherein the second dielectric layer covers the substrate and other surfaces of the first conductive layer except the top surface, and the surface of the second dielectric layer is flush with the top surface of the first conductive layer; A second conductive layer is formed on the second dielectric layer, wherein the second conductive layer at least covers a portion of a top surface of the first conductive layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming a first conductive layer on the surface of the first dielectric layer comprises: A first conductive material layer is deposited to cover the entire conductive area and the first dielectric layer, and the first conductive material layer is patterned to remove a portion exceeding the conductive area and / or a portion of the conductive material where the sidewall of the first conductive layer is too thick, to form the first conductive layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming a second dielectric layer on the substrate comprises: A second dielectric material layer is deposited to cover the substrate and the first conductive layer, and the top surface of the first conductive layer is used as a stop layer to planarize the second dielectric material layer to obtain a second dielectric layer flush with the first conductive layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming a second conductive layer on the second dielectric layer comprises: A second conductive material layer is deposited to cover the top surface of the first conductive layer, and the second conductive material layer is patterned to form a second conductive layer with each end extending to each side of the first conductive layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming a first dielectric layer on the conductive area includes: A dielectric block is formed on the conductive area, and the dielectric block is etched to obtain the first dielectric layer with rounded corners and at least a portion of the surface of the conductive area is exposed.

6. The method for forming a semiconductor structure according to claim 1, wherein: The forming method further comprises: A third dielectric layer is formed on the second dielectric layer, wherein the third dielectric layer covers the second dielectric layer, and a surface of the third dielectric layer is flush with a surface of the second conductive layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming a third dielectric layer on the second dielectric layer comprises: A third dielectric material layer is deposited to cover the second dielectric layer, and the third dielectric material layer is planarized using the second conductive layer as a stop layer to obtain a third dielectric layer flush with the second conductive layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: After forming the second dielectric layer on the substrate, the forming method further comprises: forming a third dielectric layer on the second dielectric layer, wherein the third dielectric layer covers the second dielectric layer; etching the third dielectric layer to form an opening, wherein the bottom of the opening at least exposes a portion of the surface of the first conductive layer; The method for forming the second conductive layer on the second dielectric layer includes: forming the second conductive layer in the opening, wherein a surface of the second conductive layer is flush with a surface of the third dielectric layer.

9. A semiconductor structure, characterized in that: The semiconductor structure comprises: A substrate, wherein a conductive area is provided on a surface of the substrate; A first dielectric layer located above the conductive area, wherein the first dielectric layer at least exposes a portion of the surface of the conductive area; a first conductive layer conformally covering the first dielectric layer, the first conductive layer also covering the surface of the exposed conductive area; a second dielectric layer located above the substrate, the second dielectric layer covering the substrate and other surfaces of the first conductive layer except the top surface, and the surface of the second dielectric layer is flush with the top surface of the first conductive layer; A second conductive layer is located above the second dielectric layer, and the second conductive layer at least covers a portion of a top surface of the first conductive layer.

10. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure further comprises: A third dielectric layer is located above the second dielectric layer, the third dielectric layer covers the second dielectric layer, and a surface of the third dielectric layer is flush with a surface of the second conductive layer.

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