Radar echo signal detection method, device, system and storage medium

Abstract

The embodiment of the present invention provides a detection method, device, system and storage medium for radar echo signals. The method includes: obtaining multiple discrete data points of the original analog echo signal of a detection signal period to obtain a data set; determining the detection processing clock period corresponding to the detection signal based on the rising edge of the detection signal to obtain a reference clock period; determining the sampling point whose amplitude under the reference clock period does not exceed the first preset threshold value to obtain a reference sampling point; taking the product of the sampling clock period and the number of reference sampling points as the detection delay time; delaying the discrete data points in the data set based on the detection delay time to obtain a processed data set. The present invention can improve the accuracy of echo simulation and meet the requirements of radar target echo simulation, so as to improve the reliability of radar performance testing.

Description

Technical Field

[0001] The present invention relates to the technical field of echo simulation, and in particular to a detection method, device, system and storage medium for radar echo signals. Background Art

[0002] At present, when simulating radar target echo, a high-speed ADC (Analog-to-digital converter) is generally used to collect radar pulse signals, and the collected signals are transmitted to an FPGA (Field-Programmable Gate Array) for detection processing to determine the rising edge time of the detection signal. Based on the rising edge time, the signal is delayed and then modulated to simulate the target echo signal, i.e., the target simulated echo signal. After the target simulated echo signal is received by the radar, the radar performance (such as radar ranging accuracy, etc.) can be tested.

[0003] Usually, the sampling rate of ADC is generally above 1GSPS, while the processing frequency of FPGA is generally within 350MHz. For example, the sampling rate of ADC is 2GSPS, the sampling clock period of ADC is 500ps, the detection processing frequency of FPGA is 250MHz, the detection processing clock period of FPGA is 4ns, and the detection accuracy is one detection processing clock period of FPGA, that is, the detection accuracy is ±2ns. It can be seen that this detection accuracy can no longer meet the requirements of radar target echo simulation. The target simulation echo signal obtained under this detection accuracy is quite different from the target echo signal received when the radar actually detects the target, which will reduce the reliability of radar performance testing. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a radar echo signal detection method, device, system and storage medium, which can improve the accuracy of echo simulation and meet the requirements of radar target echo simulation, so as to improve the reliability of radar performance testing. The specific technical solution is as follows:

[0005] The present invention provides a radar echo signal detection method, comprising:

[0006] Acquire a plurality of discrete data points of the original analog echo signal of a detection signal cycle to obtain a data set, wherein the detection signal includes a pulse level signal generated based on the sampling points of the radar pulse signal;

[0007] Based on the rising edge of the detection signal, determine the detection processing clock period corresponding to the detection signal to obtain a reference clock period, determine the sampling point whose amplitude under the reference clock period does not exceed the first preset threshold value to obtain a reference sampling point;

[0008] The product of the sampling clock period and the number of the reference sampling points is used as the detection delay time, wherein the sampling clock period is the clock period for collecting the radar pulse signal;

[0009] Delay processing is performed on discrete data points in the data set based on the detection delay time to obtain a processed data set, wherein the processed data set is used to generate a processed simulated echo signal.

[0010] Optionally, performing delay processing on discrete data points in the data set based on the detection delay time to obtain a processed data set includes:

[0011] Delaying the delayed clock cycle to which the discrete data points belong by the detection delay time length to obtain discrete data points after the clock cycle is changed, wherein the discrete data points after the clock cycle is changed are arranged in the order of the delayed clock cycle, and the delayed clock cycle is the clock cycle after the sampling clock cycle is delayed by a preset time length, and the preset time length is 2R / v, R is the distance between the radar pulse signal emission point and the target point, and v is the signal propagation speed;

[0012] The first N discrete data points of the discrete data points after the clock cycle is changed are set to zero to obtain a processed data set, wherein the value of N is the same as the number of the reference sampling points.

[0013] Optionally, the step of obtaining a plurality of discrete data points of the original analog echo signal of one detection signal cycle includes:

[0014] Perform detection processing based on the sampling points of the radar pulse signal to obtain a detection signal;

[0015] Performing digital down-conversion processing on the sampling points of the radar pulse signal to obtain processed sampling points;

[0016] Delay processing is performed on the processed sampling points of a detection signal cycle based on the rising edge time of the detection signal and the preset time length to obtain delayed processing data;

[0017] Performing amplitude modulation processing and Doppler modulation processing on the delayed processed data respectively to obtain modulated processed data;

[0018] The modulated processed data is digitally up-converted to obtain a plurality of discrete data points of the original analog echo signal of one detection signal cycle.

[0019] Optionally, the method for generating the detection signal includes:

[0020] Compare the amplitudes of the plurality of sampling points in the same detection processing clock cycle with the second preset threshold value respectively to obtain a plurality of comparison results;

[0021] Based on the comparison result, a detection value corresponding to the sampling point is obtained to obtain multiple detection values; the detection value is 0 or 1; when the detection value is 0, the amplitude of the sampling point is less than the second preset threshold value; when the detection value is 1, the amplitude of the sampling point is not less than the second preset threshold value;

[0022] Performing an OR operation on the plurality of detection values ​​to obtain the amplitude of the detection signal in the detection processing clock period;

[0023] A detection signal is generated based on the amplitude of the detection signal in a plurality of consecutive detection processing clock cycles.

[0024] Optionally, the method for generating the detection signal includes:

[0025] Performing a sum operation on the amplitudes of the plurality of sampling points in the same detection processing clock cycle to obtain a sum operation result;

[0026] When the sum operation result is greater than a third preset threshold value, setting the amplitude of the detection signal in the detection processing clock period to 1;

[0027] When the sum operation result is not greater than the third preset threshold value, setting the amplitude of the detection signal in the detection processing clock period to 0;

[0028] A detection signal is generated based on the amplitude of the detection signal in a plurality of consecutive detection processing clock cycles.

[0029] Optionally, the method for determining the rising edge of the detection signal includes:

[0030] If at least one of the detection values ​​corresponding to the sampling points in the target detection processing clock cycle is 0 and at least one of the detection values ​​is 1, and the detection values ​​corresponding to the sampling points in the next detection processing clock cycle of the target detection processing clock cycle are all 1, then the starting time of the target detection processing clock cycle is determined to be the rising edge of the detection signal.

[0031] The present invention also provides a programmable logic controller, which is configured as the above-mentioned radar echo signal detection method.

[0032] The present invention also provides an echo simulation system, comprising: an analog-to-digital converter, an FPGA and a digital-to-analog converter; the output end of the analog-to-digital converter is connected to the input end of the FPGA, and the output end of the FPGA is connected to the input end of the digital-to-analog converter;

[0033] The analog-to-digital converter transmits a plurality of discrete data points of the original analog echo signal to the FPGA;

[0034] The FPGA is configured as the above-mentioned radar echo signal detection method;

[0035] The FPGA transmits the processed data set to the digital-to-analog converter, so that the digital-to-analog converter generates a processed analog echo signal based on the processed data set.

[0036] The present invention also provides a radar echo signal detection device, comprising:

[0037] The data acquisition module is used to obtain multiple discrete data points of the original analog echo signal of a detection signal cycle to obtain a data set; the detection signal is a pulse level signal generated based on the sampling points of the radar pulse signal;

[0038] A reference clock cycle acquisition module is used to determine the detection processing clock cycle corresponding to the detection signal based on the rising edge of the detection signal to obtain the reference clock cycle; determine the sampling point whose amplitude under the reference clock cycle does not exceed the first preset threshold value to obtain the reference sampling point;

[0039] A detection delay time determination module, used to use the product of a sampling clock period and the number of reference sampling points as the detection delay time; the sampling clock period is a clock period for collecting the radar pulse signal;

[0040] The delay processing module is used to perform delay processing on discrete data points in the data set based on the detection delay time to obtain a processed data set; the processed data set is used to generate a processed simulated echo signal.

[0041] The present invention also provides a computer-readable storage medium, on which a program is stored, and when the program is executed by a processor, the above-mentioned radar echo signal detection method is implemented.

[0042] The embodiment of the present invention provides a radar echo signal detection method, device, system and storage medium, which obtains multiple discrete data points of an original analog echo signal of a detection signal period to obtain a data set; determines the detection processing clock period to which the rising edge of the detection signal belongs to obtain a reference clock period; determines the sampling point whose amplitude under the reference clock period does not exceed the first preset threshold value to obtain a reference sampling point; uses the product of the sampling clock period and the number of reference sampling points as the detection delay time; delays the discrete data points in the data set based on the detection delay time to obtain a processed data set; the processed data set is used to generate a processed analog echo signal, and the accuracy of the processed analog echo signal is higher than that of the original analog echo signal. The present invention can improve the accuracy of echo simulation and meet the requirements of radar target echo simulation, so as to improve the reliability of radar performance testing.

[0043] Of course, it is not necessary to achieve all of the advantages described above at the same time to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A schematic diagram of modulus detection provided by an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of radar target distance and echo delay provided by an embodiment of the present invention;

[0047] Figure 3 A flow chart of a radar echo signal detection method provided by an embodiment of the present invention;

[0048] Figure 4 A schematic diagram of generating an original simulated echo signal provided by an embodiment of the present invention;

[0049] Figure 5 A schematic diagram of detection processing provided by an embodiment of the present invention;

[0050] Figure 6 A structural diagram of an echo simulation system provided by an embodiment of the present invention;

[0051] Figure 7 A structural diagram of a radar echo signal detection device provided by an embodiment of the present invention;

[0052] Figure 8 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] When testing radar performance, it is often necessary to simulate the target detection echo signal generated by the radar. When simulating radar target echo, a high-speed ADC (Analog-to-digital converter) is generally used to collect radar pulse signals. The sampling rate of the ADC is generally above 1GSPS. After the ADC converts the continuous radar pulse signal into multiple discrete radar pulse signals, the collected signal is transmitted to the FPGA (Field-Programmable Gate Array). The processing frequency of the FPGA is generally within 350MHz.

[0055] In the radar target echo simulation process, the radar pulse signal is converted by ADC to obtain multiple discrete radar pulse signals. The collected signal is detected to obtain an envelope signal (also called a detection signal) to determine the rising edge time of the radar pulse signal. Based on the rising edge time, the signal is delayed and modulated to simulate the target simulated echo signal.

[0056] When detecting the collected radar pulse signal, the modulus detection method is used. Figure 1 As shown in the figure, due to the limited detection processing clock of FPGA, after the signal collected by ADC is transmitted to FPGA, it is generally multiple parallel data streams. For example, if the sampling rate of ADC is 1GSPS and the processing clock of FPGA is 250MHz, then FPGA divides ADC data into 4 parallelisms for processing, and these 4 parallelisms are interleaved and parallel. Assume that the data stream transmitted to FPGA after ADC collection is: 0 ,a 1 ,a 2 ……a n , where n is a natural number. The four parallelisms of FPGA are:

[0057] Parallelism 1 (din_0): a 0 , a 4 , a 8 ……a4n

[0058] Parallelism 2 (din_1): a 1 , a 5 , a 9 ……a 4n+1

[0059] Parallelism 3 (din_2): a 2 , a 6 , a 10 ……a 4n+2

[0060] Parallelism 4 (din_3): a 3 , a 7 , a 11 ……a 4n+3

[0061] The steps of modulus detection method are as follows:

[0062] 1) Perform modulo processing on the data of each parallel degree.

[0063] Since the collected signal is obtained based on the discretization of the radar pulse signal, the radar pulse signal is a sine wave signal with positive and negative signal sizes, it is necessary to perform modulus processing on the data to convert negative values ​​into positive values.

[0064] 2) Perform a sum operation on the data with the same parallelism after modulo calculation to obtain the accumulated value.

[0065] The purpose of the sum operation is to make a judgment on multiple data in the same detection processing clock cycle, so that the data in the same detection processing clock cycle are all 0. When no radar pulse signal is detected, the value obtained by summing the data with the same parallelism after modulo calculation is 0. When a radar pulse signal is detected, the value obtained by summing the data with the same parallelism after modulo calculation is not 0.

[0066] 3) Compare the accumulated value with a preset threshold value. If the accumulated value is greater than the preset threshold value, the detection signal is at a high level; if the accumulated value is less than the preset threshold value, the detection signal is at a low level, thereby generating a detection signal.

[0067] The rising edge of the detection signal is taken as the starting time of the radar pulse signal. Figure 1 It can be seen that the collected radar pulse signal a appears at the rising edge of the detection signal 0 and a 1 The value is 0, a 2 and a 4The value is not 0. That is to say, there is a deviation between the start time of the radar pulse signal obtained based on the above modulus detection method and the actual start time of the radar pulse signal. Since the sampling rate of the ADC is 1GSPS, the sampling clock period of the ADC is 1ns, the detection processing frequency of the FPGA is 250MHz, the detection processing clock period of the FPGA is 4ns, and the detection accuracy is one detection processing clock period of the FPGA, that is, the detection accuracy is ±2ns. Therefore, under the condition that the detection processing frequency of the FPGA is 250MHz, it is impossible to accurately reach the 1ns sampling clock period of the ADC.

[0068] When testing the radar ranging accuracy, it is necessary to use the radar pulse signal starting time obtained by the detection method to calculate the radar target distance, such as Figure 2 As shown, it is a schematic diagram of radar target distance and echo delay. The rising edge time of the input signal is the rising edge time of the detection signal obtained by the detection method. Assuming that the distance between the target and the radar is R, the corresponding delay is D=2R / v, v is the propagation speed of the radar pulse signal, and optionally, v can be the speed of light. Based on the above formula, it can be seen that if the accuracy of the starting time of the radar pulse signal is not high, the original echo simulation signal obtained during the echo simulation will deviate from the actual echo simulation signal, resulting in the target distance simulated based on the target original echo simulation signal being inconsistent with the actual target distance, which will reduce the reliability of the radar performance test.

[0069] Based on the problem that the accuracy of obtaining the starting time of the radar pulse signal by the modulus detection method is not high, thereby reducing the reliability of the radar performance test, the present invention provides a detection method for a radar echo signal, such as Figure 3 As shown, the method includes:

[0070] Step 301: Obtain a plurality of discrete data points of an original analog echo signal of a detection signal period to obtain a data set, wherein the detection signal includes a pulse level signal generated based on sampling points of a radar pulse signal.

[0071] In this embodiment, combined with Figure 4 To illustrate the method of obtaining multiple discrete data points of the original analog echo signal of a detection signal cycle, such as Figure 4As shown, the radar pulse signal is subjected to analog-to-digital conversion in the ADC module to obtain the sampling points of the radar pulse signal; the detection module performs detection processing based on the sampling points of the radar pulse signal to obtain the detection signal; the sampling points of the radar pulse signal are subjected to digital down-conversion processing in the DDC (Digital Down Convertion) module to obtain the processed sampling points; the delayed module performs delay processing on the processed sampling points of a detection signal cycle based on the rising edge moment of the detection signal and the preset duration to obtain delayed processing data; the delayed processing data is subjected to amplitude modulation processing and Doppler modulation processing respectively in the modulation module to obtain modulated processing data; the modulated processing data is subjected to digital up-conversion processing in the DUC (Digital Up Convertion) module to obtain multiple discrete data points of the original analog echo signal of one detection signal cycle; the multiple discrete data points are converted into continuous signals in the DAC (Digital to analog converter) module to obtain the original analog echo signal.

[0072] The detection signal period is the period of the detection signal obtained by performing modulo detection processing on the radar pulse signal. The multiple discrete data points of the original analog echo signal are the data of a detection signal period after being processed by the DUC module. Since the data in the data set is generated after modulo detection processing, there is a deviation compared with the actual echo simulation signal. The purpose of the present invention is to process the data of the data set so that the generated processed analog echo signal can improve the accuracy of echo simulation.

[0073] In an optional implementation, assuming that the sampling rate of the ADC is 2GSPS, the sampling clock period of the ADC is 500ps, the detection processing frequency of the FPGA is 250MHz, the detection processing clock period of the FPGA is 4ns, and the detection accuracy is one FPGA detection processing clock period, that is, the detection accuracy is ±2ns. In this way, the ADC acquisition data received by the FPGA is 8-parallel data, and the schematic diagram of the detection processing is as follows: Figure 5 As shown, the eight degrees of parallelism are parallelism 1 (din_0), parallelism 2 (din_1), parallelism 3 (din_2), parallelism 4 (din_3), parallelism 5 (din_4), parallelism 6 (din_5), parallelism 7 (din_6), and parallelism 8 (din_7).

[0074] When performing detection, a method for generating a detection signal is as follows: the amplitudes of multiple sampling points under the same detection processing clock cycle are compared with the second preset threshold value respectively to obtain multiple comparison results; based on the comparison results, the detection value corresponding to the sampling point is obtained to obtain multiple detection values; the detection value is 0 or 1; when the detection value is 0, the amplitude of the sampling point is less than the second preset threshold value; when the detection value is 1, the amplitude of the sampling point is not less than the second preset threshold value; multiple detection values ​​are ORed to obtain the amplitude of the detection signal under the detection processing clock cycle; the detection signal is generated based on the amplitude of the detection signal under multiple consecutive detection processing clock cycles. It should be noted that the second preset threshold value is determined based on the minimum amplitude of multiple sampling points under the same detection processing clock cycle. In practical applications, it is necessary to ensure that the selected second preset threshold value is greater than 0 and less than or equal to the minimum amplitude of the sampling point. In this way, the second preset threshold value can be used to distinguish between sampling points with an amplitude of 0 and sampling points with a minimum amplitude, so that when the amplitude of the sampling point is less than the second threshold value, the detection value is 0, and when the amplitude of the sampling point is not less than the second threshold value, the detection value is 1.

[0075] In this embodiment, Figure 5 The CLK cycle in is the detection processing clock cycle of the FPGA. In one detection processing clock cycle, there are 8 sampling points for the radar pulse signal, namely 0, 1, 2, 3, 4, 5, 6, and 7. These 8 sampling points are located in the T1 detection processing clock cycle. Figure 5 It can be seen that the amplitude of the radar pulse signal corresponding to sampling points 0 and 1 is 0. The amplitude of these two sampling points is less than the second preset threshold value, and the corresponding detection value at parallelism 1 and parallelism 2 is 0; the amplitude of the radar pulse signal corresponding to sampling points 2-7 is not 0. The amplitude of these six sampling points is greater than the second preset threshold value, and the corresponding detection value at parallelism 3-8 is 1. The detection values ​​of multiple parallelisms are combined into a multi-bit number. The composition principle is: the detection value of parallelism 1 is bit0, the detection value of parallelism 2 is bit1, and so on. The detection value of parallelism n is bit(n-1), so the detection value under this detection processing clock cycle is "11111100". After these 8 detection values ​​are ORed, the envelope detection signal under the detection processing clock cycle T1 is obtained.

[0076] For a pulse signal, the detection value of the signal outside the pulse width is a multi-bit number with a value of 0, and the detection value of the signal inside the pulse width is a multi-bit number that is not 0. The moment when the detection value changes from a constant 0 value to a non-zero value is the rising edge moment of the pulse signal. By taking the detection value at this moment for analysis, the rising edge position of the current pulse signal arriving at the processing system can be found. Through the above method, the detection value under the detection processing clock cycle T1 can be obtained as "00000000", and the detection value under the detection processing clock cycle T1 is "11111100". The value after OR operation of these 8 detection values ​​is 1, indicating that the corresponding rising edge moment under the detection processing clock cycle is the starting moment of the radar pulse signal. Of course, through the above method, the detection value under the detection processing clock cycle T2-T8 can be "11111111", the detection value under the detection processing clock cycle T9 is "011111111", and the detection value under the detection processing clock cycle T10 is "00000000".

[0077] Another method for generating a detection signal is: adding the amplitudes of multiple sampling points under the same detection processing clock cycle to obtain a sum operation result; when the sum operation result is greater than a third preset threshold value, setting the amplitude of the detection signal under the detection processing clock cycle to 1; when the sum operation result is not greater than the third preset threshold value, setting the amplitude of the detection signal under the detection processing clock cycle to 0; generating a detection signal based on the amplitudes of the detection signals under multiple consecutive detection processing clock cycles. It should be noted that the third preset threshold value can be determined based on the minimum amplitude of multiple sampling points under the same detection processing clock cycle. In practical applications, it is necessary to ensure that the selected third preset threshold value is greater than 0 and less than the minimum amplitude of the sampling point. In this way, when only one sampling point has an amplitude that is not 0 among multiple sampling points under the same detection processing clock cycle, the third preset threshold value can be used to distinguish between sampling points with all amplitudes of 0 and sampling points with at least one amplitude that is not 0, so that the amplitude of the detection signal is set to 1 when the sum operation result is greater than the third preset threshold value, and the amplitude of the detection signal is set to 0 when the sum operation result is not greater than the third preset threshold value.

[0078] Step 302: Based on the rising edge of the detection signal, determine the detection processing clock period corresponding to the detection signal to obtain a reference clock period, determine the sampling point whose amplitude under the reference clock period does not exceed the first preset threshold value, and obtain a reference sampling point.

[0079] As an optional implementation, a method for determining the rising edge of a detection signal includes: if at least one detection value corresponding to a sampling point in a target detection processing clock cycle is 0 and at least one detection value is 1, and the detection values ​​corresponding to the sampling points in a detection processing clock cycle after the target detection processing clock cycle are all 1, then determining the starting time of the target detection processing clock cycle as the rising edge of the detection signal.

[0080] The detection processing clock cycle at the rising edge of the detection signal is used as the reference clock cycle, such as Figure 5 As shown, the detection processing clock cycle at the rising edge of the detection signal is T2, and the detection processing clock cycle T2 is used as the reference clock cycle to determine the sampling point whose amplitude is less than the first preset threshold value under the reference clock cycle T2. Optionally, the sampling point corresponding to the sampling point amplitude of 0 can be used as the reference sampling point. Figure 5 , the reference sampling points are sampling points 0 and 1. It should be noted that the first preset threshold value is determined according to the minimum amplitude of multiple sampling points under the reference clock cycle. In practical applications, it is necessary to ensure that the selected first preset threshold value is greater than 0 and less than the minimum amplitude of the sampling point. In this way, the first preset threshold value can be used to distinguish between the sampling point with an amplitude of 0 and the sampling point with the minimum amplitude, so that when the amplitude of the sampling point does not exceed the first threshold value, a reference sampling point is obtained, and the amplitude of the reference sampling point is 0.

[0081] Step 303: taking the product of the sampling clock period and the number of reference sampling points as the detection delay time length; the sampling clock period is the clock period for collecting radar pulse signals.

[0082] The sampling clock period is the sampling clock period of the ADC to collect radar pulse signals. When the sampling rate of the ADC is 1GSPS, the sampling clock period of the ADC is 1ns. When the sampling rate of the ADC is 2GSPS, the sampling clock period of the ADC is 500ps. The time difference between the arrival of the radar pulse signal and the leading edge of the FPGA clock period (the time difference between the actual arrival time and the rising edge of the signal envelope detection signal processed by the FPGA) is extracted, that is, the product of the number of 0s in the detection value bit number and the ADC sampling clock period is used as the detection delay time. Figure 5 It can be seen that the rising edge time obtained by detection is 2×500ps=1ns earlier than the actual arrival time of the radar pulse signal. Therefore, it is necessary to delay 1ns based on the rising edge time. That is, the delay difference between the arrival signal and the leading edge of the FPGA clock cycle is: 2×500ps=1ns.

[0083] For an 8-bit detection value, its corresponding delay difference (ie, detection delay time) is shown in Table 1.

[0084] Table 1 Correspondence between detection value and delay difference

[0085]

[0086]

[0087] It should be noted that, under normal circumstances, the data collected by the ADC enters the FPGA in time sequence, and the data to the FPGA is processed in parallel. Therefore, in the binary data corresponding to the multiple bits composed of the detection value, the number of bits with values ​​of "1" and "0" are continuous and uninterrupted. If there is a discontinuity between "1" and "0", it means that the quality of the external input signal is not good, or the signal has burrs. At this time, the FPGA skips the detection processing clock cycle and performs detection detection in the next detection processing clock cycle.

[0088] Step 304: Delay processing is performed on discrete data points in the data set based on the detection delay time to obtain a processed data set; the processed data set is used to generate a processed simulated echo signal.

[0089] Since there is a detection delay time at the rising edge of the detection signal obtained by the modulo detection method, it is necessary to also delay the multiple discrete data points of the original analog echo signal. By delaying the discrete data points in the data set, the accuracy of the processed analog echo signal can be improved.

[0090] As an optional implementation, step 304 includes: delaying the delayed clock cycle to which the discrete data point belongs by a detection delay time to obtain discrete data points after the clock cycle is changed, wherein the discrete data points after the clock cycle is changed are arranged in the order of the delayed clock cycles, the delayed clock cycle is the clock cycle after the sampling clock cycle is delayed by a preset time, the preset time is 2R / v, R is the distance between the radar pulse signal emission point and the target point, and v is the signal propagation speed; setting the first N discrete data points of the discrete data points after the clock cycle is changed to zero to obtain a processed data set; wherein the N value is the same as the number of reference sampling points.

[0091] based on Figure 5 The 8-parallel ADC data received by the FPGA shown in the figure is collected by Figure 4 The echo simulation process shown can obtain multiple discrete data points of the original simulated echo signal as shown below:

[0092] Parallelism 1 (1st path): a 0 , a 8 , a 16 ……a 8n

[0093] Parallelism 2 (second path): a1 , a 9 , a 17 ……a 8n+1

[0094] Parallelism 3 (third path): a 2 , a 10 , a 18 ……a 8n+2

[0095] Parallelism 4 (4th path): a 3 , a 11 , a 19 ……a 8n+3

[0096] Parallelism 5 (5th path): a 4 , a 12 , a 20 ……a 8n+4

[0097] Parallelism 6 (6th path): a 5 , a 13 , a 21 ……a 8n+5

[0098] Parallelism 7 (7th path): a 6 , a 14 , a 22 ……a 8n+6

[0099] Parallelism 8 (8th path): a 7 , a 15 , a 23 ……a 8n+7

[0100] Depend on Figure 5 It can be seen that the delay difference is 1ns, and the processed data obtained by delay processing in step 304 is as follows:

[0101] Parallelism 1 (1st path): 0, a 6 , a 14 ……a 8n-2

[0102] Parallelism 2 (2nd path): 0, a 7 , a 15 ……a 8n-1

[0103] Parallelism 3 (third path): a 0 , a 8 , a 16 ……a 8n

[0104] Parallelism 4 (4th path): a 1 , a 9 , a 17 ……a 8n+1

[0105] Parallelism 5 (5th path): a 2 , a 10 , a 18 ……a 8n+2

[0106] Parallelism 6 (6th path): a 3 , a 11 , a 19 ……a 8n+3

[0107] Parallelism 7 (7th path): a 4 , a 12 , a 20 ……a 8n+4

[0108] Parallelism 8 (8th path): a 5 , a 13 , a 21 ……a 8n+5

[0109] In this way, the high-precision delay processing of the original simulated echo signal is completed, and the processed simulated echo signal generated based on the processed data set can meet the requirements of radar target echo simulation, so as to improve the reliability of radar performance testing. In addition, the present invention does not increase hardware costs and is convenient for upgrading.

[0110] The present invention also provides a programmable logic controller, which is configured as the radar echo signal detection method described in steps 301 to 304.

[0111] The present invention also provides an echo simulation system, such as Figure 6 As shown, the echo simulation system includes: an analog-to-digital converter 61 (ADC), an FPGA 62, and a digital-to-analog converter 63 (DAC); the output end of the analog-to-digital converter is connected to the input end of the FPGA, and the output end of the FPGA is connected to the input end of the digital-to-analog converter. The analog-to-digital converter transmits multiple discrete data points of the original analog echo signal to the FPGA; the FPGA is configured as the radar echo signal detection method described in steps 301 to 304; the FPGA transmits the processed data set to the digital-to-analog converter, so that the digital-to-analog converter generates a processed analog echo signal based on the processed data set.

[0112] like Figure 6As shown, FPGA62 includes a DDC unit 621, a detection unit 622, a delay unit 623, a modulation unit 624, a DUC unit 625, a delay difference unit 626, and a micro-delay unit 627.

[0113] After receiving the data from the ADC, the FPGA uses the DDC unit 621 to perform digital down conversion (DDC: Digital DownConvertion) processing and uses the detection unit 622 to perform detection processing. The function of the DDC is to perform orthogonal demodulation on the intermediate frequency signal and output an orthogonal signal (IQ signal) with zero intermediate frequency to reduce the data rate for subsequent processing. The detection unit outputs an envelope detection signal, which is used as a trigger signal for the delay unit. The envelope detection signal output by the detection unit is transmitted to the delay difference unit to calculate the delay difference.

[0114] Delay processing is performed after DDC. The purpose of delay is to simulate the target echo at a distance of R. The corresponding relationship between radar target distance and echo delay is: t = 2R / c, where c is the speed of light. Delay is the time it takes for electromagnetic waves to transmit a round-trip distance. The implementation principle of the delay module is to cache data in RAM, and after a delay of t, read the data in RAM to complete the simulation of the target distance.

[0115] The modulation unit performs amplitude modulation and Doppler modulation on the delayed data to simulate the amplitude change and speed change of the target.

[0116] The digital up conversion unit (DUC) completes the digital orthogonal up conversion processing of the modulated IQ data and outputs the intermediate frequency echo signal, and its output is a multi-parallel output signal.

[0117] The micro-delay unit completes the high-precision delay processing of the echo signal. The delay difference of the detection output is used, and the envelope detection signal is used as the reference of the signal delay to fine-tune the envelope delay.

[0118] The present invention also provides a radar echo signal detection device, such as Figure 7 As shown, the device comprises:

[0119] The data acquisition module 701 is used to obtain multiple discrete data points of the original analog echo signal of a detection signal cycle to obtain a data set; the detection signal is a pulse level signal generated based on the sampling points of the radar pulse signal.

[0120] The data acquisition module 701 includes:

[0121] The discrete data point acquisition unit is used to perform detection processing based on the sampling points of the radar pulse signal to obtain the detection signal; perform digital down-conversion processing on the sampling points of the radar pulse signal to obtain the processed sampling points; perform delay processing on the processed sampling points of a detection signal cycle based on the rising edge time of the detection signal and a preset time length to obtain delayed processing data; perform amplitude modulation processing and Doppler modulation processing on the delayed processing data to obtain modulation processing data; perform digital up-conversion processing on the modulated processing data to obtain multiple discrete data points of the original analog echo signal of a detection signal cycle.

[0122] The first detection unit is used to compare the amplitudes of multiple sampling points in the same detection processing clock cycle with the second preset threshold value to obtain multiple comparison results; based on the comparison results, the detection value corresponding to the sampling point is obtained to obtain multiple detection values; the detection value is 0 or 1; when the detection value is 0, the amplitude of the sampling point is less than the second preset threshold value; when the detection value is 1, the amplitude of the sampling point is not less than the second preset threshold value; multiple detection values ​​are ORed to obtain the amplitude of the detection signal in the detection processing clock cycle; the detection signal is generated based on the amplitude of the detection signal in multiple consecutive detection processing clock cycles.

[0123] The second detection unit is used to add the amplitudes of multiple sampling points under the same detection processing clock cycle to obtain a sum operation result; when the sum operation result is greater than a third preset threshold value, the amplitude of the detection signal under the detection processing clock cycle is set to 1; when the sum operation result is not greater than the third preset threshold value, the amplitude of the detection signal under the detection processing clock cycle is set to 0; and the detection signal is generated based on the amplitudes of the detection signals under multiple consecutive detection processing clock cycles.

[0124] The reference clock cycle acquisition module 702 is used to determine the detection processing clock cycle corresponding to the detection signal based on the rising edge of the detection signal to obtain the reference clock cycle; determine the sampling point whose amplitude under the reference clock cycle does not exceed the first preset threshold value to obtain the reference sampling point.

[0125] The reference clock cycle obtaining module 702 includes:

[0126] A rising edge determination unit is used to determine the starting time of the target detection processing clock cycle as the rising edge of the detection signal if at least one detection value corresponding to the sampling point in the target detection processing clock cycle is 0 and at least one detection value is 1, and the detection values ​​corresponding to the sampling points in the next detection processing clock cycle of the target detection processing clock cycle are all 1.

[0127] The detection delay time length determination module 703 is used to use the product of the sampling clock period and the number of reference sampling points as the detection delay time length; the sampling clock period is the clock period for collecting radar pulse signals.

[0128] The delay processing module 704 is used to perform delay processing on discrete data points in the data set based on the detection delay time to obtain a processed data set; the processed data set is used to generate a processed simulated echo signal.

[0129] The delay processing module 704 includes:

[0130] The delay processing unit is used to delay the delayed clock cycle to which the discrete data points belong by the detection delay time to obtain the discrete data points after the clock cycle is changed, wherein the discrete data points after the clock cycle is changed are arranged in the order of the delayed clock cycles, the delayed clock cycle is the clock cycle after the sampling clock cycle is delayed by a preset time, the preset time is 2R / v, R is the distance between the radar pulse signal emission point and the target point, and v is the signal propagation speed; the first N discrete data points of the discrete data points after the clock cycle is changed are set to zero to obtain a processed data set, wherein the N value is the same as the number of reference sampling points.

[0131] An embodiment of the present invention provides a computer-readable storage medium on which a program is stored. When the program is executed by a processor, the above-mentioned radar echo signal detection method is implemented.

[0132] An embodiment of the present invention provides an electronic device, such as Figure 8 As shown, the electronic device 80 includes at least one processor 801, at least one memory 802 and a bus 803 connected to the processor 801; wherein the processor 801 and the memory 802 communicate with each other through the bus 803; the processor 801 is used to call the program instructions in the memory 802 to execute the above-mentioned radar echo signal detection method. The electronic device in this article can be a server, a PC, a PAD, a mobile phone, etc.

[0133] The present application also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program that initializes the steps included in the above-mentioned radar echo signal detection method.

[0134] The present application is described with reference to the flowcharts and / or block diagrams of the methods, systems and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0135] In a typical configuration, the device includes one or more processors (CPU), memory and bus. The device may also include input / output interface, network interface and the like.

[0136] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip. The memory is an example of a computer-readable medium.

[0137] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0138] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0139] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. It should also be noted that the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0140] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0141] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A detection method for radar echo signal, It is characterized in that include: Acquire a plurality of discrete data points of the original analog echo signal of a detection signal cycle to obtain a data set, wherein the detection signal includes a pulse level signal generated based on the sampling points of the radar pulse signal; Based on the rising edge of the detection signal, determine the detection processing clock period corresponding to the detection signal to obtain a reference clock period, determine the sampling point whose amplitude under the reference clock period does not exceed the first preset threshold value, and obtain the reference sampling point, wherein the first preset threshold value is determined according to the minimum amplitude of multiple sampling points under the reference clock period, and the first preset threshold value is greater than 0 and less than the minimum amplitude of the sampling point; The product of a sampling clock period and the number of the reference sampling points is used as a detection delay time, wherein the sampling clock period is a clock period for collecting the radar pulse signal; Delay processing is performed on discrete data points in the data set based on the detection delay time to obtain a processed data set, wherein the processed data set is used to generate a processed simulated echo signal.

2. The radar echo signal detection method according to claim 1, It is characterized in that The delay processing of the discrete data points in the data set based on the detection delay time to obtain the processed data set includes: Delaying the delayed clock cycle to which the discrete data points belong by the detection delay time length to obtain discrete data points after the clock cycle is changed, wherein the discrete data points after the clock cycle is changed are arranged in the order of the delayed clock cycle, and the delayed clock cycle is the clock cycle after the sampling clock cycle is delayed by a preset time length, and the preset time length is 2R / v, R is the distance between the radar pulse signal emission point and the target point, and v is the signal propagation speed; The first N discrete data points of the discrete data points after the clock cycle is changed are set to zero to obtain a processed data set, wherein the value of N is the same as the number of the reference sampling points.

3. The radar echo signal detection method according to claim 2, It is characterized in that The step of obtaining a plurality of discrete data points of the original analog echo signal of a detection signal cycle includes: Perform detection processing based on the sampling points of the radar pulse signal to obtain a detection signal; Performing digital down-conversion processing on the sampling points of the radar pulse signal to obtain processed sampling points; Delay processing is performed on the processed sampling points of a detection signal cycle based on the rising edge time of the detection signal and the preset time length to obtain delayed processing data; Performing amplitude modulation processing and Doppler modulation processing on the delayed processed data respectively to obtain modulated processed data; The modulated processed data is digitally up-converted to obtain a plurality of discrete data points of the original analog echo signal of one detection signal cycle.

4. The radar echo signal detection method according to claim 1 or 3, It is characterized in that The method for generating the detection signal comprises: Compare the amplitudes of the plurality of sampling points in the same detection processing clock cycle with the second preset threshold value respectively to obtain a plurality of comparison results, wherein the second preset threshold value is determined according to the minimum amplitude of the plurality of sampling points in the same detection processing clock cycle, and the second preset threshold value is greater than 0 and less than or equal to the minimum amplitude of the sampling point; Based on the comparison result, a detection value corresponding to the sampling point is obtained to obtain multiple detection values; the detection value is 0 or 1; when the detection value is 0, the amplitude of the sampling point is less than the second preset threshold value; when the detection value is 1, the amplitude of the sampling point is not less than the second preset threshold value; Performing an OR operation on the plurality of detection values ​​to obtain the amplitude of the detection signal in the detection processing clock period; A detection signal is generated based on the amplitude of the detection signal in a plurality of consecutive detection processing clock cycles.

5. The radar echo signal detection method according to claim 1 or 3, It is characterized in that The method for generating the detection signal comprises: Performing a sum operation on the amplitudes of the plurality of sampling points in the same detection processing clock cycle to obtain a sum operation result; When the sum operation result is greater than a third preset threshold value, the amplitude of the detection signal in the detection processing clock cycle is set to 1, wherein the third preset threshold value is determined according to the minimum amplitude of multiple sampling points in the same detection processing clock cycle, and the third preset threshold value is greater than 0 and less than the minimum amplitude of the sampling point; When the sum operation result is not greater than the third preset threshold value, setting the amplitude of the detection signal in the detection processing clock period to 0; A detection signal is generated based on the amplitude of the detection signal in a plurality of consecutive detection processing clock cycles.

6. The radar echo signal detection method according to claim 4, It is characterized in that The method for determining the rising edge of the detection signal comprises: If at least one of the detection values ​​corresponding to the sampling points in the target detection processing clock cycle is 0 and at least one of the detection values ​​is 1, and the detection values ​​corresponding to the sampling points in the next detection processing clock cycle of the target detection processing clock cycle are all 1, then the starting time of the target detection processing clock cycle is determined to be the rising edge of the detection signal.

7. A programmable logic controller, It is characterized in that The programmable logic controller is configured as the radar echo signal detection method according to any one of claims 1-6.

8. An echo simulation system, It is characterized in that include: Analog-to-digital converters, FPGAs, and digital-to-analog converters; The output end of the analog-to-digital converter is connected to the input end of the FPGA, and the output end of the FPGA is connected to the input end of the digital-to-analog converter; The analog-to-digital converter transmits a plurality of discrete data points of the original analog echo signal to the FPGA; The FPGA is configured as a radar echo signal detection method according to any one of claims 1 to 6; The FPGA transmits the processed data set to the digital-to-analog converter, so that the digital-to-analog converter generates a processed analog echo signal based on the processed data set.

9. A detection device for radar echo signal, It is characterized in that include: A data acquisition module is used to obtain multiple discrete data points of the original analog echo signal of a detection signal cycle to obtain a data set; The detection signal is a pulse level signal generated based on the sampling points of the radar pulse signal; A reference clock cycle obtaining module, used to determine the detection processing clock cycle corresponding to the detection signal based on the rising edge of the detection signal, and obtain a reference clock cycle; Determine a sampling point whose amplitude under the reference clock cycle does not exceed a first preset threshold value, and obtain a reference sampling point, wherein the first preset threshold value is determined according to a minimum amplitude of a plurality of sampling points under the reference clock cycle, and the first preset threshold value is greater than 0 and less than the minimum amplitude of the sampling point; A detection delay time determination module, used to use the product of a sampling clock period and the number of reference sampling points as the detection delay time; the sampling clock period is a clock period for collecting the radar pulse signal; The delay processing module is used to perform delay processing on discrete data points in the data set based on the detection delay time to obtain a processed data set; the processed data set is used to generate a processed simulated echo signal.

10. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores a program, and when the program is executed by a processor, the radar echo signal detection method according to any one of claims 1 to 6 is implemented.

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