Troubleshooting methods, devices, and electronic equipment in chip verification process

Abstract

This application provides a fault handling method, apparatus, and electronic device in the chip verification process, comprising: identifying faults during chip verification; acquiring fault information in response to fault identification; determining a target fault debugging strategy matching the fault information; executing the target fault debugging strategy to debug the fault; and continuing the chip verification process from the fault location point in response to the end of fault debugging. This application achieves fault debugging during the chip verification process, avoiding modification of the source code corresponding to chip verification and re-simulation of the modified source code, effectively shortening the fault repair time in the chip verification process, thereby improving the efficiency of chip verification.

Description

Technical Field

[0001] This application relates to the field of chip verification, and in particular to a fault handling method, apparatus and electronic device in the chip verification process. Background Technology

[0002] With societal development, chip verification has become increasingly important. As chip design becomes more complex, the verification time for each module of the chip also increases, leading to longer repair times for faults that occur during chip verification and impacting the efficiency of chip verification.

[0003] Therefore, improving the efficiency of chip verification has become a problem that needs to be solved. Summary of the Invention

[0004] The purpose of this application is to at least partially solve one of the technical problems in the aforementioned technologies.

[0005] The first aspect of this application provides a fault handling method in a chip verification process, comprising: performing fault identification during the chip verification process; in response to identifying a fault, acquiring fault information of the fault; determining a target fault debugging strategy matching the fault information; executing the target fault debugging strategy to debug the fault; and in response to the end of fault debugging, continuing the chip verification process from the location of the fault.

[0006] The fault handling method in the chip verification process provided in the first aspect of this application also has the following technical features, including:

[0007] According to one embodiment of this application, determining the target fault debugging strategy that matches the fault information includes: determining the fault object and the corresponding fault type in the chip verification process from the fault information; and determining the target fault debugging strategy based on the fault object and the fault type.

[0008] According to one embodiment of this application, determining the target fault debugging strategy based on the fault object and the fault type includes: in response to a configuration fault of the fault object during chip verification, modifying the configuration parameters of the fault object and using this as the target fault debugging strategy; in response to an operational fault of the fault object during chip verification, invoking a matching debugging test sequence, debugging the operational fault of the fault object based on the execution results of the debugging test sequence, and using this as the target fault debugging strategy; and in response to a verification missing fault of the fault object during chip verification, invoking a corresponding functional test sequence, supplementing the missing verification functions of the fault object based on the execution results of the functional test sequence, and using this as the target fault debugging strategy.

[0009] According to one embodiment of this application, executing the target fault debugging strategy to debug the fault includes: in response to the identification of the fault, starting a general debugging library, wherein the general debugging library is connected to the chip verification platform; receiving a target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the general debugging library; and executing the target fault debugging strategy according to the target fault debugging instruction.

[0010] According to one embodiment of this application, starting the general debugging library includes: triggering the execution of startup code to start the general debugging library, wherein the startup code is compiled in the code of the chip verification platform; or, executing a script to start the general debugging library.

[0011] According to one embodiment of this application, after executing the target debugging processing strategy to debug the fault, the method further includes: receiving a debugging detection instruction transmitted by the general debugging library; running the debugging detection instruction; and determining that the fault debugging in the chip verification process is completed based on the running result of the debugging detection instruction.

[0012] A second aspect of this application provides a fault handling apparatus in a chip verification process, comprising: an identification module for identifying faults during the chip verification process and, in response to identifying a fault, acquiring fault information of the fault; a determination module for determining a target fault debugging strategy that matches the fault information; a debugging module for executing the target fault debugging strategy to debug the fault; and a verification module for continuing the chip verification process from the location of the fault in response to the end of fault debugging.

[0013] The second aspect of this application provides a fault handling device in the chip verification process, which further has the following technical features, including:

[0014] According to one embodiment of this application, the determining module is further configured to: determine the fault object and the corresponding fault type in the chip verification process from the fault information; and determine the target fault debugging strategy based on the fault object and the fault type.

[0015] According to one embodiment of this application, the determining module is further configured to: in response to a configuration fault of the fault object during chip verification, modify the configuration parameters of the fault object and use them as the target fault debugging strategy; in response to an operational fault of the fault object during chip verification, invoke a matching debugging test sequence, debug the operational fault of the fault object based on the execution results of the debugging test sequence, and use them as the target fault debugging strategy; in response to a verification missing fault of the fault object during chip verification, invoke a corresponding functional test sequence, supplement the missing verification functions of the fault object based on the execution results of the functional test sequence, and use them as the target fault debugging strategy.

[0016] According to one embodiment of this application, the debugging module is further configured to: in response to the identification of the fault, start a general debugging library, wherein the general debugging library is connected to the chip verification platform; receive a target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the general debugging library, and execute the target fault debugging strategy according to the target fault debugging instruction.

[0017] According to one embodiment of this application, the debugging module is further configured to: trigger the execution of startup code to start the general debugging library, wherein the startup code is compiled in the code of the chip verification platform; or, execute a script to start the general debugging library.

[0018] According to one embodiment of this application, the debugging module is further configured to: receive debugging and detection instructions transmitted by the general debugging library; run the debugging and detection instructions; and determine, based on the running result of the debugging and detection instructions, that the fault debugging in the chip verification process has been completed.

[0019] A third aspect of this application provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a fault handling method in the chip verification process provided in the first aspect of this application.

[0020] A fourth aspect of this application provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute a fault handling method in the chip verification process provided in the first aspect of this application.

[0021] A fifth aspect of this application provides a computer program product that, when executed by an instruction processor, performs a fault handling method in the chip verification process provided in the first aspect of this application.

[0022] The fault handling method and apparatus provided in this application for chip verification process identify faults during chip verification and acquire corresponding fault information after fault identification. Based on the acquired fault information, a matching target fault debugging strategy is determined. Furthermore, the target fault debugging strategy is executed, and after fault debugging is completed, chip verification continues from the location where the fault occurred. This application realizes fault debugging during the chip verification process, avoiding modification of the source code corresponding to chip verification and re-simulation of the modified source code, effectively shortening the fault repair time during chip verification and thus improving the efficiency of chip verification.

[0023] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0024] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0025] Figure 1 This is a flowchart illustrating a fault handling method during chip verification according to an embodiment of this application.

[0026] Figure 2 This is a flowchart illustrating a fault handling method during chip verification according to another embodiment of this application.

[0027] Figure 3 This is a flowchart illustrating a fault handling method during chip verification according to another embodiment of this application.

[0028] Figure 4 This is a flowchart illustrating a fault handling method during chip verification according to another embodiment of this application.

[0029] Figure 5 This is a schematic diagram of a fault handling device in the chip verification process according to an embodiment of this application;

[0030] Figure 6 This is a schematic diagram of a fault handling device in the chip verification process according to another embodiment of this application;

[0031] Figure 7 This is a block diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0032] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0033] The following description, with reference to the accompanying drawings, details a fault handling method, apparatus, electronic device, and storage medium in the chip verification process according to embodiments of this application.

[0034] Figure 1 This is a flowchart illustrating a fault handling method during chip verification according to an embodiment of this application, as shown below. Figure 1 As shown, the method includes:

[0035] S101 performs fault identification during chip verification and obtains fault information in response to the identification of a fault.

[0036] In practice, chip verification can be achieved through a chip verification platform. By monitoring the operation of the chip verification platform, the chip verification process can be monitored.

[0037] In this embodiment, the chip and the chip verification platform contain corresponding code, and the chip verification process can be monitored through the printed information in the code.

[0038] Among these features, faults that occur during the chip verification process can be identified through printed information.

[0039] Furthermore, after a fault is detected, the chip verification process can be paused, and relevant information about the fault that occurred during the current chip verification process can be obtained based on the printed information.

[0040] Faults that occur during chip verification can include partial loss of the chip's functions to be verified, as well as operational lag during the chip verification process.

[0041] S102, Determine the target fault debugging strategy that matches the fault information.

[0042] In practice, each step of the chip verification process may fail. Therefore, it is necessary to determine the debugging method that can effectively debug and resolve the fault based on the detailed information included in the fault information, and then generate a matching target fault debugging strategy.

[0043] For example, if the fault that occurs during chip verification is that the code corresponding to the function to be verified of the chip cannot call the required parameters, the calling process of the parameters can be debugged, thereby generating a matching target fault debugging strategy.

[0044] For example, if the fault that occurs during chip verification is a running lag, the steps that cause the running lag can be adjusted, the cause of the lag can be analyzed, and a matching target fault debugging strategy can be generated.

[0045] S103, execute the target fault debugging strategy and perform fault debugging.

[0046] In this embodiment, the chip verification platform can perform relevant operations based on the information carried in the target fault debugging strategy, thereby enabling the debugging of faults that occur during the chip verification process.

[0047] For example, calling relevant parameters according to the target fault debugging strategy. Another example is adjusting lag based on the target fault debugging strategy.

[0048] This can be understood as debugging faults that occur during chip verification by executing the steps carried in the target fault debugging strategy.

[0049] S104, in response to the end of fault debugging, continues the chip verification process from the location of the fault.

[0050] In practice, it is possible to determine whether the current fault debugging has ended based on relevant settings.

[0051] Furthermore, based on the troubleshooting results after the debugging is completed, the chip verification process can continue.

[0052] This can be understood as the correct result corresponding to the location where the fault occurred during the chip verification process. Therefore, the chip verification can continue from the location where the fault occurred, based on this correct result.

[0053] The fault handling method provided in this application for chip verification process identifies faults during chip verification and acquires corresponding fault information after fault identification. Based on the acquired fault information, a matching target fault debugging strategy is determined. Furthermore, the target fault debugging strategy is executed, and after fault debugging is completed, chip verification continues from the location where the fault occurred. This application realizes fault debugging during the chip verification process, avoiding modification of the corresponding source code and re-simulation of the modified source code, effectively shortening the fault repair time during chip verification and thus improving the efficiency of chip verification.

[0054] In the above embodiments, the determination of the target fault debugging strategy can be combined with... Figure 2 To understand further, Figure 2 This is a flowchart illustrating a fault handling method during chip verification according to another embodiment of this application, as shown below. Figure 2 As shown, the method includes:

[0055] S201, determine the fault object and corresponding fault type in the chip verification process from the fault information.

[0056] In this embodiment of the application, the fault object that caused the fault during the chip verification process can be determined from the fault information, such as a certain running step in the chip verification process, or a certain parameter configured in the chip verification process, etc.

[0057] Furthermore, obtain the fault type corresponding to the faulty object.

[0058] Optionally, information about the faulty object and its corresponding fault type can be obtained from the printed information of the chip verification.

[0059] When a fault occurs during the chip verification process, the text information and / or return code information of the faulty object, as well as the text information and / or return code information of the corresponding fault type, can be presented in the printed information to determine the information of the faulty object and the corresponding fault type.

[0060] S202, Determine the target fault debugging strategy based on the fault object and fault type.

[0061] Furthermore, after obtaining the fault object and its corresponding fault type, the corresponding target fault debugging strategy can be determined based on the corresponding solution.

[0062] Optionally, in response to a configuration fault of a fault object during chip verification, the configuration parameters of the fault object are modified and used as the target fault debugging strategy.

[0063] In this embodiment, to ensure the test cases run correctly, the chip verification platform needs to configure corresponding runtime support for the test cases. During the configuration of this runtime support, errors may occur in parameter configuration or object configuration; these can be identified as configuration faults of the faulty objects.

[0064] Furthermore, in the chip verification process, in the case of a faulty object that cannot run or runs incorrectly due to configuration failure, the relevant configuration parameters can be modified and used as the target fault debugging strategy in the fault scenario.

[0065] For example, if the registers configured by the test verification platform for test cases have incorrect parameter configurations, the code to be verified may be unable to obtain the required information from the registers, or the intermediate execution results of the code to be verified may not be stored in the registers, causing the code to be verified in the test cases to fail to run normally.

[0066] In this fault scenario, the fault object is the register configured by the chip verification platform for the test case, and its fault type is a configuration fault corresponding to parameter configuration error. Therefore, the debugging method of modifying the register parameters can be identified as the target fault debugging strategy in this fault scenario.

[0067] Optionally, in response to a fault type of a faulty object during chip verification, a matching debug test sequence is invoked, and the operational fault of the faulty object is debugged based on the execution result of the debug test sequence, which is then used as the target fault debugging strategy.

[0068] In this embodiment of the application, to verify a certain function of the chip, it is necessary to simulate all the operation steps of the function. However, there may be a failure in the operation of a certain step.

[0069] In implementation, there are multiple test sequences for the test cases corresponding to a certain function to be verified. Each test sequence can simulate at least one running step. Therefore, when a certain running step fails, it can be understood that the corresponding test sequence has failed.

[0070] Optionally, the test sequence that is experiencing a runtime failure can be adjusted by calling other test sequences and used as the corresponding repair test sequence. The results of running the repair test sequence can be used to debug the test sequence that is experiencing a runtime failure.

[0071] As one possible implementation, a test sequence that experiences a runtime failure may produce an incorrect result after completion. In this failure scenario, the result of a repaired test sequence can be used to replace the failure result of the original test sequence, and this repaired result can be considered the correct result for the next step in the test sequence that experienced the failure. Furthermore, the test sequence experiencing the failure can be debugged based on the repaired result.

[0072] As another possible implementation, the test sequence that fails may fail during the test sequence's execution, preventing it from continuing. In this failure scenario, the test sequence that fails has intermediate results that have already been executed.

[0073] Optionally, in the fault sub-scenario where the intermediate result is correct, the repair execution result of the repair test sequence can be integrated with the intermediate result, and the integrated execution result can be used as the correct execution result for the step to be run corresponding to the test sequence that has experienced execution failure. Furthermore, the test sequence that has experienced execution failure is debugged based on the integrated execution result.

[0074] Optionally, in the fault sub-scenario where the intermediate result is an incorrect result, the faulty test sequence can be replaced based on the repair run result of the repair test sequence, and the repair run result of the repair test sequence can be used as the correct run result of the step to be run corresponding to the faulty test sequence. Furthermore, the faulty test sequence can be debugged based on the repair run result.

[0075] Furthermore, in response to a fault type of missing verification of a fault object during chip verification, the corresponding functional test sequence is invoked. Based on the running results of the functional test sequence, the missing verification function of the fault object is supplemented, and this is used as the target fault debugging strategy.

[0076] In this embodiment of the application, the chip has multiple functions to be verified, and there is a possibility that some of these functions may have verification failures.

[0077] In some implementations, there is a possibility that the chip's functions that need to be verified have not been verified.

[0078] In this fault scenario, the chip verification platform can construct corresponding test cases based on the function to be verified and determine them as the corresponding target fault debugging strategy. Simulation based on the test cases in this target fault debugging strategy can achieve the verification of the function to be verified.

[0079] In other implementations, there is a possibility that the chip's functions to be verified are only partially verified.

[0080] In this fault scenario, the chip verification platform can construct corresponding test sequences based on the missing verification parts and determine them as the corresponding target fault debugging strategy. Simulation based on the test sequences in this target fault debugging strategy can verify the function to be verified.

[0081] The fault handling method provided in this application for chip verification process identifies the fault object and corresponding fault type from the fault information, and then determines the corresponding target fault debugging strategy. Based on detailed fault information, the accuracy and effectiveness of the target fault debugging strategy are improved, thereby shortening the time spent on fault debugging and effectively improving the efficiency of chip verification fault debugging and chip verification efficiency.

[0082] In the above embodiments, the acquisition of fault information and the execution of the target fault debugging strategy can also be implemented through a general debugging library, which can be combined with Figure 3 To understand further, Figure 3 This is a flowchart illustrating a fault handling method during chip verification according to another embodiment of this application, as shown below. Figure 3 As shown, the method includes:

[0083] S301, in response to the detection of a fault, starts the general debugging library, which is connected to the chip verification platform.

[0084] In practice, the chip verification platform has a matching general debugging library. After the chip verification platform starts simulation, the general debugging library can be used to realize information interaction between the chip verification platform and other devices.

[0085] One possible implementation is to trigger the execution of startup code to launch a general debugging library, where the startup code is compiled into the code of the chip verification platform.

[0086] In this embodiment, the startup code corresponding to the general debugging library can be compiled into the chip verification platform.

[0087] For example, the code for the chip verification platform can be written in the SV language (System Verilog), and the startup code corresponding to the general debugging library can be compiled into it. Based on the execution of the startup code, the general debugging library can be started.

[0088] This allows you to set corresponding trigger events for the startup code of the general debugging library. When the corresponding trigger event occurs, the startup code will be executed, thereby starting the general debugging library.

[0089] Optionally, the corresponding trigger event can be set to a failure during the chip verification process. This can be understood as follows: when a failure occurs during chip verification, the startup code of the general debug library can obtain the corresponding enable instruction. Based on this enable instruction, the startup code is executed to start the general debug library.

[0090] Optionally, the corresponding trigger event can be set to pause the chip verification process. This can be understood as follows: when a fault occurs during the chip verification process, the process will be paused. When the chip verification process is paused, the startup code of the general debug library can obtain the corresponding enable instruction. Based on this enable instruction, the startup code is executed to start the general debug library.

[0091] As another possible implementation, a script can be executed to start a general debugging library.

[0092] In this embodiment of the application, the general debug library contains a corresponding startup script, which can be used to start the general debug library.

[0093] For example, you can use the Tool Command Language (TCL) to write a startup script for a general-purpose debugging library, and then use the execution of the TCL script to start the general-purpose debugging library.

[0094] Optionally, a startup script for the general debugging library can be pre-defined and stored in a designated location. Furthermore, a corresponding trigger event can be set for the startup script of the general debugging library. When the trigger event occurs, the execution of the startup script can be automatically triggered, thereby starting the general debugging library.

[0095] The corresponding trigger event can be set to either a fault occurring during chip verification or a pause in the chip verification process.

[0096] Optionally, when a fault is detected during the chip verification process, a corresponding script input window can be obtained, and the startup script of the general debugging library can be entered in the window, thereby starting the general debugging library through the execution of the startup script.

[0097] The script input window can be triggered by a fault occurring during chip verification or by pausing the chip verification process.

[0098] Furthermore, the general-purpose debugging library can provide a relevant user interface. By launching the general-purpose debugging library, the chip verification platform can interact with other devices.

[0099] S302, receive the target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the general debugging library, and execute the target fault debugging strategy according to the target fault debugging instruction.

[0100] In this embodiment, the target fault debugging strategy can be transmitted to the chip verification platform through data interaction between the general debugging library and the chip verification platform.

[0101] Optionally, the general debug library contains a set input format. Therefore, the target fault debugging strategy can be converted based on the input format set by the general debug library to generate the corresponding target fault debugging instruction, and then the target fault debugging instruction can be transmitted to the chip verification platform through the general debug library.

[0102] Optionally, the general debug library contains set instructions. Based on the target fault debugging strategy, the set instructions are combined to generate the corresponding target fault debugging instructions, and the target fault debugging instructions are transmitted to the chip verification platform through the general debug library.

[0103] The target fault debugging instruction carries a debugging method for faults that occur during chip verification. The chip verification platform can read and execute the debugging method carried in the received target fault debugging instruction, thereby realizing the debugging of faults that occur during chip verification.

[0104] The fault handling method provided in this application for chip verification process achieves data interaction with the chip verification platform by starting a general debugging library, thereby transmitting the target fault debugging strategy to the chip verification platform. Furthermore, the chip verification platform debugs faults occurring during chip verification based on the target fault debugging instructions corresponding to the received target fault debugging strategy. In this application, the debugging of faults occurring during chip verification is achieved by starting a general debugging library, thus improving the efficiency of chip verification fault debugging.

[0105] Furthermore, troubleshooting faults during chip verification requires further testing to obtain the results of the troubleshooting process. This can be combined with... Figure 4 understand, Figure 4 This is a flowchart illustrating a fault handling method during chip verification according to another embodiment of this application, as shown below. Figure 4 As shown, the method includes:

[0106] S401 receives debugging and detection commands transmitted from the general debugging library.

[0107] In this embodiment of the application, in order to ensure the accuracy of chip verification, it is necessary to detect the faults during the chip verification process.

[0108] Optionally, detection can be performed using debugging detection commands. These commands can be set based on the target debugging strategy.

[0109] Furthermore, after the set debugging and detection instructions are transmitted to the chip verification platform through the general debugging library, the chip verification platform can detect the results of fault debugging based on the received instructions.

[0110] Among them, the debugging and detection command can be a detection after debugging the running steps, or a detection after debugging the parameters with configuration errors.

[0111] S402 executes the debugging and testing command. Based on the execution result of the debugging and testing command, it is determined that the fault debugging in the chip verification process has been completed.

[0112] In this embodiment of the application, the results of fault debugging can be detected based on the execution of the debugging and detection command. A corresponding detection duration can be set, and the results of fault debugging can be judged based on the execution results within the detection duration.

[0113] Optionally, the debugging and detection commands can be used to detect debugging failures in the running steps.

[0114] The fault operation steps can be debugged by calling a matching repair test sequence, thus allowing for the detection of the repair test sequence's repair operation results. The subsequent steps of chip verification can continue running from the debugged fault location. When the running time reaches the set detection duration, the operation is paused, and the results within that detection duration are obtained.

[0115] Optionally, the debugging and detection command can detect faults caused by incorrect configuration parameters.

[0116] Incorrect configuration parameters can be debugged by modifying the configuration parameters. Therefore, the debugged parameters can be tested. Chip verification can be run based on the debugged configuration parameters. When the running time reaches the set test duration, the run will be paused, and the running results within that test duration will be obtained.

[0117] Furthermore, if the running results within the detection period are correct, the fault can be judged to have been successfully debugged. Conversely, if the running results within the detection period are abnormal, the current fault debugging can be judged to have been unsuccessful, and the target fault debugging strategy needs to be adjusted until debugging is successful, at which point the adjustment ends.

[0118] The fault handling method provided in this application for chip verification process detects the results of fault debugging through debugging and detection commands, thereby achieving accurate debugging of faults that occur during chip verification.

[0119] Corresponding to the fault handling methods in the chip verification process provided in the above embodiments, one embodiment of this application also provides a fault handling device in the chip verification process. Since the fault handling device in the chip verification process provided in this application corresponds to the fault handling methods in the chip verification process provided in the above embodiments, the implementation methods of the above-mentioned fault handling methods in the chip verification process are also applicable to the fault handling device in the chip verification process provided in this application, and will not be described in detail in the following embodiments.

[0120] Figure 5 This is a schematic diagram of the fault handling device in the chip verification process according to an embodiment of this application, as shown below. Figure 5 As shown, the fault handling device 500 in the chip verification process includes an identification module 51, a determination module 52, a debugging module 53, and a verification module 54, wherein:

[0121] The identification module 51 is used to identify faults during the chip verification process and to obtain fault information in response to the identification of a fault.

[0122] Module 52 is used to determine the target fault debugging strategy that matches the fault information;

[0123] Debugging module 53 is used to execute the target fault debugging strategy and perform fault debugging.

[0124] Verification module 54 is used to continue the chip verification process from the location of the fault in response to the end of fault debugging.

[0125] Figure 6 This is a schematic diagram of the fault handling device in the chip verification process according to another embodiment of this application, as shown below. Figure 6 As shown, the fault handling device 600 in the chip verification process includes an identification module 61, a determination module 62, a debugging module 63, and a verification module 64, wherein:

[0126] It should be noted that the identification module 51, determination module 52, debugging module 53, and verification module 54 have the same structure and function as the identification module 61, determination module 62, debugging module 63, and verification module 64.

[0127] In this embodiment of the application, the determining module 62 is further configured to: determine the fault object and the corresponding fault type in the chip verification process from the fault information; and determine the target fault debugging strategy based on the fault object and the fault type.

[0128] In this embodiment, the determining module 62 is further configured to: in response to a configuration fault of a fault object during chip verification, modify the configuration parameters of the fault object and use them as a target fault debugging strategy; in response to an operational fault of a fault object during chip verification, call a matching debugging test sequence, debug the operational fault of the fault object based on the execution results of the debugging test sequence, and use it as a target fault debugging strategy; in response to a verification missing fault of a fault object during chip verification, call the corresponding functional test sequence, supplement the missing verification functions of the fault object based on the execution results of the functional test sequence, and use it as a target fault debugging strategy.

[0129] In this embodiment of the application, the debugging module 63 is further configured to: in response to the identification of a fault, start a general debugging library, wherein the general debugging library is connected to the chip verification platform; receive a target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the general debugging library, and execute the target fault debugging strategy according to the target fault debugging instruction.

[0130] In this embodiment of the application, the debugging module 63 is further configured to: trigger the execution of startup code to start a general debugging library, wherein the startup code is compiled in the code of the chip verification platform; or, execute a script to start a general debugging library.

[0131] In this embodiment of the application, the debugging module 63 is further configured to: receive debugging detection instructions transmitted by the general debugging library;

[0132] Run the debugging and testing commands, and determine the completion of fault debugging in the chip verification process based on the results of the debugging and testing commands.

[0133] The fault handling device for chip verification provided in this application identifies faults during chip verification and acquires corresponding fault information after fault identification. Based on the acquired fault information, a matching target fault debugging strategy is determined. Furthermore, the target fault debugging strategy is executed, and after fault debugging is completed, chip verification continues from the location where the fault occurred. This application realizes fault debugging during chip verification, avoiding modification of the source code corresponding to chip verification and re-simulation of the modified source code, effectively shortening the fault repair time during chip verification and thus improving the efficiency of chip verification.

[0134] To achieve the above embodiments, this application also provides an electronic device, a computer-readable storage medium, and a computer program product.

[0135] Figure 7 This is a block diagram of an electronic device according to an embodiment of this application, based on... Figure 7 The electronic device shown can perform Figures 1 to 4 The embodiment describes a fault handling method during chip verification.

[0136] To implement the above embodiments, this application also provides a readable storage medium storing computer instructions for causing a computer to execute... Figures 1 to 4 The embodiment describes a fault handling method during chip verification.

[0137] To implement the above embodiments, this application also provides a computer program product that, when the instruction processor in the computer program product is executed, performs... Figures 1 to 4 The embodiment describes a fault handling method during chip verification.

[0138] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0139] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0140] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0141] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0142] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0143] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments.

[0144] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0145] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A fault handling method in the chip verification process, characterized in that, include: During the chip verification process, fault identification is performed, and in response to the identification of a fault, fault information of the fault is obtained; Determine the target fault debugging strategy that matches the fault information; The target fault debugging strategy is executed to debug the fault. In response to the end of fault debugging, the chip verification process continues from the location of the fault. The step of determining the target fault debugging strategy that matches the fault information includes: The fault object and corresponding fault type in the chip verification process are determined from the fault information; The target fault debugging strategy is determined based on the fault object and the fault type. The step of determining the target fault debugging strategy based on the fault object and the fault type includes: In response to the fault type being a configuration fault of the fault object during the chip verification process, the configuration parameters of the fault object are modified and used as the target fault debugging strategy; In response to the fault type being the operational fault of the fault object during the chip verification process, a matching debugging test sequence is invoked, and the operational fault of the fault object is debugged according to the running result of the debugging test sequence, which is used as the target fault debugging strategy. In response to the fault type being a verification missing fault of the fault object during the chip verification process, the corresponding functional test sequence is invoked, and the missing verification function of the fault object is supplemented according to the running result of the functional test sequence, which serves as the target fault debugging strategy.

2. The method according to claim 1, characterized in that, The execution of the target fault debugging strategy to debug the fault includes: In response to the detection of the fault, a general debugging library is started, wherein the general debugging library is connected to the chip verification platform; Receive the target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the general debugging library, and execute the target fault debugging strategy according to the target fault debugging instruction.

3. The method according to claim 2, characterized in that, The startup of the general debugging library includes: The startup code is triggered to run, launching the general debugging library, wherein the startup code is compiled into the code of the chip verification platform; or, Execute the script to start the general debugging library.

4. The method according to claim 2 or 3, characterized in that, After executing the target fault debugging strategy and debugging the fault, the method further includes: Receive the debugging and detection commands transmitted by the general debugging library; Run the debugging and testing instructions, and determine the completion of fault debugging in the chip verification process based on the execution results of the debugging and testing instructions.

5. A fault handling device in the chip verification process, characterized in that, include: The identification module is used to identify faults during the chip verification process, and in response to the identification of a fault, to obtain fault information of the fault; A determination module is used to determine a target fault debugging strategy that matches the fault information; The debugging module is used to execute the target fault debugging strategy and perform fault debugging on the fault. The verification module is used to continue the chip verification process from the location of the fault in response to the end of fault debugging. The determining module is further configured to: The fault object and corresponding fault type in the chip verification process are determined from the fault information; The target fault debugging strategy is determined based on the fault object and the fault type. The determining module is further configured to: In response to the fault type being a configuration fault of the fault object during the chip verification process, the configuration parameters of the fault object are modified and used as the target fault debugging strategy; In response to the fault type being the operational fault of the fault object during the chip verification process, a matching debugging test sequence is invoked, and the operational fault of the fault object is debugged according to the running result of the debugging test sequence, which is used as the target fault debugging strategy. In response to the fault type being a verification missing fault of the fault object during the chip verification process, the corresponding functional test sequence is invoked, and the missing verification function of the fault object is supplemented according to the running result of the functional test sequence, which serves as the target fault debugging strategy.

6. The apparatus according to claim 5, characterized in that, The debugging module is also used for: In response to the detection of the fault, a general debugging library is started, wherein the general debugging library is connected to the chip verification platform; Receive the target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the general debugging library, and execute the target fault debugging strategy according to the target fault debugging instruction.

7. The apparatus according to claim 6, characterized in that, The debugging module is also used for: The startup code is triggered to run, launching the general debugging library, wherein the startup code is compiled into the code of the chip verification platform; or, Execute the script to start the general debugging library.

8. The apparatus according to claim 6 or 7, characterized in that, The debugging module is also used for: Receive the debugging and detection commands transmitted by the general debugging library; Run the debugging and testing instructions, and determine the completion of fault debugging in the chip verification process based on the execution results of the debugging and testing instructions.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-4.

10. A readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-4.

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