A memory simulation verification method and device

Abstract

The application discloses a memory simulation verification method and device, and the simulation verification method comprises the following steps: acquiring a simulation storage point of a key path of a memory, wherein the key path is the farthest path between the memory and an access port; verifying whether the read-write function of the memory is correct; if yes, extracting a timing parameter of the simulation storage point for simulation verification, wherein the timing parameter is generated in the process of verifying the read-write function of the simulation storage point. After the read-write function of the simulation storage point is verified to be correct, the timing parameter of the simulation storage point is extracted for simulation verification, so that the accuracy of the read-write function verification and the timing parameter is ensured, the read-write function can be verified at the same time of characteristic parameter simulation, the application can be applied to the design of a storage compiler, and the workload of simulation verification can be greatly reduced, and the design efficiency of the storage compiler is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory simulation verification, and particularly relates to a simulation verification method and device of a memory. BACKGROUND

[0002] Since the number of memories contained in a memory compiler is very large, it is difficult to implement functional simulation for all memories, and the traditional method selects only part of the storage points for functional simulation at the initial design stage, resulting in incomplete verification. Feature timing simulation does not determine functional simulation, which leads to functional failure of part of the storage points or insufficient verification of the feature results, and further causes errors in the feature extraction data of the memory compiler.

[0003] Therefore, how to ensure that the feature extraction data is correct when the memory is simulated and verified is a technical problem to be solved at present. SUMMARY

[0004] In view of the above technical problems, the simulation verification method and device of the memory provided by the present application can ensure that the feature extraction data is correct when the memory is simulated and verified.

[0005] The embodiments of the present application provide the following solutions:

[0006] In a first aspect, the embodiments of the present application provide a simulation verification method of a memory, comprising:

[0007] obtaining a simulation storage point of a critical path of the memory, wherein the critical path is the farthest path between the memory and an access port;

[0008] verifying whether the read-write function of the memory is correct;

[0009] If yes, extracting a timing parameter of the simulation storage point for simulation verification, wherein the timing parameter is generated in the process of verifying the read-write function of the simulation storage point.

[0010] In an optional embodiment, the obtaining of the simulation storage point of the critical path of the memory comprises:

[0011] obtaining capacity information of the memory;

[0012] obtaining address information according to the capacity information;

[0013] obtaining the simulation storage point according to the address information.

[0014] In an optional embodiment, the obtaining of the address information according to the capacity information comprises:

[0015] a word and a data multiplex value of the capacity information are obtained;

[0016] it is judged whether the word is an integral power of 2;

[0017] if yes, the address information is obtained according to a first address value and the data multiplex value, wherein the first address value is a power value of the word;

[0018] if no, the address information is obtained according to a second address value and the data multiplex value, wherein the second address value is the power value of the word plus 1.

[0019] In an optional embodiment, the verifying whether the read-write function of the memory is correct comprises:

[0020] the simulation storage point and the access port are initialized to obtain an initialization result;

[0021] the read-write function of the simulation storage point is verified according to the initialization result.

[0022] In an optional embodiment, the initializing the simulation storage point and the access port comprises:

[0023] a verification vector is obtained, wherein the verification vector comprises 0 and 1;

[0024] if the verification vector is 0, the access port is initialized to output 1 and the initial value of the simulation storage point is initialized to 1;

[0025] if the verification vector is 1, the initial value of the simulation storage point is initialized to 0 and the access port is initialized to output 0.

[0026] In an optional embodiment, the memory is a single-port memory, and the initializing the access port to output 1 and the initializing the initial value of the simulation storage point to 1 comprises:

[0027] 1 is written to the memory through a non-critical path to make the access port output 1, which is equivalent to initializing the access port output to 1 in a write operation, wherein the non-critical path is a path other than the critical path;

[0028] the simulation storage point is initialized to 1 through a simulation command, and 0 is written to the simulation storage point through the critical path to make the access port output 0;

[0029] the corresponding storage point is read through the non-critical path, and the access port reads out 1, which is equivalent to initializing the access port to 1 in a read operation;

[0030] the critical path reads the simulation storage point;

[0031] The initial value of the simulation storage point is initialized as 0, and the output of the access port is initialized as 0, comprising:

[0032] The non-critical path is written as 0, and the output of the access port is 0, which is equivalent to initializing the output of the access port as 0 when writing;

[0033] The simulation storage point is initialized as 0 by a simulation command, and then 1 is written to the simulation storage point through the critical path, and the output of the access port is 1;

[0034] The corresponding storage point is read through the non-critical path, and the access port reads 0, which is equivalent to initializing the access port as 0 when reading;

[0035] The simulation storage point is read through the critical path.

[0036] In an optional embodiment, the read and write functions of the simulation storage point are verified according to the initialization result, comprising:

[0037] The first initialization result of the simulation storage point and the second initialization result of the access port are obtained;

[0038] A verification value is written to the simulation storage point;

[0039] If the value of the simulation storage point is the same as the first initialization result, it is determined that the write function is incorrect;

[0040] If the simulation storage point is different from the first initialization result, it is determined that the write function is correct.

[0041] The output result of the access port is read through the critical path;

[0042] If the output result is the same as the second initialization result, it is determined that the read function is incorrect;

[0043] If the output result is different from the second initialization result, it is determined that the read function is correct.

[0044] Secondly, the embodiment of the application also provides a simulation verification device of a memory, comprising:

[0045] An acquisition module is configured to acquire a simulation storage point of a critical path of a memory, wherein the critical path is the farthest path between the memory and an access port;

[0046] A verification module is configured to verify whether the read and write functions of the memory are correct;

[0047] The extraction module is configured to extract a timing parameter of the simulation memory point for simulation verification when the read-write function of the simulation memory point is correct, wherein the timing parameter is generated in the process of verifying the read-write function of the simulation memory point.

[0048] In an optional embodiment, the obtaining module comprises:

[0049] The first obtaining submodule is configured to obtain capacity information of the memory.

[0050] The first obtaining submodule is configured to obtain address information according to the capacity information.

[0051] The second obtaining submodule is configured to obtain the simulation memory point according to the address information.

[0052] In an optional embodiment, the first obtaining submodule comprises:

[0053] The first obtaining submodule is configured to obtain a word and a data multiplexing value of the capacity information.

[0054] The first judging unit is configured to judge whether the word is an integer power of 2.

[0055] The first obtaining unit is configured to obtain the address information according to a first address value and the data multiplexing value when the word is an integer power of 2, wherein the first address value is a power value of the word.

[0056] The second obtaining unit is configured to obtain the address information according to a second address value and the data multiplexing value when the word is not an integer power of 2, wherein the second address value is a power value of the word plus 1.

[0057] In an optional embodiment, the verification module comprises:

[0058] The third obtaining submodule is configured to initialize the simulation memory point and the access port to obtain an initialization result.

[0059] The first verification submodule is configured to verify the read-write function of the simulation memory point according to the initialization result.

[0060] In an optional embodiment, the third obtaining submodule comprises:

[0061] The second obtaining unit is configured to obtain a verification vector, wherein the verification vector comprises 0 and 1.

[0062] The first initialization unit is configured to initialize the access port to output 1 and initialize an initial value of the simulation memory point to 1 when the verification vector is 0.

[0063] The second initialization unit is configured to initialize the initial value of the simulation storage point as 0 and initialize the output of the access port as 0 when the verification vector is 1.

[0064] In an optional embodiment, the storage is a single-port storage, and the first initialization unit comprises:

[0065] The first write sub-unit is configured to write 1 to the storage through a non-critical path to make the output of the access port as 1, which is equivalent to initializing the output of the access port as 1 when a write operation is performed, wherein the non-critical path is a path other than the critical path.

[0066] The second write sub-unit is configured to initialize the simulation storage point as 1 through a simulation command, write 0 to the simulation storage point through the critical path, and make the output of the access port as 0.

[0067] The first read sub-unit is configured to read the corresponding storage point through the non-critical path, and read out the access port as 1, which is equivalent to initializing the access port as 1 when a read operation is performed.

[0068] The second read sub-unit is configured to read the simulation storage point through the critical path.

[0069] The second initialization unit comprises:

[0070] The third write sub-unit is configured to write 0 to the storage through the non-critical path to make the output of the access port as 0, which is equivalent to initializing the output of the access port as 0 when a write operation is performed.

[0071] The fourth write sub-unit is configured to initialize the simulation storage point as 0 through a simulation command, and then write 1 to the simulation storage point through the critical path to make the output of the access port as 1.

[0072] The third read sub-unit is configured to read the corresponding storage point through the non-critical path, and read out the access port as 0, which is equivalent to initializing the access port as 0 when a read operation is performed.

[0073] The fourth read sub-unit is configured to read the simulation storage point through the critical path.

[0074] In an optional embodiment, the first verification sub-module comprises:

[0075] The third acquisition unit is configured to acquire a first initialization result of the simulation storage point and a second initialization result of the access port.

[0076] The first write unit is configured to write a verification value to the simulation storage point.

[0077] The first determining unit determines that the write function is incorrect when the value of the simulation storage point is the same as the first initialization result.

[0078] The second determining unit determines that the write function is correct when the simulation storage point is different from the first initialization result.

[0079] The first reading unit reads the output result of the access port through the critical path.

[0080] The third determining unit determines that the read function is incorrect when the output result is the same as the second initialization result.

[0081] The fourth determining unit determines that the read function is correct when the output result is different from the second initialization result.

[0082] In a third aspect, an electronic device is also provided, and the electronic device comprises:

[0083] The memory is configured to store a computer program.

[0084] The processor is configured to execute the computer program to implement the steps of the method in any of the first aspect.

[0085] In a fourth aspect, a computer readable storage medium is also provided, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the method in any of the first aspect.

[0086] Compared with the prior art, the simulation verification method and device for the memory provided by the application have the following advantages:

[0087] The application verifies the read-write function of the simulation storage point, extracts the timing parameters of the simulation storage point, and performs simulation verification, so that the read-write function verification is correct and the accuracy of the timing parameters is ensured, the read-write function can be verified while the characteristic parameter simulation is performed, the application can be applied to the design of the storage compiler, and the workload of the simulation verification can be greatly reduced, and the design efficiency of the storage compiler is effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0088] In order to more clearly illustrate the technical solutions in the embodiments of the present specification or the prior art, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present specification, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0089] Figure 1 A flowchart of a simulation verification method for a memory provided by the embodiments of the present application is provided.

[0090] Figure 2 A layout schematic diagram of a dual-port SRAM provided for an embodiment of the present application;

[0091] Figure 3 A clock logic schematic diagram for verifying that access port B writes "0" to the simulation storage point, access port A reads "0" through the critical path, and access port B writes "0" function, and access port A reads "0" from the simulation storage point through the critical path, provided for an embodiment of the present application;

[0092] Figure 4 A clock logic schematic diagram for verifying that access port B writes "1" to the simulation storage point, access port A reads "1" through the critical path, and access port B writes "1" function, and access port A reads "1" from the simulation storage point through the critical path, provided for an embodiment of the present application;

[0093] Figure 5 A structure schematic diagram of a simulation verification device of a memory provided for an embodiment of the present application. DETAILED DESCRIPTION

[0094] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art belong to the scope of protection of the embodiments of the present application.

[0095] It can be understood that the simulation verification method of the embodiments of the present application can be applied to the simulation verification of various memories. The following will take SRAM (Static Random Access Memory) as an example to specifically describe how to apply the method of the embodiments of the present application to simulation verification to extract correct timing parameters.

[0096] Please refer to Figure 1 , Figure 1 A flowchart of a simulation verification method of a memory provided for an embodiment of the present application, comprising:

[0097] S11, obtaining a simulation storage point of a critical path of a memory, wherein the critical path is the farthest path between the memory and an access port.

[0098] Specifically, the simulation storage point is determined by the clock control and the storage position on the layout of the memory. Generally, the farthest path is the four corners of the storage array, but it is determined according to the layout and the port position. For a dual-port SRAM including an access port A and an access port B, the layout is as follows Figure 2As shown, the layout includes an L data path (or left data path) and an R data path (or right data path), the critical path of the L data path is the upper left corner of the left storage array, and the critical path of the R data path is the upper right corner of the right storage array, therefore, the simulation storage points include the storage point at the upper left corner of the A port path and the storage point at the upper right corner of the B port path. The storage point at the upper left corner can be operated through the A port or the B port, because the clock path of the A port to the storage point at the upper left corner is longer, therefore, the storage point at the upper left corner is the storage point corresponding to the critical path of the A port, and the storage point at the upper right corner is the storage point corresponding to the critical path of the B port. In the dual-port SRAM, there are two sets of clocks, the access port A reads and writes data to the storage point A through the clock and decoding A, and the access port B reads and writes data to the storage point B through the clock and decoding B. Of course, cross writing or reading can also be performed. Those skilled in the art can understand that the same storage point can be written through A or B, and can be read out through A, B or AB at the same time, and cannot be written into the same storage point at the same time.

[0099] In actual application, the memory is divided into different storage capacities, which causes the simulation storage point of the critical path to be unable to be quickly confirmed.

[0100] In a specific embodiment, the simulation storage point of the critical path of the memory is obtained, including:

[0101] Capacity information of the memory is obtained, address information is obtained according to the capacity information, and the simulation storage point is obtained according to the address information.

[0102] Specifically, the capacity information includes words, bits and data multiplexing values, the storage capacity is mainly determined by the word line and the bit line, and the data multiplexing values of the memory with the same capacity mainly include 4, 8 and 16. The data multiplexing value represents the number of columns of the storage unit of one data path, therefore, the address information of the simulation storage point can be obtained according to the capacity information.

[0103] The capacity information can be represented as SRAM MxN_mux, wherein M represents the word, N represents the bit, that is, the number of data paths, the first data path is the leftmost in the left data path, and the Nth data path is the rightmost in the right data path. When determining the critical path, it is necessary to determine the storage point corresponding to the critical path in which data path, and mux represents the word length, that is, the number of columns of the storage unit of each data path. The capacity of the MxN memory is M / mux, the number of rows of the storage unit is Nx mux, and the total number of columns of the storage unit is addr=ceil[log2(M)], the number of data paths iobits=N, and the number of rows wordline=M / mux.

[0104] The address information of the access port A key path storage point is composed of row number and column number, specifically including:

[0105] Row number: AA1[(addr-1):log2(mux)] = wordline-1 (binary),

[0106] Column number: column number in the first data path: AA2[(log2(mux)-1):0] = 0 (binary).

[0107] The address information of the access port B key path storage point is also composed of row number and column number, specifically including:

[0108] Row number: AB1[(addr-1):log2(mux)] = wordline-1 (binary),

[0109] Column number: column number in the Nth data path: AB2[(log2(mux)-1):0] = mux-1 (binary).

[0110] In a specific embodiment, the address information is obtained according to the capacity information, including:

[0111] Obtaining the word and data multiplexing value of the capacity information; judging whether the word is an integral power of 2;

[0112] If yes, obtaining the address information according to the first address value and the data multiplexing value, wherein the first address value is the power value of the word; if no, obtaining the address information according to the second address value and the data multiplexing value, wherein the second address value is the power value of the word plus 1.

[0113] Specifically, if M is an integral power of 2, i.e. M = 2 n , addr = n, taking the capacity information SRAM 512x14_mux8 as an example, M = 512 = 2 n , addr = ceil[log2(512)] = 9, wordline = 512 / 8 = 64.

[0114] Row number of the A key path corresponding storage point: AA1[8:3] = 111111 (binary of 63),

[0115] Column number of the A key path corresponding storage point in the first data path: AA2[2:0] = 000 (binary of 0).

[0116] The dual-port memory SRAM 512x14_mux8, the A port word line is from bottom to top 64, in turn indicates WLA<0>~WLA<63>, each data passage includes 8 columns of storage units, from left to right in turn indicates 0~7. The address information of storage point A is composed of row number and column number, namely 111111000, under the condition of address determination, each data passage selects an effective storage node, namely the leftmost column storage unit (0) in the uppermost row (WLA<63>) storage unit of the data passage, the memory has 14 data passages, from left to right in turn indicates 0~13, the leftmost side is the A port output of the first data passage and is indicated as QA<0>, the rightmost data passage A port output is indicated as QA<13>, and CLKA is the clock control signal of the A port of the dual-port memory. From the layout of the memory in the design, it can be known that CLKA to QA<0> is the farthest path of the A port of the memory.

[0117] The B key path corresponds to the row number of the storage point: AB1[8:3]=111111 (the binary of 63)

[0118] The B key path corresponds to the column number of the storage point in the 14th data passage: AB2[2:0]=111 (the binary of 7)

[0119] The dual-port memory SRAM 512x14_mux8, the B port word line is from bottom to top 64, in turn indicates WLB<0>~WLB<63>, each data passage includes 8 columns of storage units, from left to right in turn indicates 0~7. The address information of storage point B is composed of row number and column number, namely 111111111, under the condition of address determination, each data passage selects an effective storage node, namely the rightmost column storage unit (7) in the uppermost row (WLB<63>) storage unit of the data passage, the memory has 14 data passages, from left to right in turn indicates 0~13, the leftmost side data passage B port output is indicated as QB<0>, and the rightmost data passage B port output is indicated as QB<13>, and CLKB is the clock control signal of the B port of the dual-port memory. From the layout of the memory in the design, it can be known that CLKB to QB<13> is the farthest path of the B port of the memory.

[0120] If M is not an integer power of 2, namely 2 n <M<2 n +1, then addr=n+1, taking the capacity information SRAM 136x11_mux4 as an example, addr=ceil[log2(136)]=8, wordline=136 / 4=34.

[0121] A critical path corresponding to the number of rows of storage points: AA1 [7:2] = 100001 (binary of 33)

[0122] A critical path corresponding to the number of columns of storage points in the first data path: AA2 [1:0] = 00 (binary of 0)

[0123] The dual-port memory 136x11_mux4, the A port word line has a total of 34 from bottom to top, indicating WLA<0>~WLA<33> in turn, each data path includes four columns of storage units, from left to right, indicating 0~3. The address information of the storage point A is composed of the number of rows and columns, that is, 10000100. Under the condition of address determination, each data path selects an effective storage node, that is, the leftmost column of storage units (0) in the uppermost row (WLA<33>) of the storage unit. The memory has 11 data paths, from left to right, indicating 0~10. The A port output of the leftmost data path is represented as QA<0>, and the A port output of the rightmost data path is represented as QA<10>. CLKA is the clock control signal of the A port of the dual-port memory. According to the layout of the memory in the design, CLKA to QA<0> is the farthest path of the A port of the memory.

[0124] A critical path corresponding to the number of rows of storage points: AA1 [7:2] = 100001 (binary of 33)

[0125] A critical path corresponding to the number of columns of storage points in the first data path: AA2 [1:0] = 00 (binary of 0)

[0126] The dual-port memory 136x11_mux4, the A port word line has a total of 34 from bottom to top, indicating WLA<0>~WLA<33> in turn, each data path includes four columns of storage units, from left to right, indicating 0~3. The address information of the storage point A is composed of the number of rows and columns, that is, 10000100. Under the condition of address determination, each data path selects an effective storage node, that is, the leftmost column of storage units (0) in the uppermost row (WLA<33>) of the storage unit. The memory has 11 data paths, from left to right, indicating 0~10. The A port output of the leftmost data path is represented as QA<0>, and the A port output of the rightmost data path is represented as QA<10>. CLKA is the clock control signal of the A port of the dual-port memory. According to the layout of the memory in the design, CLKA to QA<0> is the farthest path of the A port of the memory.

[0127] After the simulation storage point is confirmed in the memory, step S12 is entered.

[0128] S12, verifying whether the read-write function of the memory is correct.

[0129] Specifically, the verification of the read-write function can be performed by writing verification data "0" and "1" to the simulation storage point, and then reading the verification data through the access port. If the read verification data is consistent, it indicates that the read-write function is correct; otherwise, it indicates that the read-write function is incorrect.

[0130] Further, if the access port is directly read, the read is the initial value of the access port, and the write verification data of the simulation storage point cannot be accurately read, which may cause errors in writing and reading.

[0131] In a specific embodiment, verifying whether the read-write function of the simulation storage point is correct comprises:

[0132] initializing the simulation storage point and the access port to obtain an initialization result; and verifying the read-write function of the simulation storage point according to the initialization result.

[0133] Specifically, after the simulation storage point and the access port are initialized, opposite verification data is written to the simulation storage point to ensure that the write operation is correctly performed, and the written verification data can be accurately read through the access port, so as to judge whether the read-write function of the simulation storage point is correct. The initialization of the simulation storage point and the access port before the corresponding writing and reading can ensure the correctness of the writing and reading. If the initialization is not performed and the writing or reading is directly performed, the initial value may be the same as the written or read value, and it is impossible to accurately judge whether the writing or reading is correct.

[0134] In an optional embodiment, initializing the simulation storage point and the access port comprises:

[0135] obtaining a verification vector, wherein the verification vector comprises 0 and 1; if the verification vector is 0, initializing the output of the access port to be 1 and the initial value of the simulation storage point to be 1; and if the verification vector is 1, initializing the initial value of the simulation storage point to be 0 and the output of the access port to be 0.

[0136] Specifically, the data in the storage is represented in binary 0 and 1. The verification vector 0 and 1 can be used to comprehensively verify in different ways. When the verification vector is 0, the output of the access port is initialized to be 1 and the initial value of the simulation storage point is initialized to be 1. When verifying the read-write function, the opposite verification data 0 can be written to see the change of the output of the access port. Similarly, when the verification vector is 1, the initial value of the simulation storage point and the access port are initialized, and then the opposite verification data 1 is written.

[0137] In an optional embodiment, the storage is a single-port storage, and initializing the output of the access port to be 1 and the initial value of the simulation storage point to be 1 comprises:

[0138] write 1 to the memory through the non-critical path, so that the access port outputs 1, which is equivalent to initializing the access port output to 1 in the write operation, wherein the non-critical path is a path other than the critical path; initialize the simulation storage point to 1 through the simulation command, and write 0 to the simulation storage point through the critical path, so that the access port outputs 0; read the corresponding storage point through the non-critical path, and the access port reads out 1, which is equivalent to initializing the access port to 1 in the read operation; read the simulation storage point through the critical path.

[0139] initialize the initial value of the simulation storage point to 0, and initialize the access port output to 0, including: write 0 through the non-critical path, so that the access port outputs 0, which is equivalent to initializing the access port output to 0 in the write operation; initialize the simulation storage point to 0 through the simulation command, and then write 1 to the simulation storage point through the critical path, so that the access port outputs 1; read the corresponding storage point through the non-critical path, and the access port reads out 0, which is equivalent to initializing the access port to 0 in the read operation; read the simulation storage point through the critical path.

[0140] Specifically, those skilled in the art can understand that one data path of the memory corresponds to a bit storage unit of 1, and the structure thereof includes a sensitive amplifier, a write driver, an output buffer (or Out buffer) and a column gating unit. The input and output of the bit storage unit of 1 are realized through the same input and output port. In the single-port memory, the non-critical path write operation of the access port is the same as the critical path, and the difference is only that the addresses are different, and the positions stored in the memory are different. The critical path writes the simulation storage point, and the non-critical path writes other storage points. The simulation storage point and the other storage points can be output through the access port. Write 1 to the memory through the non-critical path of the access port, so that the access port outputs 1, in order to initialize the access port; initialize the initial value of the simulation storage point to 1 through the simulation command, in order to initialize the simulation storage point, so that when 0 is written to the simulation storage point again, the change of the simulation storage point can be used to verify that the write 0 to the simulation storage point is successfully operated, and the change of the access port read through the critical path is used to verify that the read 0 operation is successful. Similarly, it is necessary to verify that the write 1 to the simulation storage point is successfully operated, write 0 to the memory through the non-critical path, so that the access port outputs 0, and initialize the initial value of the simulation storage point to 0 through the simulation command, so that 1 can be written to the storage point, that is, the change of the simulation storage point can be used to verify that the write 1 to the simulation storage point is successfully operated, and the change of the access port read through the critical path is used to verify that the read 1 operation is successful.

[0141] The person skilled in the art can understand that the initialization of the simulation storage point is realized by a forced statement of a simulation command, and the simulation storage point data is read out after a verification value is written, so that whether the write operation is correct is determined by the change of the simulation storage point. Since the correctness of the memory write function is uncertain, the initialization of the simulation storage point can be ensured to be successful by using the simulation forced statement.

[0142] In a specific embodiment, according to the initialization result, the read and write functions of the simulation storage point are verified, including:

[0143] The first initialization result of the simulation storage point and the second initialization result of the access port are obtained; a verification value is written to the simulation storage point; if the value of the simulation storage point is the same as the first initialization result, it is determined that the write function is incorrect; if the simulation storage point is different from the first initialization result, it is determined that the write function is correct. The output result of the access port is read through the critical path; if the output result is the same as the second initialization result, it is determined that the read function is incorrect; if the output result is different from the second initialization result, it is determined that the read function is correct.

[0144] Specifically, after the simulation storage point and the access port are initialized, the verification value is written to the simulation storage point through the critical path. Since the first initialization result is opposite to the verification value, whether the read and write functions are correct can be verified by the output result of the access port. The output result is the same as the second initialization result, that is, the output result has not changed, which indicates that the verification value has not been successfully written, and therefore the read and write functions are incorrect. Similarly, the output result has changed, which indicates that the verification value has been successfully written, and therefore the read and write functions are correct.

[0145] When the storage is a single-port storage, for the read "1" operation, in the first stage, 0 is written through the non-critical path to initialize the output port Q as 0, and 1 is written through the critical path; in the second stage, the non-critical path (the initialized output port Q) is read, and the critical path is read as "1", which indicates that the read and write "1" are correct. The initialization of the critical path storage point is realized by a forced statement of a simulation command. Similarly, for the read "0" operation, in the first stage, 1 is written through the non-critical path to initialize the output port Q as 1, and 0 is written through the critical path; in the second stage, the non-critical path (the initialized output port Q) is read, and the critical path is read as "0", which indicates that the read and write "0" are correct. The initialization of the critical path storage point is realized by a forced statement of a simulation command.

[0146] It should be noted that the method of the embodiment of the present application can also be applied to the read and write function verification of a dual-port SRAM. In the dual-port SRAM, the initialization includes the simulation storage point and the output port Q. The initialization of Q can be realized by writing to the non-simulation storage point, and the initialization of the simulation storage point is realized by a forced statement of a simulation command. The read 0 verification of the simulation storage point is realized by reading 0 of the simulation storage point through the access port A, which can be referred to in the description of the read 0 verification of the simulation storage point in the embodiment of the present application. Figure 3The first stage can write 1 through the input port DA on the rising edge of CLKA through a non-critical path, there are two rising edges of CLKA in the figure, the rising edge is a write through the access port A when the read-write control signal is low, and the rising edge is a read through the access port A when the read-write control signal is high; there is one rising edge of CLKA, which is a write through the access port B. First, write 1 through the input port DA, initialize the access end QA output to 1, QA is the read result of the access port A, and ensure that the next step of reading 0 through the clock CLKA control through the critical path can see the change of QA output. The second stage writes 0 through the B port to the storage point corresponding to the critical path of the A port, simulates the storage point function verification, and the initial value is 1. Since the access port A and the access port B correspond to a storage point at the same address in the dual-port SRAM, the verification value written through the access port B can also be read through the A port; the third stage reads through the critical path, that is, reads the value of the simulation storage point through the critical path of the access port A, and the QA output is 0, that is, the simulation storage point reads 0, proving that the write 0 operation is successful, and the write 0 verification of the simulation storage point is correct. It can be understood that in the process of verifying the write 0 of the simulation storage point, since it is written through the access port B, the write 0 function of the access port B is also verified at the same time. In the above process, the read timing parameters of the access port A and the write timing parameters of the access port B can be obtained.

[0147] Similarly, the read 1 verification of the simulation storage point is through the access port A to read 1 of the simulation storage point, which can be referred to in Figure 4 , there are also three operations, the first stage writes 1 through the access port B to the storage point corresponding to the critical path of the A port, simulates the write function verification of the simulation storage point, and the initial value is 0; the second stage writes 0 through the non-critical path of the access port A, initializes the QA output to 0, and ensures that the read 1 can see the output change; the third stage reads through the critical path of the access port A, and the QA output is 1, proving that the read 1 operation is successful, and the change of the simulation storage point proves that the write 1 verification is correct. The critical path or non-critical path of the simulation storage point is determined by the address information of the storage point.

[0148] It should be noted that, as for the dual-port SRAM, the access port A and the access port B correspond to the same storage unit, i.e., the same storage point, when the same address signal is used, and the same storage point can be written and read by the access port A; the access port A writes and the access port B reads; the access port B writes and the access port B reads; the access port B writes and the access port A reads; the same storage point can also be read by the access port A and the access port B at the same time, but a write operation cannot be performed on a storage point at the same time. The access port A and the access port B have independent clock control signals, read-write control signals, and address signals, and the storage point for reading and writing is determined by the read-write control signal WEN, the address signal, and the clock signal. When writing, the read-write control signal WEN = 0, and the output port Q is the value written at the current address; when reading, the read-write control signal WEN = 1, and the output port Q is the value read at the current address. Figure 3 and Figure 4 The address signal is not shown in Figure 3 For example, although the second stage writes the address of the storage point through the access port B, the critical path address of the access port A is the same, but it is not the critical path of B.

[0149] The access port B also has a critical path simulation storage point, and the read-write function thereof can also be verified by the above method. During verification, the access port A is written and the access port B is read, and after the read-write function is verified, step S13 is entered.

[0150] S13, if so, the timing parameters of the simulation storage point are extracted for simulation verification, wherein the timing parameters are generated during the process of verifying the read-write function of the simulation storage point.

[0151] Specifically, the timing parameter is the data transmission time length from the simulation storage point to the access port when the clock is valid. The related performance of the memory can be simulated and verified by the timing parameter, and the timing parameter is generated during the verification of the read-write function of the simulation storage point by the critical path. Those skilled in the art can understand that the timing is extracted for generating a lib file during simulation verification, and the memory generated by the storage compiler in the later stage can directly call the data file when applied to a digital flow.

[0152] The timing parameter extracts the read time of the critical path. During verification, the simulation storage point is written through the access port, and then the data of the simulation storage point is read through the critical path. The verification value written is consistent with the data of the output port Q, proving that the function is correct, and the critical path delay data is extracted. The change of the storage point can be used to determine whether the writing is successful, and the change of the data of the output port Q can be used to determine whether the reading is successful.

[0153] After the simulation of the timing parameter, it can be determined whether the data of the timing parameter is valid through the determination criteria in Table 1. Ten cases in Table 1 are determined, and the cases that meet the criteria are marked with a symbol, and the cases that do not meet the criteria are marked with a symbol. The data is correct, which indicates that the function is correct, and the timing parameter is extracted. If the result is inconsistent with the table, an error is reported, that is, the characteristic modeling and QA check are completed through large-scale characteristic verification.

[0154] Table 1:

[0155]

[0156] Those skilled in the art can understand that the rising edge is the change process from high level to low level, which can be 10% rising to 90%; the falling edge is the change process from low level to high level, which can be 90% falling to 10%; and the delay time has no change in the level value.

[0157] Based on the same inventive concept as the simulation verification method, the embodiment of the application also provides a simulation verification device of a memory, which refers to Figure 5 , comprising:

[0158] The acquisition module 501 is configured to acquire a simulation storage point of a critical path of a memory, wherein the critical path is the farthest path between the memory and an access port.

[0159] The verification module 502 is configured to verify whether the read-write function of the memory is correct.

[0160] The extraction module 503 is configured to extract a timing parameter of the simulation storage point for simulation verification when the read-write function of the simulation storage point is correct, wherein the timing parameter is generated in the process of verifying the read-write function of the simulation storage point.

[0161] In an optional embodiment, the acquisition module comprises:

[0162] The first acquisition submodule is configured to acquire capacity information of the memory.

[0163] The first obtaining submodule is configured to obtain address information according to the capacity information.

[0164] The second obtaining submodule is configured to obtain the simulation storage point according to the address information.

[0165] In an optional embodiment, the first obtaining submodule comprises:

[0166] The first acquisition unit is configured to acquire a word and data multiplexing value of the capacity information.

[0167] The first judgment unit is configured to determine whether the word is an integer power of 2.

[0168] a first obtaining unit, configured to obtain the address information according to a first address value and the data multiplexing value when the word is an integral power of 2, wherein the first address value is a power value of the word;

[0169] a second obtaining unit, configured to obtain the address information according to a second address value and the data multiplexing value when the word is not an integral power of 2, wherein the second address value is the power value of the word plus 1.

[0170] In an optional embodiment, the verification module comprises:

[0171] a third obtaining sub-module, configured to initialize the simulation storage point and the access port, and obtain an initialization result;

[0172] a first verification sub-module, configured to verify the read-write function of the simulation storage point according to the initialization result.

[0173] In an optional embodiment, the third obtaining sub-module comprises:

[0174] a second obtaining unit, configured to obtain a verification vector, wherein the verification vector comprises 0 and 1;

[0175] a first initialization unit, configured to initialize the access port output as 1 and initialize the initial value of the simulation storage point as 1 when the verification vector is 0;

[0176] a second initialization unit, configured to initialize the initial value of the simulation storage point as 0 and initialize the access port output as 0 when the verification vector is 1.

[0177] In an optional embodiment, the storage is a single-port storage, and the first initialization unit comprises:

[0178] a first writing sub-unit, configured to write 1 to the storage through a non-critical path to make the access port output as 1, which is equivalent to initializing the access port output as 1 in a write operation, wherein the non-critical path is a path other than the critical path;

[0179] a second writing sub-unit, configured to initialize the simulation storage point as 1 through a simulation command, and write 0 to the simulation storage point through the critical path to make the access port output as 0;

[0180] a first reading sub-unit, configured to read the corresponding storage point through the non-critical path, and read out the access port as 1, which is equivalent to initializing the access port as 1 in a read operation;

[0181] a second reading sub-unit, configured to read the simulation storage point through the critical path.

[0182] The second initialization unit comprises:

[0183] The third write sub-unit is configured to write 0 through the non-critical path, so that the output of the access port is 0, which is equivalent to initializing the output of the access port to 0 in a write operation;

[0184] The fourth write sub-unit is configured to initialize the simulation storage point to 0 through a simulation command, and then write 1 to the simulation storage point through the critical path, so that the output of the access port is 1;

[0185] The third read sub-unit is configured to read the corresponding storage point through the non-critical path, so that the access port reads 0, which is equivalent to initializing the access port to 0 in a read operation;

[0186] The fourth read sub-unit is configured to read the simulation storage point through the critical path.

[0187] In an optional embodiment, the first verification sub-module comprises:

[0188] The third acquisition unit is configured to acquire a first initialization result of the simulation storage point and a second initialization result of the access port;

[0189] The first write unit is configured to write a verification value to the simulation storage point;

[0190] The first determination unit is configured to determine that the write function is incorrect when the value of the simulation storage point is the same as the first initialization result;

[0191] The second determination unit is configured to determine that the write function is correct when the simulation storage point is different from the first initialization result;

[0192] The first read unit is configured to read an output result of the access port through the critical path;

[0193] The third determination unit is configured to determine that the read function is incorrect when the output result is the same as the second initialization result;

[0194] The fourth determination unit is configured to determine that the read function is correct when the output result is different from the second initialization result.

[0195] Based on the same inventive concept as the simulation verification method, embodiments of the present application also provide an electronic device, comprising:

[0196] A memory is configured to store a computer program;

[0197] A processor is configured to execute the computer program to implement the steps of any of the methods in the simulation verification method.

[0198] Based on the same inventive concept as the simulation verification method, the embodiments of the present application also provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of any of the methods in the simulation verification method.

[0199] The technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0200] 1. After verifying that the read-write function of the simulation storage point is correct, the timing parameters of the simulation storage point are extracted for simulation verification, which ensures the correctness of the read-write function verification and the accuracy of the timing parameters, can verify the read-write function while simulating the characterization parameters, greatly reduces the workload of simulation verification, and effectively improves the design efficiency of the storage compiler.

[0201] 2. The simulation verification of the storage is usually design iteration, and in the traditional simulation verification method, the characterization modeling only simulates the characterization parameters, and the read-write function is not considered. If the previous data extraction is incorrect, the function simulation needs to be returned for verification. According to the method of the embodiments of the present application, data is only extracted when the function is correct, so there is no error in data extraction. The simulation verification process can be effectively simplified, unnecessary iteration can be reduced, verification efficiency can be improved, and simulation verification time can be reduced.

[0202] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0203] The present application is described with reference to flowcharts and / or block diagrams according to the method, device (module, system), and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing devices to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices produce a machine that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The device that implements the functions specified in one flow or multiple flows and / or blocks Figure 1 The device that implements the functions specified in one flow or multiple flows and / or blocks

[0204] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the Figure 1 function specified in the flow or flows and / or blocks Figure 1 of the block or blocks.

[0205] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions that are executed on the computer or other programmable apparatus provide steps for implementing the Figure 1 function specified in the flow or flows and / or blocks Figure 1 of the block or blocks.

[0206] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such additional variations and modifications as fall within the scope of the application.

[0207] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A simulation verification method of a memory, characterized by, The method comprises the following steps: acquiring a simulation storage point of a memory critical path, wherein the critical path is the farthest path between the memory and an access port; verifying whether the read-write function of the memory is correct; if yes, extracting a timing parameter of the simulation storage point for simulation verification, wherein the timing parameter is generated in the process of verifying the read-write function of the simulation storage point; the step of verifying whether the read-write function of the memory is correct comprises: initializing the simulation storage point and the access port to obtain an initialization result; verifying the read-write function of the simulation storage point according to the initialization result; the step of initializing the simulation storage point and the access port comprises: acquiring a verification vector, wherein the verification vector comprises 0 and 1; if the verification vector is 0, initializing the access port to output 1 and initializing the initial value of the simulation storage point to 1; if the verification vector is 1, initializing the initial value of the simulation storage point to 0 and initializing the access port to output 0.

2. The simulation verification method of memory according to claim 1, wherein, the step of acquiring the simulation storage point of the memory critical path comprises: acquiring capacity information of the memory; obtaining address information according to the capacity information; obtaining the simulation storage point according to the address information.

3. The simulation verification method of memory according to claim 2, wherein, the step of obtaining address information according to the capacity information comprises: acquiring a word and a data multiplexing value of the capacity information; judging whether the word is an integer power of 2; if yes, obtaining the address information according to a first address value and the data multiplexing value, wherein the first address value is the power value of the word; if no, obtaining the address information according to a second address value and the data multiplexing value, wherein the second address value is the power value of the word plus 1.

4. The simulation verification method of memory according to claim 1, wherein, the memory is a single-port memory, and the step of initializing the access port to output 1 and initializing the initial value of the simulation storage point to 1 comprises: writing 1 to the memory through a non-critical path to make the access port output 1, which is equivalent to initializing the access port output to 1 in a write operation, wherein the non-critical path is a path other than the critical path; initializing the simulation storage point to 1 through a simulation command and then writing 0 to the simulation storage point through the critical path to make the access port output 0; reading the corresponding storage point through the non-critical path, and the access port reads out 1, which is equivalent to initializing the access port to 1 in a read operation; the critical path reads the simulation storage point; the step of initializing the initial value of the simulation storage point to 0 and initializing the access port to output 0 comprises: writing 0 through the non-critical path to make the access port output 0, which is equivalent to initializing the access port output to 0 in a write operation; initializing the simulation storage point to 0 through a simulation command and then writing 1 to the simulation storage point through the critical path to make the access port output 1; reading the corresponding storage point through the non-critical path, and the access port reads out 0, which is equivalent to initializing the access port to 0 in a read operation; reading the simulation storage point through the critical path.

5. The simulation verification method of memory according to claim 1, wherein, the step of verifying the read-write function of the simulation storage point according to the initialization result comprises: acquiring a first initialization result of the simulation storage point and a second initialization result of the access port; writing a verification value to the simulation storage point; if the value of the simulation storage point is the same as the first initialization result, determining that the write function is incorrect; if the value of the simulation storage point is different from the first initialization result, determining that the write function is correct; reading an output result of the access port through the critical path; if the output result is the same as the second initialization result, determining that the read function is incorrect; if the output result is different from the second initialization result, determining that the read function is correct.

6. A memory emulation verification apparatus, comprising: The method comprises the steps of: acquiring a simulation storage point of a memory critical path, wherein the critical path is the farthest path between the memory and an access port; verifying whether the read and write functions of the memory are correct; extracting a timing parameter of the simulation storage point when the read and write functions of the simulation storage point are correct, for simulation verification, wherein the timing parameter is generated in the process of verifying the read and write functions of the simulation storage point; the step of verifying whether the read and write functions of the memory are correct comprises the steps of: initializing the simulation storage point and the access port to obtain an initialization result; verifying the read and write functions of the simulation storage point according to the initialization result; the step of initializing the simulation storage point and the access port comprises the steps of: acquiring a verification vector, wherein the verification vector comprises 0 and 1; if the verification vector is 0, initializing the access port output as 1 and initializing the initial value of the simulation storage point as 1; if the verification vector is 1, initializing the initial value of the simulation storage point as 0 and initializing the access port output as 0.

7. An electronic device, comprising: The method comprises the steps of: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method according to any one of claims 1 to 5.

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