Read voltage level correction method, memory storage device and control circuit unit

Abstract

This invention provides a read voltage level correction method, a memory storage device, and a memory control circuit unit. The method includes: using a first read voltage level as a starting read voltage level to perform a first data read operation on a first physical unit among a plurality of physical units to obtain a second read voltage level used to successfully read the first physical unit; recording correlation information between the first read voltage level and the second read voltage level in a transient lookup table; and performing a second data read operation based on the correlation information recorded in the read voltage level tracking table and the transient lookup table.

Description

Technical Field

[0001] This invention relates to a read voltage level tracking method, and more particularly to a read voltage level correction method for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit. Background Technology

[0002] The rapid growth of portable electronic devices such as laptops and mobile phones in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory (e.g., flash memory) is ideally suited for integration into these portable electronic devices due to its characteristics such as data non-volatility, low power consumption, small size, no mechanical structure, and high read / write speeds. Solid-state drives (SSDs) are a type of memory storage device that uses flash memory modules as its storage medium. Therefore, the flash memory industry has become a very popular segment of the electronics industry in recent years.

[0003] When reading data, the memory storage device reads data according to a preset read voltage level. However, as the operation of the memory modules and environmental conditions vary, the critical voltage of the memory modules may shift. In this case, reading data using the preset read voltage level may result in too many error bits. Generally, the memory storage device determines the optimal read voltage level by performing an optimal read voltage level tracking operation.

[0004] In optimal read voltage level tracking, the memory storage device continuously monitors and records the optimal read voltage level of the memory module. However, the actual operating and environmental conditions (e.g., temperature) at the time the memory storage device reads data may differ from the conditions when the optimal read voltage level was last monitored. Alternatively, the memory storage device may be unable to continuously monitor the optimal read voltage level due to a power outage or entering a low-power mode, resulting in a significant interval between the actual data read and the previous monitoring time. As operating and environmental conditions change and time passes, the optimal read voltage level of the memory module may shift again, rendering the previously identified optimal read voltage level inaccurate. Directly using the previously monitored results may actually lead to degraded read operation performance. Summary of the Invention

[0005] This invention provides a reading voltage level correction method, a memory storage device, and a memory control circuit unit, which can reduce the time spent searching for a physical unit to successfully read the voltage level, thereby increasing the overall efficiency of data reading operations.

[0006] This invention provides a read voltage level correction method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of physical cells. The method includes: performing a first data read operation on a first physical cell among the plurality of physical cells using a first read voltage level as a starting read voltage level to obtain a second read voltage level used to successfully read the first physical cell; recording correlation information between the first read voltage level and the second read voltage level in a transient lookup table; and performing a second data read operation based on a read voltage level tracking table and the correlation information recorded in the transient lookup table. The read voltage level tracking table records multiple optimal read voltage levels for the plurality of physical cells.

[0007] In one embodiment of the present invention, the step of using the first read voltage level as the starting read voltage level to perform the first data read operation on the first entity unit among the plurality of entity units further includes: obtaining a first optimal read voltage level corresponding to the first entity unit from the read voltage level tracking table as the first read voltage level.

[0008] In one embodiment of the present invention, the step of using the first read voltage level as the starting read voltage level to perform the first data read operation on the first entity unit among the plurality of entity units further includes: determining the first read voltage level based on the association information recorded in the read voltage level tracking table and the transient lookup table.

[0009] In one embodiment of the present invention, the above method includes performing a decoding operation when performing the first data reading operation on the first entity unit among the plurality of entity units using the first read voltage level as the starting read voltage level, or when performing the second data reading operation according to the association information recorded in the read voltage level tracking table and the transient lookup table.

[0010] In one embodiment of the present invention, the step of recording the correlation information between the first read voltage level and the second read voltage level in the transient lookup table includes: counting the number of times the first read voltage level and the second read voltage level are correlated to generate a count value; and recording the count value in the transient lookup table.

[0011] In one embodiment of the present invention, the step of performing the second data reading operation based on the associated information recorded in the read voltage level tracking table and the transient lookup table includes: when the second data reading operation indicates reading data of the second entity unit among the plurality of entity units, obtaining the second optimal read voltage level of the second entity unit from the read voltage level tracking table; and searching the transient lookup table according to the second optimal read voltage level or the index value corresponding to the second optimal read voltage level, so as to sequentially obtain the second read voltage level corresponding to the count value in descending order of the plurality of count values ​​as the starting read voltage level for performing the second data reading operation.

[0012] In one embodiment of the present invention, the method further includes: updating the read voltage level tracking table according to the association information recorded in the transient lookup table; and clearing the transient lookup table after updating the read voltage level tracking table.

[0013] This invention provides a memory storage device, including a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to a host system. The rewritable non-volatile memory module includes multiple physical units. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to perform a first data read operation on a first physical unit among the multiple physical units using a first read voltage level as a starting read voltage level, to obtain a second read voltage level used to successfully read the first physical unit. The memory control circuit unit is further configured to record correlation information between the first read voltage level and the second read voltage level in a transient lookup table. Furthermore, the memory control circuit unit is further configured to perform a second data read operation based on the correlation information recorded in the read voltage level tracking table and the transient lookup table. The read voltage level tracking table records multiple optimal read voltage levels for the multiple physical units.

[0014] In one embodiment of the present invention, the memory control circuit unit is further configured to obtain a first optimal read voltage level corresponding to the first physical unit from the read voltage level tracking table as the first read voltage level.

[0015] In one embodiment of the present invention, the memory control circuit unit is further configured to determine the first read voltage level based on the associated information recorded in the read voltage level tracking table and the transient lookup table.

[0016] In one embodiment of the present invention, the memory control circuit unit is further configured to perform a decoding operation when performing the first data read operation on the first entity unit among the plurality of entity units using the first read voltage level as the starting read voltage level, or when performing the second data read operation according to the association information recorded in the read voltage level tracking table and the transient lookup table.

[0017] In one embodiment of the present invention, in the operation of recording the correlation information between the first read voltage level and the second read voltage level in the transient lookup table, the memory control circuit unit is further configured to count the number of times the correlation exists between the first read voltage level and the second read voltage level to generate a count value. Furthermore, the memory control circuit unit is further configured to record the count value in the transient lookup table.

[0018] In one embodiment of the present invention, in the operation of performing the second data read operation based on the associated information recorded in the read voltage level tracking table and the transient lookup table, the memory control circuit unit is further configured to obtain a second optimal read voltage level of the second entity unit from the read voltage level tracking table when the second data read operation indicates reading data of the second entity unit among the plurality of entity units. Furthermore, the memory control circuit unit is further configured to search the transient lookup table based on the second optimal read voltage level or the index value corresponding to the second optimal read voltage level, and sequentially obtain the second read voltage level corresponding to the count value in descending order of the plurality of count values ​​as the starting read voltage level for performing the second data read operation.

[0019] In one embodiment of the present invention, the memory control circuit unit is further configured to update the read voltage level tracking table according to the association information recorded in the transient lookup table. Furthermore, the memory control circuit unit is further configured to clear the transient lookup table after updating the read voltage level tracking table.

[0020] This invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module comprising multiple physical units. The memory control circuit unit includes a host interface, a memory interface, an error checking and correction circuit, and a memory management circuit. The host interface is coupled to a host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface, the memory interface, and the error checking and correction circuit. The memory management circuit is used to perform a first data read operation on a first physical unit among the multiple physical units using a first read voltage level as a starting read voltage level, to obtain a second read voltage level used to successfully read the first physical unit. The memory management circuit is further used to record the correlation information between the first read voltage level and the second read voltage level in a transient lookup table. Furthermore, the memory management circuit is further used to perform a second data read operation based on the correlation information recorded in the read voltage level tracking table and the transient lookup table. The read voltage level tracking table records multiple optimal read voltage levels for the multiple physical units.

[0021] In one embodiment of the present invention, the memory management circuit is further configured to obtain a first optimal read voltage level corresponding to the first physical cell from the read voltage level tracking table as the first read voltage level.

[0022] In one embodiment of the present invention, the memory management circuit is further configured to determine the first read voltage level based on the associated information recorded in the read voltage level tracking table and the transient lookup table.

[0023] In one embodiment of the present invention, the memory management circuit is further configured to perform a decoding operation when performing the first read operation on the first entity unit among the plurality of entity units using the first read voltage level as the starting read voltage level, or when performing the second data read operation according to the association information recorded in the read voltage level tracking table and the transient lookup table.

[0024] In one embodiment of the present invention, in the operation of recording the correlation information between the first read voltage level and the second read voltage level in the transient lookup table, the memory management circuit is further configured to count the number of times the first read voltage level and the second read voltage level are correlated to generate a count value. Furthermore, the memory management circuit is further configured to record the count value in the transient lookup table.

[0025] In one embodiment of the present invention, in the operation of performing the second data read operation based on the associated information recorded in the read voltage level tracking table and the transient lookup table, the memory management circuit is further configured to obtain a second optimal read voltage level of the second entity unit from the read voltage level tracking table when the second data read operation indicates reading data of the second entity unit among the plurality of entity units. Furthermore, the memory management circuit is further configured to search the transient lookup table based on the second optimal read voltage level or the index value corresponding to the second optimal read voltage level, and sequentially obtain the second read voltage level corresponding to the count value in descending order of the plurality of count values ​​as the starting read voltage level for performing the second data read operation.

[0026] In one embodiment of the present invention, the memory management circuit is further configured to update the read voltage level tracking table according to the association information recorded in the transient lookup table. Furthermore, the memory management circuit is further configured to clear the transient lookup table after updating the read voltage level tracking table.

[0027] Based on the above, the read voltage level correction method, memory storage device, and memory control circuit unit provided in this embodiment of the invention can record correlation information in a transient lookup table and fine-tune the previously monitored optimal read voltage level according to the correlation information recorded in the transient lookup table. Compared to the general practice of only using the previously monitored optimal read voltage level to perform optimal read voltage level search and decoding operations, this invention can reduce the time spent searching for a successfully read physical unit's read voltage level, thereby increasing the overall efficiency of the data read operation.

[0028] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of a host system, memory storage device, and I / O device according to another exemplary embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention;

[0032] Figure 4 This is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0033] Figure 5 This is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0034] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0035] Figure 7 This is a flowchart illustrating a reading voltage level correction method according to an exemplary embodiment of the present invention;

[0036] Figure 8 This is a flowchart illustrating an exemplary embodiment of the present invention of a method for updating the optimal read voltage level. Detailed Implementation

[0037] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0038] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). Typically, a memory storage device is used in conjunction with a host system to enable the host system to write data to or read data from the memory storage device.

[0039] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to another exemplary embodiment of the present invention.

[0040] Please refer to Figure 1 and Figure 2 The host system 11 generally includes a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 are all coupled to the system bus 110.

[0041] In this exemplary embodiment, the host system 11 is coupled to the memory storage device 10 via a data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 is coupled to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0042] In this exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means. The memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near-field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to various I / O devices such as the Global Positioning System (GPS) module 205, network interface card 206, wireless transmission device 207, keyboard 208, screen 209, and speaker 210 via the system bus 110. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 via the wireless transmission device 207.

[0043] In one exemplary embodiment, the host system mentioned is any system that can substantially cooperate with a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, however… Figure 3 This is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Please refer to... Figure 3In another exemplary embodiment, the host system 31 can also be a system such as a digital camera, camcorder, communication device, audio player, video player, or tablet computer, while the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0044] Figure 4 This is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 4 The memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable non-volatile memory module 406.

[0045] The connection interface unit 402 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 402. In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Peripheral Component Interconnect Express (PCI Express) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 402 may be packaged in a chip with the memory control circuit unit 404, or the connection interface unit 402 may be disposed outside a chip containing the memory control circuit unit 404.

[0046] The memory control circuit unit 404 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11.

[0047] The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable non-volatile memory module 406 can be a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0048] Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0049] In this exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND flash memory, the data write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0050] In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In this exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of storage units that are erased. For example, the physical erase unit is a physical block.

[0051] Figure 5 This is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Please refer to... Figure 5 The memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

[0052] The memory management circuit 502 controls the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 502 is equivalent to the description of the operation of the memory control circuit unit 404.

[0053] In this exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware format. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0054] In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in code form in a specific area of ​​the rewritable non-volatile memory module 406 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 502 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 406 into the random access memory of the memory management circuit 502. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0055] Furthermore, in another exemplary embodiment, the control instructions for the memory management circuit 502 can also be implemented in hardware. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 406. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erasure circuit issues an erasure command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit processes data to be written to the rewritable non-volatile memory module 406 and data to be read from the rewritable non-volatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 502 may also issue other types of command sequences to the rewritable non-volatile memory module 406 to instruct it to perform corresponding operations.

[0056] The host interface 504 is coupled to the memory management circuitry 502. The memory management circuitry 502 can communicate with the host system 11 through the host interface 504. The host interface 504 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuitry 502 through the host interface 504. Furthermore, the memory management circuitry 502 can transmit data to the host system 11 through the host interface 504. In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it should be understood that the invention is not limited thereto, and the host interface 504 can also be compatible with PATA, IEEE 1394, PCI Express, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0057] Memory interface 506 is coupled to memory management circuitry 502 and used to access rewritable non-volatile memory module 406. That is, data to be written to rewritable non-volatile memory module 406 is converted by memory interface 506 into a format acceptable to rewritable non-volatile memory module 406. Specifically, when memory management circuitry 502 needs to access rewritable non-volatile memory module 406, memory interface 506 transmits a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by memory management circuitry 502 and transmitted to rewritable non-volatile memory module 406 via memory interface 506. These instruction sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or codes. For example, the read instruction sequence may include information such as the identification code to be read and the memory address.

[0058] In one exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.

[0059] Error checking and correction circuit 508 is coupled to memory management circuit 502 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 502 receives a write command from host system 11, error checking and correction circuit 508 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 406. Subsequently, when memory management circuit 502 reads data from rewritable non-volatile memory module 406, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 508 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0060] Buffer memory 510 is coupled to memory management circuitry 502 and is used to temporarily store data and instructions from host system 11 or data from rewritable non-volatile memory module 406. Buffer memory 510 may be static random access memory (SRAM) or dynamic random access memory (DRAM), etc., and the present invention is not limited thereto. Power management circuitry 512 is coupled to memory management circuitry 502 and is used to control the power supply to memory storage device 10.

[0061] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 406 is also referred to as a flash memory module, and the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module. In one exemplary embodiment, Figure 5 The memory management circuit 502 is also known as the flash memory management circuit.

[0062] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 6 The memory management circuit 502 can logically group the physical cells 610(0) to 610(B) of the rewritable non-volatile memory module 406 into storage area 601 and idle area 602. Physical cells 610(0) to 610(A) in storage area 601 and physical cells 610(A+1) to 610(B) in idle area 602 are used to store data from host system 11. Specifically, physical cells in storage area 601 are considered to be physical cells with stored data, while physical cells in idle area 602 are used to replace physical cells in storage area 601. That is, when a write command and data to be written are received from host system 11, memory management circuit 502 will use physical cells extracted from idle area 602 to write data, replacing physical cells in storage area 601.

[0063] In this exemplary embodiment, each entity cell refers to an entity erase unit. However, in another exemplary embodiment, an entity cell may also refer to an entity address, an entity programmable unit, or a combination of multiple consecutive or non-consecutive entity addresses. Memory management circuitry 502 configures logic cells 612(0) to 612(C) to map entity cells 610(0) to 610(A) in memory area 601. In this exemplary embodiment, each logic cell refers to a logic address. However, in another exemplary embodiment, a logic cell may also refer to a logic programmable unit, a logic erase unit, or a combination of multiple consecutive or non-consecutive logic addresses. Furthermore, each of logic cells 612(0) to 612(C) may be mapped to one or more entity cells.

[0064] The memory management circuit 502 can record the mapping relationship between logical units and physical units (also known as logical-physical address mapping relationship) in at least one logical-physical address mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access operations for the memory storage device 10 according to this logical-physical address mapping table.

[0065] In one exemplary embodiment, the memory storage device 10 supports error correction, and data is first encoded before being stored in the rewritable non-volatile memory module 406. When reading a physical cell, the memory management circuit 502 first selects a preset read voltage level to read the memory cells included in these physical cells to obtain the verification bits (bit 0 or 1) of these memory cells. The error checking and correction circuit 508 performs a decoding operation based on the verification bits of these memory cells to generate multiple decoded bits. These decoded bits can form a decoded data (i.e., a codeword). In one exemplary embodiment, the memory management circuit 502 determines whether the data is a valid codeword based on the checksum corresponding to the data. If the data is not a valid codeword, the memory management circuit 502 determines that the decoding has failed.

[0066] If decoding fails, it indicates that these memory cells contain irreparable error bits. In this exemplary embodiment, the memory management circuit 502 will reacquire another read voltage level adjacent to the previous read voltage level to read these memory cells, thereby reacquiring the verification bits of the memory cells. The memory management circuit 502 will then perform the aforementioned decoding operation based on the reacquired verification bits to obtain another set of data consisting of multiple decoded bits. If decoding fails again, the memory management circuit 502 will reacquire another read voltage level to read these memory cells. In one exemplary embodiment, the memory management circuit 502 may reacquire read voltage levels to attempt decoding until decoding is successful or the number of reacquiring read voltage levels exceeds a preset number. In other words, when there are irreparable error bits, by reacquiring read voltage levels, the verification bits of some memory cells may be changed, potentially altering the decoding result of the decoding operation.

[0067] Through the aforementioned rereading mechanism, the optimal read voltage level for the physical cell can be found. This optimal read voltage level can be used to read the data from the physical cell and successfully decode it. The operation of finding the optimal read voltage level for the physical cell can be called an "optimal read level search" operation. This can be performed when the rewritable non-volatile memory module 406 is idle (or in background mode), after a failure in hard-bit mode decoding, or during hard-bit mode decoding (e.g., at the read voltage with the fewest error bits). The determined optimal read voltage level can be used for subsequent reads of the rewritable non-volatile memory module 406.

[0068] It should be noted that when attempting to read physical cells in the rewritable non-volatile memory module 406 based on a read command received from the host system 11 or as needed in background mode, the memory management circuit 502 first uses a preset read voltage level to read the memory cells included in the physical cell. Furthermore, the memory management circuit 502 can use the data obtained using this preset read voltage level to perform hard-bit mode decoding, soft-bit mode decoding, or decoding using encoded data generated by multi-frame encoding; the present invention is not limited to these decoding methods. The detailed execution process of hard-bit mode decoding, soft-bit mode decoding, or multi-frame encoding decoding can be known from existing technology and will not be elaborated here. If decoding using hard-bit mode decoding or soft-bit mode decoding fails, the memory management circuit 502 can obtain another read voltage level adjacent to the preset read voltage level to read the memory cells included in the physical cell, thereby re-obtaining the data and performing decoding. If decoding is successful, it indicates that the current read voltage level can be used to read the data of the physical cell and that decoding has been successful.

[0069] In other words, the memory management circuit 502 can use a starting read voltage level (e.g., a first read voltage level) to perform an optimal read voltage level search operation and various decoding operations (e.g., hard-bit mode decoding and soft-bit mode decoding) during data read operations, and can obtain a read voltage level (also referred to as a second read voltage level) that can be used to read the data of the physical cell and successfully decode it based on the results of the above operations. In other words, the memory management circuit 502 can obtain a second read voltage level used to successfully read the physical cell through the above operations.

[0070] In this exemplary embodiment, the memory management circuit 502 may use a first read voltage level as the starting read voltage level to perform a data read operation on a first physical unit among the plurality of physical units, in order to obtain a second read voltage level used to successfully read this first physical unit. For example, the memory management circuit 502 may perform a decoding operation during the read operation to obtain the aforementioned second read voltage level, and the present invention is not limited thereto.

[0071] In this exemplary embodiment, the memory management circuit 502 records the correlation information between the first read voltage level and the second read voltage level in a transient lookup table. For example, this correlation information includes a count of the number of times the first read voltage level and the second read voltage level are correlated. Specifically, the memory management circuit 502 can count the number of times the first read voltage level and the second read voltage level are correlated to generate a count value, and record the count value in the transient lookup table. For example, Table 1 below is a transient lookup table in an exemplary embodiment, which records the correlation information between the first read voltage level and the second read voltage level.

[0072] Table 1

[0073] Read voltage level a1 Read voltage level a2 Read voltage level b1 1 0 Read voltage level b2 0 0

[0074] In Table 1, read voltage level a1 and read voltage level a2 represent the first read voltage level, and read voltage level b1 and read voltage level b2 represent the second read voltage level. According to Table 1, after the memory management circuit 502 uses read voltage level a1 as the starting read voltage level to perform a data read operation on the physical unit, it obtains the read voltage level b1 used to successfully read this physical unit. In this exemplary embodiment, the memory management circuit 502 counts the number of times there is a correlation between read voltage level a1 and read voltage level b2, generating a count value. For example, the count value recorded in the column corresponding to read voltage level a1 and read voltage level b1 in Table 1 is 1. This indicates that there is a correlation between read voltage level a1 and read voltage level b1 once. However, Table 1 is only an example, and the specific records can be adjusted according to practical needs.

[0075] In one exemplary embodiment, it is assumed that the rewritable non-volatile memory module 406 is an MLC NAND flash memory module. When the physical cells included in the MLC NAND flash memory module store data, each physical cell corresponds to three threshold voltages. Specifically, each memory cell of the MLC NAND flash memory module can store two cells, and the physical programmed cells on the same word line can be classified into at least lower physical programmed cells and upper physical programmed cells. In this exemplary embodiment, the lower physical programmed cell corresponds to one of the three threshold voltages, and the upper physical programmed cell corresponds to two of the three threshold voltages. Therefore, when the rewritable non-volatile memory module 406 is an MLC NAND flash memory module, the memory management circuit 502 records three read voltage levels for each physical cell; these read voltage levels can be referred to as a "read voltage level group". In other words, when the physical programmable unit read by the memory management circuit 502 is the upper physical programmable unit, the first read voltage level, which serves as the starting read voltage level, may include multiple read voltage levels, and the second read voltage level obtained after performing the data read operation may include multiple read voltage levels. It is worth noting that the number of read voltage levels included in the first and second read voltage levels may vary depending on the type of the rewritable non-volatile memory module 406, and this invention is not limited thereto.

[0076] In this exemplary embodiment, the memory management circuit 502 can save storage space by assigning index values ​​to entity units with the same read voltage level group when recording the read voltage level group (e.g., optimal read voltage level group) for each entity unit. Specifically, the memory management circuit 502 can establish an entity unit index lookup table and an index lookup table, and can establish separate index lookup tables for entity programmable units belonging to different valid bits of the storage unit. For example, Table 2 below is an example of an entity unit index lookup table in an exemplary embodiment, which is used to record the correspondence between entity units and index values. Table 3 below is an example of an index lookup table in an exemplary embodiment, which is used to record the correspondence between index values ​​and the read voltage level of the upper entity programmable unit. Table 4 below is an example of an index lookup table in an exemplary embodiment, which is used to record the correspondence between index values ​​and the read voltage level of the lower entity programmable unit.

[0077] Table 2

[0078] Entity unit Index value 610(0) RRT1 610(1) RRT2 610(2) RRT3 610(3) RRT4 610(4) RRT3

[0079] Table 3

[0080] Index value Read voltage level c1 Read voltage level c3 RRT1 14V 23V RRT2 11V 21V RRT3 -2V 4V RRT4 -9V -6V

[0081] Table 4

[0082] Index value Read voltage level c2 RRT1 5V RRT2 10V RRT3 -6V RRT4 -9V

[0083] Specifically, the memory management circuit 502 can assign an index value RRT1 to the physical unit 610(0) when recording the read voltage level group of the physical unit 610(0). The memory management circuit 502 records the index value RRT1 corresponding to the physical unit 610(0) in the physical unit index lookup table (such as the physical unit 610(0) and the corresponding index value RRT1 shown in Table 2), records the read voltage levels c1 and c3 of the upper physical programmable unit of the physical unit 610(0) in the index lookup table associated with the upper physical programmable unit (such as the index value RRT1 and the corresponding read voltage levels 14V and 23V shown in Table 3), and records the read voltage level c2 of the lower physical programmable unit in the index lookup table associated with the lower physical programmable unit (such as the index value RRT1 and the corresponding read voltage level 5V shown in Table 4). The recording method of other physical units and their read voltage level groups in Table 2 can be referred to the above, and will not be repeated here.

[0084] According to Table 2, the index value corresponding to entity unit 610(0) is RRT1. The memory management circuit 502 inputs this index value RRT1 into Table 3 when reading the upper entity programming unit of entity unit 610(0), resulting in a read voltage level c1 of 14V and a read voltage level c3 of 23V. Furthermore, the memory management circuit 502 inputs this index value RRT1 into Table 4 when reading the lower entity programming unit of entity unit 610(0), resulting in a read voltage level c2 of 5V. The optimal read voltage levels for other entity units can be found in the same way, and will not be repeated here.

[0085] It is worth noting that, according to Table 2, the index value corresponding to entity unit 610(4) is RRT3. This indicates that entity unit 610(4) and entity unit 610(2) have the same read voltage level group, that is, multiple entity units can correspond to the same index value. By assigning index values ​​to entity units with the same read voltage level group, storage space can be saved.

[0086] In one exemplary embodiment, it is assumed that the rewritable non-volatile memory module 406 is a TLC NAND flash memory module. When the physical cells included in the TLC NAND flash memory module store data, each physical cell corresponds to seven threshold voltages. Specifically, each memory cell of the TLC NAND flash memory module can store 3 bits, and the physical programmed cells on the same word line can be classified into at least lower physical programmed cells, middle physical programmed cells, and upper physical programmed cells. In this exemplary embodiment, the lower physical programmed cell corresponds to two of the seven threshold voltages, the middle physical programmed cell corresponds to three of the seven threshold voltages, and the upper physical programmed cell corresponds to two of the seven threshold voltages. Therefore, when the rewritable non-volatile memory module 406 is a TLC NAND flash memory module, the memory management circuit 502 records seven read voltage levels for each physical cell.

[0087] For example, Table 5 below is an example of an entity unit index lookup table in an exemplary embodiment, used to record the correspondence between entity units and index values. Table 6 below is an example of an index lookup table in an exemplary embodiment, used to record the correspondence between index values ​​and the read voltage level of the upper entity programmable unit. Table 7 below is an example of an index lookup table in an exemplary embodiment, used to record the correspondence between index values ​​and the read voltage level of the middle entity programmable unit. Table 8 below is an example of an index lookup table in an exemplary embodiment, used to record the correspondence between index values ​​and the read voltage level of the lower entity programmable unit.

[0088] Table 5

[0089] Entity unit Index value 610(0) RRT1 610(1) RRT2 610(2) RRT3 610(3) RRT4

[0090] Table 6

[0091] Index value Read voltage level c1 Read voltage level c5 RRT1 6V 12V RRT2 15V 18V RRT3 -2V 7V RRT4 -5V -4V

[0092] Table 7

[0093] Index value Read voltage level c2 Read voltage level c4 Read voltage level c6 RRT1 9V 11V 13V RRT2 16V 21V 27V RRT3 1V 6V 10V RRT4 -1V 6V 12V

[0094] Table 8

[0095] Index value Read voltage level c3 Read voltage level c7 RRT1 11V 18V RRT2 10V 16V RRT3 -4V -1V RRT4 -8V -4V

[0096] Specifically, the memory management circuit 502 can assign the index value RRT1 to the physical unit 610(0) when recording the read voltage level group of the physical unit 610(0). The memory management circuit 502 records the index value RRT1 corresponding to the physical unit 610(0) in the physical unit index lookup table (as shown in Table 5, where physical unit 610(0) and its corresponding index value RRT1 are displayed). It also records the read voltage levels c1 and c5 of the upper physical programmable unit of physical unit 610(0) in the index lookup table associated with the upper physical programmable unit (as shown in Table 6, where index value RRT1 and its corresponding 6V and 12V are displayed). Furthermore, it records the read voltage levels c2, c4, and c6 of the middle physical programmable unit in the index lookup table associated with the middle physical programmable unit (as shown in Table 7, where index value RRT1 and its corresponding 9V, 11V, and 13V are displayed). Finally, it records the read voltage levels c3 and c7 of the lower physical programmable unit in the index lookup table associated with the lower physical programmable unit (as shown in Table 8, where index value RRT1 and its corresponding 11V and 18V are displayed). The recording method for other physical units and their read voltage level groups in Table 5 can be referred to the above, and will not be repeated here.

[0097] In this exemplary embodiment, the memory management circuit 502 can record the association information between a first index value corresponding to a first read voltage level and a second index value corresponding to a second read voltage level in a transient lookup table. This association information includes a count of the number of associations between the first index value and the second index value. Specifically, the memory management circuit 502 can count the number of times there is an association between the first index value and the second index value to generate a count value, and record the count value in the transient lookup table. For example, Table 9 below is a transient lookup table in an exemplary embodiment, which records the association information between the first index value and the second index value.

[0098] Table 9

[0099] Index value RRT1 RRT2 RRT3 RRT4 RRT1 0 0 0 0 RRT2 0 0 0 0 RRT3 1 0 0 0 RRT4 0 0 0 0

[0100] Suppose that memory management circuit 502 performs a data read operation on the upper physical programmable unit of entity unit 610(0) in Table 5. According to Table 5, memory management circuit 502 uses the read voltage levels of 6V and 12V corresponding to index value RTT1 as the starting read voltage levels to perform the data read operation on the upper physical programmable unit of entity unit 610(0). Suppose that the read voltage levels used to successfully read this entity unit 610(0) are -2V and 7V corresponding to index value RTT3. In this exemplary embodiment, memory management circuit 502 counts the number of times there is correlation between index value RTT1 and index value RTT3, and generates a count value, such as the count value recorded in the column corresponding to index value RTT1 and index value RTT3 in Table 9, which is 1. This indicates that there is one correlation between index value RTT1 and index value RTT3. However, Table 9 is only an example, and the specific records can be adjusted according to practical needs.

[0101] It is worth noting that if the second read voltage level used to successfully read the physical unit is different from the read voltage level corresponding to any index value, the memory management circuit 502 will calculate the distance between the second read voltage level and the read voltage level corresponding to each index value. Furthermore, the memory management circuit 502 will record the correlation information between the calculated closest read voltage level (or its corresponding index value) and the first read voltage level (or its corresponding index value) in a transient lookup table.

[0102] In one exemplary embodiment, the memory management circuit 502 may determine the initial read voltage level to be used when performing a data read operation based on a read level tracking table. This read level tracking table records the optimal read voltage level for each physical cell. Specifically, the memory management circuit 502 may obtain the optimal read voltage level (also referred to as the first optimal read voltage level) for the corresponding first physical cell from the read level tracking table as the initial read voltage level. For example, the read voltage level tracking table may include Tables 2 to 4 or Tables 5 to 8 above. Taking Tables 2 to 4 as an example, the memory management circuit 502 may input the index value RRT1 into Table 3 when reading the upper physical programmable unit of physical cell 610(0), obtaining read voltage levels 14V and 23V as the initial read voltage levels.

[0103] In one exemplary embodiment, if a transient lookup table containing associated information exists in the memory storage device 10, the memory management circuit 502 can determine the starting read voltage level used when performing a data read operation based on the read voltage level tracking table and the associated information recorded in the transient lookup table. Specifically, the memory management circuit 502 can obtain the optimal read voltage level for the physical unit to be read from the read voltage level tracking table. For example, the memory management circuit 502 can obtain the first optimal read voltage level for the first physical unit to be read (e.g., the second physical unit in other embodiments) from the read voltage level tracking table. Furthermore, the memory management circuit 502 searches the transient lookup table based on the first optimal read voltage level (or its corresponding first index value) to sequentially obtain the second read voltage level (or the read voltage level corresponding to the second index value) corresponding to a plurality of count values ​​in descending order as the starting read voltage level. Then, the memory management circuit 502 can perform a data read operation based on this starting read voltage level.

[0104] For example, Table 10 below is a transient lookup table in an exemplary embodiment, which records the association information between the first index value and the second index value. In this exemplary embodiment, the memory management circuit 502 records the operation results after performing 1840 data read operations in the transient lookup table, including 1840 association information entries.

[0105] Table 10

[0106] Index value RRT1 RRT2 RRT3 RRT4 RRT1 0 0 100 100 RRT2 10 300 200 0 RRT3 1000 500 0 20 RRT4 0 30 0 300

[0107] In Table 10, the column with a count value of 500 indicates that after performing a data read operation on the entity unit using the read voltage level corresponding to the index value RTT2 (i.e., the first read voltage level) as the starting read voltage level, the number of times the read voltage level corresponding to the index value RTT3 (i.e., the second read voltage level) used to successfully read this entity unit is obtained is 500 times. The contents recorded in other columns are similar. In this example embodiment, it is assumed that when performing a data read operation, the data stored in the upper entity programmable unit of entity unit 610 (1) needs to be decoded. According to Table 2 above, the index value corresponding to entity unit 610 (1) is "RRT2". The memory management circuit 502 will look up the transient lookup table shown in Table 10 according to the index value RRT2 to obtain the read voltage level corresponding to the index value RRT3 corresponding to the largest count value (i.e., 500) among the multiple count values ​​corresponding to the index values ​​RRT1, RRT2, RRT3, and RRT4 corresponding to the index value RRT2 as the starting read voltage level. For example, the memory management circuit 502 can obtain the read voltage levels -2V and 4V as the starting read voltage levels according to the index lookup table shown in index value RRT3 lookup table 3 to perform data read operations. Furthermore, if decoding fails during the data read operation, the memory management circuit 502 can obtain the read voltage level corresponding to the index value RRT2 with the largest count value (i.e., 300) among the multiple count values ​​corresponding to other index values ​​RRT1, RRT2, and RRT4 corresponding to index value RRT2 as the starting read voltage level, and so on.

[0108] In other words, the memory management circuit 502 further fine-tunes the previously tracked optimal read voltage level based on the transient lookup table when relevant information is recorded there. Even if the operating and environmental conditions at the time the memory storage device 10 actually reads data are different from the conditions when the optimal read voltage level was last monitored, or if the optimal read voltage level shifts due to a long interval between the actual data reading time and the previous monitoring time, the memory management circuit 502 can predict the read voltage level that is closer to the true optimal read voltage level based on the voltage level shift changes statistically recorded in the transient lookup table, and then perform subsequent data reading operations. In this way, the performance of the read operation can be improved.

[0109] In one exemplary embodiment, the memory management circuit 502 can update the read voltage level tracking table based on the associated information recorded in the transient lookup table, and clear the transient lookup table after updating it. For example, the memory management circuit 502 can update the optimal read voltage level recorded in the read voltage level tracking table based on the transient lookup table after the total number of count values ​​recorded in the transient lookup table reaches a preset recording threshold (e.g., 10000). Furthermore, the memory management circuit 502 can also update the optimal read voltage level recorded in the read voltage level tracking table based on the transient lookup table when the memory storage device 10 is powered on again after a power outage. This invention does not limit the timing of updating the read voltage level tracking table based on the transient lookup table.

[0110] In this exemplary embodiment, the memory management circuit 502 can look up the transient table according to the optimal read voltage level (also referred to as the third optimal read voltage level) in the read voltage level tracking table, and obtain the second read voltage level corresponding to the maximum count value among the multiple count values ​​corresponding to the first read voltage level corresponding to the third optimal read voltage level. Furthermore, the third optimal read voltage level in the read voltage level tracking table is updated to this second read voltage level.

[0111] For example, suppose the memory management circuit 502 updates the read voltage level tracking table, which includes Tables 2 to 4, according to the transient lookup table in Table 10 above. According to Table 10 above, among the multiple count values ​​corresponding to index value RRT2, the index value corresponding to the largest count value is index value RRT3. Therefore, the memory management circuit 502 can update the index value RRT2 corresponding to entity cell 610(1) in Table 2 to index value RRT3. The update result can be seen in Table 11 below, for example.

[0112] Table 11

[0113] Entity unit Index value 610(0) RRT1 610(1) RRT3 610(2) RRT3 610(3) RRT4 610(4) RRT3

[0114] Figure 7 This is a flowchart illustrating a voltage level correction method according to an exemplary embodiment of the present invention. Please refer to... Figure 7 In step S702, the memory management circuit 502 uses a first read voltage level as the starting read voltage level to perform a first data read operation on a first physical unit among multiple physical units, in order to obtain a second read voltage level used to successfully read the first physical unit. In step S704, the memory management circuit 502 records the correlation information between the first read voltage level and the second read voltage level in a transient lookup table. In step S706, the memory management circuit 502 performs a second data read operation based on the correlation information recorded in the read voltage level tracking table and the transient lookup table.

[0115] Figure 8 This is a flowchart illustrating an exemplary embodiment of the method for updating the optimal read voltage level according to the present invention. In step S802, the memory management circuit 502 obtains the optimal read voltage level for the corresponding entity cell from the read voltage level tracking table. In step S804, the memory management circuit 502 determines whether a transient lookup table recording associated information exists. In step S806, if it is determined that a transient lookup table recording associated information does not exist (i.e., step S804 determines "No"), the memory management circuit 502 sets the optimal read voltage level as the starting read voltage level. In step S808, if it is determined that a transient lookup table recording associated information exists (i.e., step S804 determines "Yes"), the memory management circuit 502 searches the transient lookup table according to the optimal read voltage level or the index value corresponding to the optimal read voltage level, and sequentially obtains the second read voltage level corresponding to the count value in descending order of multiple count values ​​as the starting read voltage level. In step S810, the memory management circuit 502 performs a data read operation according to the starting read voltage level.

[0116] However, Figure 7 and Figure 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 7 and Figure 8 Each step can be implemented as multiple codes or circuits, and this invention is not limited thereto. Furthermore, Figure 7 and Figure 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0117] In summary, the read voltage level correction method, memory storage device, and memory control circuit unit provided in this embodiment of the invention can record correlation information in a transient lookup table and fine-tune the previously monitored optimal read voltage level based on the correlation information recorded in the transient lookup table. In this way, even if the actual operation and environmental conditions of the memory storage device reading data at the current time are different from the conditions when the optimal read voltage level was previously monitored, or if the optimal read voltage level shifts due to a long interval between the actual data reading time and the previous monitoring time, the memory management circuit can predict the read voltage level that is closer to the true optimal read voltage level based on the voltage level shift changes statistically recorded in the transient lookup table and perform subsequent data reading operations. Therefore, this invention can improve the efficiency of finding the actual optimal read voltage level and improve the accuracy of the found optimal read voltage level. Compared to simply using the previously monitored optimal read voltage level to perform optimal read voltage level search and decoding operations, this invention can reduce the time spent searching for a successfully read physical unit read voltage level, thereby increasing the overall efficiency of the data reading operation.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A read voltage level correction method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising multiple physical units, the method comprising: A first data read operation is performed on the first entity unit among the plurality of entity units using a first read voltage level as the starting read voltage level, so as to obtain a second read voltage level used to successfully read the first entity unit; Recording the correlation information between the first read voltage level and the second read voltage level in a transient lookup table, wherein the step of recording the correlation information between the first read voltage level and the second read voltage level in the transient lookup table includes: A count value is generated by counting the number of times that there is a correlation between the first read voltage level and the second read voltage level; Record the count value in the transient lookup table; and The second data reading operation is performed based on the correlation information recorded in the voltage level tracking table and the transient lookup table. The read voltage level tracking table records multiple optimal read voltage levels for the plurality of physical units. The steps of performing the second data reading operation based on the correlation information recorded in the voltage level tracking table and the transient lookup table include: When the second data read operation instructs the reading of data from the second entity unit among the plurality of entity units, the second optimal read voltage level of the second entity unit is obtained from the read voltage level tracking table; and The transient lookup table is searched according to the second optimal read voltage level or the index value corresponding to the second optimal read voltage level, and the second read voltage level corresponding to the largest count value among the plurality of count values ​​is used as the starting read voltage level for performing the second data read operation.

2. The read voltage level correction method according to claim 1, wherein the step of using the first read voltage level as the starting read voltage level to perform the first data read operation on the first entity unit among the plurality of entity units further includes: The first optimal read voltage level corresponding to the first physical unit is obtained from the read voltage level tracking table as the first read voltage level.

3. The reading voltage level correction method according to claim 1, wherein the step of using the first reading voltage level as the starting reading voltage level to perform the first data reading operation on the first entity unit among the plurality of entity units further includes: The first read voltage level is determined based on the correlation information recorded in the read voltage level tracking table and the transient lookup table.

4. The reading voltage level correction method according to claim 1, wherein the method comprises: Decoding is performed when the first data read operation is performed on the first entity unit among the plurality of entity units using the first read voltage level as the starting read voltage level, or when the second data read operation is performed based on the association information recorded in the read voltage level tracking table and the transient lookup table.

5. The reading voltage level correction method according to claim 1, wherein the step of performing the second data reading operation based on the correlation information recorded in the reading voltage level tracking table and the transient lookup table further includes: The transient lookup table is searched according to the second optimal read voltage level or the index value corresponding to the second optimal read voltage level, so as to obtain the second read voltage level corresponding to the count value in descending order of the multiple count values ​​as the starting read voltage level for performing the second data read operation.

6. The reading voltage level correction method according to claim 1, wherein the method further comprises: The read voltage level tracking table is updated based on the associated information recorded in the transient lookup table; as well as The transient lookup table is cleared after the read voltage level tracking table is updated.

7. A memory storage device, comprising: A connection interface unit for coupling to the host system; A rewritable non-volatile memory module comprising multiple physical units; as well as The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to use a first read voltage level as a starting read voltage level to perform a first data read operation on a first physical unit among the plurality of physical units, so as to obtain a second read voltage level used to successfully read the first physical unit. The memory control circuit unit is further configured to record the correlation information between the first read voltage level and the second read voltage level in a transient lookup table, wherein the operation of recording the correlation information between the first read voltage level and the second read voltage level in the transient lookup table is... The memory control circuit unit is further configured to count the number of times that are correlated between the first read voltage level and the second read voltage level to generate a count value, and The memory control circuit unit is also used to record the count value in the transient lookup table and The memory control circuit unit is further configured to perform a second data read operation based on the associated information recorded in the read voltage level tracking table and the transient lookup table. The read voltage level tracking table records multiple optimal read voltage levels for the plurality of physical units. The memory control circuit unit is further configured to perform the second data read operation based on the associated information recorded in the read voltage level tracking table and the transient lookup table, including: The memory control circuit unit is also configured to obtain a second optimal read voltage level of the second entity unit from the read voltage level tracking table when the second data read operation indicates that data of the second entity unit among the plurality of entity units is read; as well as The memory control circuit unit is further configured to look up the transient lookup table according to the second optimal read voltage level or the index value corresponding to the second optimal read voltage level, and use the second read voltage level corresponding to the largest count value among the plurality of count values ​​as the starting read voltage level for performing the second data read operation.

8. The memory storage device of claim 7, wherein the memory control circuit unit is further configured to obtain a first optimal read voltage level corresponding to the first physical unit from the read voltage level tracking table as the first read voltage level.

9. The memory storage device according to claim 7, wherein the memory control circuit unit is further configured to determine the first read voltage level based on the association information recorded in the read voltage level tracking table and the transient lookup table.

10. The memory storage device of claim 7, wherein the memory control circuit unit is further configured to perform a decoding operation when performing the first data read operation on the first entity unit among the plurality of entity units using the first read voltage level as the starting read voltage level, or when performing the second data read operation according to the association information recorded in the read voltage level tracking table and the transient lookup table.

11. The memory storage device of claim 7, wherein in the operation of performing the second data read operation based on the association information recorded in the read voltage level tracking table and the transient lookup table, The memory control circuit unit is further configured to look up the transient lookup table according to the second optimal read voltage level or the index value corresponding to the second optimal read voltage level, so as to obtain the second read voltage level corresponding to the count value in descending order of the multiple count values ​​as the starting read voltage level for performing the second data read operation.

12. The memory storage device of claim 7, wherein the memory control circuit unit is further configured to update the read voltage level tracking table according to the association information recorded in the transient lookup table, and The memory control circuit unit is also used to clear the transient lookup table after updating the read voltage level tracking table.

13. A memory control circuit unit for controlling a rewritable non-volatile memory module comprising a plurality of physical units, wherein the memory control circuit unit comprises: Host interface, used to couple to the host system; A memory interface for coupling to the rewritable non-volatile memory module; Error checking and correction circuitry; as well as The memory management circuit is coupled to the host interface, the memory interface, and the error checking and correction circuit. The memory management circuit is configured to use a first read voltage level as a starting read voltage level to perform a first data read operation on a first physical unit among the plurality of physical units, in order to obtain a second read voltage level used to successfully read the first physical unit. The memory management circuit is further configured to record the correlation information between the first read voltage level and the second read voltage level in a transient lookup table, wherein the operation of recording the correlation information between the first read voltage level and the second read voltage level in the transient lookup table is described in detail. The memory management circuit is further configured to count the number of times that are correlated between the first read voltage level and the second read voltage level to generate a count value, and The memory management circuit is also used to record the count value in the transient lookup table and The memory management circuit is also used to perform a second data read operation based on the association information recorded in the read voltage level tracking table and the transient lookup table. The read voltage level tracking table records multiple optimal read voltage levels for the plurality of physical units. The memory management circuit further includes the following operations for performing the second data read operation based on the associated information recorded in the read voltage level tracking table and the transient lookup table: The memory management circuit is also configured to obtain a second optimal read voltage level of the second entity unit from the read voltage level tracking table when the second data read operation indicates that data of the second entity unit among the plurality of entity units is read; as well as The memory management circuit is further configured to look up the transient lookup table based on the second optimal read voltage level or the index value corresponding to the second optimal read voltage level, and to use the second read voltage level corresponding to the largest count value among the plurality of count values ​​as the starting read voltage level for performing the second data read operation.

14. The memory control circuit unit of claim 13, wherein the memory management circuit is further configured to obtain a first optimal read voltage level corresponding to the first physical unit from the read voltage level tracking table as the first read voltage level.

15. The memory control circuit unit of claim 13, wherein the memory management circuit is further configured to determine the first read voltage level based on the associated information recorded in the read voltage level tracking table and the transient lookup table.

16. The memory control circuit unit of claim 13, wherein the memory management circuit is further configured to perform a decoding operation when performing the first read operation on the first entity unit among the plurality of entity units using the first read voltage level as the starting read voltage level, or when performing the second data read operation according to the association information recorded in the read voltage level tracking table and the transient lookup table.

17. The memory control circuit unit of claim 13, wherein in the operation of performing the second data read operation based on the association information recorded in the read voltage level tracking table and the transient lookup table, The memory management circuit is further configured to look up the transient lookup table according to the second optimal read voltage level or the index value corresponding to the second optimal read voltage level, so as to obtain the second read voltage level corresponding to the count value in descending order of the multiple count values ​​as the starting read voltage level for performing the second data read operation.

18. The memory control circuit unit of claim 13, wherein the memory management circuit is further configured to update the read voltage level tracking table according to the association information recorded in the transient lookup table, and The memory management circuitry is also used to clear the transient lookup table after updating the read voltage level tracking table.

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