Bulk wafer switch isolation

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to bulk wafer switch isolation structures and methods of fabricating the same. The structure includes a bulk substrate material; an active region on the bulk substrate material; a non-active region adjacent to the active region; and an amorphous material covering the bulk substrate material in the non-active region adjacent to the active region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices, and more particularly, to bulk wafer switch isolation structures and methods of manufacturing the same. BACKGROUND

[0002] Semiconductor devices can be fabricated on many different types of substrates depending on their specific application. For example, depending on the specific application, e.g., target RF performance, linearity, and harmonics, designers can select substrates including from standard silicon-on-insulator (SOI), high resistivity (HR) SOI, trap-rich HR SOI technology, and non-SOI trap-rich wafers.

[0003] Non-SOI trap-rich wafers are an attractive alternative due to their cost effectiveness. However, non-SOI trap-rich wafers provide poor switching capability and coplanar waveguide linearity due to the presence of dummy fill field effect transistor (FET) shapes. To address the issues of poor linearity (e.g., intermodulation distortion) and harmonics, manufacturers have turned to using trap-rich HR SOI technology. For example, HR SOI technology provides data rate protocols and greater bandwidth for higher frequency bands. Further, for RF devices, the insulating substrate of SOI technology enables stacked FET transistors to handle high voltage swings at high power outputs incident to antennas, in addition, reduced substrate coupling minimizes insertion loss and improves linearity such as harmonics. However, these alternative technologies are quite costly. SUMMARY

[0004] In an aspect of the disclosure, a structure includes a bulk substrate material, an active region on the bulk substrate material, a non-active region adjacent to the active region, and an amorphous material covering the bulk substrate material in the non-active region adjacent to the active region.

[0005] In an aspect of the disclosure, a structure includes a single crystalline bulk substrate, an active region on the single crystalline bulk substrate having active devices, a non-active region separated from the active region by a shallow trench isolation structure, and an amorphous layer on the single crystalline bulk substrate in the non-active region.

[0006] In an aspect of the disclosure, a method includes forming active devices on a substrate in an active region, forming non-active devices over the substrate in a non-active region, removing the non-active devices and exposing the substrate in the non-active region, damaging the exposed substrate in the non-active region, and forming a dielectric material over the damaged exposed substrate in the non-active region and the active devices. BRIEF DESCRIPTION OF DRAWINGS

[0007] In the following detailed description, the present disclosure is described, by way of non-limiting example, with reference to the figures mentioned and the accompanying drawings, in which:

[0008] Figure 1A A top view of an active region and a non-active region of an integrated circuit (IC) and a corresponding manufacturing process are shown, according to aspects of the present disclosure, among other features.

[0009] Figure 1B is a cross-sectional view of the non-active region of Figure 1A

[0010] Figure 2 A patterned mask over a dummy gate structure in a non-active region and a corresponding manufacturing process are shown, according to aspects of the present disclosure, among other features.

[0011] Figure 3 A dummy gate structure removed from a non-active region and a corresponding manufacturing process are shown, according to aspects of the present disclosure, among other features.

[0012] Figure 4 Exposed substrate material in a non-active region and a corresponding manufacturing process are shown, according to aspects of the present disclosure, among other features.

[0013] Figure 5 Amorphized substrate material in a non-active region and a corresponding manufacturing process are shown, according to aspects of the present disclosure, among other features.

[0014] Figure 6 Dielectric material over an active region and a non-active region and a corresponding manufacturing process are shown, according to aspects of the present disclosure, among other features. DETAILED DESCRIPTION

[0015] The present disclosure relates to semiconductor structures, and more particularly, to bulk wafer switch isolation structures and methods of manufacturing the same. More particularly, the present disclosure relates to mid-of-line (MOL) low energy argon bulk wafer switch isolation structures. Advantageously, the present disclosure increases the resistive surface of the bulk wafer substrate, which in turn improves the switching linearity and harmonics of the substrate. Furthermore, the present disclosure eliminates the need for high energy high dose argon implantation for MOL structures.

[0016] ​In embodiments, bulk wafer switch isolation structures are disposed in a non-active region (e.g., white space) of an integrated circuit (IC) chip. A method of fabrication includes exposing a substrate (silicon) in the non-active region of the IC chip by removing dummy structures, followed by performing a low-energy Ar implant to amorphize the exposed portion of the substrate. To expose the substrate, shallow trench isolation features and dummy gate structures within the non-active region can be removed, e.g., non-active FETs after silicide formation. This method of fabrication creates bulk wafer isolation structures at low cost without impacting other structures and surfaces within the active region of the IC chip. Moreover, the amorphous silicon substrate will provide isolation for adjacent active regions (e.g., radio frequency (RF) FETs).

[0017] Bulk wafer switch isolation structures of the present disclosure can be fabricated in a variety of ways using a variety of different tools. Generally, however, methods and tools are used to form structures having micrometer and nanometer scale dimensions. Methods (i.e., techniques) for fabricating bulk wafer switch isolation structures of the present disclosure have been adopted from integrated circuit (IC) technology. For example, these structures are built on wafers and are realized through a photoresist process patterned material films on top of the wafer. Specifically, fabrication of bulk wafer switch isolation structures uses three basic building blocks: (i) deposition of thin film materials on a substrate; (ii) application of a patterned mask on top of the film through a lithographic imaging process; and (iii) selective etching of the film according to the mask.

[0018] Figure 1A A top view of an active region and a non-active region of an integrated circuit (IC) according to aspects of the present disclosure is shown along with a corresponding fabrication process. Figure 1B is a cross-sectional view of the non-active region of Figure 1A More specifically and with simultaneous reference to Figure 1A and Figure 1B Structure 10 includes a substrate 12 having an active region 15 and a non-active region 17. Substrate 12 is a bulk substrate composed of any suitable material. For example, substrate 12 includes a bulk semiconductor material, such as monocrystalline silicon. Alternatively, substrate 12 can include other suitable bulk elementary semiconductor materials, such as germanium in a crystal; compound semiconductors, such as silicon carbide, silicon germanium, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and combinations thereof, or other III / V or II / VI compound semiconductors.

[0019] In an embodiment, the active region 15 includes a device 16; and the non-active region (e.g., white space) 17 includes a dummy gate structure 14. The device 16 can be a gate structure (e.g., a transistor) that includes similar dimensions as the dummy gate structure 14. The device 16 and the dummy gate structure 14 are surrounded by a shallow trench isolation structure 18a, and the dummy gate structure 14 can be formed on an insulator material 18. The shallow trench isolation structure 18a and the insulator material 18 can be an oxide material (e.g., SiO2) deposited using conventional deposition methods (e.g., chemical vapor deposition (CVD) process). The dummy gate structure 14 includes a dummy poly material 14a and a sidewall spacer 14b.

[0020] While not critical to an understanding of the present disclosure, the device 16 (e.g., gate structure) and the dummy gate structure 14 can be fabricated using conventional CMOS processes. For example, the device 16 and the dummy gate structure 14 can be fabricated using standard CMOS or alternative gate processes. In standard CMOS processing, a gate dielectric and polysilicon are formed (e.g., deposited) on the substrate material 18, and then a patterning process is performed. An insulator material such as nitride or oxide can be deposited on the patterned material, and then an anisotropic etch process is performed to form sidewalls.

[0021] In alternative gate processes, a sacrificial material (e.g., polysilicon material) is deposited on the insulator material 18 (for the dummy structure) and the substrate material 18 (for the active device). The gate dielectric material and the sacrificial material are patterned using conventional lithography and etching (reactive ion etch process). A sidewall material (e.g., nitride) is blanket deposited on the patterned gate dielectric material and the sacrificial material, and then an anisotropic etch process is performed to form sidewall spacers. This fabrication process will result in the dummy gate structure 14 including, for example, the sacrificial material 14a and the sidewall spacers 14b.

[0022] After additional processing is performed on other features (e.g., well implants, source / drain features, silicide processes, etc.), a selective etch chemistry can be utilized to remove the sacrificial material used to form the active device, while the dummy gate structure 14 is protected with a masking material well known in the art, such that the present disclosure can be fully understood without further explanation. In an embodiment, the etch process does not etch or remove the sidewall and gate dielectric materials. The removal of the sacrificial material will leave an opening between the sidewall spacers, which is filled with a dielectric material and a work function metal to form the active device 16.

[0023] Figure 2 A patterned mask 20 is shown positioned over the dummy gate structure 14 in the non-active region. The mask 20 can be any standard photolithography mask used in conventional etch processes. Figure 2An exemplary illustration shows a mask 20 patterned to include an opening 20a that exposes a single dummy gate structure 14; however, those skilled in the art will understand that the opening 20a may include any number of dummy gate structures 14 within an active region of an exposed substrate (e.g., an IC).

[0024] In an embodiment, the openings 20a of the mask 20 can be formed using any conventional photolithography and etching method known to those skilled in the art. For example, the resist formed on the mask 20 is exposed to energy (light) to form a pattern (opening). One or more openings 20a are formed in the mask 20 through the openings in the resist using an etching process with selective chemistry (e.g., reactive ion etching (RIE)). The openings 20a will expose one or more dummy gate structures 14. The resist can then be removed using a conventional oxygen ashing process or other known stripping agents.

[0025] like Figure 3 As shown, after removing the resist, the dummy gate structure 14 can be removed from the non-active region. The dummy gate structure 14 can be removed by a conventional etching process (RIE) with selective chemistry or wet chemistry. As an example, the sidewall spacer 14b can be removed by a dry etching process or by hot phosphorus and diluted HF solution. The etching process will expose the underlying insulating material 18 and the shallow trench isolation structure 18a in the non-active region.

[0026] Figure 4 The exposed substrate material 12 in the non-active region, among other features, and the corresponding manufacturing process are shown. For example, in the manufacturing process for exposing the substrate material 12, an oxide etching process known to those skilled in the art can be used to remove the exposed portions of the insulating material 18 and the shallow trench isolation structure 18a. For example, the oxide etching process may include a wet etchant, such as HF etching, which uses a chemical process instead of a dry plasma process. By removing the exposed insulating material 18 and the shallow trench isolation structure 18a, a step feature 12a is formed in the substrate 12, which includes a sidewall 12b and a top surface 12c.

[0027] Figure 5Amorphous substrate material 22 and the corresponding manufacturing process are shown, among other features. In this processing step, exposed substrate material 12, including step feature 12a, is subjected to an implant process, as indicated by the arrow denoted by reference numeral 13, which will damage substrate material 12, e.g., amorphize a crystalline substrate material. Preferably, in this implementation, mask 20 is an implant mask, which can include a layer of photosensitive material (e.g., organic photoresist) that is applied by a spin-on process, then pre-baked, followed by exposure to light projected through a photomask, post-exposure bake and development with a chemical developer. The mask has a thickness and stopping power sufficient to block the masked areas from receiving a dose of implant ions.

[0028] Still referring to Figure 5 In embodiments, the implant process includes a low dose and low energy argon implant process (e.g., eliminating the need for a standard high energy high dose argon implant). For example, the argon implant dose can be between 30 Kev to 500 Kev (as compared to a standard implant dose of approximately 900 Kev), and the energy can be between lel4 to lel5 (as compared to a standard energy of lel6). In other embodiments, to ensure full coverage, the implant process can be performed using a quad implant process (e.g., at approximately 7 degrees). The quad implant process includes dividing the required dose into four equal parts, then repositioning the wafer between each implant segment. This allows the shadowing effect of zero tilt to be symmetrical around the device features.

[0029] It will be appreciated that the implant process will damage substrate material 12, resulting in amorphous Si material 22. Amorphous Si material 22 will effectively coat or cover crystalline (or defect-free) substrate material 12, and have a higher resistivity than substrate material 12. By way of example, the energy level of the argon implant can be between 200 Kev - 900 Kev, resulting in a thickness of amorphous material 22 of approximately 50 nm. Mask 18 can be removed after the implant process.

[0030] Figure 6 Dielectric material 24 is shown, among other features, over active region 15 and non-active region 17. More specifically, in this implementation, dielectric material 24 is deposited over active region 15 and non-active region 17, and is patterned to expose step feature 12a. In this implementation, dielectric material 24 is a photoresist material, which is applied by a spin-on process, then pre-baked, followed by exposure to light projected through a photomask, post-exposure bake and development with a chemical developer. The mask has a thickness and stopping power sufficient to block the masked areas from receiving a dose of implant ions. Figure 6In this case, the dielectric material 24 can be borosilicate glass (BSG) deposited using a conventional conformal deposition method (e.g., CVD). The dielectric material 24 will cover the amorphous material 22 in the inactive region 17 as well as the active devices 16 in the active region 15. The amorphous material 22 will not recrystallize, thereby remaining in an amorphous state. In addition, the active devices in the active region 15 are at the same device level as the amorphous material 22 in the mid- process structure. In this similar structure using amorphous material 22, the amorphous material 22 will provide switch isolation; that is, the use of amorphous material 22 improves switching linearity and harmonics due to the increased resistivity of the substrate 12.

[0031] Still referring to Figure 6 The dielectric material 24 is planarized by a chemical mechanical polishing (CMP) method to form a planar surface 24a. Contacts 26 can be formed through the dielectric material 24 to the active devices (e.g., transistors) and their source and drain regions. The contacts 26 are formed by conventional photolithography, etching, and deposition methods. For example, after forming and patterning a resist mask, trenches are formed in the dielectric material 24 to expose the active devices as well as the source and drain regions. A metal or metal alloy material is deposited within the trenches. As an example, the metal can be aluminum. Any excess material on the dielectric material 24 can be removed by a CMP process.

[0032] The bulk wafer switch isolation structure can be utilized in system on a chip (SoC) technology. As will be appreciated by those skilled in the art, an SoC is an integrated circuit (also known as a "chip") that integrates all components of an electronic system onto a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with the same functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0033] The above-described process is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricant as raw chips, i.e., as single integrated circuits having a plurality of un-packaged chips, as bare chips, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as plastic carriers, pin grids, which are attached to a motherboard or other higher level carrier) or in multi-chip packages (such as ceramic carriers having surface interconnections and / or buried interconnections). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer

[0034] The description of various embodiments of the present disclosure has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The embodiments were chosen and described in order to best explain the principles of the various embodiments and their practical application, to thereby enable others skilled in the art to best utilize the various embodiments and with various modifications as are suited to the particular use contemplated.

Claims

1. A semiconductor structure, comprising: a bulk substrate material; an active region on the bulk substrate material; a non-active region adjacent to the active region; and an amorphous material covering the bulk substrate material in the non-active region adjacent to the active region. The amorphous material is a defective layer of the bulk substrate material.

2. The semiconductor structure of claim 1, wherein, The amorphous material has a higher resistivity than the bulk substrate material.

3. The semiconductor structure of claim 2, wherein, The amorphous material in the non-active region includes a step feature between shallow trench isolation structures.

4. The semiconductor structure of claim 3, wherein, The step feature includes the bulk substrate material beneath the amorphous material.

5. The semiconductor structure of claim 4, wherein, The bulk substrate material is a single crystalline Si material and the amorphous material is a defective layer of the single crystalline Si material.

6. The semiconductor structure of claim 1, wherein, The amorphous material is disposed between shallow trench isolation structures.

7. The semiconductor structure of claim 1, wherein, An active device in the active region, and wherein the amorphous material provides substrate isolation for the active device in the active region.

8. The semiconductor structure of claim 1, further comprising: A dielectric material covering the amorphous material in the non-active region and the active device.

9. The semiconductor structure of claim 8, further comprising: The non-active region including the amorphous material is free of dummy gate structures.

10. The semiconductor structure of claim 9, wherein, The active device in the active region is at the same level as the amorphous material.

11. The semiconductor structure of claim 8, wherein, The active region is free of the amorphous material.

12. The semiconductor structure of claim 1, wherein, 13. A semiconductor structure, comprising: a single crystalline substrate; an active region on the single crystalline substrate having an active device; a non-active region separated from the active region by shallow trench isolation structures; and an amorphous layer on the single crystalline substrate in the non-active region. The amorphous layer is a defective layer of the single crystalline substrate. The amorphous layer includes a step feature between shallow trench isolation structures.

14. The semiconductor structure of claim 13, wherein, The step feature includes the single crystalline substrate beneath the amorphous layer.

15. The semiconductor structure of claim 13, wherein, The non-active region is free of dummy gate structures.

16. The semiconductor structure of claim 15, wherein, A dielectric material covering the amorphous layer in the non-active region and the active region.

17. The semiconductor structure of claim 13, wherein, The active device in the active region is at the same level as the amorphous layer in the non-active region.

18. The semiconductor structure of claim 13, further comprising:

20. A method of fabricating a semiconductor structure, comprising:

19. The semiconductor structure of claim 13, wherein, forming an active device on a substrate in an active region; forming a non-active device on the substrate in a non-active region; removing the non-active device and exposing the substrate in the non-active region; damaging the exposed substrate in the non-active region to form an amorphous layer on the substrate; and forming a dielectric material on the amorphous layer in the non-active region and the active device. ​ ​

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