Dtscr device and electronic apparatus

Abstract

The application discloses a DTSCR device and an electronic device. The DTSCR device comprises a substrate, a buried oxide layer and a P-type substrate which are sequentially stacked, and a preset P+ doped region, a preset N+ doped region and a plurality of N well regions are sequentially arranged on the P-type substrate along a first direction, the plurality of N well regions are sequentially connected in the first direction, a part of the preset N+ doped region in the first direction forms a preset N well region, the preset N well region is arranged relative to the preset N+ doped region in a second direction, and the total volume of the preset N well region is associated with the number of N well regions, wherein the preset P+ doped region and the preset N+ doped region are both source regions. The application introduces the N well region in the N+ doped region of the intrinsic SCR, increases the resistance of the preset P+ doped region of the intrinsic SCR, reduces the ESD current required for the opening of the intrinsic SCR, weakens the parasitic SCR current discharge effect, reduces the opening delay of the intrinsic SCR, and thus completely suppresses the secondary triggering of the DTSCR.

Description

Technical Field

[0001] This application relates to the field of electrostatic discharge protection technology for integrated circuits, and in particular to a DTSCR device and electronic device. Background Technology

[0002] Electrostatic discharge (ESD) protection plays a crucial role in chip-level reliability design. By designing dedicated ESD protection units and placing them in the overall chip protection network, reliable and effective protection can be provided for the functional circuits inside integrated circuits under transient, low-charge, and high-voltage electrostatic shocks.

[0003] Diode-triggered silicon controlled rectifiers (DTSCRs) are widely used in ESD protection in advanced processes due to their adjustable trigger voltage and strong current discharge capability per unit area.

[0004] In related technologies, when a DTSCR device experiences an ESD impact (VESD) at its electrostatic input terminal, the diode chain in the trigger circuit turns on first. After the diode chain turns on, the parasitic PNP BJTs in the vertical direction of each diode conduct, and the substrate, acting as the collector, collects a large amount of current. Since the trigger current required by the intrinsic SCR is higher than the trigger current of the parasitic SCR in the diode chain, the parasitic SCR turns on first to discharge part of the ESD current. However, due to its limited current discharge capability, it cannot achieve voltage clamping, thus causing the overall trigger voltage of the DTSCR to increase again. At the same time, the current collected by the substrate is higher than the current discharged by the parasitic SCR, thereby increasing the current used to trigger the intrinsic SCR until it reaches the intrinsic SCR's trigger current, at which point the intrinsic SCR turns on. After the SCR turns on, its on-resistance is very low, and as the main ESD current discharge unit, it can clamp the voltage to a lower potential, thus resulting in a secondary triggering phenomenon. This secondary triggering phenomenon causes the overall trigger voltage of the DTSCR to be high, which cannot meet the ESD design requirements and also prevents precise adjustment of the DTSCR trigger voltage. Summary of the Invention

[0005] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application provides a DTSCR device and an electronic device.

[0006] The DTSCR device according to the embodiments of this application includes a substrate, a buried oxide layer and a P-type substrate stacked in sequence. A preset P+ doped region, a preset N+ doped region and a plurality of N-well regions are sequentially disposed on the P-type substrate along a first direction. The plurality of N-well regions are connected in sequence in the first direction. The preset N+ doped region forms a preset N-well region in a portion of the first direction. The preset N-well region is partially disposed relative to the preset N+ doped region in the second direction. The total volume of the preset N-well region is related to the number of N-well regions. Both the preset P+ doped region and the preset N+ doped region are source regions.

[0007] In some embodiments, the preset N-well region includes multiple sub-well regions, which are spaced apart along the second direction.

[0008] In some implementations, the number of sub-well regions is associated with the number of N-well regions.

[0009] In some implementations, each of the sub-well regions has the same volume, and the more N-well regions there are, the fewer the number of sub-well regions there are.

[0010] In some embodiments, the preset N-well region is continuously arranged in the second direction.

[0011] In some implementations, the length of the preset N-well region in the second direction is associated with the number of N-well regions.

[0012] In some implementations, the more N-well regions there are, the shorter the length of the preset N-well region in the second direction.

[0013] In some embodiments, a first metal region is disposed on the preset P+ doped region, and a second metal region is disposed on the preset N+ doped region, both the first metal region and the second metal region being grounded.

[0014] In some embodiments, each of the N-well regions includes a P+ doped region and an N+ doped region disposed along the first direction; A third metal region is disposed on the P+ doped region of the first N-well region in the first direction, and the third metal region is connected to the electrostatic input terminal. A fourth metal region is disposed on the N+ doped region of the last N-well region in the first direction, and the fourth metal region is grounded.

[0015] In some embodiments, except for the first and last N-well regions in the first direction, the P+ doped region of each N-well region is connected to the N+ doped region of the previous N-well region, and the N+ doped region is connected to the P+ doped region of the next N-well region.

[0016] In some embodiments, the DTSCR device includes a metal conductive region, and except for the first and last N-well regions in the first direction, the P+ doped region of each N-well region is connected to the N+ doped region of the previous N-well region through the metal conductive region, and the N+ doped region is connected to the P+ doped region of the next N-well region through the metal conductive region.

[0017] In some embodiments, the material of the metallic conductive region includes copper.

[0018] In some embodiments, the preset N+ doped region is used for implanting N+ doping, and the preset P+ doped region is used for implanting P+ doping.

[0019] In some implementations, multiple N-well regions are used for implanting N-type doping.

[0020] The electronic device implemented in this application includes the DTSCR device described in any of the above embodiments.

[0021] In the DTSCR device and electronic device of this application, a predetermined N-well region is formed in a portion of the predetermined N+ doped region of the intrinsic SCR, thereby increasing the resistance of the predetermined P+ doped region of the intrinsic SCR. This reduces the ESD current required for the intrinsic SCR to turn on, weakens the parasitic SCR current discharge effect, reduces the turn-on delay of the intrinsic SCR, and thus completely suppresses secondary triggering of the DTSCR. Furthermore, the combination of the N-well addition method and SOI process in the DTSCR device can significantly improve the substrate resistance of the SCR region. At the same time, the SOI process can also reduce the leakage current caused by the Darlington effect in the diode chain. The total volume of the predetermined N-well region is related to the number of N-well regions, which makes the trigger voltage of the final designed DTSCR device flexible and adjustable, and eliminates secondary triggering. The overall leakage current of the device is also relatively low, thus meeting different ESD design requirements.

[0022] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0023] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein: Figure 1 This is a schematic diagram of the structure of a DTSCR device in related technologies.

[0024] Figure 2 This is a schematic diagram of the structure of the DTSCR device according to an embodiment of this application.

[0025] Figure 3 Is it like this? Figure 2 A cross-sectional schematic diagram of AA.

[0026] Figure 4 Is it like this? Figure 2 A cross-sectional view of BB.

[0027] Figure 5 yes Figure 1 The related technologies shown include DTSCR devices and Figure 2 The diagram shows a performance comparison of the DTSCR devices applied for under low ESD stress.

[0028] Figure 6 yes Figure 1 The related technologies shown include DTSCR devices and Figure 2 The diagram shows a performance comparison of the DTSCR devices applied for under high ESD stress. Detailed Implementation

[0029] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0030] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0032] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0033] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0034] Please combine Figure 1In the DTSCR device of the related technology, a P-type silicon substrate 100 is included. A first N-well region 101, a second N-well region 102 and a third N-well region 103 are formed on the P-type silicon substrate 100. A first P+ implantation region 111 and a first N+ implantation region 112 are formed on the first N-well region 101. A second P+ implantation region 113 and a second N+ implantation region 114 are formed on the second N-well region 102. A third P+ implantation region 115 and a third N+ implantation region 116 are formed on the third N-well region 103. A fourth P+ implantation region 117 and a fourth N+ implantation region 118 are formed on a P-type silicon substrate 100. A source electrode 121 is provided on the fourth P+ implantation region 117, a source electrode 122 is provided on the fourth N+ implantation region 118, a source electrode 128 is provided on the third N+ implantation region 116, and a drain electrode 123 is provided on the first P+ implantation region 111. The source electrodes 121, 122 and 128 are all grounded to GND, and the drain electrode 123 is connected to the electrostatic input terminal VESD.

[0035] Please combine further Figure 1 D1, D2, and D3 are diodes formed within the first N-well region 101, the second N-well region 102, and the third N-well region 103, respectively, and diodes D1, D2, and D3 form a diode chain. A first conductive region 124 is formed between diodes D1 and D2, and a second conductive region 126 is formed between diodes D2 and D3.

[0036] like Figure 1The working principle of the DTSCR device in the middle when an ESD impact occurs at the electrostatic input terminal is as follows: When the ESD pulse arrives, the diode chain is first triggered. Then, the parasitic PNP BJT in the vertical direction of each diode will also turn on along with the diode. The current collected at the P-Sub position will bias the positive PN junction formed by P-Sub and the third N-well region 103 of the third diode D3. At this time, the parasitic SCR turns on and discharges most of the current through the parasitic SCR. A smaller portion of the current will flow out from the fourth P+ injection region 117 of the intrinsic SCR on the left, and form a bias voltage that acts positively on the PN junction (P-Sub / N+) of the NPN BJT inside the intrinsic SCR. This voltage difference is represented by ΔVBE. As ESD current increases, the discharge capability of the parasitic SCR becomes limited. The current flowing through the fourth P+ injection region (pin 117) of the intrinsic SCR increases, leading to a larger ΔVBE until it reaches the turn-on voltage of the PN junction (P-Sub / N+) of the NPN BJT inside the SCR. At this point, the intrinsic SCR turns on. The shorter path determines a smaller on-resistance and a larger ESD current discharge level, while also clamping the equivalent voltage at the port to a lower value. During this process, the parasitic SCR discharge current delays the turn-on of the intrinsic SCR, resulting in a secondary triggering phenomenon. This secondary triggering phenomenon causes a higher overall trigger voltage for the DTSCR, which fails to meet ESD design requirements.

[0037] Please combine Figure 2-4 In view of this, the present application provides a DTSCR device 10, which includes a substrate 11, a buried oxide layer 12 and a P-type substrate 13 stacked sequentially. A preset P+ doped region 131, a preset N+ doped region 132 and a plurality of N-well regions 15 are sequentially disposed on the P-type substrate 13 along a first direction x. The plurality of N-well regions 15 are connected sequentially in the first direction x.

[0038] A portion of the preset N+ doped region 132 in the first direction x constitutes a preset N well region 14. The preset N well region 14 is partially disposed in the second direction z relative to the preset N+ doped region 132. The total volume of the preset N well region 14 is related to the number of N well regions 15.

[0039] Among them, the preset P+ doped region 131 and the preset N+ doped region 132 are both source regions.

[0040] It should be noted that the first direction x and the second direction z are set perpendicularly. For example, the first direction x can be horizontal (or horizontal), and the second direction z can be the extension direction of the preset N-well region 14.

[0041] Specifically, in the DTSCR device 10 of this embodiment, a diode is formed in each N-well region 15, and all the diodes constitute a diode chain. For example... Figure 2 As shown, taking a DTSCR device 10 comprising three N-well regions as an example, the N-well region 15 includes a first N-well region 151, a second N-well region 152, and a third N-well region 153. A first diode D21 is formed in the first N-well region 151, a second diode D22 is formed in the second N-well region 152, and a third diode D23 is formed in the third N-well region 153. The first diode D21, the second diode D22, and the third diode D23 form a diode chain along a first direction x.

[0042] Both the preset P+ doped region 131 and the preset N+ doped region 132 are source regions, and both need to be grounded to GND in practical applications. A portion of the preset N+ doped region 132 is used to form a preset N-well region 14, i.e., an N-Well region is introduced. This increases the intrinsic SCR substrate lead-out resistance of the DTSCR device 10, thereby significantly reducing the intrinsic SCR trigger current of the DTSCR device 10. This allows for rapid turn-on after the diode chain turns on, thus suppressing secondary triggering of the DTSCR device 10. The overall trigger voltage of the DTSCR device 10 is thus correlated with the number of diodes in the DTSCR device 10. The overall trigger voltage of the DTSCR device 10 can be precisely adjusted by the number of diodes in the DTSCR device 10, thereby meeting different ESD design requirements.

[0043] Furthermore, the DTSCR device 10 can be formed using an SOI (Silicon-On-Insulator) process to create a stacked substrate 11, a buried oxide layer 12, and a P-type substrate 13. It should be noted that the SOI process refers to introducing a buried oxide layer 12 between the top silicon layer and the back substrate.

[0044] In the DTSCR device 10 of this application, a preset N-well region 14 is formed in a portion of the preset N+ doped region 132 of the intrinsic SCR, thereby increasing the resistance of the preset P+ doped region 131 of the intrinsic SCR. This reduces the ESD current required for the intrinsic SCR to turn on, weakens the parasitic SCR current discharge effect, reduces the turn-on delay of the intrinsic SCR, and thus completely suppresses the secondary triggering of the DTSCR device 10. Furthermore, the combination of the N-well addition method of the DTSCR device and the SOI process can significantly improve the substrate resistance of the SCR region. At the same time, the SOI process can also reduce the leakage current caused by the Darlington effect of the diode chain. The total volume of the preset N-well region is related to the number of N-well regions, which makes the trigger voltage of the final designed DTSCR device 10 flexible and adjustable, and there will be no secondary triggering phenomenon. The overall leakage current of the device will also be relatively low, thereby meeting different ESD design requirements.

[0045] In some embodiments, the preset N-well region 14 includes multiple sub-well regions, which are spaced apart along the second direction z.

[0046] It should be noted that the specific number of sub-well regions is not limited; it can be two, three, four, five, or even more segments. For example, please refer to [link / reference needed]. Figure 2 In this application, the number of sub-well regions is two segments. The configuration of the preset N-well region 14, which includes multiple sub-well segments, is equivalent to a fixed substrate resistance, making the SCR trigger voltage fixed, since the preset N-well region 14 is essentially a fixed N+ doped region. If the SCR trigger voltage is less than the diode chain trigger voltage (when there are many diodes), the SCR triggers first, resulting in almost all the discharge current of the DTSCR device 10 being discharged from the SCR. Changing the number of diodes has no effect on the overall device trigger voltage. Different numbers of segments can result in different substrate resistances; therefore, the substrate resistance of the SCR can be adjusted by setting different sub-well segments. Thus, the segmented N-well configuration makes the trigger voltage of the final DTSCR device 10 flexible and adjustable, and prevents secondary triggering. The overall leakage current of the device is also relatively low, thus meeting different ESD design requirements. The DTSCR device 10 can simultaneously avoid secondary triggering and achieve adjustable voltage.

[0047] In some implementations, the number of sub-well regions is associated with the number of N-well regions 15.

[0048] In this way, the trigger voltage of the SCR and the trigger voltage of the diode chain remain basically consistent. Thus, the trigger voltage of the entire DTSCR device 10 can be precisely adjusted by adjusting the number of diodes in the diode chain, avoiding mutual interference. At the same time, secondary triggering can be suppressed, ensuring that the DTSCR device 10 performs at its best.

[0049] In some implementations, each sub-well region has the same volume, and the more N-well regions 15 there are, the fewer sub-well regions there are.

[0050] It should be noted that the SCR substrate resistance is positively correlated with the volume of the sub-well region. When the number of sub-well segments occupies a larger volume, the SCR substrate resistance is larger and the trigger voltage is smaller. Conversely, the smaller the number of sub-well segments occupies a smaller volume, the smaller the substrate resistance and the larger the trigger voltage of the SCR substrate.

[0051] Understandably, the more N-well regions 15 there are, the more diodes are needed, and the higher the required trigger voltage. Conversely, the fewer sub-well regions there are, the lower the substrate resistance, and the higher the trigger voltage required for the SCR substrate. Therefore, by setting the number of N-well regions 15 to be greater and the number of sub-well regions to be less, the trigger voltage of the SCR and the trigger voltage of the diodes can be kept basically consistent. In this way, secondary triggering can be suppressed. At the same time, adjusting the number of diodes in the diode chain can precisely adjust the trigger voltage of the entire DTSCR device 10.

[0052] In some embodiments, the preset N-well regions 14 are continuously arranged in the second direction z. In this embodiment, the preset N-well regions 14 may include multiple preset N-well regions 14, which are arranged at intervals along the second direction z to form a straight line.

[0053] In some implementations, the length of the preset N-well region 14 in the second direction z is associated with the number of N-well regions 15.

[0054] Understandably, since the volume of the preset N-well region 14 is related to its length, and the volume of the preset N-well region 14 affects the trigger voltage of the SCR substrate resistor, which needs to be substantially consistent with the trigger voltage of the diode chain, the length of the preset N-well region 14 in the second direction z is related to the number of N-well regions 15.

[0055] In some implementations, the more N-well regions 15 there are, the shorter the length of the preset N-well region 14 in the second direction z.

[0056] Since the shorter the length of the preset N-well region 14 in the first direction x, the smaller the volume of the preset N-well region 14, the smaller the substrate resistance of the SCR, and the larger the trigger voltage of the SCR substrate resistance. Since one N-well region 15 corresponds to one diode, the more diodes there are, the larger the trigger voltage of the diode. Thus, the more N-well regions 15 there are, the shorter the length of the preset N-well region 14 in the second direction z, which can ensure that the trigger voltage of the SCR and the trigger voltage of the diode remain basically consistent, thereby avoiding secondary triggering. At the same time, adjusting the number of diodes in the diode chain can precisely adjust the trigger voltage of the entire DTSCR device 10.

[0057] In some embodiments, a first metal region 141 is disposed on a preset P+ doped region 131, and a second metal region 142 is disposed on a preset N+ doped region 132. Both the first metal region 141 and the second metal region 142 are grounded. Both the first metal region 141 and the second metal region 142 serve as source electrodes.

[0058] In some embodiments, each N-well region 15 includes a P+ doped region and an N+ doped region disposed along a first direction x. A third metal region 143 is disposed on the P+ doped region of the first N-well region 141 along the first direction x. The third metal region 143 is connected to the electrostatic input terminal VESD. A fourth metal region 146 is disposed on the N+ doped region of the last N-well region 15 along the first direction x. The fourth metal region 146 is grounded.

[0059] Specifically, the first N-well region 151 includes a first P+ doped region 133 and a first N+ doped region 134; the second N-well region 152 specifically includes a second P+ doped region 135 and a second N+ doped region 136; and the third N-well region 153 specifically includes a third P+ doped region 137 and a third N+ doped region 138. Among the multiple N-well regions 15, the leftmost P+ doped region is the first P+ doped region 133. A third metal region 143 is disposed on the first P+ doped region 133, and the third metal region 143 is connected to the electrostatic input terminal VESD. Here, the third metal region 143 serves as the drain electrode.

[0060] The rightmost N+ doped region among the multiple N-well regions 15 is the third N+ doped region. A fourth metal region 146 is provided in the N+ doped region of the last N-well region 15, and the last N-well region 15 is grounded to GND. That is to say, in this embodiment of the invention, there are three grounded source regions, namely the preset P+ doped region 131, the preset N+ doped region 132, and the N+ doped region of the last N-well region 15, corresponding to three source electrodes, namely the second metal region 142, the first metal region 141, and the fourth metal region 146.

[0061] In some implementations, except for the first N-well region 15 and the last N-well region 15 in the first direction x, the P+ doped region of each N-well region 15 is connected to the N+ doped region of the previous N-well region 15, and the N+ doped region is connected to the P+ doped region of the next N-well region 15.

[0062] In some embodiments, the DTSCR device 10 includes a metal conductive region 145. Except for the first N-well region 15 and the last N-well region 15 in the first direction x, the P+ doped region of each N-well region 15 is connected to the N+ doped region of the previous N-well region 15 through the metal conductive region 145, and the N+ doped region is connected to the P+ doped region of the next N-well region 15 through the metal conductive region 145.

[0063] In some embodiments, the material of the metallic conductive region 145 includes copper.

[0064] In some embodiments, the preset N+ doped region 132 is used for implanting N+ doping, and the preset P+ doped region 131 is used for implanting P+ doping.

[0065] In some implementations, each of the plurality of N-well regions 15 is used for implanting N-type doping.

[0066] Please see Figure 5 , Figure 5 for Figure 1 The DTSCR device 10 and shown in the related technologies Figure 2 The diagram shows a performance comparison of the DTSCR device 10 in this application under low ESD stress. More specifically, Figure 5 This paper presents the relationship between ΔVBE and the injection position of the N-well region for DTSCR device 10 in related technologies and DTSCR device 10 in this application under the condition of gradually increasing low TLP transient voltage pulse.

[0067] Comparison of ESD performance of two DTSCR devices 10 Figure 5 It can be seen that under the same, lower TLP transient voltage pulse, the ΔVBE at the N-well injection site is about 0.3V, while at other sites without N-well injection, the ΔVBE is about 0.1V. Therefore, the injection of the N-well region causes an increase in local resistance, which in turn produces a larger voltage drop when the same substrate current flows through it, so that the ΔVBE at this location can reach the voltage required for the PN junction to turn on in the forward direction more quickly.

[0068] Please see Figure 6 , Figure 6 for Figure 1 The existing DTSCR device 10 shown is Figure 2 The diagram shows a performance comparison of the DTSCR device 10 provided in this embodiment of the invention under high ESD stress. More specifically, Figure 6 This paper presents the relationship between ΔVBE and the injection position of the N-well region for DTSCR device 10 in related technologies and DTSCR device 10 in this application under the condition that the TLP transient voltage pulse gradually increases.

[0069] The comparison of the ESD performance of the two devices shows that at locations with higher ΔVBE values, as the amplitude of the TLP transient voltage pulse increases, it is easier to reach the PN forward turn-on voltage and complete the injection of electrons into the N+ region. This results in a significant increase in the electron concentration at the N-well injection location, which is represented by ΔCurrentDensity. The electron concentration difference at the N-well injection location is much higher than that at the non-N-well injection location.

[0070] Therefore, by Figure 5 and Figure 6As shown in the performance comparison diagram, compared with the DTSCR device 10 in related technologies, the DTSCR device 10 provided in this embodiment suppresses the high trigger voltage caused by secondary triggering of the DTSCR device 10 by increasing the resistance of a local area. This makes the trigger voltage of the protection device dependent on the number of diodes, achieving precise adjustment of the trigger voltage. By changing the number of diodes, the DTSCR can meet different ESD protection requirements without increasing leakage current or area. Utilizing the strong discharge capability per unit area of ​​intrinsic SCR devices, the high ESD protection capability of the silicon controlled rectifier is guaranteed.

[0071] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0072] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A DTSCR device, characterized in that, The DTSCR device includes a substrate, a buried oxide layer and a P-type substrate that are sequentially stacked using SOI technology. A preset P+ doped region, a preset N+ doped region and a plurality of N-well regions are sequentially disposed on the P-type substrate along a first direction. The plurality of N-well regions are sequentially connected in the first direction. A portion of the preset N+ doped region in the first direction constitutes a preset N-well region. The preset N-well region is partially disposed in the second direction relative to the preset N+ doped region. The preset N-well region includes multiple sub-well regions, which are spaced apart along the second direction. The number of sub-well regions and / or the length of the preset N-well region in the second direction are set to be related to the number of N-well regions, so that the trigger voltage of the intrinsic SCR matches the trigger voltage of the diode chain. Each sub-well region has the same volume, and the more N-well regions there are, the fewer sub-well regions there are. Wherein, both the preset P+ doped region and the preset N+ doped region are source regions.

2. The DTSCR device as described in claim 1, characterized in that, The preset N-well region is continuously arranged in the second direction.

3. The DTSCR device as described in claim 2, characterized in that, The more N-well regions there are, the shorter the length of the preset N-well region in the second direction.

4. The DTSCR device as described in claim 1, characterized in that, A first metal region is provided on the preset P+ doped region, and a second metal region is provided on the preset N+ doped region. Both the first metal region and the second metal region are grounded.

5. The DTSCR device as described in claim 1, characterized in that, Each of the N-well regions includes a P+ doped region and an N+ doped region disposed along the first direction; A third metal region is disposed on the P+ doped region of the first N-well region in the first direction, and the third metal region is connected to the electrostatic input terminal. A fourth metal region is disposed on the N+ doped region of the last N-well region in the first direction, and the fourth metal region is grounded.

6. The DTSCR device as described in claim 1, characterized in that, Except for the first and last N-well regions in the first direction, the P+ doped region of each N-well region is connected to the N+ doped region of the previous N-well region, and the N+ doped region is connected to the P+ doped region of the next N-well region.

7. The DTSCR device as described in claim 6, characterized in that, The DTSCR device includes a metal conductive region. Except for the first N-well region and the last N-well region in the first direction, the P+ doped region of each N-well region is connected to the N+ doped region of the previous N-well region through the metal conductive region, and the N+ doped region is connected to the P+ doped region of the next N-well region through the metal conductive region.

8. The DTSCR device as described in claim 7, characterized in that, The material of the metallic conductive region includes copper.

9. The DTSCR device according to any one of claims 1-6, characterized in that, The preset N+ doping region is used for implanting N+ doping, and the preset P+ doping region is used for implanting P+ doping.

10. The DTSCR device according to any one of claims 1-6, characterized in that, Multiple N-well regions are used for implanting N-type doping.

11. An electronic device, characterized in that, Includes the DTSCR device as described in any one of claims 1-10.

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