Metal oxide semiconductor field effect transistor with enhanced high frequency performance

Abstract

The present invention provides a metal oxide semiconductor field effect transistor with enhanced high frequency performance, comprising a semiconductor substrate serving as a drain region and an epitaxial region disposed on the upper surface of the substrate. The MOSFET device comprises a plurality of body regions and a plurality of source regions formed in the epitaxial region. The body regions are disposed near the upper surface of the epitaxial region and are laterally spaced apart from each other, and each source region is disposed in a corresponding body region near the upper surface of the body region. The MOSFET device comprises a gate structure having a plurality of planar gates and a trench gate. Each planar gate is disposed on the upper surface of the epitaxial region and overlaps with the corresponding body region. The trench gate is formed to partially pass through the epitaxial region and between the body regions, and the upper surface of the trench gate is recessed below the upper surface of the epitaxial region.

Description

Technical Field

[0001] The present invention relates generally to electrical, electronic and computer technology and, more particularly, to power transistor devices and methods of manufacturing. Background Art

[0002] Power transistors, such as power metal oxide semiconductor field effect transistors (MOSFETs), are typically designed to maintain a high source-to-drain current density in the on-state and a high blocking voltage between the drain and source in the off-state. There are many transistor device types, such as lateral and vertical devices, planar gate and trench gate, unipolar and bipolar transistors, each designed for a specific application. Many design parameters are mutually exclusive, so that improving one parameter can lead to degradation of another. Therefore, there are specific performance trade-offs in different transistor designs.

[0003] The design and performance criteria of transistors can be measured using several properties, including the drain-source breakdown voltage (BV ds ), characteristic on-resistance (R sp ), gate capacitance (C g ) and gate-drain capacitance (C gd ). These performance characteristics depend largely on factors such as the design, structure and material selection of the transistor. In addition, these transistor performance characteristics often follow opposite trends in key design parameters, such as gate length, channel and drift region doping concentrations, drift region length, total gate width, etc., making the design of transistor devices challenging. For example, increasing the drift region doping concentration in a transistor reduces the characteristic on-resistance and also reduces the breakdown voltage, which may make the transistor device unable to meet the breakdown voltage rating for a specific application. Similarly, a large gate width can reduce the total on-resistance of the transistor device, but it also increases the parasitic gate capacitance, thereby increasing the switching loss of the transistor. Therefore, transistor design in practice often involves trade-offs in certain key design parameters in order to reach a compromise between various performance characteristics.

[0004] An important performance parameter that determines the efficiency and reliability of transistor devices is the Miller capacitance, or gate-drain capacitance. As the demand for higher efficiency continues to increase, the design of power MOSFETs tends to be smaller gate size, which in turn reduces the gate charge (Q g ) and a lower threshold voltage (V t), which makes the device more susceptible to drain voltage peaks due to the Miller capacitance coupling effect. At the same time, higher transistor switching frequencies, as well as increased parasitic inductance, lead to an increase in drain ringing voltage. The combined impact of these effects makes today's power transistor devices prone to drain voltage-induced false conduction, thereby damaging the device. Another extremely challenging fact is that Miller capacitance is particularly difficult to reduce, and as a design compromise, often leads to an increase in the on-resistance of the device. Common methods of reducing parasitic gate-drain capacitance inevitably lead to higher device on-resistance, so reducing Miller capacitance in power transistor devices may be one of the most difficult design goals to achieve, and it is also a key need for product performance and application reliability.

[0005] In the Chinese application CN112614891A filed by the inventor on December 17, 2020 (priority date March 4, 2020), a metal oxide semiconductor field effect transistor with enhanced high-frequency performance is disclosed, which includes an epitaxial region formed on the upper surface of a substrate and at least two body regions formed in the epitaxial region, the body regions being located near the upper surface of the epitaxial region and spaced laterally from each other. The device also includes at least two source regions arranged in the corresponding body regions and close to the upper surface of the body regions, and a gate structure including at least two planar gates and one trench gate. Each planar gate is located on the upper surface of the epitaxial region and overlaps with at least a portion of the corresponding body region. The trench gate is located between the two body regions and at least partially in the epitaxial region; and a drain contact is located on the back of the substrate and electrically connected to the substrate. The technical solution of this application can obtain lower on-resistance, lower gate-drain (Miller) capacitance, lower switching loss, and higher off-state blocking voltage.

[0006] However, the shortcoming of this invention is that although lower on-resistance, lower gate-drain (Miller) capacitance, lower switching loss, and higher off-state blocking voltage can be obtained, it is very difficult to further improve the performance on this basis.

[0007] Based on the above technical solutions, the present application provides a metal oxide semiconductor field effect transistor device with further reduced gate coupling capacitance, and obtains lower on-resistance, lower gate-drain (Miller) capacitance, lower switching loss, and higher off-state blocking voltage. Summary of the Invention

[0008] The first object of the present invention is to provide a metal oxide semiconductor field effect transistor device with further reduced gate coupling capacitance, and to obtain lower on-resistance, lower gate-drain (Miller) capacitance, lower switching loss, and higher off-state blocking voltage.

[0009] The second object of the present invention is to provide a method for manufacturing a metal oxide semiconductor field effect transistor device with further reduced gate coupling capacitance, and to obtain lower on-resistance, lower gate-drain (Miller) capacitance, lower switching loss, and higher off-state blocking voltage.

[0010] A third object of the present invention is to provide a capacitor having a further reduced gate coupling capacitance.

[0011] A fourth object of the present invention is to provide a method for manufacturing a capacitor having a further reduced gate coupling capacitance.

[0012] A first aspect of the present invention provides a metal oxide semiconductor field effect transistor device, comprising:

[0013] a semiconductor substrate having a first conductivity type, the substrate serving as a drain region of the metal oxide semiconductor field effect transistor;

[0014] an epitaxial region having a first conductivity type, which is disposed on the upper surface of the substrate;

[0015] a plurality of body regions having a second conductivity type formed in the epitaxial region, the second conductivity type being opposite to the first conductivity type, the body regions being disposed proximate to an upper surface of the epitaxial region and laterally spaced apart from each other;

[0016] a plurality of source regions of a first conductivity type, each of the source regions being disposed in a corresponding body region and close to an upper surface of the body region; and

[0017] A gate structure includes: one or more planar gates and a trench gate, each of the planar gates is located on the upper surface of the epitaxial region and overlaps at least a portion of the corresponding body region; the trench gate is formed in at least a portion of the epitaxial region and between the body region; and an upper surface of the trench gate is configured to be recessed from the upper surface of the epitaxial region.

[0018] A second aspect of the present invention provides a method for manufacturing a metal oxide semiconductor field effect transistor device, the method comprising:

[0019] forming an epitaxial region having the first conductivity type on at least a portion of an upper surface of a substrate having the first conductivity type, the substrate serving as a drain region of the metal oxide semiconductor field effect transistor;

[0020] forming a plurality of body regions of a second conductivity type in the epitaxial region, the second conductivity type being opposite in polarity to the first conductivity type, the body regions being disposed proximate to an upper surface of the epitaxial region and spaced apart from each other in a laterally direction;

[0021] forming a plurality of source regions of a first conductivity type, each of the source regions being disposed in a corresponding body region and close to an upper surface of the body region; and

[0022] A gate structure is formed including one or more planar gates and a trench gate, wherein each planar gate is disposed on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region; the trench gate is formed in at least a portion of the epitaxial region and between the body regions; and an upper surface of the trench gate is configured to be recessed from the upper surface of the epitaxial region.

[0023] A third aspect of the present invention provides a capacitor comprising:

[0024] a semiconductor substrate having a first conductivity type;

[0025] an epitaxial region having a first conductivity type, which is disposed on at least a portion of the upper surface of the substrate, the epitaxial region constituting a first plate of the capacitor;

[0026] a trench gate formed in at least a portion of the epitaxial region and proximate to an upper surface of the epitaxial region; the trench gate comprises a conductor or semiconductor material, the conductor or semiconductor material forming a second plate of the capacitor and surrounded by a dielectric layer, the dielectric layer electrically isolating the conductor or semiconductor from the epitaxial region;

[0027] a plurality of doped regions of a first conductivity type disposed in the epitaxial region and on opposite sides of the trench gate and close to an upper surface of the epitaxial region; and

[0028] Multiple doped regions with a second conductivity type, wherein the second conductivity type has a polarity opposite to that of the first conductivity type, and the first end of each of the doped regions with the second conductivity type is adjacent to a corresponding one of the doped regions with the first conductivity type, and the second end thereof is opposite to the first end and adjacent to the corresponding side wall of the trench gate.

[0029] A fourth aspect of the present invention provides a method for manufacturing a capacitor, the method comprising:

[0030] forming an epitaxial region of a first conductivity type on at least a portion of an upper surface of the substrate, the epitaxial region constituting a first plate of the capacitor;

[0031] forming a trench gate in at least a portion of the epitaxial region and near an upper surface of the epitaxial region; the trench gate contains a conductor or semiconductor material serving as a second plate of the capacitor, and the trench gate is surrounded by a dielectric layer, the dielectric layer electrically isolating the conductor or semiconductor from the epitaxial region;

[0032] forming a plurality of doped regions having a first conductivity type in the epitaxial region on opposite sides of the trench gate and close to an upper surface of the epitaxial region; and

[0033] A plurality of doped regions with a second conductivity type are formed, wherein the polarity of the second conductivity type is opposite to that of the first conductivity type; a first end of each of the doped regions with the second conductivity type is adjacent to a corresponding one of the doped regions with the first conductivity type, and a second end relative to the first end is adjacent to a corresponding side wall of the trench gate.

[0034] The present invention can bring at least one of the following beneficial effects:

[0035] Lower on-resistance

[0036] Lower gate-drain (Miller) capacitance;

[0037] Lower switching losses;

[0038] Higher off-state blocking voltage.

[0039] Lower coupling capacitance between planar gate and trench gate.

[0040] These and other features and advantages of the present invention will be apparent from the following detailed description of illustrative embodiments taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above characteristics, technical features, advantages and their implementation methods.

[0042] The embodiments of the present invention are described below with reference to the accompanying drawings which are presented by way of example only and are non-limiting and non-exhaustive. Unless otherwise specified, reference numerals used in the accompanying drawings identify the same elements throughout the several views.

[0043] Figure 1A and 1B are cross-sectional views of at least a portion of a vertical double diffused metal oxide semiconductor field effect transistor (VDMOSFET) device including diagrams of on-resistance and parasitic gate-drain capacitance;

[0044] Figures 2A to 2C is at least a portion of a cross-sectional view of a trench gate MOSFET device showing reduced on-resistance and illustrating some effects of varying body region depth in the device;

[0045] Figures 3A to 3Cis at least a portion of a cross-sectional view of a split trench WMOSFET device showing reduced parasitic gate-to-drain capacitance and increased off-state blocking voltage, and illustrating some of the effects of varying body region depth in the device;

[0046] Figure 4A a perspective view showing at least a portion of a supergate MOSFET device according to a comparative embodiment of the present invention;

[0047] Figure 4B For the Figure 4A A cross-sectional view of the supergate MOSFET device at A-A';

[0048] Figure 4C for Figure 4B A cross-sectional view of a supergate MOSFET device having an accumulation layer formed near a trench gate structure as shown in FIG;

[0049] Figure 5 The relationship between the characteristic on-resistance Rsp and breakdown voltage of three different types of MOSFET devices is conceptually described.

[0050] Figure 6 a perspective view showing at least a portion of a supergate MOSFET device according to another comparative embodiment of the present invention;

[0051] Figures 7A to 7I for Figure 4B A schematic cross-sectional view of a manufacturing process of at least a portion of a supergate MOSFET device according to a comparative embodiment of the present invention is shown;

[0052] Figure 8 is a cross-sectional view of at least a portion of a supergate MOSFET device having a gate structure with enhanced voltage blocking capability in a comparative embodiment of the present invention;

[0053] Figures 9A to 9L for Figure 8 A schematic cross-sectional view of a manufacturing process of at least a portion of a supergate MOSFET device according to a comparative embodiment of the present invention is shown;

[0054] Figure 10 is a cross-sectional view of at least a portion of a supergate MOSFET device having an enhanced source contact according to a comparative embodiment of the present invention;

[0055] Figure 11 A schematic diagram of a function curve showing the change in drain voltage over time of a supergate MOSFET device according to one or more comparative embodiments of the present invention compared with a standard MOSFET device; and

[0056] Figure 12FIG. 1 is a graph showing a function curve of gate voltage versus time of a supergate MOSFET device according to one or more comparative embodiments of the present invention compared with a standard MOSFET device.

[0057] Figure 13 A cross-sectional view illustrating at least a portion of an exemplary supergate MOSFET device having reduced gate coupling capacitance according to one or more embodiments of the present invention;

[0058] Figure 14 shows a cross-sectional view of at least a portion of an exemplary capacitor including a trench structure;

[0059] Figure 15 An electrical schematic diagram illustrating at least a portion of an exemplary switching DC-DC voltage regulator circuit, to which one or more embodiments of the present invention may be applied;

[0060] Figure 16 A cross-sectional view illustrating at least a portion of an exemplary capacitor according to one or more embodiments of the present invention includes: Figure 14 The trench structure shown is improved to provide increased capacitance; and

[0061] Figure 17 A cross-sectional view illustrating at least a portion of an exemplary power structure including an exemplary supergate MOSFET device integrated with an exemplary trench capacitor structure according to one or more embodiments of the present invention is shown.

[0062] It should be understood that the elements shown in the figures are for simplicity and clarity of representation. In commercially feasible embodiments, in order to reduce obstructions in the drawings, there may be some useful or necessary elements that are well-known but are not shown in the drawings. DETAILED DESCRIPTION

[0063] The principles of the present invention, as illustrated in one or more embodiments, will be described herein in conjunction with a laterally diffused metal oxide semiconductor (LDMOS) device and a method for manufacturing the LDMOS device, which enhances high frequency performance without significantly compromising power and linearity performance. However, it should be understood that the present invention is not limited to the specific devices and / or methods illustratively listed herein. On the contrary, in view of the teachings herein, those skilled in the art will clearly recognize that many modifications may be made to the embodiments, and such modifications are within the scope of the present invention. That is, the embodiments herein are not intended to be, and should not be construed as, limitations of the present invention.

[0064] For the purpose of describing and protecting the embodiments of the present invention, the term MISFET that may be used herein should be broadly understood to include any type of metal-insulator-semiconductor field-effect transistor (metal-insulator-semiconductorfield-effect transistor). For example, the term MISFET may include semiconductor field-effect transistors (i.e., MOSFETs) that utilize oxide materials as gate dielectrics, as well as other semiconductor field-effect transistors that do not utilize oxide materials. In addition, although the term "metal" is mentioned in the abbreviations MISFET and MOSFET, MISFET and MOSFET also include semiconductor field-effect transistors whose gates are formed of non-metallic materials (e.g., polysilicon), in which case MISFET and MOSFET may be used interchangeably.

[0065] Although the overall manufacturing methods and structures formed in the present invention are novel, certain individual processing steps required to implement one or more portions of the methods of one or more embodiments of the present invention can utilize conventional semiconductor manufacturing techniques and conventional semiconductor manufacturing tools. These techniques and tools are well known to those skilled in the art. Furthermore, numerous existing publications describe numerous processing steps and tools for manufacturing semiconductor devices, including, for example, Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, by P.H. Holloway et al. (Cambridge University Press, 2008) and Processing and Properties of Compound Semiconductors, by R.K. Willardson et al. (Academic Press, 2001), which are incorporated herein by reference. It should be emphasized that although individual processing steps are described herein, these steps are illustrative only, and other equally suitable alternatives that may be familiar to those skilled in the art are also within the scope of the present invention.

[0066] It should be understood that the various layers and / or regions shown in the drawings are not necessarily drawn to scale. Furthermore, for economy of illustration, one or more semiconductor layers commonly used in integrated circuit devices may not be shown in the drawings. However, this does not necessarily mean that these semiconductor layers not explicitly shown will be omitted from actual integrated circuit devices.

[0067] Figure 1AA cross-sectional view of at least a portion of a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOSFET) device 100 is shown. The VDMOSFET device 100 includes a substrate 102, which may be formed of single-crystal silicon. The single-crystal silicon is modified by adding impurities or dopants (e.g., boron, phosphorus, arsenic, etc.) to change the conductivity of the material (e.g., N-type or P-type). In this conventional gate comparison example, the substrate 102 has an N conductivity type and is therefore referred to as an N-type substrate (N+SUB).

[0068] An epitaxial region 104 is formed on the upper surface of the substrate 102. In this conventional gate comparison example, the epitaxial region 104 has an N conductivity type (N-EPI) by adding impurities or dopants. In the VDMOSFET device 100, the epitaxial region 104 serves as a lightly doped drift region of the device. In this conventional gate comparison example, body regions 106 (P-BODY) having a P-type conductivity type are formed near the upper surface of the epitaxial region 104 and are spaced apart from each other in the laterally direction. The VDMOSFET device 100 also includes a source region 108 formed in at least a portion of each body region 106 and near the upper surface of the body region. Preferably, a conventional implantation process can be used to dope the source region 108 with impurities at a known concentration level, thereby selectively changing the conductivity of the material as needed. For example, the source region 108 is of N conductivity type (N+). A heavily doped region 110 formed near the upper surface of the body region 106 has the same conductivity type as the body region 106 (e.g., P-type in this example) and is laterally adjacent to the corresponding source region 108 to form a body region contact of the VDMOSFET device 100. Each of the source regions 108 is electrically connected to the corresponding body region contact 110.

[0069] In the VDMOSFET structure, the substrate 102 serves as the drain region of the device. A drain contact 112 formed on the back side of the substrate 102 provides electrical connection to the substrate / drain 102 .

[0070] A gate 114 is formed over at least a portion of the body region 106 and the epitaxial drift region 104 between the source region 108. A thin oxide layer 116 (e.g., silicon dioxide SiO2) is formed below the gate 114 as a gate oxide to electrically isolate the gate from the source region 108, the body region 106, and the epitaxial region 104 in the VDMOSFET device 100. Insulating spacers 118 are formed on the sides of the gate 114 and the gate oxide layer 116 to electrically isolate the gate from the source region 108. As is well known to those skilled in the art, a bias voltage applied to the gate forms a channel in the body region 106 below the gate to control current flow between the source region 108 and the substrate 102 serving as the drain region.

[0071] The VDMOSFET device 100 uses a planar gate structure on the surface of the device, which has the advantages of simple manufacturing process and good application reliability. However, the VDMOSFET design also has obvious disadvantages, including high on-resistance and large parasitic gate-drain capacitance (i.e., Miller capacitance), which makes this device unsuitable for high-power, high-frequency applications. ON Mainly due to the body region (P-body) channel resistance R BODY (also known as MOSFET channel resistance), junction field effect transistor (JFET) channel resistance R JFET and the epitaxial drift region resistance R EPI The combination of R ON =R BODY +R JFET +R EPI ). Among them, R EPI is the dominant factor (in a 100 V device, it accounts for 100% of the total on-resistance R ON about 50 percent or more).

[0072] Figure 1B for Figure 1A FIG. 1 is a cross-sectional view of at least a portion of an exemplary VDMOSFET device 100 in FIG. 1 , wherein parasitic gate-drain capacitance (eg, Miller capacitance) is shown. Figure 1B As shown, the larger parasitic gate-drain capacitance C gd This is mainly due to the large overlap between the gate 114 and the epitaxial drift region 104. This large parasitic gate-drain capacitance C gd Components can cause significant switching power losses in high-frequency applications and are therefore undesirable.

[0073] Efforts have been made to reduce the on-resistance of VDMOSFET devices, thereby improving conductivity. In particular, it is hoped that the channel density of the VDMOSFET device 100 can be increased by reducing the lateral spacing of the body regions 106. However, the junction field effect transistor effect caused by the narrower body region spacing increases the JFET resistance R between the body regions 106. JFET , thus offsetting the benefits of increased channel density, the MOSFET channel resistance R BODY and the JFET channel resistance R JFETSimilarly, although the JFET channel resistance can be reduced by increasing the doping concentration in the upper surface of the epitaxial region 104 (JFET region), this reduction in the JFET channel resistance will also lead to an undesirable reduction in the avalanche breakdown voltage when the device is in the off state. In this regard, there are also attempts to use a charge balancing method to balance the positive charge in the N-type epitaxial drift region 104 and the negative charge in the P-type body region 106 in the off state of the device, so as to increase the doping concentration of the epitaxial drift region 104, thereby reducing the drift region on-state resistance R EPI However, for a given size, the doping concentration is limited to a specific level, usually below 10 17 / cm 3 about.

[0074] Figures 2A to 2C Cross-sectional views of at least a portion of typical trench gate MOSFET devices 200, 230, and 250, respectively, showing reduced on-resistance and conceptually illustrating some of the effects of varying body region depth within the device. Figure 2A As shown, the trench gate MOSFET device 200 includes a substrate 202 , which may be formed of single crystal silicon formed by adding impurities or dopants having an N conductivity type, and thus may be referred to as an N-type substrate (N+SUB).

[0075] The epitaxial region 204 is formed on the upper surface of the substrate 202. In this example, the epitaxial region 204 has an N conductivity type (N-EPI) by adding impurities or dopants. Figure 1A Similar to the VDMOSFET device 100 shown in FIG, in the VDMOSFET device 200, the epitaxial region 204 serves as the lightly doped drift region of the device. In this embodiment, body regions (P-BODY) 206 having a P-type conductivity type are formed near the upper surface of the epitaxial region 204 and are spaced apart from each other in the laterally direction. The MOSFET device 200 also includes a source region 208 formed in at least a portion of each body region 206 and near the upper surface of the body region. Preferably, a conventional implantation process can be used to dope the source region 208 with impurities at a known concentration level to have an N-type conductivity type (N+). A heavily doped region 210 having a P-type conductivity type is formed near the upper surface of the body region 206 and is laterally adjacent to the corresponding source region 208 to form a source contact of the MOSFET device 200. Each of the source regions 208 is electrically connected to the corresponding body region contact 210.

[0076] and Figure 1ASimilar to the VDMOSFET device 100 shown, in this MOSFET device 200, the substrate 202 serves as the drain region of the device. A drain contact 212, preferably formed on the back side of the substrate / drain 202, provides electrical connection to the substrate / drain 202.

[0077] The MOSFET device 200 also includes a trench gate 214, which is formed of polysilicon through the upper surface of the epitaxial region 204 between the body region 206 and the source region 208. The trench gate 214 can be manufactured by forming a channel (i.e., a trench) partially through the epitaxial region 204 and between the body region 206 and the source region 208, and filling the channel with a dielectric material 216. The dielectric material is preferably an oxide, such as silicon dioxide. The trench gate 214 is then formed to partially pass through the dielectric material 216, extending vertically beyond the source region 208 and the body region 206. The thickness of the dielectric material 216 surrounding the sidewalls of the trench gate 214 is preferably just enough to prevent direct electrical contact between the trench gate 214 and the adjacent source region 208 and the body region 206.

[0078] and Figure 1A In contrast to the planar gate design of the VDMOSFET device 100, the trench gate MOSFET device 200 eliminates the JFET resistance factor R JFET However, the parasitic gate-drain (Miller) capacitance C gd Still very high. Figure 2B In the exemplary trench MOSFET device 230 shown, the gate-to-drain capacitance can be slightly reduced by increasing the thickness of the dielectric material 216 at the bottom of the trench. Figure 2A The device 200 shown in FIG is the same except that the depth of the body region 206 into the epitaxial drift region 204 is slightly reduced. Although the device 230 reduces the parasitic gate-drain capacitance C gd However, a weak point 232 is generated between the bottom corner of the polysilicon trench gate 214 and the epitaxial region 204 , which may lead to an undesirable decrease in the breakdown voltage of the device.

[0079] The difficulty of forming a channel in the body region 206 is further complicated by the fact that the depth of the body region in the epitaxial region 204 must be strictly controlled with respect to the depth of the trench gate 214. The body region 206 cannot be too shallow because Figure 2B As shown in the MOSFET device 230 shown, this can lead to a weak point 232 that breaks down prematurely at high blocking voltages. Figure 2CAs shown in the trench gate MOSFET device 250 in FIG, the body region 206 cannot be too deep in the epitaxial region 204, because this will increase the gate oxide thickness near the bottom of the trench gate 214, as is desired. Figure 2C 2. The thick oxide region 252 in the trench gate MOSFET device 250 reduces gate control of the channel formed in the body region 206, thereby making it difficult for the device to turn on; that is, the MOSFET device 250 will exhibit an undesirable increase in the device threshold voltage.

[0080] Figures 3A to 3C 3 and 4 are cross-sectional views of at least a portion of exemplary split trench gate MOSFET devices 300, 330, and 350, respectively. Figure 3A As shown, the split trench gate MOSFET device 300 includes a substrate 302, which can be formed of single crystal silicon. The single crystal silicon is formed by adding impurities or dopants with N conductivity type, and thus can be called an N-type substrate (N+SUB). An epitaxial region 304 is formed on the upper surface of the substrate 302. In this example, the epitaxial region 304 has an N conductivity type (N-EPI) by adding impurities or dopants. Figure 1A The VDMOSFET device 100 shown in FIG. Figure 2A Similar to the trench gate MOSFET device 200 shown in , in this MOSFET device 300, the epitaxial region 304 serves as a lightly doped drift region of the device. In this conventional gate comparative example, a body region (P-BODY) 306 having a P-type conductivity type is formed near the upper surface of the epitaxial region 304 and is spaced apart from each other in the lateral direction. The MOSFET device 300 also includes a source region 308 formed in at least a portion of each body region 306 and near the upper surface of the body region. Preferably, a conventional method of implanting N-type impurities can be used to form a source region 308 (N+) having an N-type conductivity type. In this embodiment, a heavily doped region 310 having a P-type conductivity type is formed near the upper surface of the body region 306 and is laterally adjacent to the corresponding source region 308 to form a body region contact of the MOSFET device 300. Thus, each of the source regions 308 is electrically connected to the corresponding body region contact 310.

[0081] and Figure 1A The VDMOSFET device 100 and Figure 2A Similar to the trench gate MOSFET device 200 shown in FIG, in the split trench gate MOSFET device 300, the substrate 302 serves as the drain region of the device. A drain contact 312 formed on the back side of the substrate / drain 302 provides electrical connection to the substrate / drain 302.

[0082] The MOSFET device 300 also includes a dielectric trench 314 filled with a dielectric material (e.g., silicon dioxide). The dielectric trench 314 extends vertically in the epitaxial region 304 and between the body region 306 and the source region 308. A trench gate 316, which may include polysilicon, is formed in the dielectric trench 314. The depth of the trench gate 316 is just below the bottom of the body region 306. A shield gate 318 is also formed in the trench 314 and is located vertically below the trench gate 316. The shield gate 318 is electrically isolated from the trench gate 316 and the epitaxial region 304 by the dielectric material in the dielectric trench 314. In this comparative example, the trench gate 316 is slightly wider than the shield gate 318, so that the shield gate is surrounded by a thicker layer of dielectric material than the trench gate. Preferably, the shield gate 318 is connected to the source region 308.

[0083] In the MOSFET device 300, the shield gate 318 helps to reduce the parasitic gate-drain capacitance C gd , and improve the off-state blocking voltage. However, any improvements offered by this split-trench gate MOSFET design only apply when the device is in the off-state; that is, when the maximum doping concentration is determined by the device's required breakdown voltage, there is essentially no improvement in on-state performance. Split-trench gate designs face similar difficulties in precisely controlling the depth and thickness of body region 306.

[0084] For example, Figure 3B The split trench gate MOSFET device 330 is shown with a shallow body region 306. Figure 2B As illustrated, the shallow body region 306 in the MOSFET device 330 creates a weak point region 332 near the bottom corner of the trench gate 316 , which can lead to premature breakdown of the device at high blocking voltages.

[0085] same, Figure 3C A split trench gate MOSFET device 350 is shown with a deep body region 306 such that the bottom of the body region extends below the bottom of the trench gate 316. Figure 2C As described, the deep body region 306 in the MOSFET device 350 forms a thick oxide region 352 near the bottom corner of the trench gate 316. The thick oxide region 352 reduces the gate control of the channel formed in the body region 306, thereby increasing the threshold voltage of the device and making it difficult for the device to turn on.

[0086] As shown in one or more comparative examples, the present inventors have attempted to exploit the beneficial properties of planar gate and trench gate structures to provide MOSFET devices having what is herein referred to as a supergate structure, which advantageously achieves enhanced high frequency performance without significantly degrading power and linearity performance in the device. Figure 4A and4B 1 and 2 are perspective and cross-sectional views of at least a portion of a supergate MOSFET device 400 according to a comparative example of the present invention (see CN112614891A for details).

[0087] The MOSFET device 400 includes a substrate 402, which can be formed of single crystal silicon (e.g., with a <100> or <111> crystal orientation). The single crystal silicon is formed into a desired conductivity type (e.g., N-type or P-type) and doping level by adding impurities or dopants (e.g., boron, phosphorus, arsenic, antimony, etc.). A P-type substrate can be formed by adding a specified concentration level (e.g., about 10 per cubic centimeter) to the substrate material. 14 to about 10 18 The substrate 402 may be formed by adding p-type impurities or dopants (e.g., group III elements such as boron) with a predetermined concentration of p-type impurities or dopants (e.g., group III elements such as boron) to the substrate material, for example, by diffusion or implantation processes to change the conductive properties of the material as needed. In other embodiments, an N-type substrate may be formed by adding N-type impurities or dopants (e.g., group V elements such as phosphorus) to the substrate material at a predetermined concentration level. In this embodiment, the substrate 402 is doped to have an N-type conductivity type and may therefore be referred to as an N-type substrate (N+SUB). Similar other materials that may be used to form the substrate 402 include, but are not limited to, germanium, gallium arsenide, silicon carbide, gallium nitride, indium phosphide, and the like.

[0088] The epitaxial region 404 is formed on the upper surface of the substrate 402. In this supergate comparative example, the epitaxial region 404 has an N-conductivity type (N-EPI) by adding impurities or dopants. Similarly, P-type epitaxy (for example, by adding P-type dopants) can also be considered. Figure 1A The VDMOSFET device 100 and Figure 2A Similar to the trench gate MOSFET device 200 shown in FIG, in this MOSFET device 400, the epitaxial region 404 serves as a lightly doped drift region of the device. In this embodiment, a body region (P-BODY) 406 having a P-type conductivity type is formed near the upper surface of the epitaxial region 404 and is spaced apart from each other in the lateral direction. The body region 406 in this embodiment can be formed by implanting P-type impurities (e.g., boron) into a designated area of ​​the epitaxial region 404 using standard complementary metal oxide semiconductor (CMOS) manufacturing technology. Relative to the doping level of the substrate, the body region 406 is preferably doped more heavily, for example, about 5×10 16 atoms / cm3 (cm 3 ) to about 1×10 18 atoms / cm 3 In one or more alternative embodiments employing P-type epitaxial regions, body region 406 may include an N-type well formed using CMOS-like fabrication techniques.

[0089] The MOSFET device 400 also includes a source region 408 formed in at least a portion of each body region 406 and proximate to the upper surface of the body region. Preferably, the source region 408 is doped with an impurity having a conductivity type opposite to that of the body region 406. In this supergate comparative example, the source region 408 is of N-type conductivity (N+). In this supergate comparative example, a heavily doped region 410 having P-type conductivity is formed proximate to the upper surface of the body region 406 and laterally adjacent to the corresponding source region 408, thereby forming a body region contact of the MOSFET device 400. A corresponding source (S) electrode 412 electrically connects each source region 408 to the corresponding body region contact 410.

[0090] and Figure 1A Similar to the VDMOSFET device 100 shown, in this MOSFET device 400, the substrate 402 serves as the drain region of the device. A drain (D) electrode 414 is preferably formed on the backside of the substrate / drain 402, providing an electrical connection to the substrate / drain. Unlike standard lateral MOSFET devices, where both the drain and source electrodes are formed on the top surface of the device, the drain contact 414 of this MOSFET device 400 is formed on the bottom surface of the device, opposite the source electrode 414. In other words, the drain electrode 414 and the source electrode 412 are distributed on two opposite surfaces in the vertical direction of the MOSFET device 400.

[0091] The MOSFET device 400 also includes a gate structure, which includes at least two parts, a planar gate (G1) 416 and a trench gate (G2) 418. In the illustration of the supergate comparative example, two planar gates 416 are respectively arranged on both sides of the trench gate 418. The planar gate 416 and the trench gate 418 are preferably formed into a comb (strip) structure that is physically isolated from each other, even if the planar gate and the trench gate are electrically connected at one end or both ends of their strip structures (not shown in the figure, but the meaning is clear). In one or more alternative embodiments, the planar gate 416 and the trench gate 418 can form a connected gate structure having the functions of a planar gate and a trench gate, which will be combined below. Figure 6 Described in further detail.

[0092] In one or more supergate embodiments, a trench gate 418, which may include polysilicon, is formed substantially vertically through the upper surface of the epitaxial region 404 between the body region 406 and the source region 408, such that there is a source region 408 on both sides of the trench gate 418. More specifically, the trench gate 418 can be fabricated by forming an opening (e.g., a trench or a groove) partially through the epitaxial region 404 and between the body region 406 and the source region 408, and filling the opening with a dielectric material 420. In one or more supergate embodiments, the dielectric material 420 is an oxide, such as silicon dioxide, however, the present invention is not limited to any particular electrically insulating material. The trench gate 418 is then formed partially through the dielectric material 420 and extends vertically below the source region 408 and the body region 406. Thus, the dielectric material 420 electrically isolates the trench gate 418 from the surrounding epitaxial region 404 , thereby preventing direct electrical contact between the trench gate 418 and the adjacent source region 408 and body region 406 . Therefore, the dielectric material 420 may be referred to as a trench gate oxide layer.

[0093] In one or more embodiments, each planar gate 416 is disposed on the upper surface of the epitaxial region 404 and overlaps at least a portion of the corresponding body region 406. A dielectric layer 422 is formed between each planar gate 416 and the body region 406 and the upper surface of the epitaxial region 404 to electrically isolate the planar gate 416 from the body region and the epitaxial region, and thus may be referred to as a planar gate oxide layer. Figure 4A Not explicitly shown, such as Figure 4B As shown, dielectric spacers 424 are preferably formed on the sidewalls of the planar gate 416 and a portion of the sidewalls of the trench gate 418 extending above the upper surface of the epitaxial layer 404. Figure 4B As shown, the gate spacer 424 electrically isolates the planar gate from the trench gate and electrically isolates the planar gate 416 from the corresponding source electrode 412 .

[0094] Continue to refer Figure 4B The MOSFET device 400 further includes a first gate electrode 426 electrically connected to the planar gate 416, and a second gate electrode 428 electrically connected to the trench gate 418. The gate electrodes 426 and 428 can be implemented by forming a metal silicide layer on at least a portion of the upper surface of the gates 416 and 418, respectively. As known to those skilled in the art, in the gate silicidation process, a metal film (e.g., titanium, tungsten, platinum, cobalt, nickel, etc.) is deposited on the upper surface of the polysilicon gate, and annealing is performed to cause the deposited metal film to react with the silicon in the polysilicon gate, ultimately forming a metal silicide contact.

[0095] When a positive bias voltage exceeding the threshold voltage is applied to the N-channel MOSFET device, for example, by applying a positive voltage between the planar gate 416 and the corresponding source region 408, a channel is formed in the body region 406 under the planar gate, thereby turning on the MOSFET device 400. At the same time, since the trench gate 418 is electrically connected to the planar gate 416, a positive bias voltage will be applied to the trench gate, thereby Figure 4C As shown, a strong accumulation layer 430 having majority carriers (e.g., electrons in this embodiment) is formed near the surface of the trench gate oxide layer 420 in the epitaxial region 404. This accumulation layer 430 beneficially increases the conductance of the MOSFET device 400, which enables the device to achieve a very low on-resistance, for example, about 2 milliohm-square millimeter (2mΩ-mm2) at a blocking voltage rating of 30 volts. 2 As will be described below, the supergate MOSFET device 400 achieves substantial performance improvements compared to conventional planar gate and trench gate devices.

[0096] Figure 5 Conceptual description of the characteristic on-resistance R of three different types of MOSFET devices sp The proportional relationship between (ohm-square centimeter) and breakdown voltage (volts). Specifically, reference numeral 502 represents the relationship with Figure 2A The trench gate MOSFET device 200 shown in FIG. 1 has a characteristic on-resistance R of the trench gate MOSFET device. sp The proportional relationship between the breakdown voltage and the breakdown voltage. Figure 3A The ratio between the characteristic on-resistance Rsp and the breakdown voltage of the split trench gate MOSFET device 300 shown in FIG. 506 represents a supergate MOSFET device (e.g., Figure 4A The characteristic on-resistance R of the supergate MOSFET device 400 shown in FIG. sp The proportional relationship between the breakdown voltage and the on-resistance. Ideally, a MOSFET device would exhibit a high breakdown voltage and a low characteristic on-resistance. However, in practice, device characteristics are often contradictory. That is, a MOSFET device with a very low on-resistance will also have a very low breakdown voltage, and vice versa, as shown in the trench gate and split trench gate MOSFET devices denoted by reference numerals 502 and 504, respectively.

[0097] like Figure 5As shown, the supergate MOSFET device (labeled 506) formed according to the supergate comparative embodiment of the present invention has at least two obvious advantages compared to the trench gate MOSFET device (labeled 502) or the split trench gate MOSFET device (labeled 504). First, compared to 502 and 504, the characteristic on-resistance R sp The slope of the proportional relationship 506 with the breakdown voltage is significantly reduced, that is, compared with a trench gate MOSFET device or a split trench gate MOSFET device with the same rated breakdown voltage, the super MOSFET device has a significantly smaller characteristic on-resistance. As a result, the chip size can be scaled down proportionally to the chip size, further resulting in a significant reduction in parasitic gate capacitance and gate-to-drain capacitance.

[0098] Typically, the capacitance C of a parallel plate capacitor is determined by the following formula:

[0099]

[0100] Wherein, ε0 is the absolute dielectric constant (i.e., the dielectric constant of vacuum ε0 = 8.854×10-12 F / m), εr is the relative dielectric constant of the medium or dielectric material between the parallel plates, A is the surface area of ​​one side of each parallel plate, and d is the distance between the parallel plates (i.e., the thickness of the dielectric material between the parallel plates). Therefore, by reducing the chip size, the surface area of ​​one or both parallel plates of parasitic gate capacitance and / or parasitic gate-drain capacitance can be reduced. Reducing parasitic gate capacitance and gate-to-drain capacitance is beneficial to reducing switching losses in high-frequency applications (e.g., synchronous DC-DC converters).

[0101] Continue to refer Figure 5 As shown by the trapezoidal shape of label 506, a second significant advantage of the supergate MOSFET device of the comparative example of the present invention is that the supergate MOSFET device is able to adjust the characteristic on-resistance during device operation, while conventional MOSFET devices have a fixed characteristic on-resistance. This is mainly because in conventional MOSFET designs, the doping concentration, and its associated carrier concentration, is fixed after the device is manufactured. In contrast, in the supergate MOSFET device of one or more embodiments of the present invention, the carrier concentration is not fixed, but depends on the bias applied to the trench gate structure and can be easily adjusted. This brings many benefits, including providing greater flexibility in device design, a wider process window, and providing higher reliability for the operation of the supergate MOSFET device.

[0102] Figure 6FIG1 is a perspective view of at least a portion of a typical supergate MOSFET device 600 shown as another comparative example of the present invention. More specifically, the supergate MOSFET device 600 is Figure 4A and 4B The typical supergate MOSFET device 400 shown in FIG is similar to the typical supergate MOSFET device 400 shown in FIG, except that the MOSFET device 600 includes a simplified gate design that replaces the planar gate ( Figure 4B 416) and trench gate ( Figure 4B 418) are combined together to form a T-shaped gate 602 having planar gate and trench gate functions in the MOSFET device 600. Specifically, the gate 602 includes a planar gate portion 604 and a trench gate portion 606 as connected structures.

[0103] The trench gate portion 606 is located between the two body regions 406 and extends at least partially vertically into the epitaxial region 404. The trench gate portion 606 in the supergate comparative embodiment of the present invention is not limited to any particular size, but the depth of the trench gate portion 606 is preferably about 1-2 microns (μm). The planar gate portion 604 begins at the trench gate portion 606 and extends along the upper surfaces of the epitaxial region 404 and the body region 406 in two opposite lateral directions (i.e., horizontal directions) to the edge of the corresponding source region 408. An insulating layer 608 is formed under the gate 602 to electrically isolate the gate from adjacent structures and regions. Preferably, a dielectric spacer 610 is provided on the sidewalls of the gate 602 to prevent electrical contact between the gate and the source electrode 412.

[0104] The planar gate and trench gate portions 604 and 606 preferably operate in the same manner as the planar gate 416 and trench gate 418, respectively, of the exemplary MOSFET device 400 in FIG. 4 b. More specifically, by applying a gate bias signal between the gate 602 and the source region 408 that is greater than the threshold voltage of the MOSFET device 600, each planar gate portion 604 induces the formation of a channel in the corresponding body region 406 directly beneath the planar gate portion; when the applied gate bias signal is below the device threshold voltage, the channel is essentially closed. Simultaneously, the applied gate bias signal causes the trench gate portion 606 to form a strong accumulation layer 612 containing majority carriers and having the profile of the trench gate portion near the gate oxide layer 608. As previously described, even with only a narrow space between the body regions 406, this strong accumulation layer 612 can increase the conductance of the MOSFET device 600, thereby reducing the on-resistance of the device. Connecting the gate 602 to the source electrode 412 closes the channel within the body region 406 , thereby turning off the MOSFET device 600 .

[0105] By way of example only, and not limitation, Figures 7A to 7I Shown Figure 4B Schematic cross-sectional view of an exemplary manufacturing process of at least a portion of a super MOSFET device according to a comparative embodiment of the present invention.

[0106] refer to Figure 7A As shown, the exemplary fabrication process begins with substrate 702. In one or more embodiments, substrate 702 comprises single crystal silicon or other alternative semiconductor materials, such as, but not limited to, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium nitride, etc. In this illustrative embodiment, substrate 702 is doped with N-type impurities or dopants (e.g., phosphorus) to form an N-type conductive type substrate (N+SUB). P-type conductive type substrates are also contemplated in embodiments of the present invention. Substrate 702 is preferably cleaned and surface treated.

[0107] An epitaxial layer 704 is then formed on the upper surface of the substrate 702, for example, by an epitaxial growth process. In one or more embodiments, the epitaxial layer has an N-type conductivity (N-EPI), although a similar P-type epitaxial layer may also be used. The doping concentration of the epitaxial layer 704 is preferably lower than the doping concentration of the substrate 702.

[0108] like Figure 7B As shown, a hard mask layer 706 is formed on the surface of the epitaxial layer 704. In one or more embodiments, the hard mask layer 706, which may include silicon nitride, is preferably formed using a standard deposition process. The hard mask layer 706 is then patterned (e.g., using standard photolithography and etching) and etched to form a trench 708 at least partially located in the epitaxial layer 704. In one or more supergate comparative embodiments, the trench 708 may be formed using reactive ion etching (RIE). Subsequently, as shown in FIG. Figure 7C As shown, a first dielectric layer 710 is formed on the inner walls (e.g., sidewalls and bottom) of the trench 708. In one or more embodiments, the first dielectric layer 710 can be an oxide layer. Although the supergate comparative embodiment of the present invention is not limited to any specific dielectric material, in one or more embodiments, the first dielectric layer 710 includes silicon dioxide formed using a dry or wet oxidation process. The first dielectric layer 710 will form the gate oxide (e.g., Figure 4A 418 in the ).

[0109] Now refer to Figure 7D , for example, by removing the hard mask layer ( Figure 7C706 in FIG). Then, a second dielectric layer 711 is formed on the upper surface of the epitaxial layer 704. In one or more embodiments, the second dielectric layer 711 may be an oxide layer. The second dielectric layer 711 will form the gate oxide of the planar gate of the supergate MOSFET device (e.g., Figure 4A 416). Usually, a chemical reaction between oxygen and silicon is driven by a high temperature environment (e.g., about 800 degrees Celsius (°C) to 1200°C) to produce silicon dioxide to form the first and second dielectric layers 710, 711; however, even at room temperature, a thin layer (e.g., about 1-3 angstroms) can be formed in the ambient environment. ) native oxide. To grow thicker oxides in a controlled environment, several known methods can be used, such as oxidation by in-situ steam generation or a remote plasma source (e.g., remote plasma oxidation (RPO)).

[0110] Next, if Figure 7E As shown, a gate structure including a planar gate 712 and a trench gate 714 is formed. The planar gate and trench gate 712, 714 preferably comprise polysilicon and are formed using a standard deposition process, followed by patterning (e.g., using standard photolithography and etching) and etching. In this supergate comparative embodiment, a planar gate 712 is provided on each side of the trench gate 714. Although in Figure 7E It is not explicitly shown in the figure, but the planar gate 712 and the trench gate 714 preferably form a comb-like (i.e., strip-like) structure that is structurally separated from each other, in which the planar gate and the trench gate are electrically connected at one end or both (opposite) ends of the strip. In one or more alternative embodiments, the planar gate 712 and the trench gate 714 can form a combination as described above. Figure 6 The connected structure has the functions of a planar gate and a trench gate.

[0111] like Figure 7F As shown, a standard selective etching process is used to remove the second dielectric layer ( Figure 7E The exposed portion of the second dielectric layer 711 (i.e., the portion of the second dielectric layer not covered by the planar gate 712 and the trench gate 714) is removed. A self-aligned body region 716 is then formed in the epitaxial layer 704 near the upper surface of the epitaxial layer. In this exemplary supergate comparative embodiment, the body region 716 is preferably formed by implanting a P-type dopant at a prescribed concentration level into the epitaxial layer 704 and then performing a thermal treatment (e.g., annealing) to drive the dopant into the epitaxial layer.

[0112] Optional, in Figure 7FIn the illustrated supergate comparative embodiment, the implanted region 718 is preferably formed in the epitaxial layer 704, near the upper surface of the epitaxial layer, and between the body region 716 and the trench gate 714. In one or more supergate comparative embodiments, the implanted region 718 is formed by implanting N-type dopants at a specified concentration level into the epitaxial layer 704 between the planar gate 712 and the trench gate 714. During the implantation process, the planar gate and the trench gate act as masks. Preferably, the implanted region 718 is used to increase the N-type doping concentration level at the edge of the channel formed in the body region 716, thereby reducing the on-resistance of the MOSFET device. The implanted region 718 can also limit the channel region under the gate 712, thereby improving high frequency performance. Although embodiments of the present invention are not limited to any particular doping concentration, in one or more embodiments, the implanted region 718 preferably has a doping concentration of approximately 1×10 16 to 1×10 18 atoms / cubic centimeter.

[0113] like Figure 7G As shown, dielectric spacers 720 are then formed on the sidewalls of the planar gate 712 and the trench gate 714. Although the present invention is not limited to any particular dielectric material, in one or more supergate comparative embodiments, the dielectric spacers 720 may include silicon dioxide or silicon nitride. An etching process is then used to create the desired patterning to form source region contacts (e.g., N-type) and body region pickup contacts (e.g., P-type) in the device.

[0114] exist Figure 7H In the embodiment, the source regions 722 are formed in the corresponding body regions 716 near the upper surface of the body regions and the self-aligned planar gate 712. In this exemplary comparative embodiment, the source regions 722 having an N conductivity type are formed using, for example, a standard implantation process (e.g., ion implantation). In this comparative embodiment, heavily doped regions 724 having a P conductivity type are formed near the upper surface of the body regions 716 and laterally adjacent to the corresponding source regions 722 to form the body region contacts of the supergate MOSFET device. Therefore, each source region 722 is electrically connected to a corresponding body region contact 724.

[0115] Now refer to Figure 7I, using a standard front-end silicidation process, metal silicide contacts 726 are formed on the source region 722, and metal silicide contacts 728 and 730 are formed on the planar gate and trench gate, respectively. As is well known, in the silicidation process, a layer of metal is first deposited on the upper surface of the wafer, and then heat treated (e.g., thermal annealing) is performed to form an alloy (metal silicide) at the location where the metal contacts the exposed silicon. The unreacted metal is then removed using, for example, a standard etching process to form a low-resistance silicide at the source and gate contacts. Metal (e.g., aluminum) is then used for front-end interconnection and passivation, and dielectric deposition and patterning are performed in the front-end-of-line (FEOL) process. After the FEOL process, the wafer is flipped for backside thinning (e.g., using chemical mechanical polishing, CMP) and backside metallization to form the drain contact 732 of the supergate MOSFET device.

[0116] Figure 8 FIG. 8 is a cross-sectional view of at least a portion of a supergate MOSFET device 800 according to a comparative embodiment of the present invention. Figure 4B The supergate MOSFET device 400 is similar to the supergate MOSFET device 400 shown in FIG. , except that its gate structure is configured to have enhanced voltage blocking capability. Figure 8 As shown, supergate MOSFET device 800 includes a substrate 802, which can be formed of single crystal silicon modified by adding impurities or dopants (such as boron, phosphorus, arsenic, antimony, etc.) having a desired conductivity type (N-type or P-type) and doping level. In this exemplary embodiment, substrate 802 is doped to have an N conductivity type and can therefore be referred to as an N-type substrate (N+SUB). Other materials can also be considered to form substrate 802, such as, but not limited to, germanium, gallium arsenide, silicon carbide, gallium nitride, indium phosphide, etc.

[0117] An epitaxial region 804 is formed on the upper surface of the substrate 802. In this supergate comparative example, the epitaxial region 804 is formed by adding N-conductivity type impurities or dopants (N-EPI). Of course, P-type epitaxy can also be considered. In the MOSFET device 800, the epitaxial region 804 serves as a lightly doped drift region of the device. In this embodiment, two body regions (P-BODY) 806 with P-type conductivity are formed near the upper surface of the epitaxial region 804 and are spaced apart from each other in the lateral direction. The body region 806 in this embodiment can be formed by implanting P-type impurities (e.g., boron) into a designated area of ​​the epitaxial region 804 using standard complementary metal oxide semiconductor (CMOS) manufacturing technology.

[0118] The source region 808 is formed in at least a portion of the corresponding body region 806 and near the upper surface of the body region. Preferably, in the exemplary MESFET device 800, the source region 808 has an N-type conductivity type. In this supergate comparative embodiment, a heavily doped region 810 formed near the upper surface of the body region 806 and laterally adjacent to the corresponding source region 808 has a P-type conductivity type, thereby forming a body region contact of the MOSFET device 800. A corresponding source (S) electrode 812 electrically connects each source region 808 to the corresponding body region contact 810.

[0119] In the supergate MOSFET device 800, the substrate 802 serves as the drain region of the device. Accordingly, for example, in the back-end-of-line (BEOL) process, a drain (D) electrode 814 is preferably formed on the back side of the substrate / drain 802 to provide electrical connection to the substrate / drain. Figure 4B Similar to the MOSFET device 400 shown in the figure, the drain electrode 814 is formed on the back side of the MOSFET device 800, which is located on the side opposite to the source electrode 812 formed on the upper / front surface of the device. That is, the drain electrode 814 and the source electrode 812 are distributed on two opposite surfaces in the vertical direction of the MOSFET device 800.

[0120] The MOSFET device 800 also includes a gate structure comprising at least two parts, a planar gate (G1) 816 and a trench gate (G2) 818. In the illustration of the comparative example of the supergate of the present invention, two planar gates 816 are respectively arranged on either side of the trench gate 818. The planar gate 816 and the trench gate 818 are preferably formed into a comb-like (strip-like) structure that is structurally separated from each other, that is, the planar gate and the trench gate are electrically connected at one or both ends of their strip structures (not explicitly shown in the figure, but implied). In one or more alternative embodiments, the planar gate 816 and the trench gate 818 can form a connected gate structure having the functions of a planar gate and a trench gate.

[0121] In one or more embodiments, a trench gate 818, which may include polysilicon, may be generally formed vertically through the upper surface of the epitaxial region 804 located between the body regions 806 and between the source regions 808, such that there is a source region 808 on both sides of the trench gate 818. The MOSFET device 800 also includes a dielectric layer 820 that electrically isolates the trench gate 818 from the surrounding epitaxial region 804, thereby preventing direct electrical contact between the trench gate 818 and the adjacent source regions 808 and body regions 806. In one or more supergate comparative embodiments, the dielectric layer 820 includes an oxide, such as silicon dioxide, and may be referred to as a trench gate oxide layer, however, the embodiment is not limited to any particular electrically insulating material.

[0122] In one or more comparative embodiments, each planar gate 816 is disposed on the upper surface of the epitaxial region 804, with at least a portion thereof overlapping the corresponding body region 806. A second dielectric layer 822 is formed between each planar gate 816 and the body region 806 and the upper surface of the epitaxial region 804 to electrically isolate the planar gate 816 from the body region and the epitaxial region, and thus may be referred to as a planar gate oxide layer. Dielectric spacers 824 are preferably formed on the sidewalls of the planar gate 816 and the sidewalls of the trench gate 818. The gate spacers 824 electrically isolate the planar gate from the trench gate and electrically isolate the planar gate 816 from the corresponding source electrode 812.

[0123] Continue to refer Figure 8 The supergate MOSFET device 800 further includes a first gate electrode 826 connected to the planar gate 816, and a second gate electrode 828 connected to the trench gate 818. The gate electrodes 826 and 828 can be implemented by forming a metal silicide layer on at least a portion of the upper surface of the gates 816 and 818, respectively.

[0124] In order to optimize the voltage blocking capability of the supergate MOSFET device 800, the trench gate structure is preferably configured with a trench gate oxide layer 820, and the portion of the trench gate oxide layer 820 located at the lower portion 830 of the trench gate structure is thicker than the portion located at the upper portion 832 of the trench gate structure. Although the supergate comparative embodiments of the present invention are not limited to any particular dimensions, in one or more supergate comparative embodiments, the thickness of the trench gate oxide layer 820 at the upper portion 832 of the trench gate structure is approximately 10-50nm, while the thickness of the trench gate oxide layer at the lower portion 830 of the trench gate structure is approximately 50-500nm. The planar gate oxide layer 822 under each planar gate (G1) 816 is preferably around 5-50nm. The following is combined with Figures 9A to 9L , illustratively introduces a method for configuring a supergate MOSFET device having a trench gate structure.

[0125] Specifically, Figures 9A to 9L for Figure 8 The super grid comparative example of the present invention is shown Figure 8 A schematic cross-sectional view of a process for fabricating at least a portion of a supergate MOSFET device 800 in the illustrated embodiment. Figure 9AAs shown, the exemplary fabrication process begins with a substrate 902. In one or more embodiments, the substrate 902 comprises single crystal silicon or other alternative semiconductor materials, such as, but not limited to, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium nitride, etc. In this illustrative embodiment, the substrate 902 is doped with N-type impurities or dopants (e.g., phosphorus) to form an N-type conductive type substrate (N+SUB). P-type conductive type substrates are also contemplated for use in comparative supergate embodiments of the present invention. The substrate 902 is preferably cleaned and surface treated.

[0126] An epitaxial layer 904 is then formed on the upper surface of the substrate 902, for example, by epitaxial growth. In one or more embodiments, the epitaxial layer has an N-type conductivity (N-EPI), although a similar P-type epitaxial layer may also be used. The doping concentration of the epitaxial layer 904 is preferably lower than the doping concentration of the substrate 902.

[0127] like Figure 9B As shown, a hard mask layer 906 is formed on the surface of the epitaxial layer 904. In one or more embodiments, a standard deposition process is preferably used to form the hard mask layer 906, which may include silicon nitride. The hard mask layer 906 is then patterned using, for example, standard photolithography and etching, and a trench 908 is formed at least partially in the epitaxial layer 904 using, for example, an etching process. In one or more supergate comparative embodiments, reactive ion etching (RIE) may be used to form the trench 908. Subsequently, as shown in FIG9 c, the hard mask layer 906 is removed using, for example, etching.

[0128] The manufacturing process of the supergate MOSFET device 800 begins with the following two steps: Figure 7A and 7B Described in Figure 4B The fabrication process of the exemplary supergate MOSFET device 400 shown is the same. Figure 9D , forming an insulating layer 910 in the trench 908 and on at least a portion of the upper surface of the epitaxial layer 904. In one or more embodiments, the insulating layer 910 comprises an oxide (e.g., silicon dioxide) grown or deposited in the trench 908 and on the upper surface of the epitaxial layer 904. Figure 9E As shown, an etch-back process, such as wet etching, is used to remove the insulating layer 910 on the upper surface of the epitaxial layer 904 and the insulating layer 910 on a portion of the sidewalls in the trench 908, allowing a portion of the insulating layer 910 to remain at the bottom of the trench, as shown in FIG. Figure 9F As shown, the wafer is subjected to a thermal oxidation process to form a relatively thin conformal gate oxide layer 912. Although the supergate comparison example of the present invention is not limited to any specific dimensions, in one or more embodiments, the thickness of the oxide layer 912 on the upper surface of the epitaxial layer 904 and on the sidewalls of the trench 908 is about 30-50 nm.

[0129] like Figure 9G As shown, in one or more supergate comparative embodiments, a narrow trench 914 is formed in the insulating layer 910 using anisotropic etching (eg, RIE). Figure 9H As shown, a thin gate oxide layer 916 (eg, about 30-50 nm) is grown on the upper portion of the sidewalls of the first trench 908 and the upper surface of the epitaxial layer 904. Figure 9I As shown, a gate structure including a planar gate 918 and a trench gate 920 is formed. Each planar gate and trench gate 918, 920 preferably comprises polysilicon and is formed using a standard deposition process, followed by patterning (e.g., using standard photolithography and etching) and etching. In this embodiment, a planar gate 918 is provided on each side of the trench gate 920. Although in Figure 9I Although not explicitly shown, the planar gate 918 and the trench gate 920 preferably form a comb-like (i.e., strip-like) structure that is structurally separated from each other, in which the planar gate and the trench gate are electrically connected at one end or both (opposite) ends of the strip.

[0130] Now refer to Figure 9J As shown, a selective etching process is used to remove the gate oxide layer ( Figure 9I The exposed portion of the gate oxide layer 916 (i.e., the portion of the gate oxide layer not covered by the planar gate 918 and the trench gate 920) is removed. A self-aligned body region 922 is then formed in the epitaxial layer 904 near the upper surface of the epitaxial layer. In this exemplary embodiment, the body region 922 is preferably formed by implanting a P-type dopant at a specified concentration level into the epitaxial layer 904 and then performing a thermal treatment (e.g., annealing) to drive the dopant into the epitaxial layer.

[0131] Optional, in Figure 9J In the illustrated supergate comparative embodiment, the implant region 924 is preferably formed in the epitaxial layer 904, close to the upper surface of the epitaxial layer, and located between the body region 922 and the trench gate 920. In one or more embodiments, the implant region 924 is formed by implanting N-type dopants at a predetermined concentration level into the epitaxial layer 904 between the planar gate 918 and the trench gate 920. During the implantation process, the planar gate and the trench gate serve as masks. Figure 7FThe implanted region 924 is similar to the implanted region 718 shown in FIG. , and preferably, the implanted region 924 is used to increase the N-type doping concentration level at the edge of the channel formed in the body region 922, thereby reducing the on-resistance of the MOSFET device. The implanted region 924 can also limit the channel area under the gate 918, thereby improving high-frequency performance. Although the embodiments of the present invention are not limited to any particular doping concentration, in one or more embodiments, the implanted region 924 preferably has a doping concentration of approximately 1×10 16 to 1×10 18 atoms / cubic centimeter.

[0132] like Figure 9K As shown, dielectric spacers 926 are then formed on the sidewalls of the planar gate 918 and the trench gate 920. Although the present invention is not limited to any particular dielectric material, in one or more embodiments, the dielectric spacers 926 may include silicon dioxide. An etching process is then used to create the desired patterning to form source region contacts (e.g., N-type) and body region contacts (e.g., P-type) in the device.

[0133] exist Figure 9L In the embodiment, source regions 928 are formed in the corresponding body regions 922 near the upper surface of the body regions and the self-aligned planar gate 918. In the present exemplary embodiment, the source regions 928 having an N conductivity type are formed using, for example, a standard implantation process (e.g., ion implantation). In the supergate comparative embodiment, heavily doped regions 930 having a P conductivity type are formed near the upper surface of the body regions 922 and laterally adjacent to the corresponding source regions 928 to form the body region contacts of the supergate MOSFET device. Therefore, each source region 928 is electrically connected to a corresponding body region contact 930.

[0134] A standard front-end silicide process is used to form metal silicide contacts (812) on the source region 928, and metal silicide contacts (826 and 828) are formed on the planar gate 918 and the trench gate 920, respectively. Metal (such as aluminum, etc.) is then used for front-end interconnection and passivation, and dielectric deposition and patterning are performed in the front-end-of-Tine (FEOL) process. After the FEOL process, the wafer is flipped for backside thinning (e.g., CMP) and backside metallization to form a drain contact (814), thereby forming Figure 8 A supergate MOSFET device 800 is shown.

[0135] Figure 10 FIG. 1 is a cross-sectional view of at least a portion of a supergate MOSFET device having an enhanced source contact in another supergate comparative embodiment of the present invention. Figure 4BThe supergate MOSFET device 400 shown in FIG is identical except for the source contact. Specifically, as shown in FIG. Figure 10 As shown, the supergate MOSFET device 1000 includes an embedded source contact 1002 formed in the corresponding body region 406, the source contact 1002 being close to the upper surface of the body region and electrically connected to the adjacent source region 408. In one or more embodiments, each embedded source contact 1002 includes a metal, such as tungsten, although, of course, embodiments of the present invention are not limited to tungsten. This source contact structure provides a larger contact area between the source metal and the source region 408, thereby helping to reduce the resistance of the source contact. It is satisfying that this source contact structure can be used with any supergate MOSFET device structure described herein, and it is obvious to those skilled in the art based on this revelation. Although not described in Figure 10 It is clearly shown in the figure, but metal silicide can also be formed around the embedded source contact 1002 using the same metal silicide process as that used to form the planar gate and trench gate contacts 426 and 428. For those skilled in the art, this solution will also be obvious based on this revelation.

[0136] Compared to standard MOSFET device designs, the MOSFET devices of the supergate comparative embodiments of the present invention achieve superior performance. For example, Figure 11 Compared with the standard MOSFET device (labeled 1104), the supergate MOSFET device (labeled 1102), e.g. Figure 4B Schematic diagram of the function curve of the drain voltage of the super gate MOSFET device 400 as a function of time. Figure 11 As can be seen from the graph, the drain voltage of the new supergate MOSFET device rises much faster over time (i.e., dv / dt) than the standard MOSFET device. This proves that the switching speed of the new supergate MOSFET device has been improved.

[0137] Figure 12 To compare with a standard MOSFET device (reference numeral 1204), a supergate MOSFET device (reference numeral 1202), such as Figure 4B Schematic diagram of a function curve showing the gate voltage of the super gate MOSFET device 400 changing with time. Figure 12 As can be seen in FIG, the gate voltage of a standard MOSFET device exhibits a severe perturbation 1206 when the device is turned off. This perturbation is primarily due to the large parasitic Miller capacitance (C gd) is caused by the drain voltage coupling effect (as described above), which may exceed the threshold voltage of the device, resulting in mis-conduction of the device. Such mis-conduction of the device may lead to a short-circuit state, especially when the MOSFET device is used as a low-side transistor in a power switching application (such as a DC-DC converter). By comparison, it can be found that the super-gate MOSFET device represented by the reference numeral 1202 exhibits very small gate voltage disturbances, which are far below the threshold voltage of the device, thereby effectively eliminating the problem of mis-conduction of the device. Therefore, compared with traditional MOSFET devices, in higher frequency DC-DC converter applications, the super-gate MOSFET devices of the comparative embodiments of the present invention have higher efficiency and higher reliability.

[0138] for Figure 10 The illustrative embodiment of the supergate MOSFET device 1000 shown can further reduce the coupling capacitance between the planar gate G1 or the trench control gate G2 by recessing the trench gate G2 below the upper silicon surface of the device.

[0139] Figure 13 By way of example only and not limitation, a cross-sectional view of at least a portion of an exemplary supergate MOSFET device 1300 having reduced gate coupling capacitance according to one or more embodiments of the present invention is shown. The MOSFET device 1300 is similar to Figure 10 The illustrative MOSFET device 100 shown in FIG. 1 is shown in FIG. 2 , except that the control gate is recessed below the upper surface of the device.

[0140] More specifically, refer to Figure 13 MOSFET device 1300 includes a control gate (G2) formed as a trench gate 1302. The trench gate 1302 may be connected to Figure 10 406 , and the like. The trench gate 1302 is fabricated in a manner consistent with the trench gate 418 shown in , for example, by forming an opening (e.g., a trench or channel) partially through the epitaxial region 404 between the P-type body regions 406 and filling the opening with a dielectric material 1304. The dielectric material 1304 can be an oxide, such as silicon dioxide, although the present invention is not limited to any particular electrically insulating material. The trench gate 1302 is then formed partially through the dielectric material 1304, extending vertically below the source region 408 and the body region 406. Thus, the dielectric material 1304 electrically isolates the trench gate 1304 from the surrounding epitaxial region 404, thereby preventing direct electrical contact between the trench gate 1302 and the adjacent source region 408 and body region 406, and may therefore be referred to as a "trench gate oxide layer."

[0141] In one or more embodiments, an additional dielectric material layer 1306 is formed on the upper surface of the trench gate 1302, filling the trench and making it substantially flush with the upper surface of the epitaxial layer 404. Subsequently, a thin gate oxide layer 1308 (e.g., about 3-50 nm) is formed (e.g., grown) on the upper surface of the epitaxial layer 404 and the upper surface of the dielectric material layer 1306. Planar gates (G1) 416 are formed on the upper surface of the gate oxide layer 1308. Each planar gate 416 preferably comprises polysilicon and is formed using a standard chemical vapor deposition (CVD) process and subsequently patterned (e.g., using standard photolithography and etching). In this illustrative embodiment, there are two planar gates 416 arranged on either side of the recessed trench gate 1302. Although in Figure 13 Although not explicitly shown, the planar gate 416 and the trench gate 1302 may be formed as physically separated finger-like (ie, lift-off) structures, wherein the planar gate and the trench gate are electrically connected at one or both (opposite) ends of the fingers.

[0142] like Figure 13 As shown, the thickness of the trench gate oxide layer 1304 of the trench gate 1302 is substantially constant. However, it should be understood that in one or more alternative embodiments, the thickness of the trench gate oxide layer 1304 can be varied, so that the trench gate 1302 has a tapered profile. For example, in one or more embodiments, the thickness of the trench gate oxide layer 1304 can be formed such that the thickness at the bottom of the trench is greater than the thickness at the top of the trench, which is similar to the embodiment of FIG. Figure 9I The formation of the exemplary trench gate 920 shown in FIG.

[0143] like Figure 13 As shown, by Figure 10 The gate 418 shown in the figure is separated into a planar gate 1310 and a groove-shaped trench gate 1302 (groove gate), and the groove-shaped trench gate 1302 is recessed below the upper surface of the MOSFET device 1300. Thus, when the trench gate 1302 is grounded and acts as a shielding gate during the turn-off cycle, the coupling capacitance between the drain terminal and the control gate (G2) is beneficially reduced, thereby providing improved high-frequency switching performance in the MOSFET device 1300.

[0144] In an optional embodiment of the present invention, the plane grid 1310 can be removed (specifically as Figure 17 The example shown is an example in which the planar gate 1310 is removed. In the case where the planar gate 1310 is removed, the overlap area between the trench gate and the planar gate is reduced due to the recess of the trench gate, and the distance is further increased, thereby significantly reducing the coupling capacitance. Therefore, the purpose of the present invention can also be achieved.

[0145] In another optional embodiment of the present invention, the plane grid can also be configured as follows Figure 6A shape similar to the T-shaped gate shown can also achieve the purpose of the present invention.

[0146] In short, since the trench gate is very close to the source region, it is easy to be coupled with high voltage. If the capacitance is too large, the high voltage coupled by the trench gate will be easily coupled to the planar gate. If the coupled voltage exceeds the threshold voltage, the device will be turned on by mistake. Figure 13 The arrangement of the MOSFET device 1300 and its optional embodiments can further reduce the capacitance between the planar gate and the trench gate (relative to FIG. 1 to FIG. 2 ). Figure 12 MOSFET device shown), thereby solving the technical problem.

[0147] In some applications, such as in DC-DC regulators, the trench gate 1302 can also be used to form capacitors integrated with MOSFET devices and other circuit components on the same substrate, which is more efficient than traditional capacitor structures. Figure 14 A cross-sectional view of at least a portion of an exemplary capacitor 1400 is shown, comprising a trench structure suitable for integration with MOSFET devices and other circuit components on a common substrate. Figure 14 , capacitor 1400 includes a trench structure including a conductive or semiconductor material 1402 (eg, polysilicon) forming a first plate of the capacitor, surrounded by a layer of dielectric material 1404, and a substrate material 404 forming a second plate of the capacitor.

[0148] The groove structure is preferably Figure 13 MOSFET device 1300 is fabricated in a manner consistent with the formation of the trench gate structure of the MOSFET device 1300 shown. More specifically, in one or more embodiments, the trench structure of capacitor 1400 is fabricated by forming an opening (e.g., a trench or channel) that partially passes through epitaxial region 404 and extends vertically and filling the opening with dielectric material 1404. Alternatively, dielectric material 1404 may be deposited or grown on the sidewalls of the opening. Figure 13 Like dielectric material 1304 shown in FIG, dielectric material 1404 may include an oxide (e.g., silicon dioxide), although the present invention is not limited to any particular insulating material. After an opening is formed partially through dielectric material 1404 in the trench, the opening is filled with conductive or semiconductor material 1402, which forms the first plate of capacitor 1400. Thus, dielectric material 1404 electrically isolates conductive or semiconductor material 1402 from surrounding epitaxial region 404, thereby preventing direct electrical contact between the first plate and the second plate.

[0149] More dielectric material is then deposited / grown in the trench on the upper surface of the conductive or semiconductor material 1402 so that the upper surface of the trench is substantially planar with the upper surface of the epitaxial layer 404. Subsequently, an insulating layer 1406 is formed over the trench and the upper surface of the epitaxial layer 404.

[0150] Figure 15 An electrical schematic diagram of at least a portion of an exemplary switching DC-DC voltage regulator circuit 1500 is shown, which is implemented as a Buck converter, in which aspects of one or more embodiments of the present invention may be utilized. The voltage regulator circuit 1500 includes a first MOSFET device M1 (which may be referred to herein as a high-side device) and a second MOSFET device M2 (which may be referred to herein as a low-side device). The drain (D) of the high-side device M1 is connected to the input voltage V IN , the source (S) of M1 is connected to the output switching node SW, and the gate (G) of M1 is connected to the first drive circuit 1502. The drain of the low-side device M2 is connected to the output switching node SW, the source of M2 is connected to ground, or an alternative voltage return of the circuit 1500, and the gate of M2 is connected to the second drive circuit 1504.

[0151] The first and second driver circuits 1502 and 1504 form part of a controller circuit 1506 for generating first and second control signals provided to the gates of the MOSFET devices M1 and M2, respectively. The first driver circuit 1502 is coupled between the switching node SW and the boot supply voltage BOOT, and the second driver circuit 1504 is coupled between the driver supply voltage V DR In one or more embodiments, each of the driver circuits 1502, 1504 can be implemented using an inverter. The driver supply voltage V DR is preferably provided to the second driver circuit 1504, and the boot supply voltage BOOT is preferably provided to the first driver circuit 1502. The diode D1 is connected, which has a DR The anode of the diode D1 is coupled and has a cathode connected to the boot supply voltage. The capacitor C1 is preferably connected between the boot supply voltage BOOT and the switch node SW. The diode D1 and the capacitor C1 together form a bootstrap circuit for generating a sufficiently high voltage V G (V G Not shown in the figure) to fully turn on the N-channel MOSFET as a high-side switch, which is usually required when using the N-channel MOSFET for the high-side transistor of the Buck converter.

[0152] The voltage regulator circuit 1500 further includes a circuit connected to the input voltage V IN and ground between the input capacitor C IN, and connect the regulated output voltage V OUT and the output capacitor C between ground OUT An output inductor L coupled between the switching node SW and the output of the voltage regulator circuit 1500 OUT To generate a regulated output voltage V OUT . Inductor L1 and output capacitor C OUT Together they can serve as energy storage elements for the regulator circuit 1500 .

[0153] when Figure 14 The capacitor 1400 shown is used in a DC-DC regulator application (e.g., Figure 15 , the first plate of the capacitor (including the conductor / semiconductor material 1402 in the trench) is preferably connected to ground (e.g., one or both ends of the trench), and the second plate of the capacitor is connected to the input voltage V via the drain terminal 414 of the high-side MOSFET device M1. IN Therefore, the input capacitor C can be realized using capacitor 1400 IN and integrated with a MOSFET device. However, since the drain is connected to a high potential voltage, a large depletion region will be formed in the epitaxial layer 404. The boundary 1408 of the depletion region in the epitaxial layer 404 is conceptually as Figure 14 This large depletion region causes the capacitance of capacitor 1400 to decrease, which is undesirable.

[0154] To increase capacitance without significantly increasing the area consumed by the capacitor, one can Figure 16 Modifications shown Figure 14 illustrative capacitor 1400. Specifically, Figure 16 is a cross-sectional view illustrating at least a portion of an exemplary capacitor 1600 according to one or more embodiments of the present invention, the exemplary capacitor 1600 including a trench structure, Figure 14 The exemplary capacitor 1400 shown is consistent with that which has been modified to provide increased capacitance.

[0155] Now refer to Figure 16Capacitor 1600 includes a first doped region 1602 having the same conductivity type as epitaxial layer 404, in this embodiment, referred to as an N+ region, formed in the epitaxial layer near its upper surface. N+ regions 1602 are formed on opposite sides of trench structures 1402 and 1404. Second doped regions 1604 have a conductivity type opposite to that of first doped regions 1602, in this embodiment, referred to as P+ regions, formed in epitaxial layer 404 near its upper surface. Each P+ region 1604 has a first end adjacent to a corresponding N+ region 1602 and a second end, opposite the first end, adjacent to a corresponding sidewall of trench 1404. N+ regions 1602 are connected to corresponding P+ regions 1604 using a conductive material 1606 formed on at least a portion of the upper surfaces of the N+ and P+ regions. In one or more embodiments, conductive material 1606, which serves as an electrode of capacitor 1600, is preferably formed using a silicide process.

[0156] With this improved design of capacitor 1600, drain 414 is at a high potential, and holes are the primary carriers in P+ region 1604. Furthermore, P+ region 1604 acts as a hole source, supplying holes along the periphery of trench dielectric layer 1404. This creates a narrower depletion region in the device, conceptually depicted as boundary 1608. When the voltage potential between electrode 1606 and ground increases beyond a specified amount, an inversion layer 1610 forms at the oxide-semiconductor interface near the periphery of trench 1404. This inversion layer 1610 serves as the second plate of capacitor 1600. Depletion region 1608 connects to heavily doped p-type polysilicon layer 1604, which in turn connects to heavily doped n-type polysilicon 1602 via silicide layer 1606. As the voltage potential increases further, the width of depletion region 1608 does not increase significantly because the charge in inversion layer 1610 increases exponentially with the surface potential. In this way, the capacitance of capacitor 1600 is beneficially increased.

[0157] In the illustrative DC-DC buck regulator circuit 1500, the source node of the high-side MOSFET device M1 is connected to the drain node of the low-side MOSFET device M2. The voltage on the source node of M1 may ring to a high voltage. To reduce this potential ringing voltage, a voltage regulator connected to the input voltage V IN A decoupling capacitor is placed between the drain of the high-side device M1 and ground. The decoupling capacitor is preferably placed as close as possible to the drain of the high-side device M1. However, such decoupling capacitors are traditionally packaged together with the power devices, which introduces some parasitic loop inductance. This parasitic loop inductance weakens the filtering effect of the decoupling capacitor. To minimize this parasitic loop inductance, it is best to integrate the decoupling capacitor into the switch. A portion of the control gate in the trench can be used as a decoupling capacitor.

[0158] Figure 17 FIG1 shows a cross-sectional view of at least a portion of an exemplary power structure 1700 according to one or more embodiments of the present invention. The power structure 1700 integrates one or more power MOSFET devices 1702 on a common substrate 1706, each power MOSFET device being connected to a common substrate 1706. Figure 13 The illustrative MOSFET device 1300 is formed in a manner consistent with the illustrated embodiment, and one or more capacitor devices 1704, each capacitor device being formed in a manner consistent with the embodiment shown. Figure 16 Advantages of the power structure 1700 include reducing the coupling capacitance between the planar gate (Gate) and the control gate (CG) in the MOSFET device 1702, increasing the capacitance of the trench capacitor 1704, reducing parasitic inductance, and thereby reducing ringing in the integrated device.

[0159] Therefore, reference Figure 13-17 As shown in the illustrative embodiment, aspects of the present invention advantageously provide a high-density capacitor formed using processes and structures compatible with MOSFET devices. In this way, capacitors according to embodiments of the present invention can be easily monolithically integrated with power MOSFET transistors, which is an effective way to overcome the voltage ringing problem that plagues traditional buck converter circuits.

[0160] At least some of the techniques of the present invention can be implemented in integrated circuits. When forming an integrated circuit, identical molds are typically fabricated in a repetitive patterning manner on the surface of a semiconductor wafer. Each mold includes the devices described herein and may also include other structures and / or circuits. Individual molds are cut from the wafer and then packaged into integrated circuits. Those skilled in the art will know how to cut and package molds from a wafer to form an integrated circuit. Any exemplary structure or circuit shown in the accompanying drawings, or a portion thereof, may be part of an integrated circuit. Such integrated circuit manufacturing methods are also considered part of the present invention.

[0161] Those skilled in the art should understand that the above-mentioned exemplary structures in one or more embodiments of the present invention can be applied to power MOSFET devices in their original form (i.e., a single wafer with multiple unpackaged chips), bare chips, or in packaged form, or as components of intermediate products or end products, such as radio frequency (RF) power amplifiers, power management integrated circuits, power system integration, etc.

[0162] Essentially any high-frequency, high-power application and / or electronic system, such as, but not limited to, radio frequency power amplifiers and power management integrated circuits, may utilize integrated circuits consistent with the present disclosure. Systems suitable for implementing various embodiments of the present disclosure may include, but are not limited to, DC-DC converters / voltage regulators. Systems incorporating such integrated circuits are considered part of the present disclosure. Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the embodiments of the present disclosure.

[0163] The examples of embodiments of the present invention herein are intended to provide a general understanding of various embodiments and are not intended to be a complete description of all elements and features of devices and systems that may utilize the circuits and techniques of the present invention. Numerous other embodiments will become apparent to those skilled in the art based on the teachings herein or may be derived therefrom, allowing for structural and logical substitutions and modifications without departing from the scope of the present invention. The accompanying drawings are also representative and not drawn to scale. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0164] The various embodiments of the present invention listed herein are referred to individually and / or collectively as "embodiments." The term "embodiment" is used for convenience only and is not intended to limit the scope of application of the present invention to any single embodiment or embodiments or inventive concepts. Therefore, although specific embodiments are illustrated and described herein, it should be understood that arrangements that achieve the same inventive objectives may be substituted for the specific embodiments shown; that is, the present invention is intended to cover any and all adaptations or variations of the various embodiments. Combinations of the above-described embodiments, as well as other embodiments not specifically described herein, will also be apparent to those skilled in the art.

[0165] The terms used herein are only used to describe specific embodiments and are not intended to limit the present invention. As used herein, the singular form of the article may also include the plural form, unless the context clearly indicates another situation. Further, when "comprising" and / or "consisting of" are used in this specification, only the existence of the features, steps, operations, elements and / or components described herein is included, and the existence or addition of one or more other features, steps, operations, elements, components and / or their components is not excluded. Terms such as "above", "below", "above" and "below" are used to indicate the relative positional relationship between elements or structures, rather than absolute position.

[0166] Based on the teachings of the various embodiments of the present invention, those skilled in the art will be able to perform other implementations and applications of the technology of the embodiments of the present invention. Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it should be understood that the embodiments of the present invention are not limited to these precise embodiments, and those skilled in the art may make various other modifications to the embodiments without departing from the scope of the claims.

Claims

1. A metal oxide semiconductor field effect transistor device, characterized in that: include: - a semiconductor substrate having a first conductivity type, said substrate serving as a drain region of said metal oxide semiconductor field effect transistor; - an epitaxial region having a first conductivity type, which is disposed on the upper surface of the substrate; a plurality of body regions having a second conductivity type formed in the epitaxial region, the second conductivity type being opposite to the first conductivity type, the body regions being disposed proximate to an upper surface of the epitaxial region and laterally spaced apart from each other; a plurality of source regions of a first conductivity type, each of the source regions being disposed in a corresponding body region and close to an upper surface of the body region; as well as - a gate structure comprising: one or more planar gates and a trench gate, Each of the planar gates is located on the upper surface of the epitaxial region and overlaps at least a portion of the corresponding body region; The trench gate is formed between at least a portion of the epitaxial region and the body region; an upper surface of the trench gate is recessed relative to the upper surface of the epitaxial region, and no planar gate is disposed directly above the trench gate. The recess is provided on the trench gate so that an overlapping area between the trench gate and the planar gate is reduced, a distance between the trench gate and the planar gate is increased, and a coupling capacitance is reduced. The trench gate comprises: Conductor or semiconductor structures; and A dielectric layer surrounds at least the sidewalls, the bottom, and the top of the conductor or semiconductor structure, and the dielectric layer electrically isolates the conductor or semiconductor structure from the epitaxial region.

2. The device according to claim 1, characterized in that The plurality of planar gates and the trench gates form finger structures that are physically separated from each other, and the finger structures are electrically connected together through one end or both ends thereof.

3. The device according to claim 1, characterized in that in, At least one of the trench gates and at least one of the planar gates include doped polysilicon material.

4. The device according to claim 1, characterized in that in, The gate structure is configured to form a channel in each body region below the planar gate when the applied forward bias voltage exceeds the threshold voltage of the n-channel metal oxide semiconductor field effect transistor device, thereby turning on the device; at the same time, a strong accumulation layer of majority carriers is formed in the epitaxial region near the surface of the trench gate.

5. The device according to claim 4, characterized in that The gate structure is configured such that the concentration of majority carriers in the device is a function of a bias voltage applied to the trench gate.

6. The device according to claim 1, characterized in that Also included is a dielectric layer disposed between the trench gate and the adjacent epitaxial region, the dielectric layer comprising: A first portion constituting a bottom wall of the trench gate and partially extending upward to a sidewall of the trench gate; and a second portion, the second portion being a sidewall of the trench gate and extending upward to an upper surface of the epitaxial region; The first portion has a first thickness, the second portion has a second thickness, and the first thickness is greater than the second thickness.

7. The device according to claim 1, characterized in that It also includes at least two doped regions, which have a second conductivity type and are formed in each body region and close to the upper surface of the body region, and are laterally adjacent to each source region, and the two doped regions form each body region contact of the device.

8. The device according to claim 1, wherein The doping concentration of each body region is 5×10 16 atoms / cm 3 to 1×10 18 atoms / cm 3 .

9. The device according to claim 1, characterized in that It also includes a plurality of gate electrodes electrically connected to the respective planar gates and trench gates of the gate structure; each gate electrode includes a metal silicide layer formed on at least a portion of the upper surface of a corresponding planar gate and trench gate.

10. The device according to claim 1, wherein The invention also includes at least two recessed source region contacts, each of which is formed in a corresponding integral region and close to the upper surface of the body region, and is electrically connected to a corresponding source region and is located adjacent to the source region.

11. A method for manufacturing a metal oxide semiconductor field effect transistor device, characterized in that: The method comprises: forming an epitaxial region having the first conductivity type on at least a portion of an upper surface of a substrate having the first conductivity type, the substrate serving as a drain region of the metal oxide semiconductor field effect transistor; forming a plurality of body regions of a second conductivity type in the epitaxial region, the second conductivity type being opposite in polarity to the first conductivity type, the body regions being disposed proximate to an upper surface of the epitaxial region and spaced apart from each other in a laterally direction; forming a plurality of source regions of a first conductivity type, each of the source regions being disposed in a corresponding body region and close to an upper surface of the body region; and A gate structure is formed including one or more planar gates and a trench gate, wherein each planar gate is disposed on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region; the trench gate is formed in at least a portion of the epitaxial region and between the body regions; an upper surface of the trench gate is recessed relative to the upper surface of the epitaxial region, and no planar gate is disposed directly above the trench gate, wherein the recess is disposed on the trench gate so that an overlapping area between the trench gate and the planar gate is reduced, a distance between the trench gate and the planar gate is increased, and a coupling capacitance is reduced; The step of forming the trench gate comprises: forming a conductive or semiconductive structure; and A dielectric layer is formed at least surrounding the sidewalls, bottom and top of the conductor or semiconductor structure, wherein the dielectric layer electrically isolates the conductor or semiconductor structure from the epitaxial region.

12. The method according to claim 11, characterized in that Also includes configuring the gate structure, When the applied forward bias voltage exceeds the threshold voltage of the n-channel metal oxide semiconductor field effect transistor device, a channel is formed in each body region below the planar gate, thereby turning on the device; at the same time, a strong accumulation layer of majority carriers is formed in the epitaxial region near the surface of the trench gate.

13. The method according to claim 11, characterized in that The method further includes forming the plurality of planar gates and the trench gates into finger structures that are physically separated from each other, wherein the finger structures are electrically connected together through one end or both ends thereof.

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