Discharge control circuit, corresponding system, vehicle and method

Abstract

Embodiments of the present disclosure relate to discharge control circuits, corresponding systems, vehicles, and methods. In an embodiment, the circuit includes a drive circuit configured to be coupled to a control terminal of an electronic switch and configured to apply a discharge signal to the control terminal, causing the electronic switch to become conductive and provide an electrical discharge path for an energized element; a sensing node configured to be coupled to the control terminal and configured to sense a voltage at the control terminal and a feedback network coupled between the sensing node and the drive circuit, wherein the feedback network includes a comparator circuit coupled to the sensing node and configured to compare a voltage at the control terminal sensed at the sensing node with a reference threshold, and provide a comparison signal having a first value and a second value in response to the voltage at the control terminal being higher or lower than the reference threshold, respectively, wherein the drive circuit is configured to generate a discharge signal according to the comparison signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102020000022966, filed on September 29, 2020, which is incorporated herein by reference. Technical Field

[0003] This specification relates to discharge circuits. Background Art

[0004] A traction inverter for an EV may include a high voltage (HV) capacitor, currently referred to as a direct current (DC) link capacitor, or DC link for short.

[0005] Such capacitors may be rather "huge" components, with high capacitance values ​​(1 mF or even more), which may be charged to high voltages (eg, in excess of 800 V).

[0006] Various situations, such as: motor "ignition" shut-off, power supply loss (eg, 12V), controller (eg, MCU) "freezing" benefit from capacitor rapid discharge.

[0007] Generally, it is desirable to quickly discharge the DC link in all situations where inadequate discharge could result in a hazardous condition, such as generation of undesirable motor torque or exposure of the driver, passengers, or any operator to electric shock.

[0008] Although not a mandatory specification, discharging the DC link voltage to below 60V in less than 1 second helps avoid shock hazards and is often selected as a favorable option based on extensive experience.

[0009] Actively discharging the DC link voltage by intentionally performing a shoot-through on each phase "leg" of the vehicle motor is an option that could be considered for this purpose. This behavior could be somewhat similar to a hard system fault, which is otherwise undesirable due to the potential fire hazard; in fact, the current during the shoot-through could easily reach several kA for hundreds of nanoseconds if not properly controlled.

[0010] Discharging the DC link in a single iteration is hardly feasible and a PWM (Pulse Width Modulation) strategy may be considered, where the high-side (HS) switch is kept permanently ON (i.e., conducting) and the low-side (LS) driver is switched on and off with a PWM signal applied in order to generate intermittent shoot-through.

[0011] Observe that the timing of this PWM action can be critical. The current in the output stage can increase with a slope of 10A / ns, and insufficient accuracy in controlling the current evolution can easily lead to severe damage. Furthermore, it is difficult to predict the slope of the current during the shoot-through discharge in a reliable way.

[0012] In fact, this parameter depends on many factors, namely: the DC link voltage during discharge, the parasitic inductance value of the discharge loop, the ambient temperature, the HS / LS driver output current characteristics, and / or the HS / LS driver input gate charge characteristics.

[0013] All these entities are interrelated and may change rapidly during shoot-through discharge, which is not conducive to implementing real-time estimation and compensation strategies.

[0014] In theory, an associated controller (such as an MCU) capable of applying a PWM signal with a frequency in the range of tens of kHz and a resolution of a few ns could provide such precise control.

[0015] This approach is rarely feasible because various factors can cause the PWM signal duration (mainly the “on” time, T ON ), namely: propagation delays of the PCB traces from the MCU to the input of the gate driver, propagation delays of the gate driver circuit, which can be achieved via a mix of analog and digital gates, variations in the charge / discharge connected between the output of the gate driver and the input of the HV switch (HS / LS), and / or variations in the HV switch input characteristics (such as gate charge).

[0016] All of the above quantities are subject to process and temperature distribution, and the uncertainty resulting from their combination is usually too high to meet application specifications related to controlling the discharge current in a precise manner.

[0017] Therefore, even an ideal controller capable of generating a signal with theoretically infinite accuracy will end up being ineffective due to the uncertainty introduced by the transfer function from the MCU output to the HV switch output current.

[0018] Furthermore, achieving accurate timing via an open-loop strategy will involve bench experiments and will be exposed to temperature and process propagation.

[0019] A closed loop strategy based on driver temperature sensing and over-temperature protection would otherwise result in a slow and ineffective mechanism, since the external driver would inevitably operate close to or beyond the safe operating area or SOA. Additionally, a closed loop strategy based on temperature sensing may involve a so-called "estimation observer" where an increase in driver temperature indicates an effect indicating the intensity of the over-current phenomenon.

[0020] Limiting the temperature rise when adjusting the "on" resistance, Rdson in an electronic switch such as a field effect transistor, can involve expensive cooling systems, which can have an impact on the overall cost of the system.

[0021] Finally, strategies aimed at limiting current peaks using a two-level shutdown approach will result in overloading the HV driver, ultimately leading to reliability issues.

[0022] Increasing the HV driver equivalent resistance by reducing the gate drive voltage of the HV driver is an effective technique to reduce the current slope and peak.

[0023] However, in doing so, conduction losses increase dramatically, leading to possible SOA (SOA = safe operating area) violations.

[0024] It is also desirable to be able to achieve active discharge of the DC link without using additional circuitry, as this may result in savings in the final bill of materials (BoM).

[0025] Documents such as Chinese Patent Application No. 109713886A, No. 109245505A or No. 111244927A are examples of prior art in this field. Summary of the invention

[0026] The embodiments contribute in solving the various problems outlined above.

[0027] Embodiments provide traction systems for electric vehicles (EVs) or power conversion systems utilizing high voltage energization elements for filtering or stability purposes.

[0028] Further embodiments provide for any type of device where rapid power down is a desired feature for functional and / or safety purposes.

[0029] Other embodiments provide corresponding systems.A traction system for an electric vehicle (EV) may be an example of such a system.

[0030] One or more embodiments may be directed to a corresponding vehicle, such as an electric vehicle (EV).

[0031] One or more embodiments may be directed to a corresponding method.

[0032] One or more embodiments facilitate fast discharge of a DC link capacitor in an HV converter substantially utilizing an already existing functional driver stage.

[0033] One or more embodiments are directed to a fast closed-loop control based discharge strategy that facilitates control of output stage current, which in turn facilitates operation of the HV driver in a safe operating area (SOA) during the entire discharge process.

[0034] One or more embodiments employ a control strategy based on monitoring the actual duty cycle applied to the control terminal (gate) of an external driver, which control strategy is insensitive to propagation delays.

[0035] One or more embodiments may be embedded into an integrated circuit (IC) having the capability to facilitate DC link discharge functionality at a system level with reduced complexity and risk compared to existing solutions.

[0036] More generally, one or more embodiments may be implemented in systems (eg DC / DC or AC / DC or DC / AC converters) in which energized elements need to be discharged in a short time that is barely compatible with normal operating time.

[0037] One or more embodiments may result in a cheaper BoM compared to conventional solutions: this may be related to the fact that no (additional) active discharge circuitry is taken into account.

[0038] To this end, one or more embodiments may similarly result in a reduction in PCB space, as long as additional active discharge circuit devices (eg, several resistors and power MOS transistors) can be avoided.

[0039] One or more embodiments may correspondingly result in improved performance in terms of failure in time (FIT): fewer components involve fewer FITs.

[0040] One or more embodiments may employ a fast closed-loop strategy that may be insensitive to propagation delays and process spread of low voltage (LV) domain circuits.

[0041] One or more embodiments do not involve using isolated comparators to "report" temperature or phase voltage to the MCU, as long as the corresponding functions can be implemented in the HV domain as needed.

[0042] One or more embodiments facilitate monitoring (eg, using the MC pin) the actual duty cycle applied to the control terminal (gate) of an external driver.

[0043] One or more embodiments may include a (fast) analog comparator that facilitates a fast reaction time when sensing the gate voltage.

[0044] One or more embodiments are directed to simple mixed-signal circuits comprising programmable analog delays and discrete logic gates.

[0045] As described above, one or more embodiments rely on a closed-loop strategy implemented in the HV domain that is insensitive to process and temperature spreads of all LV domain circuits.

[0046] In one or more embodiments, this implementation facilitates operating the external switch in a safe operating area (SOA) during the entire discharge process.

[0047] It is recalled again that, although the traction system in an electric vehicle (EV) will be mentioned below primarily by way of example of a possible use environment of the embodiments, the embodiments are not limited to this possible use environment. As described above, for example, one or more embodiments may be applied in power conversion systems employing high voltage energization elements for filtering or stability purposes, or more generally, in those application environments involving rapid power off for functional and / or safety purposes. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings.

[0049] Figure 1 is a functional block diagram of a traction system for an electric vehicle (EV), which is an example of a possible use environment of the embodiments;

[0050] Figure 2 Is achieved as Figure 1 An example circuit diagram of the method of solution shown;

[0051] Figure 3 and Figure 3A is an exemplary circuit diagram of an embodiment; and

[0052] Figure 4 and Figure 5 Includes various timing diagram examples of possible temporal behavior of signals. DETAILED DESCRIPTION

[0053] In the following description, one or more specific details are described to provide a deeper understanding of the examples of the embodiments of the present description. These embodiments can be obtained without one or more specific details, or by other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not described or explained in detail so as not to obscure certain aspects of the embodiments.

[0054] References to "an embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases that may appear in one or more points of this specification (such as "in an embodiment" or "in an embodiment") do not necessarily refer to the same embodiment.

[0055] Furthermore, in one or more embodiments, particular conformations, structures, or characteristics may be combined in any suitable manner.

[0056] The headings / references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0057] Figure 1 is a functional block diagram of a traction system of an electric vehicle (EV) represented by V, the outline of which is schematically reproduced by dashed lines.

[0058] In this regard, it is recalled again that, although in this exemplary description traction systems in electric vehicles (EVs) will be primarily discussed, the embodiments are not limited to this possible environment of use.

[0059] As noted, for example, one or more embodiments may be applied in power conversion systems employing high voltage energizing elements for filtering or stabilization purposes, or more generally, in environments involving rapid power down for functional and / or safety purposes.

[0060] The core of the system as illustrated herein is represented by a (multiphase) electric motor M driven by a drive train based on electronic circuitry comprising integrated circuits (semiconductor chips or dies).

[0061] like Figure 1 Such a drive train as shown may include, for example:

[0062] A collection of low voltage (LV) die safety mechanisms 100,

[0063] The first high voltage (HV) die group 102 is configured to provide functions such as over voltage monitoring (OV VH) / under voltage (UV) monitoring for high voltage, under voltage monitoring (UV VL) for low voltage, thermal shutdown, watchdog, etc.

[0064] Brake control 104,

[0065] A second high voltage (HV) die group 106, configured to provide functions such as desaturation (DES), current sensing (over current / short circuit - ISEN), over temperature (TSEN OT), and shoot-through discharge as discussed below, and / or

[0066] The third high voltage (HV) die group 108 is configured to provide functions such as active VDS / VCE clamp (VCECLAMP), over voltage monitoring for low voltage (OV VL), gate command voltage monitor (VGE), etc.

[0067] VGE is a safety mechanism that checks the consistency of the received gate drive logic command with the state of the HV driver gate. For example, if the HV driver receives a shutdown command from the control logic, the gate voltage of the HV driver should drop below the "shutdown" threshold within a defined (possibly programmable) filtering time.

[0068] It will be further appreciated that in addition to the through discharge functionality discussed in detail below (which may advantageously be included in the second high voltage die group 106), Figure 1 The arrangement shown in may be considered conventional in the art and therefore a more detailed description need not be provided here.

[0069] An example of such a conventional arrangement may be an electric vehicle (EV) traction inverter for driving an electric motor M, which includes three sets (or "phases") of windings that are energized via corresponding electronic switches (such as power transistors).

[0070] For simplicity of presentation and explanation, the description will primarily relate to a single phase (and a single switch), with the understanding that the same principles discussed herein can be extended to multiple phases / switches.

[0071] Furthermore, it should be understood that Figure 1 What is shown is merely an example of one context among many possible use environments of the embodiments: As noted, one or more embodiments may be implemented in systems (DC / DC or AC / DC or DC / AC converters, to name a few) where energized elements are expected to discharge in a short period of time.

[0072] like Figure 2 As shown (and again for simplicity Figure 1 In the example use environment described in ), such energizing elements may include high voltage (HV) capacitors, currently referred to as direct current (DC) link capacitors, or simply DC link. As mentioned above, such capacitors may be relatively "huge" components with high capacitance values ​​(1 mF or even greater) that may be charged to high voltages (e.g., in excess of 800 V).

[0073] One or more embodiments provide a shoot-through discharge function that can be advantageously implemented in conjunction with an isolated gate driver 10 that provides galvanic isolation between a low voltage side LV and a high voltage side HV, the high voltage side HV comprising two power switches Q1 and Q2 arranged between high voltage rails HV+ and HV-, with a capacitor LC coupled between the high voltage rails.

[0074] The two power switches Q1 , Q2 may include power transistors such as (silicon carbide or SIC) power MOSFETs or insulated gate bipolar transistors (IGBTs).

[0075] exist Figure 2 In the exemplary case shown, the two power switches designated Q1 and Q2 are examples of “phase” switches of the motor M, and the parallel connection of a resistor R and a capacitor Qg is an example of the gate of Q2.

[0076] It should be noted that in the arrangement as illustrated herein, transistors Q1 and Q2 do not represent additional switches for implementing the shoot-through discharge functionality: in the arrangement as illustrated herein, transistors Q1 and Q2 are “functional” switches for driving an electrical load.

[0077] For example, transistors Q1 and Q2 may be switches driving the "U" phase of motor M, with other switch pairs (currently referred to as Q3 / Q4 and Q5 / Q6, not visible for simplicity) being used to drive the "V" and "W" phases of motor M, respectively.

[0078] As described below, these switch (transistor) pairs can also provide an ASC (Asynchronous Stop Command) feature. This is a safety feature that brakes the motor M in the event that there is a hindrance to effective control of the motor torque.

[0079] The shoot-through discharge technique as exemplified herein may be implemented in parallel on three phases so that the technique may cooperate to discharge the DC link during a shoot-through period.

[0080] exist Figure 2 In the circuit illustrated in FIG. 1 , the through command IN+ may be generated (by a controller C (such as, for example, included in Figure 1 The MCU in the system shown in FIG. 1 generates a functional signal as a backup) with less priority than any other safety mechanism. For example, the backup MCU in the low voltage (LV) domain can generate the IN+ signal (in a manner known per se to those skilled in the art) as a PWM signal to be converted into a shoot-through pulse.

[0081] In one or more embodiments, the pass-through functionality may be advantageously implemented in the HV domain via redundant logic, such as a safety MCU, for example.

[0082] As an example, one or more embodiments may utilize the BRAKE pin (currently used to implement the ASC functionality discussed previously) in order to trigger a pass-through action. This may involve utilizing a dual threshold comparator (see discussion below) that can distinguish between an ASC request and a pass-through request. Figure 3A ) to implement "fuzzy" logic circuits.

[0083] Compared to conventional solutions, this solution advantageously uses a single pin to implement two functions without a penalty in terms of pin count.

[0084] One or more embodiments facilitate fully implementing the pass-through functionality on the HV side utilizing the same signal path as the ASC functionality without compromising time resolution.

[0085] It should be noted that the BRAKE pin on the HV side (dedicated to ASC) can be considered a conventional feature. However, using this pin for pass-through is affected by the propagation delay (and associated uncertainty) of the BRAKE comparator and the associated pre-driver stage. One or more embodiments can solve this problem by adopting a closed-loop layout, where the BRAKE pin is used to trigger the pass-through action, while the delay is compensated via the closed loop.

[0086] Pass-through commands can also be considered as safety path signals, for example, signals applied by the backup MCU in the high voltage (HV) domain (such as PWM brake signals (see Figure 1 Block 104)) in the figure is to be converted into a through pulse.

[0087] An architecture as previously described can benefit from a pass-through signal being included in a functional path having a priority dictated by the implementation of the functional path, the pass-through signal not moving the associated finite state machine (FSM) to a safe LCKO state (safety lockout, essentially a forced shutdown exit) and reengagement occurring automatically at the next PWM rising edge.

[0088] It should be noted that discharging a DC link using a controlled shoot-through action is conventional per se in the art.

[0089] For example, the action may involve controlling the peak discharge current by modulating the RDSon of the transistor providing the discharge path, using a 2LTO (Dual Level Turn Off) technique to reduce the gate voltage.

[0090] One or more embodiments facilitate maintaining a discharge switch in the SOA ("safe operating area").

[0091] Advantageously, one or more embodiments can avoid "masking" overcurrent / desaturation diagnostic functionality that may conflict with the shoot-through functionality. In fact, in one or more embodiments, the peak current will not trigger protection as long as the peak value is considered a "functional" value by the system.

[0092] One or more embodiments help maintain diagnostic priorities intact, which results in safer system operation. At least in principle in one or more embodiments, even a misconfiguration of the shoot-through function that results in an undesirably high discharge current can be remedied by intervention of overcurrent or desaturation protection of an external switch.

[0093] An interesting factor in implementing the DC link discharge function as discussed herein is to limit the discharge current by controlling the switch on time of the discharge switch (which can be directly managed) while avoiding the inherent disadvantages of the 2LTO (two-level turn-off) technology, where the current can be limited by the RDSon (drain-source resistance of the switch when conducting) of the low-side switch.

[0094] As discussed, this way of limiting the peak current has a number of disadvantages, which become particularly evident in view of the current trend towards smaller switches (SiC / IGBT / MOSFET): for the same RDSon value, smaller switches exhibit reduced short-circuit immunity. Therefore, it is highly desirable to maintain the SOA operation of the switch.

[0095] To this end, one or more embodiments may employ a method in which:

[0096] The high-side switch HS is forced into a stable "on" (conducting) state;

[0097] A PWM (Pulse Width Modulation) signal is applied to the low-side switch LS so that the T ON value (switch conduction) is higher than the required on-time, as long as it can be combined as follows Figure 4 and Figure 5 The internal clamping action discussed achieves this "true" on-time.

[0098] Of course, one or more embodiments may employ a complementary approach, where the low-side switch LS is forced into a stable “on” state and a PWM signal is applied to the high-side switch HS.

[0099] Both strategies can be considered feasible to perform effective shoot-through discharge.

[0100] In some embodiments, the system software may select either strategy based on the initial scenario before starting the program (eg, the state of the HS / LS switches, the presence of short-term faults, and other factors that affect the selection of the discharge strategy).

[0101] can be via the LV side (see, for example, Figure 2 ) and the "safety" logic C on the HV side manages the related ON / OFF signals using the ASC capability maintained via the BRAKE signal as previously discussed.

[0102] It should be noted that the safety logic in the LV domain will disable the relevant interlocks before implementing the pass-through action. In contrast, with the safety logic in the HV domain, the interlocks are implemented in the LV die and are therefore bypassed.

[0103] It should also be noted that in one or more embodiments, there is no need to manage BRAKE priority with respect to VH UV, as long as one or more embodiments do not involve modulating voltage VH.

[0104] As discussed, with reference to an exemplary but non-mandatory application to a traction inverter, one or more embodiments are intended to address issues that may arise in response to certain conditions (e.g., motor "ignition" interruption or shutdown, IGN shutdown) where it is desired to discharge the DC link (essentially the capacitor LC) to cope with undesirably high energy storage in the high voltage or HV domain (e.g., when the vehicle V is not powered).

[0105] As mentioned repeatedly, such capacitors can be quite "huge" components, with high capacitance values ​​(1 mF or more), which can be charged to high voltages (eg, in excess of 800 V).

[0106] exist Figure 1 In the arrangement illustrated in , a passive discharge function (eg, by means of a bleeder resistor) can (already) be provided for general safety purposes. This facilitates a constant but rather slow discharge path.

[0107] An active discharge function can also be provided according to an "enable" action, for example in the event of a crash (car crash) or when the high-voltage protection cover of the electronic control unit (ECU) is removed for maintenance purposes. For example, this active discharge function can be implemented by a dedicated switch whose energy is limited by a series resistor. This function can reduce the DC link voltage to below 60V in less than 1s to prevent the risk of electric shock.

[0108] This active discharge function can be implemented on a HV NMOS based board (mounted as low side) and configured to be normally inactive (off) because the interlock shorts the gate to source voltage (VGS).

[0109] In response to the HV safety box cover being opened, the interlock is released with VGS self-generated from the DC link voltage and clamped by a discharge diode maintained conductive (ON) with an NMOS transistor until the DC link is fully discharged.

[0110] One or more embodiments utilize traction module "phase" switches to (quickly) discharge the DC link while avoiding the risk of (serious) damage due to uncontrolled discharge current. This approach has the advantage of reducing costs and utilizing precise shoot-through timing control so as not to overstress the phase switches due to repeated overcurrent events.

[0111] As in the case of active discharge discussed previously, Figure 1 In the environment illustrated in , three-phase switches in the "legs" of the motor M can therefore be used instead of the LS NMOS transistors.

[0112] In one or more embodiments, the (phase) interlock is temporarily disabled, wherein the high side HS (respectively, the low side LS) remains permanently conductive (on) and the low side LS (respectively, the high side HS) is alternately switched on / off in PWM mode to generate shoot-through as needed.

[0113] As previously discussed, in one or more embodiments as illustrated herein, the current is not limited via a resistor and can be controlled by accurately modulating the shoot-through time interval.

[0114] This helps to consider the fact that the discharge current can rise with a slope of 10A / ns, which equates to values ​​as high as 4kA in 400ns, which could result in severe damage.

[0115] Additionally, one or more embodiments facilitate providing closed-loop control of the conduction time of the discharge switch.

[0116] This makes it possible to avoid unexpected situations in which an "on" command sent to the switch may be subject to inaccurately estimated propagation delays, so that the switch may be undesirably forced into the "off" state immediately after receiving the "on" command, or even prevented from receiving the "on" command, thereby remaining in the "off" state.

[0117] As discussed (and by reference to Figure 1 and Figure 2 ), the interlock function can be temporarily disabled on both the HS drive and the LS drive.

[0118] Advantageously, one or more embodiments may be applied in conjunction with isolated gate drivers of the type currently available under the trade names L9502 and L9502B from the STMicroelectronics group of companies (see st.com), for example using the IN_M_DIS bits in the register map of the specified LV SPI reg map (safety potential registers - configurations that have an impact on safety functions and are therefore under a "lock" key in order to prevent undesired access to these registers).

[0119] In the L9502 / L9502B isolated gate drivers, the HS FET can be permanently turned on, while the DES / ISEN (desaturation for over-current / short-circuit) protection will be activated and configured as needed. The LS FET can be driven with a low duty cycle PWM (e.g. 20kHz) signal, which corresponds to T ON With T OFF Advantageously, the T generated by the associated controller (MCU) ONThe value of is chosen to be higher than the propagation delay of the entire chain. In the case of embodiments relying on the L9502 / L9502B platform, a T of (at least) 10 μs is chosen. ON The value helps correct operation and avoids undesirable "skipped" pulses.

[0120] This may result in a duty cycle of up to 50% with the pulse duration modulated as discussed below.

[0121] Dedicated circuitry on the HV side may be provided that is configured to clamp (eg, LS) the output pulse duration using a programmable delay.

[0122] In one or more embodiments, the delay can be selected to limit the output current peak to a safe operating value.

[0123] Advantageously, the DES / ISEN protection is not triggered during a shoot-through discharge except in the case of a misconfiguration, in which case the DES / ISEN protection can be configured to take over and protect the traction module from undesired damage.

[0124] Figure 3 is a circuit diagram example of an embodiment of the discharge circuit 20, which can be advantageously included in the Figure 1 and Figure 2 In the arrangement shown.

[0125] Note again that reference to this arrangement is not to be construed as limiting the embodiments: one or more embodiments may be implemented in systems (DC / DC or AC / DC or DC / AC converters, just to name a few examples) where energized elements are expected to be discharged in a short time, i.e. where rapid de-energization of the system for functional and / or safety purposes is a desired feature.

[0126] to this end, Figure 3 More generally it concerns a discharge circuit (entirety 20) configured to discharge an energized element (here a DC link capacitor LC, shown in dashed lines) via at least one electronic switch SP.

[0127] As an example, in Figure 1 In the operating environment shown (in an exemplary and non-limiting manner), the electronic switch SP can be one of the "phase" switches of a motor M of an electric vehicle V, which is configured to be operated according to a space vector modulation scheme conventional in the art.

[0128] Such an electronic switch SP comprises a control terminal G SP (The gate in the case of a field effect transistor based on Si or SiC - or an IGBT as exemplified herein).

[0129] In short, Figure 3 The illustrated discharge circuit 20 includes a pair of electronic switches 21, 22 (eg, P-type and N-type power MOSFET transistors).

[0130] like Figure 2 As shown, such a circuit 20 may be integrated as a pre-driver stage (e.g., in a device of the L9502 / L9502B type as discussed previously and repeated) and coupled to a discharge circuit including switches Q1 and Q2. Figure 3 The circuit 20 illustrated in FIG. 2 can be configured to (pre) drive corresponding switches Qx in a traction inverter, so that six circuits 20 can be provided in the traction inverter for driving U, V and W phases in the motor, each phase including two switches (such as Q1 and Q2).

[0131] For simplicity and ease of explanation, the structure and operation of a single circuit 20 coupled to a single (discharging) switch SP will be discussed below.

[0132] like Figure 3 The circuit 20 shown comprises:

[0133] A first (high-side or HS) switch 21 is coupled between a first (high-side) voltage node VH and a first output node VO+, and

[0134] A second (low-side or LS) switch 22 is coupled between the second output node VO- and a second (low-side) voltage node VL.

[0135] The switches 21, 22 have their control terminals (gates in the case of field effect transistors such as MOSFETs) coupled to the outputs of respective drive circuits 31, 32 (supplied via voltage nodes VH and VON and via voltage nodes VL and VON, respectively).

[0136] The drive circuits 31 , 32 are in turn controlled by a gate drive logic circuit 40 to which a command signal i_gate_cmd (generated in a manner known to those skilled in the art) is applied.

[0137] The switch drive / type (e.g., p-type and n-type) is configured so that the switches 21, 22 can be turned on and off (made conductive and non-conductive) to change the control terminal G applied to the electronic switch SP (via resistors RCHG and RDCHG). SP The voltage at the nodes VO+, VO- (the gate in the case of a field effect transistor such as a power MOSFET).

[0138] That is, the pre-driver output stage as illustrated herein comprises a push-pull stage including switches 21 and 22 that form a "split" output (VO+ / VO-). G can be implemented via the VO+ output SP The switching speed can be adjusted by changing the RCHG resistor value. Similarly, G can be realized via the VO- output. SP The switching speed can be adjusted by changing the RDCHG resistor value.

[0139] Although illustrated herein as a MOSFET, the switch SP may include any type of voltage-controlled power element (eg, a conventional MOSFET, a silicon carbide (SiC) MOSFET, an insulated gate bipolar transistor (IGBT), or a gallium nitride (GaN) transistor).

[0140] As described above, the switch SP may be included in a motor (such as Figure 1 in one of the “phases” of the M) (e.g., called grounded GNDS).

[0141] It is further noted that both the switch SP and the energization element (a rather "huge" component in case of a DC link capacitor) may be different elements from the embodiment.

[0142] Reference numeral 50 denotes a comparator configured to compare the voltage at the control terminal (gate) of the electronic switch SP with a reference value V2LTO generated in a manner known per se to a person skilled in the art: as previously discussed repeatedly, such a comparator may have been included in the L9502 / L9502B isolated gate driver as a 2LTO comparator for safety / diagnostic purposes.

[0143] Reference numeral 60 generally designates a (programmable) delay circuit coupled to the output of comparator 50 .

[0144] Programmable delay circuit 60 may be implemented in any manner known to those skilled in the art in order to generate a fast programmable delay.

[0145] An inverter chain or a capacitor / current circuit are examples of possible implementations of such a delay.

[0146] In one or more embodiments, the delay circuit 60 may include an analog delay (RC low-pass circuit) that may be controlled (reset) via the signal i_shoot_dly.

[0147] The signal i_shoot_dly may be generated (in a manner known per se to a person skilled in the art) in such a way that the delay circuit 60 applies a controlled delay (eg a delay selected in the range of 0 ns-70 ns, in selected steps of 5 ns-10 ns).

[0148] The (possibly) delayed output from the comparator 50 (as i_shoot_comp) is applied to a gate control logic comprising an AND gate 70 which receives at its inputs the logic complement of the signal i_shoot_comp, the command signal i_gate_cmd applied to the drive logic circuit 40, and the shoot-through enable signal i_shoot_en, which may be combined as follows: Figure 3A The shoot-through enable signal i_shoot_en is generated as discussed above.

[0149] The output from AND gate 70 is applied as a PRESET signal (active low) to a flip-flop 80 which is clocked by command signal i_gate_cmd.

[0150] Digital delay 78 is illustrated as acting on the i_gate_cmd signal applied to the clock input of flip-flop 80. Digital delay 78 solves the synchronization problem and causes the clock pulse to reach flip-flop 80 (only) after gate 70 has released the reset command to the preset input (active low).

[0151] Input D of flip-flop 80 is coupled to ground and output Q from flip-flop 80 is applied to driver logic circuit 40 as o_gate_cmd signal, which may be generated (in a manner known per se) according to the following truth table.

[0152] Presets D CLK Q 0 X X 1 1 X 1 D 1 X X <![CDATA[Q 0 ]]>

[0153] In case flip-flop 80 is disabled, for example in response to i_shoot_en=0, the o_gate_cmd signal assumes its inactive state (in the exemplary case shown, this is high: high means that the push / pull stage forces a low voltage on the gate of the driver as long as the HS shown is PMOS).

[0154] Therefore, if Figure 3 The operation of the circuit 20 illustrated in FIG. 1 is controlled via a gate control circuit for pass-through operation (mixed analog-digital type) according to two digital signals (eg, serial peripheral interface or SPI signals), namely:

[0155] A shoot-through enable signal (SHOOT_EN), such as i_shoot_en, is applied to flip-flop 80, and

[0156] A delay control signal (TSHOOT), such as i_shoot_dly, is applied to delay circuit 60 .

[0157] The i_shoot_en enable signal may be a configuration bit stored in a register map (shoot_en_spi, safety potential register). This may be the case when the shoot-through action is managed by a safety controller that has access to the gate pre-driver register map.

[0158] The i_shoot_en enable signal can also be a digital signal determined by the device logic. This may be the case when the shoot-through action is managed by a safety controller that does not have access to the gate pre-driver register map but has access to the safety-related pins of the gate pre-driver (the so-called BRAKE pin). This logic is able to sense (as previously discussed) the BRAKE pin assertion and enable shoot-through regardless of shoot_en_spi.

[0159] A possible i_shoot_en implementation may involve both implementations (by ORing their effects).

[0160] For example, the SHOOT_EN bit can be the SLR bit in the register map. This can be bypassed via the BRAKE pin when SPI driving is not used (high side pass-through).

[0161] Similarly, the delay control signal (TSHOOT) can be a 3-bit SLR signal in the L9502 / L9502B isolated gate driver.

[0162] Figure 3A A possible method of generating a shoot-through trigger signal i_shoot_en using the same HV pin (e.g., “BRAKE”) used to implement the ASC (Asynchronous Stop Command) function is shown. As illustrated here, the shoot-through trigger signal i_shoot_en can be generated by the HV power stage ( Figure 1 The safety circuit arrangement implemented in 108) generates such a trigger signal.

[0163] This “safety” logic can be configured to drive a dedicated safety input (e.g., BRAKE) of the HV gate pre-driver to implement the ASC function.

[0164] This safety feature works in selected system scenarios to actively brake the motor, resulting in a forced stop. This is achieved by shorting the rotor BEMF (back electromotive force) to quickly stop the motor rotation, in order to avoid injecting overvoltage into the battery line and generating unwanted torque.

[0165] In a three-phase system, for example, when the three LSs are forced to turn on, the ASC function can be implemented to force the three HS switches to turn off.

[0166] The BRAKE pin is considered a trigger for this function. For example, the three HS pre-drivers may be programmed to force the outputs off when BRAKE is asserted, while the three LS switches may be programmed to force the outputs on when BRAKE is asserted. Dual or complementary implementations are also possible that implement the ASC function to force the three HS on, while the three LS are forced off.

[0167] In one or more embodiments, the BRAKE pin can be used as a trigger for a shoot-through pulse, implementing a logic function to distinguish between a permanent on condition (ASC function) and a short on pulse (shoot-through) corresponding to two different system reactions.

[0168] like Figure 3A As shown, such logic functions may be implemented via dual threshold comparators 91, 92, where the input voltage corresponds to the BRAKE input voltage applied to 91A, 92A having corresponding "digital" and "power" thresholds (eg, applied to the inverting input).

[0169] like Figure 3A As shown, the outputs from the two comparators 91, 92 (in the case of the output from the comparator 92, in the form of logical complements) are applied to the input of an AND gate 93, which also receives the SAFE_SEL signal (as a third selection input). The output from the AND gate 93 is applied to one of the inputs of an OR gate 94, which receives the SPI enable signal shoot_en_spi as a second input, so that the output signal i_shoot_en is obtained by performing an OR operation from the output of the AND gate 93 and the signal shoot_en_sp.

[0170] If the input voltage (BRAKE) is above a "digital" threshold 91A (eg, 3.5V as determined by a 5V CMOS logic standard), but below a "power" threshold 92A (eg, 9V), the gate pre-driver triggers execution of a shoot-through pulse as discussed further below.

[0171] If the input voltage (BRAKE) is above both the “digital” threshold and the “power” threshold, the gate pre-driver generates a continuous ON condition for implementing the ASC function.

[0172] Such functionality itself is conventional in the art, which makes it unnecessary to provide a more detailed description herein. Otherwise it will be noted that one or more embodiments facilitate utilizing a single HV side pin to implement both pass-through and ASC functionality, thereby limiting the number of pins on the HV side of the gate pre-driver package.

[0173] Figure 4 and Figure 5Various timing diagrams are included which depict (for a common abscissa time scale) possible temporal behavior of signals that may occur in embodiments according to the present description.

[0174] Specifically, in the case of “normal” operation of the circuit 20 (without DC link discharge enabled), Figure 4 The following signals are illustrated (from top to bottom):

[0175] The stepped input signal HS IN+ applied to the high-side switch (here 21) results in an output signal HS VO at the node VO+, so that the high-side switch 21 is set to the “on” (conductive) state;

[0176] A pulsed input signal LS IN+ is applied to the low side switch (here 22): This can be considered to have a duration T ON The “on” time (switch 22 conducts) and the frequency f PWM The PWM modulation signal,

[0177] The same is generated at the node VO- with duration T SHOOT The “on” time and frequency f PWM The rise time of the pulse in LS IN+ of the PWM modulated signal LS VO is aligned with the rise time of the pulse in LS VO.

[0178] It can be assumed that the signals HS IN+ and LS IN+ applied to switches 21 and 22 via drive circuits 31, 32 are under the control of gate drive logic 40 in response to signal i_gate_cmd asserted during normal circuit operation (see Figure 3 , top left) (a shoot-through enable signal SHOOT_EN (such as i_shoot_en applied to the non-asserted flip-flop 80)) generated in a manner known per se to those skilled in the art.

[0179] It should be noted that in Figure 3 In the illustrated circuit, regardless of other factors, if the preset input to the flip-flop 80 is "low", the output becomes "1" (which corresponds to the "off" state of the external switch SP). Conversely, if the preset input is "high", the behavior of the flip-flop is the same as that of a conventional rising-edge triggered flip-flop.

[0180] Figure 3 The signal i_gate_cmd illustrated in can be considered as being produced by the combination of two signals:

[0181] On / off signal from the LV domain for the combined pre-driver circuit inputs IN+ / IN-,

[0182] The on / off signal from the HV domain is generated by sensing the BRAKE pin.

[0183] For example, the signal i_gate_cmd may go “high” in response to an “on” command from a controller on the LV side or from “safety” logic on the HV side.

[0184] Each of these two events can generate a corresponding "on" trigger.

[0185] Figure 4 and Figure 5 is an example of an embodiment where circuit operation (primarily DC link discharge operation) involves forcing the high-side (HS) switch 21 into a stable "on" (conductive) state and applying some kind of PWM signal applied to the low-side LS switch 22. As previously mentioned, one or more embodiments may employ a complementary approach where the low-side switch LS is forced into a stable "on" state and a PWM signal is applied to the high-side switch LS.

[0186] Figure 5 A shoot-through DC link discharge operation is involved (i_gate_cmd de-asserted and shoot-through enable signal SHOOT_EN (such as i_shoot_en applied to AND gate 70)).

[0187] For simplicity, Figure 5 Presenting the situation from the perspective of a single gate driver, each gate driver has two inputs IN- and IN+ to implement the interlocking functionality (in a manner known per se to a person skilled in the art).

[0188] Specifically, for simplicity, only the gate driver that performs the controlled shoot-through action (here, the LS gate driver 32 ) is considered, assuming that the complementary switch (here, the HS gate driver 31 ) is controlled to be stably turned on (ie, conducting).

[0189] Recalling again, one or more embodiments may employ a complementary approach where the low-side switch LS is forced into a stable “on” state and the high-side switch HS performs a controlled shoot-through action.

[0190] In the exemplary case considered here, the input IN- represents the state of the high-side switch HS (which is not directly controlled but rather "observed") as seen from the low-side switch LS; conversely, the input IN+ represents the state of the low-side switch LS controlled by the pre-driver circuit.

[0191] Typically, in response to IN- being high, a pre-driver as described herein may be configured to prevent turn-on, shielding IN+ (this is currently referred to as "interlock"). As previously discussed, one or more embodiments may contemplate disabling interlock in the presence of shoot-through.

[0192] The following signals are exemplary (again from top to bottom) reference to a shoot-through DC link discharge operation (i_gate_cmd de-asserted and shoot-through enable signal SHOOT_EN (such as i_shoot_en applied to flip-flop 80)):

[0193] Step-shaped input signal IN-,

[0194] Step-shaped input signal IN+,

[0195] As a result output voltage VO is applied to the control terminal of the power transistor SP,

[0196] The output voltage 2LTO COM from the comparator 50,

[0197] The signal i_shoot_comp applied by the delay circuit 60 to one of the inputs of the AND gate 70,

[0198] The signal i_gate_cmd applied to the gate drive logic 40,

[0199] The signal o_gate_cmd from the Q output of flip-flop 80, and

[0200] Discharge current ID through power transistor SP.

[0201] It should be noted that the voltage VO is delayed by T relative to the rising edge of i_gate_cmd (and IN+). IN_OUT_DLY_LH This delay is set via i_shoot_dly to reach and maintain a threshold value V approximately equal to the gate-source voltage of transistor SP GSTH The "plateau" value is used to achieve zero current switching, after which VO passes through the value V 2LTO (the reference input of comparator 50) starts to move again towards voltage V H rise.

[0202] In response to this, the output signal 2LTO CMP from the comparator 50 is increased by 1.1% relative to VO having crossed the value V 2LTO The delay T 2LTO_FIL Switching (eg, from “0” to “1”), this delay is related to the bandwidth of the (fast) comparator 50 (eg, a few nanoseconds).

[0203] Likewise, at time T SHOOT Afterwards, signals i_shoot_cmp and o_gate_cmd both switch (e.g., from “0” to “1”), which causes VO to start increasing from VH toward value V PLATEAU Reduce (this is related to V GSTHThis signal is maintained for a period of time, after which VO decreases back to zero.

[0204] The signal VO that falls below V2LTO is mirrored by the output signal 2LTO COMP from the comparator 50 switching back (eg, from "1" to "0") (again delayed by T 2LTO_FIL ), then at time T SHOOT It is then switched back (eg, from “1” to “0”) by the signal i_shoot_comp.

[0205] Therefore, it can be understood that the T of the discharge switch SP is determined by ON The main factor of time is i_gate_cmd( Figure 5 ) and i_shoot_comp (approximately Figure 5 This results in the control terminal (gate) G of the discharge switch SP being SP The switching on and off of the

[0206] exist Figure 3 and Figure 5 In the example, it can be assumed that the HV driver starts from the GIA destination am state (VO=low, ID=0, not conducting any current).

[0207] Consistently, the output of the fast analog comparator 50 (ie, i_shoot_comp) delayed by the delay circuit 60 assumes its idle state (“low”).

[0208] The i_gate_cmd trigger command is considered aligned with the output OFF state ("low"). As illustrated here, the signal o_gate_cmd corresponding to the output of the flip-flop 80 is in the OFF state ("high").

[0209] Those skilled in the art may readily devise alternative implementations that result in the same effect.

[0210] A control signal for the “ON” transition of the switch SP is generated at the node receiving the signal i_gate_cmd, which may be considered as a trigger input for the circuit.

[0211] In a manner known to those skilled in the art, Figure 1 Any entity in the system generates this trigger event.

[0212] For example, a controller such as 100 may trigger turn-on based on a PWM generated by its control algorithm.Differently, the turn-on event may be triggered by the LV / HV portion such as 102 and 104 in the gate pre-driver (eg, via an internal timer).

[0213] Additionally, the trigger device may be generated by control logic implemented in the HV power stage (eg, the safety MCU / logic in block 108 ).

[0214] In this case, the control signal may be fed directly to the HV side pin of the gate pre-driver in block 106 .

[0215] Regardless of the trigger injection point, the circuit 20 as illustrated herein may "observe" the effect of the switch-on command at its destination node at the control terminal (gate) of the HV discharge switch SP.

[0216] A fast comparator such as 50 (with a reaction time of a few nanoseconds) can provide fast feedback of the gate voltage state reported by the "2LTO COMP" signal. The comparison can be made according to a programmable voltage threshold such as "V2LTO", whose value can be adjusted to suit the circuit behavior of different types of HV drivers (SiC, IGBT, MOSFET, etc.). This voltage can be judiciously chosen to cause the comparator 50 to switch (only) when the HV driver is considered to be switched on.

[0217] A programmable delay circuit 60 (“T SHOOT ”), illustrated here as an RC circuit (as discussed, alternative implementations may include a chain of digital inverters or capacitor / current circuits) to further delay the comparator switching event, which helps to fine-tune the turn-on time of the HV driver.

[0218] As discussed, the signal i_shoot_comp is a (accurately) delayed version of the signal 2LTO COMP from the comparator 50. This provides a means of determining the (maximum) current peak value I reached during the shoot-through period. SHOOT_PK flexibility.

[0219] The turn-on time can thus be selected by acting on the programmable delay circuit 60 in a way that prevents SOA violations under worst case conditions. This programmability facilitates fine tuning of the closed loop speed according to different types of HV drivers (IGBT, SiC, MOSFET).

[0220] Alternatively, the programmable delay 60 may be "excluded" from the closed loop (by an amount that sets the delay to zero), such that the output of the fast comparator 50 is coupled to the circuits 70, 80 without an applied delay.

[0221] As shown herein, the signal i_shoot_comp output by the delay circuit 60 drives a mixed signal circuit 70 / 80 that includes discrete logic gates / flip-flops / latches.

[0222] As shown herein, the signal o_gate_cmd from the flip-flop 80 is coupled to the functional gate drive path at 40 for the purpose of conditioning the output from the gate drive logic 40 in such a way as to generate a turn-on command in response to a trigger event generated via the i_gate_cmd signal.

[0223] Furthermore, the circuit shown herein generates a shutdown command when i_shoot_comp (the delayed output from comparator 50 ) reports a rising edge.

[0224] Note that the functional gate drive path at 40 can be configured to ignore the o_gate_cmd input in the presence of a higher priority signal (e.g., overcurrent / short circuit / desaturation event). Although not mandatory, this strategy may be advantageous as long as it helps achieve circuit robustness against HV driver SOA violations.

[0225] The above implementation illustrates a circuit capable of determining the exact HV driver on-time during the shoot-through period. The performance of the circuit is not affected by Figure 1 The impact of increased uncertainty in the system box.

[0226] The only remaining uncertainty is related to the closed feedback network, whose accuracy can be fine-tuned according to the application specifications during the hardware design phase.

[0227] Such operation facilitates accurate control of the magnitude of the current through switch SP, and therefore the actual duty cycle of the PWM signal applied thereto, in response to feedback action achieved by sensing the gate voltage of switch SP (at node MC).

[0228] This gate voltage is compared (at comparator 50) to a reference value (V2LTO). Taking into account the particular characteristics of the circuit / system involved, it is helpful to selectively change (i.e., program) the delay applied to the signal at 60 that is fed back to control logic 40 in order to manage switches 21 and 22 (primarily switch 22 during shoot-through operation). As a result, when switch SP opposes (primarily due to Figure 5 The switch SP can effectively control the discharge of the energized element (eg, the DC link capacitor LC) when there is any undesired “spike” in the discharge current ID (the controlled behavior of VO in FIG. 1 ).

[0229] like Figure 5 As shown in the bottom curve in FIG. 1 , in one or more embodiments, the peak value I can be increased from zero to peak value I SHOOT_PK The sawtooth wave approximates the discharge current ID, the peak value I SHOOT_PK Depends on the shoot-through duration and parasitic inductance of the time interval generated by the sum of four time intervals:

[0230] From VO to V 2LTO The time spent T PLATEAU2LTO ;

[0231] Delay T 2LTO_FIL ;

[0232] Time T SHOOT ;

[0233] From VO to V H Reduce to V PLATEAU The time spent T OFF Plus maintain V PLATEAU time.

[0234] Value T 2LTO_FIL +T SHOOT can be considered as an example of the duty cycle of a PWM signal, since V 2LTO =V PLATEAU and a similar small error at turn-off (T OFF can be ignored), so a small error can be set at the turn-on.

[0235] It should be understood that time T PLATEAU2LTO can be neglected as long as it generates an error in the current peak estimation, which can be reduced by fine-tuning the T SHOOT and V 2LTO to take this error into account.

[0236] The same applies to the period T PWM_SHOOT , i.e. the period of the PWM signal generated by the "safety" logic. This can be fixed (corresponding to 20kHz, for example) or variable.

[0237] For example, consider the fact that the peak current I SHOOT_PK will decrease as the DC link gradually discharges, and increase the PWM frequency as the discharge progresses.

[0238] In fact, assuming I SHOOT_PK is constant at each discharge cycle, then QCycle subtracted at each PWM cycle can be estimated as:

[0239] Q CYCLE＝ (T 2LTO_FIL+ T SHOOT )*I SHOOT_PK

[0240] Assume that at the beginning of the shutdown, the charge Q DC_LINK =C DC_LINK *V DC_LINK is stored in the DC link (where C DC_LINK and V DC_LINKis the capacitance of the DC link and the voltage applied to both ends of the DC link), resulting in a PWM cycle N of complete discharge of the DC link CYCLES The number can be estimated as:

[0241] N CYCLES =Q DC_LINK / Q CYCLE

[0242] For reference, for a fixed frequency PWM discharge:

[0243] The 600μF DC link can be discharged using 10kHz PWM and 200ns total off time (this may be beneficial for the IGBT switches);

[0244] A 1mF DC link can be discharged using 20kHz PWM and 200ns total off time (this may be beneficial for SiC switches).

[0245] In fact, the DC link voltage gradually decreases as the DC link discharge proceeds, and the slope of the current decreases accordingly, making I SHOOT_PK Getting smaller and smaller.

[0246] The discharge current (ID) is not constant during the entire forward iteration, as long as the slope (A / ns) and peak value (I SHOOT_PK ) will decrease due to the reduction in voltage across the DC link.

[0247] To compensate for this effect, the "safety" logic can implement two strategies (these can also be implemented in parallel):

[0248] Increase PWM frequency (reduce T PWM_SHOOT ) to have smaller peaks at higher repetition rates, and / or

[0249] As the DC link voltage decreases, a wider shoot-through time (T SHOOT ) (This is easy when accessing SPI).

[0250] Therefore, the controller logic can be implemented to reduce T based on the DC link voltage PWM_SHOOT strategy.

[0251] By programming a longer T SHOOT To further reduce the discharge time, this may involve a judicious trade-off with undesirable overstress of the DC link capacitors and the traction module drives.

[0252] It is found that the through-discharge solution as exemplified herein provides a viable alternative to conventional active discharge in the art, with the ability to meet discharge timing specifications in practical application scenarios.

[0253] One or more embodiments as discussed herein have been found to be cost effective, with the ability to provide BoM savings compared to active discharge circuits.

[0254] That is, this may be related to the ability to disable interlock and / or the possibility to generate small turn-on pulses using existing (2LTO) comparators such as 50. In terms of small area, the shoot-through discharge implemented via one or more embodiments may benefit from the reuse of existing 2LTO comparators.

[0255] The through discharge implemented via one or more embodiments may also benefit from the presence of a dedicated enable bit in the SPI register map as previously discussed, and has no adverse impact on safety due to the maintained presence of the (e.g., DES / ISEN) diagnostics. To this end, a blanking time may be applied to the EDS / ISEN diagnostics. For example, such a blanking time may be higher than or equal to T (e.g., programmed via SPI). SHOOT time, so that these diagnostics remain active but are masked during the pass-through period.

[0256] The digital SPI registers can be advantageously accessed by utilizing the existing ADC_POL registers (eg, for the VGE monitor filter). No new registers and / or modifications to the existing communication protocol are involved.

[0257] The circuit (20) as exemplified herein may include:

[0258] The driving circuit device (eg, 21, 22, 31, 32, 40) is configured to be coupled (eg, VO+, VO-, RCHG, RDCHG) to a control terminal (eg, G) of an electronic switch (eg, SP). SP ), and applying a discharge signal to the control terminal (for example, see Figure 5 The corresponding behavior of VO and discharge current ID in the above circuit causes the electronic switch to become conductive and provide an electrical discharge path for the energized element (e.g., LC),

[0259] a sensing node (eg, MC) configured to be coupled to the control terminal and to sense a voltage at the control terminal,

[0260] A feedback network (e.g., 50, 60, 70, 80) is coupled between the sensing node and the driving circuit device, and the driving circuit device is configured to generate the discharge signal according to a result of comparing the voltage at the control terminal sensed at the sensing node with a reference threshold (e.g., V2LTO) (e.g., at 50).

[0261] In the circuit as illustrated herein, the feedback network may include a comparator circuit (e.g., 50) coupled to the sensing node and configured to compare the voltage at the control terminal sensed at the sensing node with the reference threshold, wherein the comparator circuit is configured to provide a comparison signal (e.g., 2LTOCOMP) having a first value and a second value, respectively, in response to the voltage at the control terminal being higher or lower than the reference threshold.

[0262] In circuits as illustrated herein, the feedback network may include a delay circuit (eg, 60 ) coupled to a comparator circuit and configured to provide a delayed copy of the comparison signal (eg, i_shoot_comp) to the driver circuit.

[0263] Thus, the control terminal (eg, G) of the electronic switch (eg, SP) can be SP ) to accurately control the discharge process (e.g., with a delay of the delay replica selected in the range of 0-70ns) to combat an uncontrolled, undesirable increase in the discharge current.

[0264] In the circuits as illustrated herein, the delay circuit (e.g., 60) may include a programmable (e.g., i_shoot_dly) delay circuit configured to apply a delay to the comparison signal from the comparator circuit, the delay having a delay value selected from a plurality of delay values ​​(e.g., a selected number of delay steps of 5-10 ns).

[0265] In circuits as illustrated herein, the delay circuit may be configured to be programmed (eg, via i_shoot_dly) to provide the comparison signal from the comparator circuit with a zero delay value to the driver circuitry.

[0266] In the circuit as exemplified herein, the delay circuit device may include one of the following devices:

[0267] Logic inverter chain,

[0268] capacitor / current circuit, and / or

[0269] RC low-pass network.

[0270] In the circuit as exemplified herein, the driving circuit device may be configured to generate a voltage drop in response to the comparison signal (eg, see Figure 5 VO in response to i_shoot_comp going high decreases from VH) changes (ie, increases and / or decreases) the discharge signal (eg, see Figure 5The duration and / or frequency of VO in the flow cell.

[0271] In circuits as exemplified herein, the drive circuit arrangement may be configured to vary at least one parameter of a frequency and a duration of the discharge cycles in response to a decrease in charge of the energization element during the sequence of discharge cycles.

[0272] In the circuit as illustrated herein, the driving circuit device may include a logic circuit (eg, 40) configured to operate the circuit:

[0273] in a functional (operating) state, wherein the drive circuit means applies a PWM modulated signal to the control terminal, causing the electronic switch to alternately conduct and not conduct, or

[0274] In a discharge state, wherein the drive circuit applies the discharge signal to the control terminal, the electronic switch becomes conductive and provides an electrical discharge path for the energized element.

[0275] The circuit as illustrated herein may include a threshold comparator (e.g., 91, 92) coupled to the drive circuit device (e.g., see signal i_shoot_en applied to logic 40 via AND gate 70 and flip-flop 80) and configured to receive a command signal (e.g., Figure 3A BRAKE in the embodiment of the present invention, wherein the logic circuit device (40) is configured to operate:

[0276] In the functional state, in response to the command signal having a first value received at the threshold comparator,

[0277] In the discharge state, in response to the command signal having a second value received at the threshold comparator.

[0278] In a circuit as exemplified herein, the driving circuit arrangement may include:

[0279] The first electronic switch (eg, 21) is configured to (eg, VO+, RCHG) connect the control terminal (eg, G SP ) is coupled to a high-side voltage node (e.g., VH),

[0280] The second electronic switch (eg, 22) is configured to (eg, VO-, RDCHG) connect the control terminal (eg, G SP ) is coupled to the low-side voltage node (VL),

[0281] Switch drive circuitry (eg, 31, 32) configured to cause the first and second electronic switches (both) to enter a conductive state to cause the electronic switches to become conductive and provide an electrical discharge path for the energized element.

[0282] In the circuit as illustrated herein, the first electronic switch and the second electronic switch may be configured to be coupled to the control terminal via respective coupling resistors (eg, RCHG, RDCHG).

[0283] A system as exemplified herein (e.g., 10) may include:

[0284] With control terminals (e.g., G SP ) of an electronic switch (eg, SP), the electronic switch being configured to respond to a discharge signal (eg, see Figure 5 VO in the circuit provides an electrical discharge path for the energized element (e.g., LC).

[0285] The circuit as illustrated herein has the drive circuit device coupled (e.g., see VO+, VO-, RCHG, RDCHG) to the control terminal of the electronic switch to apply the discharge signal to the control terminal, which causes the electronic switch to become conductive and provide an electrical discharge path for the energized element.

[0286] The system as illustrated herein may include a low voltage domain (100, LV) and a high voltage domain (102, 104, 106, 108, HV), and a circuit (eg, 20) included in the high voltage domain of the system along with the electronic switch as illustrated herein.

[0287] A system as illustrated herein may include an electric motor (e.g., M) having at least one winding configured to be selectively energized via at least one phase coupled to the motor, wherein the electronic switch (e.g., SP) includes the at least one phase switch (e.g., Q1, Q2).

[0288] A motor vehicle (e.g., V) equipped with (powered by) a system as illustrated herein may include the electric motor (e.g., M) to provide electric traction power for the vehicle, wherein the vehicle includes a DC link capacitor (e.g., LC), wherein the electronic switch (e.g., SP; Q1, Q2) is configured to provide an electrical discharge path for the DC link capacitor.

[0289] As illustrated herein, a method of operating an electronic switch (eg, SP) is to provide an electrical discharge path for a energized element (eg, LC) having a control terminal (eg, G SP ) may include:

[0290] Applying a discharge signal to the control terminal causes the electronic switch to become conductive and provide a means for energizing the element (see, for example, Figure 5 The electrical discharge path of VO and the corresponding behavior of the discharge current ID is described in detail below.

[0291] sensing a voltage at the control terminal (e.g., at MC),

[0292] According to the control terminal (G SP ) sensed at the discharge signal in a closed loop feedback arrangement (see, for example, Figure 5 VO in ),

[0293] The method comprises:

[0294] The voltage at the control terminal is compared to a reference threshold (e.g., V2LTO), and the discharge signal is generated in a closed-loop feedback arrangement according to a comparison signal (e.g., 2LTO COMP) having a first value and a second value in response to the voltage at the control terminal being higher or lower than the reference threshold, respectively.

[0295] Methods as exemplified herein may include generating the discharge signal in a closed-loop feedback arrangement based on a delayed copy of the comparison signal (eg, i_shoot_comp).

[0296] In this way, the discharge process can be accurately controlled (eg, with the delay of the delayed replica selected in the range of 0-70 ns) against an uncontrolled, undesirable increase of the discharge current.

[0297] The details and embodiments may vary, even significantly, with respect to what has been described purely by way of example, without prejudice to the underlying principles and without departing from the scope of protection.

[0298] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: a drive circuit arrangement configured to be coupled to a control terminal of the electronic switch, and the drive circuit arrangement is configured to apply a discharge signal to the control terminal so that the electronic switch becomes conductive and provides an electrical discharge path for the energized element; a sensing node configured to be coupled to the control terminal, and the sensing node is configured to sense a voltage at the control terminal; as well as a feedback network coupled between the sensing node and the driving circuit device, wherein the feedback network comprises a comparator circuit coupled to the sensing node, and the comparator circuit is configured to: comparing the voltage at the control terminal sensed at the sense node with a reference threshold, and providing a comparison signal having a first value and a second value in response to the voltage at the control terminal being above the reference threshold, or below the reference threshold, respectively, wherein the feedback network further comprises a delay circuit, the delay circuit being coupled to the comparator circuit, and the delay circuit being configured to provide a delayed copy of the comparison signal to the driver circuit arrangement so as to counteract an uncontrolled increase in discharge current in the discharge path; and The driving circuit device is configured to generate the discharge signal according to the comparison signal. 2 . The circuit of claim 1 , wherein the delay circuit comprises a programmable delay circuit configured to apply a delay having a delay value selected from a plurality of delay values ​​to the comparison signal. 3 . The circuit of claim 2 , wherein the delay circuit is configured to provide the comparison signal to the driver circuit arrangement with a zero delay value.

4. The circuit of claim 2, wherein the delay circuit comprises a logic inverter chain, a capacitor / current circuit, and / or an RC low-pass network. 5 . The circuit of claim 1 , wherein the drive circuit arrangement is configured to vary the duration and / or frequency of the discharge signal as a function of the comparison signal in a sequence of discharge cycles of the energization element.

6. The circuit of claim 5, wherein the drive circuit arrangement is configured to vary at least one of the frequency or the duration of the discharge cycles in response to a decrease in charge of the energization element during the sequence of discharge cycles.

7. The circuit according to claim 1, in, In a functional state, the drive circuit device is configured to apply a PWM modulation signal to the control terminal so that the electronic switch is alternately conductive and non-conductive, or Therein, in a discharge state, the drive circuit device is configured to apply the discharge signal to the control terminal so that the electronic switch becomes conductive and provides the electrical discharge path for the energization element.

8. The circuit according to claim 7, further comprising: a threshold comparator coupled to the driver circuit device and configured to receive a command signal, The logic circuit device of the driving circuit device is configured as follows: responsive to the command signal received at the threshold comparator having a first value, operating the circuit in the functional state, and In response to the command signal received at the threshold comparator having a second value, operating the circuit in the discharge state.

9. The circuit of claim 1 , wherein the drive circuit arrangement comprises: a first electronic switch configured to couple the control terminal to a high-side voltage node in a conductive state; a second electronic switch configured to couple the control terminal to a low-side voltage node in a conductive state; as well as A switch drive circuit arrangement is configured to cause the first electronic switch and the second electronic switch to enter the conductive state so that the electronic switches become conductive and provide the electrical discharge path for the energization element. 10 . The circuit of claim 9 , wherein the first electronic switch and the second electronic switch are configured to be coupled to the control terminal via respective coupling resistors.

11. A system comprising: The circuit of claim 1, wherein the circuit is coupled to an electronic switch comprising a control terminal.

12. The system according to claim 11, The system includes a low voltage domain and a high voltage domain, and wherein the circuit together with the electronic switch is in the high voltage domain.

13. The system of claim 11, further comprising an electric motor having at least one winding configured to be energized via at least one phase switch coupled thereto, wherein the electronic switch comprises the at least one phase switch.

14. A motor vehicle comprising: The system according to claim 13, wherein the electric motor is configured to provide electric traction power for the vehicle, wherein the vehicle comprises a DC link capacitor in the energization element, and Wherein the electronic switch is configured to provide an electrical discharge path for the DC link capacitor.

15. A method for operating an electronic switch, the method comprising: applying a discharge signal to a control terminal of the electronic switch so that the electronic switch becomes conductive and provides an electrical discharge path for the energized element; sensing a voltage at the control terminal; as well as comparing the sensed voltage at the control terminal to a reference threshold; as well as In response to the voltage at the control terminal being above or below the reference threshold, the discharge signal is provided in a closed loop feedback arrangement according to delayed copies of a comparison signal having first and second values, respectively, so as to counteract an uncontrolled increase in discharge current in the discharge path.

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