A high linearity ultra-wideband amplifier

Abstract

The application discloses a high-linearity ultra-wideband amplifier, wherein an input end of an input matching network serves as an input end of the amplifier, an output end of the input matching network is connected with an input end of an ultra-wideband amplification network, an output end of the ultra-wideband amplification network is connected with an input end of a J-class amplification output matching network, and an output end of the J-class amplification output matching network serves as an output end of the amplifier; the ultra-wideband amplification network is further connected with a first active bias network, a second active bias network, a feed matching network and a passive bias network respectively. The high-linearity ultra-wideband amplifier provided by the application adopts Darlington + common-source common-gate amplification network, is combined with a novel active bias technology, adopts J-class amplification output matching network for output matching, and realizes the characteristics of ultra-wideband, high gain, high linearity and high efficiency together, and has the advantages of wide working frequency band, high gain, high linearity, high efficiency, low power consumption and small area.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a high linearity ultra-wideband amplifier. Background Technology

[0002] With the continuous development of radar technology and modern mobile communications, electronic devices used in modern electronic warfare, such as frequency-hopping communications and broadband jammers, are increasingly operating on wider bandwidths. This urgently requires the development of broadband electronic reconnaissance receivers to meet the needs of electronic countermeasures in future warfare. Microwave broadband high-linearity amplifiers are key components of broadband electronic reconnaissance receivers, and their performance directly affects important parameters such as signal characteristics, sensitivity, and reconnaissance range. Among the many performance indicators of broadband amplifiers, gain and bandwidth are two relatively important. However, the gain and bandwidth of an amplifier cannot be increased simultaneously beyond a certain limit; these two quantities often require a trade-off. In addition to gain and bandwidth, amplifier efficiency and linearity are also important indicators that require a balance. Summary of the Invention

[0003] To address the aforementioned shortcomings in existing technologies, the high linearity ultra-wideband amplifier solution provided by this invention employs a Darlington + cascode amplification network, combined with a novel active biasing technology, and uses a Class J amplification output matching network for output matching, together achieving ultra-wideband, high gain, high linearity, and high efficiency characteristics.

[0004] To achieve the above-mentioned objectives, the technical solution adopted by the present invention is as follows: a high linearity ultra-wideband amplifier, comprising an input matching network, an ultra-wideband amplification network, a first active bias network, a second active bias network, a passive bias network, and a Class J amplification output matching network;

[0005] The input terminal of the input matching network serves as the input terminal of the amplifier. The output terminal of the input matching network is connected to the input terminal of the ultra-wideband amplification network. The output terminal of the ultra-wideband amplification network is connected to the input terminal of the Class J amplification output matching network. The output terminal of the Class J amplification output matching network serves as the output terminal of the amplifier.

[0006] The ultra-wideband amplification network is also connected to the first active bias network, the second active bias network, the power supply matching network, and the passive bias network, respectively.

[0007] The beneficial effects of this invention are as follows: This invention employs a Darlington + cascode amplification network, combined with a novel active biasing technology, and uses a Class J amplification output matching network for output matching. Together, these achieve ultra-wide bandwidth, high gain, high linearity, and high efficiency, while also considering impedance matching and gain flatness. This reduces the circuit's sensitivity to process fluctuations and temperature changes, and improves the circuit's stability and reliability. This invention has advantages such as wide operating bandwidth, high gain, high linearity, high efficiency, and small area.

[0008] Furthermore, the input matching network includes a capacitor C1 and an inductor L1;

[0009] One end of the capacitor C1 serves as the input terminal of the input matching network, and the other end of the capacitor C1 is connected to one end of the inductor L1, with the other end of the inductor L1 serving as the output terminal of the input matching network.

[0010] The beneficial effects of the above-mentioned further solutions are as follows: The input matching network used in this invention performs impedance matching on the radio frequency input signal through series capacitors and inductors.

[0011] Furthermore, the ultra-wideband amplification network includes field-effect transistors M1, M2, and M3, microstrip lines TL1 and TL2, grounding resistors R1 and R2, resistors R8, R9, R10, and R16, inductor L3, grounding capacitor C3, and grounding capacitor C5.

[0012] The gate of the field-effect transistor M1 serves as the input terminal of the ultra-wideband amplification network, and is connected to one end of resistor R16 and the second active bias network. The other end of resistor R16 is connected to the first active bias network and the passive bias network. The source of the field-effect transistor M1 is connected to one end of microstrip line TL2 and ground resistor R1. The other end of microstrip line TL2 is connected to the first active bias network, the second active bias network, and the gate of the field-effect transistor M2. The source of the field-effect transistor M2 is connected to ground resistor R2. The drain of the field-effect transistor M1 is connected to one end of microstrip line TL1. The other end of the microstrip line TL1 is connected to the drain of the field-effect transistor M2 and one end of the inductor L3. The other end of the inductor L3 is connected to one end of the resistor R8 and the source of the field-effect transistor M3. The other end of the resistor R8 is connected to the grounding capacitor C3. The drain of the field-effect transistor M3 serves as the output terminal of the ultra-wideband amplification network and is connected to the passive bias network and the power supply matching network. The gate of the field-effect transistor M3 is connected to one end of the resistor R9. The other end of the resistor R9 is connected to one end of the resistor R10 and the passive bias network. The other end of the resistor R10 is connected to the grounding capacitor C5.

[0013] The beneficial effects of the above-mentioned further solutions are as follows: The ultra-wideband amplifier network in this invention adopts a Darlington + cascode structure, and at the same time combines a parallel negative feedback structure to achieve an ultra-wideband operating frequency band and high gain characteristics. While obtaining a low noise figure, it has a moderate output power, effectively reducing circuit power consumption, and the overall circuit area also has a significant advantage.

[0014] Furthermore, the first active bias network includes a grounding resistor R3, a resistor R5, a resistor R6, a grounding capacitor C2, and a field-effect transistor M4;

[0015] The source of the field-effect transistor M4 is connected to the grounding resistor R3, the gate of the field-effect transistor M4 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the other end of the microstrip line TL12 in the ultra-wideband amplification network, the drain of the field-effect transistor M4 is connected to the grounding capacitor C2 and one end of the resistor R6, and the other end of the resistor R6 is connected to the other end of the resistor R16 in the ultra-wideband amplification network.

[0016] Furthermore, the second active bias network includes a field-effect transistor M5, a grounding resistor R4, a grounding resistor C11, and a resistor R17;

[0017] The source of the field-effect transistor M5 is connected to the grounding resistor R4 and the grounding capacitor C11, respectively. The drain of the field-effect transistor M5 is connected to one end of the resistor R17 and the gate of the field-effect transistor M1 in the ultra-wideband amplification network, respectively. The gate of the field-effect transistor M5 is connected to one end of the resistor R17, and the other end of the resistor R17 is connected to the other end of the microstrip line TL2 in the ultra-wideband amplification network.

[0018] The beneficial effects of the above-mentioned further solutions are as follows: The novel active bias network adopted in this invention provides bias voltages to transistors M1 and M2 in the first active bias network through self-biasing transistors M4 and M5. When supply voltage fluctuations are caused by process fluctuations or temperature changes, the self-biasing transistors can control the gate voltage to influence the drain saturation current, thereby controlling the input voltage and achieving negative feedback. This effectively reduces the circuit's sensitivity to process fluctuations and temperature changes, improves the circuit's linearity, and makes the amplifier more stable.

[0019] Furthermore, the passive bias network includes resistors R7, R11, R12, and grounding resistor R13;

[0020] One end of resistor R7 is connected to the other end of resistor R16 in the ultra-wideband amplification network. The other end of resistor R7 is connected to the drain of field-effect transistor M3 and one end of resistor R12 in the ultra-wideband amplification network. The other end of resistor R12 is connected to one end of grounding resistor R13 and resistor R11. The other end of resistor R11 is connected to the other end of resistor R9 in the ultra-wideband amplification network.

[0021] The beneficial effects of the above-mentioned further solutions are as follows: the gate voltage of the field effect transistor M3 in this invention is provided by a passive bias network resistor voltage divider structure. In the specific design, the voltage divider resistors are of the same type, which can effectively reduce the sensitivity of the gate voltage to process fluctuations.

[0022] Furthermore, the power supply matching network includes grounding capacitor C11, grounding capacitor C10, grounding capacitor C12, resistor R14, resistor R15, inductor L4, and inductor L5;

[0023] One end of the inductor L4 is connected to the drain of the field-effect transistor M3 in the ultra-wideband amplifier network. The other end of the inductor L4 is connected to one end of the inductor L5 and the resistor R14. The other end of the resistor R14 is connected to the grounding capacitor C12. The other end of the inductor L5 is connected to the grounding capacitor C10, one end of the resistor R15 and the power supply VDD. The other end of the resistor R15 is connected to the grounding capacitor C11.

[0024] The beneficial effects of the above-mentioned further solutions are as follows: In this invention, the power supply matching network adopts a two-stage inductor series structure to expand the bandwidth, and eliminates the resonance introduced by the inductor by adding an RC series-to-ground structure between the two inductors. The power supply terminal adopts a structure with a small capacitor and a large capacitor resistor connected in parallel to ground to filter out high-frequency and low-frequency ripple.

[0025] Furthermore, the J-type amplification output matching network includes inductor L6, inductor L7, ground inductor L8, capacitor C6, capacitor C7, capacitor C8, and ground capacitor C9;

[0026] One end of the inductor L6 serves as the input terminal of the Class J amplification output matching network and is connected to one end of the capacitor C6. The other end of the inductor L6 is connected to the other end of the capacitor C6, one end of the inductor L7, and one end of the capacitor C8. The other end of the capacitor C8 is connected to the grounding inductor L8. The other end of the inductor L7 is connected to the grounding capacitor C9 and one end of the capacitor C7. The other end of the capacitor C7 serves as the output terminal of the Class J amplification output matching network.

[0027] The advantages of the above-mentioned further solutions are as follows: The output matching uses a Class J amplifier output matching network to control harmonic impedance, thereby reducing transistor energy loss and improving amplifier efficiency. Both interstage and output circuits use RC-to-ground circuits to suppress power supply self-oscillation instability signals. Attached Figure Description

[0028] Figure 1 The diagram shows the structure of the high linearity ultrawideband amplifier provided by this invention.

[0029] Figure 2 The circuit diagram of the high linearity ultrawideband amplifier provided by the present invention. Detailed Implementation

[0030] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0031] This invention provides a high linearity ultrawideband amplifier, such as... Figure 1 As shown, it includes an input matching network, an ultra-wideband amplification network, a first active bias network, a second active bias network, a passive bias network, and a J-type amplification output matching network;

[0032] The input terminal of the input matching network is used as the input terminal of the amplifier. The output terminal of the input matching network is connected to the input terminal of the ultra-wideband amplification network. The output terminal of the ultra-wideband amplification network is connected to the input terminal of the Class J amplification output matching network. The output terminal of the Class J amplification output matching network is used as the output terminal of the amplifier.

[0033] The ultra-wideband amplification network is also connected to the first active bias network, the second active bias network, the power supply matching network, and the passive bias network, respectively.

[0034] like Figure 2 As shown, the input matching network in this embodiment of the invention includes a capacitor C1 and an inductor L1;

[0035] One end of capacitor C1 serves as the input terminal of the input matching network, and the other end of capacitor C1 is connected to one end of inductor L1, with the other end of inductor L1 serving as the output terminal of the input matching network.

[0036] like Figure 2As shown, the ultra-wideband amplification network in this embodiment of the invention includes field-effect transistors M1, M2, and M3, microstrip lines TL1 and TL2, grounding resistors R1 and R2, resistors R8, R9, R10, and R16, inductor L3, grounding capacitor C3, and grounding capacitor C5.

[0037] The gate of field-effect transistor M1 serves as the input terminal of the ultra-wideband amplifier network, connected to one end of resistor R16 and the second active bias network. The other end of resistor R16 is connected to the first active bias network and the passive bias network. The source of field-effect transistor M1 is connected to one end of microstrip line TL2 and ground resistor R1. The other end of microstrip line TL2 is connected to the first active bias network, the second active bias network, and the gate of field-effect transistor M2. The source of field-effect transistor M2 is connected to ground resistor R2. The drain of field-effect transistor M1 is connected to one end of microstrip line TL1. The other end of the wire TL1 is connected to the drain of the field-effect transistor M2 and one end of the inductor L3. The other end of the inductor L3 is connected to one end of the resistor R8 and the source of the field-effect transistor M3. The other end of the resistor R8 is connected to the grounding capacitor C3. The drain of the field-effect transistor M3 serves as the output terminal of the ultra-wideband amplification network and is connected to the passive bias network and the power supply matching network. The gate of the field-effect transistor M3 is connected to one end of the resistor R9. The other end of the resistor R9 is connected to one end of the resistor R10 and the passive bias network. The other end of the resistor R10 is connected to the grounding capacitor C5.

[0038] like Figure 2 As shown, the first active bias network in this embodiment of the invention includes a grounding resistor R3, a resistor R5, a resistor R6, a grounding capacitor C2, and a field-effect transistor M4;

[0039] The source of the field-effect transistor M4 is connected to the grounding resistor R3. The gate of the field-effect transistor M4 is connected to one end of the resistor R5. The other end of the resistor R5 is connected to the other end of the microstrip line TL12 in the ultra-wideband amplifier network. The drain of the field-effect transistor M4 is connected to the grounding capacitor C2 and one end of the resistor R6. The other end of the resistor R6 is connected to the other end of the resistor R16 in the ultra-wideband amplifier network.

[0040] like Figure 2 As shown, the second active bias network in this embodiment of the invention includes a field-effect transistor M5, a grounding resistor R4, a grounding resistor C11, and a resistor R17.

[0041] The source of the field-effect transistor M5 is connected to the grounding resistor R4 and the grounding capacitor C11, respectively. The drain of the field-effect transistor M5 is connected to one end of the resistor R17 and the gate of the field-effect transistor M1 in the ultra-wideband amplifier network, respectively. The gate of the field-effect transistor M5 is connected to one end of the resistor R17, and the other end of the resistor R17 is connected to the other end of the microstrip line TL2 in the ultra-wideband amplifier network.

[0042] like Figure 2 As shown, the passive bias network in this embodiment of the invention includes resistors R7, R11, R12 and grounding resistor R13;

[0043] One end of resistor R7 is connected to the other end of resistor R16 in the ultra-wideband amplifier network. The other end of resistor R7 is connected to the drain of field-effect transistor M3 in the ultra-wideband amplifier network and one end of resistor R12. The other end of resistor R12 is connected to the grounding resistor R13 and one end of resistor R11. The other end of resistor R11 is connected to the other end of resistor R9 in the ultra-wideband amplifier network.

[0044] like Figure 2 As shown, the power supply matching network in this embodiment of the invention includes grounding capacitor C11, grounding capacitor C10, grounding capacitor C12, resistor R14, resistor R15, inductor L4, and inductor L5.

[0045] One end of inductor L4 is connected to the drain of field-effect transistor M3 in the ultra-wideband amplifier network. The other end of inductor L4 is connected to one end of inductor L5 and resistor R14. The other end of resistor R14 is connected to grounding capacitor C12. The other end of inductor L5 is connected to grounding capacitor C10, one end of resistor R15 and power supply VDD. The other end of resistor R15 is connected to grounding capacitor C11.

[0046] like Figure 2 As shown, the J-type amplification output matching network in this embodiment of the invention includes inductor L6, inductor L7, ground inductor L8, capacitor C6, capacitor C7, capacitor C8 and ground capacitor C9;

[0047] One end of inductor L6 serves as the input terminal of the Class J amplifier output matching network and is connected to one end of capacitor C6. The other end of inductor L6 is connected to the other end of capacitor C6, one end of inductor L7, and one end of capacitor C8. The other end of capacitor C8 is connected to grounded inductor L8. The other end of inductor L7 is connected to grounded capacitor C9 and one end of capacitor C7. The other end of capacitor C7 serves as the output terminal of the Class J amplifier output matching network.

[0048] The following is combined Figure 2 The specific working principle and process of this invention are described below:

[0049] In this invention, the radio frequency input signal enters the input matching network of the amplifier through the input terminal RFin. After impedance matching by the input matching network, it enters the ultra-wideband amplification network for signal amplification. The amplified signal enters the output matching network for signal output matching, and finally forms the radio frequency output signal that reaches the output terminal RFout.

[0050] The ultra-wideband amplifier network employs a Darlington + cascode amplification network, combined with a parallel negative feedback structure, achieving an ultra-wideband operating frequency band and high gain characteristics. It achieves a low noise figure while maintaining moderate output power, effectively reducing circuit power consumption, and offering significant advantages in overall circuit area. A novel active bias network, specifically the second active bias network, provides bias voltages to transistors M1 and M2 in the first active bias network via self-biased transistors M4 and M5. When supply voltage fluctuations occur due to process variations or temperature changes, the self-biased transistors can influence the drain saturation current by controlling the gate voltage, thereby controlling the input voltage and achieving negative feedback. This effectively reduces the circuit's sensitivity to process variations and temperature changes, improves circuit linearity, and makes the amplifier more stable.

[0051] The power supply matching network uses a two-stage inductor series structure to extend the bandwidth, and eliminates the resonance introduced by the inductor by adding an RC series connection to ground between the two inductors. The power supply terminal uses a parallel structure of a small capacitor and a large capacitor resistor to ground to filter out high-frequency and low-frequency ripple.

[0052] The output matching employs a Class J amplification output matching network to achieve ultra-wide bandwidth, high gain, high linearity, and high efficiency, while also considering impedance matching and gain flatness. This reduces the circuit's sensitivity to process fluctuations and temperature changes, improving its stability and reliability. This invention offers advantages such as wide operating bandwidth, high gain, high linearity, high efficiency, and small area.

Claims

1. A high linearity ultra-wideband amplifier characterized by, The input matching network, the ultra-wideband amplification network, the first active biasing network, the second active biasing network, the passive biasing network and the class J amplification output matching network are connected in series. The input end of the input matching network is the input end of the amplifier, the output end of the input matching network is connected with the input end of the ultra-wideband amplification network, the output end of the ultra-wideband amplification network is connected with the input end of the class J amplification output matching network, and the output end of the class J amplification output matching network is the output end of the amplifier. The ultra-wideband amplification network is further connected with the first active biasing network, the second active biasing network, the feed matching network and the passive biasing network respectively. The ultra-wideband amplification network comprises a field effect transistor M1, a field effect transistor M2, a field effect transistor M3, a microstrip line TL1, a microstrip line TL2, a grounding resistor R1, a grounding resistor R2, a resistor R8, a resistor R9, a resistor R10, a resistor R16, an inductor L3, a grounding capacitor C3 and a grounding capacitor C5. The gate of the field effect transistor M1 is the input end of the ultra-wideband amplification network, is connected with one end of the resistor R16 and the second active biasing network respectively, the other end of the resistor R16 is connected with the first active biasing network and the passive biasing network respectively, the source of the field effect transistor M1 is connected with one end of the microstrip line TL2 and the grounding resistor R1 respectively, the other end of the microstrip line TL2 is connected with the first active biasing network, the second active biasing network and the gate of the field effect transistor M2 respectively, the source of the field effect transistor M2 is connected with the grounding resistor R2, the drain of the field effect transistor M1 is connected with one end of the microstrip line TL1, the other end of the microstrip line TL1 is connected with the drain of the field effect transistor M2 and one end of the inductor L3 respectively, the other end of the inductor L3 is connected with one end of the resistor R8 and the source of the field effect transistor M3 respectively, the other end of the resistor R8 is connected with the grounding capacitor C3, the drain of the field effect transistor M3 is the output end of the ultra-wideband amplification network and is connected with the passive biasing network and the feed matching network respectively, the gate of the field effect transistor M3 is connected with one end of the resistor R9, the other end of the resistor R9 is connected with one end of the resistor R10 and the passive biasing network respectively, and the other end of the resistor R10 is connected with the grounding capacitor C5.

2. The high linearity ultra-wideband amplifier of claim 1, wherein, The input matching network comprises a capacitor C1 and an inductor L1. One end of the capacitor C1 is the input end of the input matching network, the other end of the capacitor C1 is connected with one end of the inductor L1, and the other end of the inductor L1 is the output end of the input matching network.

3. The high linearity ultra-wideband amplifier of claim 1, wherein, The first active biasing network comprises a grounding resistor R3, a resistor R5, a resistor R6, a grounding capacitor C2 and a field effect transistor M4. The source of the field effect tube M4 is connected with the ground resistance R3, the gate of the field effect tube M4 is connected with one end of the resistance R5, the other end of the resistance R5 is connected with the other end of the microstrip line TL12 in the ultra wide band amplification network, the drain of the field effect tube M4 is connected with the ground capacitor C2 and one end of the resistance R6 respectively, the other end of the resistance R6 is connected with the other end of the resistance R16 in the ultra wide band amplification network.

4. The high linearity ultra-wideband amplifier of claim 1, wherein, The second active bias network comprises a field effect tube M5, a ground resistance R4, a ground capacitor C11 and a resistance R17; The source of the field effect tube M5 is connected with the ground resistance R4 and the ground capacitor C11 respectively, the drain of the field effect tube M5 is connected with one end of the resistance R17 and the gate of the field effect tube M1 in the ultra wide band amplification network respectively, the gate of the field effect tube M5 is connected with one end of the resistance R17, the other end of the resistance R17 is connected with the other end of the microstrip line TL2 in the ultra wide band amplification network.

5. The high linearity ultra-wideband amplifier of claim 1, wherein, The passive bias network comprises a resistance R7, a resistance R11, a resistance R12 and a ground resistance R13; One end of the resistance R7 is connected with the other end of the resistance R16 in the ultra wide band amplification network, the other end of the resistance R7 is connected with the drain of the field effect tube M3 and one end of the resistance R12 in the ultra wide band amplification network respectively, the other end of the resistance R12 is connected with the ground resistance R13 and one end of the resistance R11 respectively, the other end of the resistance R11 is connected with the other end of the resistance R9 in the ultra wide band amplification network.

6. The high linearity ultra-wideband amplifier of claim 1, wherein, The feed matching network comprises a ground capacitor C11, a ground capacitor C10, a ground capacitor C12, a resistance R14, a resistance R15, an inductance L4 and an inductance L5; One end of the inductance L4 is connected with the drain of the field effect tube M3 in the ultra wide band amplification network, the other end of the inductance L4 is connected with one end of the inductance L5 and the resistance R14 respectively, the other end of the resistance R14 is connected with the ground capacitor C12, the other end of the inductance L5 is connected with the ground capacitor C10, one end of the resistance R15 and the power supply VDD respectively, the other end of the resistance R15 is connected with the ground capacitor C11.

7. The high linearity ultra-wideband amplifier of claim 1, wherein, The J class amplification output matching network comprises an inductance L6, an inductance L7, a ground inductance L8, a capacitor C6, a capacitor C7, a capacitor C8 and a ground capacitor C9; One end of the inductance L6 is connected with one end of the capacitor C6 as the input end of the J class amplification output matching network, the other end of the inductance L6 is connected with the other end of the capacitor C6, one end of the inductance L7 and one end of the capacitor C8 respectively, the other end of the capacitor C8 is connected with the ground inductance L8, the other end of the inductance L7 is connected with the ground capacitor C9 and one end of the capacitor C7 respectively, the other end of the capacitor C7 is connected as the output end of the J class amplification output matching network.

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