A Multi-Channel DAC Output Signal Synchronization Method and System

Abstract

The present invention discloses a method and system for synchronizing output signals of a multi-channel DAC, which relates to the field of digital-to-analog conversion. The method includes: converting the quadrature sine signals serving as the synchronization signal sources in two DAC channels to be synchronized into analog quadrature sine signals; performing a multiplication operation on the analog quadrature sine signals of the two DAC channels; filtering the signal output after the multiplication operation to detect the output DC voltage; controlling the phase delay of the two DAC channels until the output DC voltage reaches a preset value, so as to synchronize the phases of the two DAC channels. Without relying on the DAC chip to provide a synchronization function, the present invention can achieve phase-level synchronization of the DAC.

Description

Technical Field

[0001] The present invention relates to the field of digital-to-analog conversion, and particularly to a method and system for synchronizing output signals of a multi-channel DAC. Background Art

[0002] With the development of modern wireless communication technology and optical fiber communication technology, the communication rate has been increasing rapidly. Digital communication technology has replaced analog communication technology and become the mainstream technology today. In digital communication technology, digital coherent communication has the advantage of high sensitivity. In scenarios where sensitivity and data rate are pursued, as the core component at the transmitting end, the sampling rate of the DAC (Digital to Analog Converter) also increases continuously with the improvement of the communication rate.

[0003] In the digital coherent communication scenario, a relatively strict phase synchronization relationship is required between orthogonal analog signals. Therefore, it is necessary to synchronize the output signals of the DAC. For high-sampling-rate DACs, the differences in the characteristics of components in the signal conversion and transmission paths and the differences in the transmission line paths will seriously affect the phase relationship between signals. Therefore, a scheme for accurately synchronizing the output signals of the DAC in the case of high sampling rate has become an important part of the coherent communication scheme.

[0004] Currently, the existing DAC synchronization technologies rely on the inter-chip synchronization function reserved in the DAC chip at the initial design stage, and most can only achieve sample-level synchronization. In scenarios where phase-level synchronization is required, the synchronization accuracy is insufficient. Many high-sampling-rate DACs do not provide the inter-chip synchronization function by themselves. Moreover, the synchronization of high-sampling-rate DAC chips is easily affected by physical transmission path differences and component individual differences. It is not easy to achieve phase-level synchronization only by open-loop schemes such as equal-length transmission lines. Summary of the Invention

[0005] In view of the deficiencies existing in the prior art, a first aspect of the present invention provides a method for synchronizing output signals of a multi-channel DAC, which can achieve phase-level synchronization of the DAC without relying on the synchronization function provided by the DAC chip.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] A method for synchronizing output signals of a multi-channel DAC, the method comprising the following steps:

[0008] Convert the orthogonal sine signals serving as the synchronization signal sources in two DAC channels to be synchronized into analog orthogonal sine signals;

[0009] Perform a multiplication operation on the analog orthogonal sine signals of the two DAC channels;

[0010] Filter the signal output after the multiplication operation to detect the output DC voltage;

[0011] Control the phase delay of the two DAC channels until the output DC voltage reaches a preset value, so as to synchronize the phases of the two DAC channels.

[0012] In some embodiments, the controlling the phase delay of the two DAC channels until the output DC voltage reaches a preset value to synchronize the phases of the two DAC channels includes:

[0013] Taking one DAC channel as the reference channel and setting the phase delay value of the reference channel at a preset position;

[0014] Adjust the phase delay value of the other DAC channel in real time, and determine the phase delay value corresponding to the minimum DC voltage value among the recorded DC voltage values;

[0015] Control the phase delay value of the reference channel to remain at the preset position, and make the phase delay value of the other DAC channel remain at the phase delay value corresponding to the minimum DC voltage value, so as to synchronize the phases of the two DAC channels.

[0016] In some embodiments, the adjusting the phase delay value of the other DAC channel in real time and determining the phase delay value corresponding to the minimum DC voltage value among the recorded DC voltage values includes:

[0017] Scan the delay value of the other DAC channel within the delay adjustment range with the minimum adjustable step through an adjustable delay line;

[0018] Record the collected DC voltage and find the minimum DC voltage value;

[0019] Obtain the corresponding phase delay value according to the minimum DC voltage value.

[0020] In some embodiments, the phase delay value of the adjustable delay line of the reference channel is set at the median of the delay adjustment range.

[0021] In some embodiments, the filtering the signal output after the multiplication operation to detect the output DC voltage includes:

[0022] Use a low-pass filter to filter out the second-harmonic signal in the signal output after the multiplication operation;

[0023] Use an analog-to-digital converter ADC to collect the DC voltage output by the low-pass filter.

[0024] The second aspect of the present invention provides a multi-channel DAC output signal synchronization system, which can achieve phase-level synchronization of the DAC without relying on the DAC chip to provide a synchronization function.

[0025] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0026] A multi-channel DAC output signal synchronization system, comprising:

[0027] A digital logic circuit, which includes a quadrature sine wave generator and a synchronization algorithm module, and the quadrature sine wave generator is used to generate a quadrature sine signal as a synchronization signal source;

[0028] A digital-to-analog conversion unit, which includes a first digital-to-analog converter and a second digital-to-analog converter, and the first digital-to-analog converter and the second digital-to-analog converter are used to convert the quadrature sine signals in two DAC channels to be synchronized into analog quadrature sine signals;

[0029] An analog multiplier, which is used to perform a multiplication operation on the analog quadrature sine signals of the two DAC channels;

[0030] An acquisition unit, which is used to filter the signal output after the multiplication operation to detect the output DC voltage;

[0031] A delay adjustment unit, which is connected to the synchronization algorithm module, and the synchronization algorithm module controls the delay adjustment unit to control the phase delay of the two DAC channels until the output DC voltage reaches a preset value, so as to synchronize the phases of the two DAC channels.

[0032] In some embodiments, the delay adjustment unit includes a first adjustable delay line and a second adjustable delay line. Taking one DAC channel as a reference channel, the synchronization algorithm module controls the phase delay value of the reference channel to be maintained at a preset position through the first adjustable delay line, and makes the phase delay value of the other DAC channel be maintained at the phase delay value corresponding to the minimum DC voltage value through the second adjustable delay line, so as to synchronize the phases of the two DAC channels.

[0033] In some embodiments, the synchronization algorithm module controls the second adjustable delay line to scan the delay value of the other DAC channel within the delay adjustment range with the minimum adjustable step.

[0034] In some embodiments, the synchronization algorithm module controls the first adjustable delay line to keep the phase delay value of the reference channel at the median value of the delay adjustment range.

[0035] In some embodiments, the acquisition unit includes:

[0036] A low-pass filter, which is used to filter out the second harmonic signals in the signal output after the multiplication operation;

[0037] An analog-to-digital converter ADC, which is used to collect the DC voltage output by the low-pass filter.

[0038] Compared with the prior art, the advantages of the present invention are as follows:

[0039] In the multi-channel DAC output signal synchronization method of the present invention, an orthogonal sine signal is used as the synchronization signal source. Utilizing the cross-correlation statistical characteristics of the orthogonal sine wave, an analog multiplier is employed to perform a multiplication operation on the analog orthogonal sine signals between two channels. After the output signal of the multiplier passes through a low-pass filter, the double-frequency signal is filtered out. By detecting the DC voltage output by the low-pass filter, it is possible to determine whether the phases of the DAC signals are synchronized. Since a low-speed general-purpose ADC can be used for voltage acquisition and measurement, the system cost is saved. Moreover, the entire process does not rely on the DAC chip to provide a synchronization function. By adopting a closed-loop measurement and control measure, from the perspective of phase synchronization, the synchronization accuracy problem of the DAC output signal is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a flowchart of the multi-channel DAC output signal synchronization method in an embodiment of the present invention;

[0041] Figure 2 is Figure 1 a flowchart of step S4 in

[0042] Figure 3 is a structural block diagram of the multi-channel DAC output signal synchronization system in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0044] The flowchart shown in the drawings is only an example illustration, and does not necessarily include all the contents and operations / steps, nor does it necessarily need to be executed in the described order. For example, some operations / steps can be decomposed, combined, or partially merged. Therefore, the actual execution order may be changed according to the actual situation.

[0045] Referring to Figure 1 as shown, an embodiment of the present invention provides a multi-channel DAC output signal synchronization method, which includes the following steps:

[0046] S1. Convert the orthogonal sine signal serving as the synchronization signal source in two DAC channels to be synchronized into an analog orthogonal sine signal.

[0047] In this embodiment, the quadrature sine signal serving as the synchronization signal source can be generated by a quadrature sine wave generator, and then it can be converted into an analog quadrature sine signal by using a DAC.

[0048] S2. Perform a multiplication operation on the analog quadrature sine signals of the two DAC channels.

[0049] In this embodiment, a multiplier can be used to perform a multiplication operation on the analog quadrature sine signals of the two DAC channels.

[0050] S3. Filter the signal output after the multiplication operation to detect the output DC voltage.

[0051] Specifically, step S3 includes:

[0052] S31. Use a low-pass filter to filter out the second harmonic signals in the signal output after the multiplication operation;

[0053] S32. Use an analog-to-digital converter ADC to collect the DC voltage output by the low-pass filter.

[0054] S4. Control the phase delays of the two DAC channels until the output DC voltage reaches a preset value, so as to synchronize the phases of the two DAC channels.

[0055] Specifically, referring to Figure 2 as shown, step S4 includes:

[0056] S41. Take one DAC channel as the reference channel and set the phase delay value of the reference channel at a preset position.

[0057] Any one of the two DAC channels can be selected as the reference channel. It can be understood that the phase delay value of the reference channel remains at the preset position, and then the phase synchronization is achieved by adjusting the other DAC channel. The position where the phase delay value of the reference channel is set can be reasonably set according to needs. For example, it can be set at the median value of the delay adjustment range.

[0058] S42. Adjust the phase delay value of the other DAC channel in real time, and determine the phase delay value corresponding to the minimum DC voltage value among the recorded DC voltage values.

[0059] Specifically, step S42 includes:

[0060] Scan the delay value of the other DAC channel within the delay adjustment range with the minimum adjustable step through an adjustable delay line; record the collected DC voltage, and find out the minimum DC voltage value; obtain the corresponding phase delay value according to the minimum DC voltage value.

[0061] S43. Control the phase delay value of the reference channel to be maintained at a preset position, and make the phase delay value of another DAC channel be maintained at the phase delay value corresponding to the minimum DC voltage value, so as to synchronize the phases of the two DAC channels.

[0062] The following takes a specific example for further illustration:

[0063] Select a channel as the reference channel, and set the delay value a1 of its adjustable delay line to the median value a1 = A of the delay adjustment range A min to A max of norm .

[0064] With the minimum adjustable step A step in the range of A min to A max , scan the delay value a2 of another channel, and record the DC voltage V(a) collected by the ADC. Find the minimum value V min (a) in the recorded voltage values. Then the delay value a corresponding to V min (a) is the optimal delay value a opt = arg min(V(a)).

[0065] Control the adjustable delay line of the reference channel to be maintained at the median value A norm , control the adjustable delay line of another channel to be maintained at the optimal delay value a opt , and the synchronization algorithm ends.

[0066] In summary, for the multi-channel DAC output signal synchronization method in the present invention, an orthogonal sine signal is used as the synchronization signal source, the cross-correlation statistical characteristics of the orthogonal sine wave are utilized, an analog multiplier is used to perform a multiplication operation on the analog orthogonal sine signals between two channels, and after the output signal of the multiplier passes through a low-pass filter, the double-frequency signal is filtered out. By detecting the DC voltage output by the low-pass filter, it is possible to judge whether the phases of the DAC signals are synchronized. Since a low-speed general ADC can be used for voltage acquisition and measurement, the system cost is saved, and the entire process does not rely on the DAC chip to provide a synchronization function. By adopting a closed-loop measurement and control measure, from the perspective of phase synchronization, the synchronization accuracy problem of the DAC output signal is solved.

[0067] At the same time, as shown in Figure 3 , the embodiment of the present invention further provides a multi-channel DAC output signal synchronization system, which includes a digital logic circuit, a digital-to-analog conversion unit, an analog multiplier, an acquisition unit, and a delay adjustment unit.

[0068] The digital logic circuit includes an orthogonal sine wave generator and a synchronization algorithm module, and the orthogonal sine wave generator is used to generate an orthogonal sine signal as the synchronization signal source.

[0069] The digital-to-analog conversion unit includes a first digital-to-analog converter and a second digital-to-analog converter, and the first digital-to-analog converter and the second digital-to-analog converter are used to convert the quadrature sine signals in two DAC channels to be synchronized into analog quadrature sine signals.

[0070] The analog multiplier is used to perform a multiplication operation on the analog quadrature sine signals of the two DAC channels.

[0071] The acquisition unit is used to filter the signal output after the multiplication operation to detect the output DC voltage.

[0072] The delay adjustment unit is connected to the synchronization algorithm module, and the synchronization algorithm module controls the two DAC channels to be synchronized by adjusting the delay adjustment unit until the output DC voltage reaches a preset value.

[0073] Further, the delay adjustment unit includes a first adjustable delay line and a second adjustable delay line. Taking one DAC channel as a reference channel, the synchronization algorithm module controls the phase delay value of the reference channel to be maintained at a preset position through the first adjustable delay line, and makes the phase delay value of the other DAC channel be maintained at the phase delay value corresponding to the minimum DC voltage value through the second adjustable delay line, so as to synchronize the phases of the two DAC channels.

[0074] Further, the synchronization algorithm module controls the second adjustable delay line to scan the delay value of the other DAC channel within the delay adjustment range with the minimum adjustable step.

[0075] Further, the synchronization algorithm module controls the first adjustable delay line to keep the phase delay value of the reference channel at the median value of the delay adjustment range.

[0076] Further, the acquisition unit includes:

[0077] A low-pass filter, which is used to filter out the second-harmonic signals in the signal output after the multiplication operation;

[0078] An analog-to-digital converter ADC, which is used to collect the DC voltage output by the low-pass filter.

[0079] The following Figure 3 further illustrates the principle of the multi-channel DAC output signal synchronization system in the embodiments of the present invention:

[0080] The digital logic circuit includes a synchronization algorithm module, a quadrature sine wave generator, and a data selection switch.

[0081] The data selection switches (1, 2) and signal switches (1, 2) are controlled by the synchronization algorithm module and are used to switch the user signals during normal operation and the quadrature sine wave signals during the synchronization operation. The adjustable delay lines (1, 2) are controlled by the synchronization algorithm module and are used to perform phase delay operations. During the synchronization process, the digital quadrature sine wave signals generated by the quadrature sine wave generator are sent to the digital-to-analog converter DAC to be converted into analog signals for output. The output signals of the digital-to-analog converter DAC are sent to the adjustable delay lines. After phase delay, they are switched to the analog multiplier by the signal switch. The output signals of the multiplier are sent to the low-pass filter. The DC signals output by the low-pass filter are sampled by the analog-to-digital converter ADC and then fed back to the synchronization algorithm module for synchronization effect detection.

[0082] During the synchronization process, one channel is used as the reference channel, and the adjustable delay line is used to adjust the delay of the other channel. When the analog-to-digital converter ADC samples the DC voltage value to reach the minimum, the two channels reach phase synchronization.

[0083] In summary, for the multi-channel DAC output signal synchronization method in the present invention, the orthogonal sine signal is used as the synchronization signal source. Utilizing the cross-correlation statistical characteristics of the orthogonal sine wave, the analog multiplier is used to perform multiplication operations on the analog orthogonal sine signals between two channels. After the output signals of the multiplier pass through the low-pass filter, the double-frequency signals are filtered out. By detecting the DC voltage output by the low-pass filter, it is possible to judge whether the phases of the DAC signals are synchronized. Since a low-speed general-purpose ADC can be used for voltage acquisition and measurement, the system cost is saved. Moreover, the entire process does not rely on the DAC chip to provide a synchronization function. Adopting closed-loop measurement and control measures, from the perspective of phase synchronization, the synchronization accuracy problem of the DAC output signals is solved.

[0084] It should be noted that in this article, the terms "including", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or system. Without further limitations, the element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or system including that element.

[0085] The serial numbers of the above embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments. The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for synchronizing multi-channel DAC output signals, characterized in that, The method includes the following steps: Convert the quadrature sine signal serving as the synchronization signal source in the two DAC channels to be synchronized into an analog quadrature sine signal; Perform a multiplication operation on the analog quadrature sine signals of the two DAC channels; Filter the signal output after the multiplication operation to detect the output DC voltage; Control the phase delay of the two DAC channels until the output DC voltage reaches a preset value to synchronize the phases of the two DAC channels; Among them, the controlling the phase delay of the two DAC channels until the output DC voltage reaches a preset value to synchronize the phases of the two DAC channels includes: Taking one DAC channel as the reference channel and setting the phase delay value of the reference channel at a preset position; Adjust the phase delay value of the other DAC channel in real time and determine the phase delay value corresponding to the minimum DC voltage value among the recorded DC voltage values; Control the phase delay value of the reference channel to remain at the preset position and make the other DAC channel's phase delay value remain at the phase delay value corresponding to the minimum DC voltage value to synchronize the phases of the two DAC channels; The adjusting the phase delay value of the other DAC channel in real time and determining the phase delay value corresponding to the minimum DC voltage value among the recorded DC voltage values includes: Scanning the delay value of the other DAC channel within the delay adjustment range with the minimum adjustable step through an adjustable delay line; Record the collected DC voltage and find the minimum DC voltage value; Obtain the corresponding phase delay value according to the minimum DC voltage value; The filtering the signal output after the multiplication operation to detect the output DC voltage includes: Using a low-pass filter to filter out the second harmonic signals in the signal output after the multiplication operation; Collecting the DC voltage output by the low-pass filter using an analog-to-digital converter ADC.

2. The multi-channel DAC output signal synchronization method according to claim 1, wherein The phase delay value of the adjustable delay line of the reference channel is set at the median of the delay adjustment range.

3. A multi-channel DAC output signal synchronization system, characterized in that, Includes: A digital logic circuit, which includes a quadrature sine wave generator and a synchronization algorithm module, and the quadrature sine wave generator is used to generate a quadrature sine signal serving as the synchronization signal source; A digital-to-analog conversion unit, which includes a first digital-to-analog converter and a second digital-to-analog converter, and the first digital-to-analog converter and the second digital-to-analog converter are used to convert the quadrature sine signals in the two DAC channels to be synchronized into analog quadrature sine signals; An analog multiplier, which is used to perform a multiplication operation on the analog quadrature sine signals of the two DAC channels; An acquisition unit, which is used to filter the signal output after the multiplication operation to detect the output DC voltage; A delay adjustment unit, which is connected to the synchronization algorithm module, and the synchronization algorithm module controls the phase delay of the two DAC channels by adjusting the delay adjustment unit until the output DC voltage reaches a preset value to synchronize the phases of the two DAC channels; And the delay adjustment unit includes a first adjustable delay line and a second adjustable delay line. Taking one DAC channel as a reference channel, the synchronization algorithm module controls the phase delay value of the reference channel to be maintained at a preset position through the first adjustable delay line, and makes the phase delay value of another DAC channel be maintained at the phase delay value corresponding to the minimum DC voltage value through the second adjustable delay line, so as to synchronize the phases of the two DAC channels; Wherein, the synchronization algorithm module controls the second adjustable delay line to scan the delay value of another DAC channel within the delay adjustment range with the minimum adjustable step.

4. The multi-channel DAC output signal synchronization system according to claim 3, characterized in that, The synchronization algorithm module controls the first adjustable delay line to control the phase delay value of the reference channel to be maintained at the median value of the delay adjustment range.

5. The multi-channel DAC output signal synchronization system according to claim 4, characterized in that, The acquisition unit includes: A low-pass filter, which is used to filter out the second harmonic signals in the signal output after the multiplication operation; An analog-to-digital converter ADC, which is used to acquire the DC voltage output by the low-pass filter.

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