In-module serial communication interface for RF devices

Abstract

Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication device has a first interface circuit configured to couple the data communication device to a primary serial bus, a second interface circuit configured to couple the data communication device to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a command sequence to be transmitted through the second interface circuit. The command sequence can be configured or selected to access a register in at least one device coupled to one of the secondary serial buses.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application serial number 17 / 003,724 filed in the United States Patent and Trademark Office on August 26, 2020, and provisional patent application serial number 62 / 899,223 filed in the United States Patent and Trademark Office on September 12, 2019, the contents of which are incorporated herein as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to serial communications over a shared serial bus, and more particularly to a high-speed, low-latency serial bus that can support radio frequency device operations. Background Art

[0004] A mobile communication device may include various components, including circuit boards, integrated circuit (IC) devices, and / or system-on-chip (SoC) devices. The components may include processing circuits, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus may operate according to standardized or proprietary protocols. In one example, the serial bus operates according to an inter-integrated circuit (I2C bus or I 2 C). The I2C bus was developed to connect low-speed peripheral devices to processors, where the I2C bus is configured as a multi-drop bus. The two-wire I2C bus includes a serial data line (SDA) that carries a data signal and a serial clock line (SCL) that carries a clock signal.

[0005] The serial bus can adopt a multi-host protocol, in which one or more devices can be used as the host and slave of different messages transmitted on the serial bus. In one example, the improved inter-integrated circuit (I3C) protocol can be used to control operations on the serial bus. The I3C protocol is defined by the Mobile Industry Processor Interface (MIPI) Alliance, and certain implementation aspects are derived from the I2C protocol. In another example, the radio frequency front end (RFFE) interface defined by the alliance provides a communication interface for controlling various radio frequency (RF) front-end devices, including power amplifiers (PA), low noise amplifiers (LNA), antenna tuners, filters, sensors, power management devices, switches, etc. These devices can be co-located in a single IC device or set in multiple IC devices. In a mobile communication device, multiple antennas and radio transceivers can support multiple concurrent RF links. In another example, the system power management interface (SPMI) defined by the MIPI Alliance provides a hardware interface that can be implemented between a baseband or application processor and peripheral components. In some implementations, the system uses SPMI to support power management operations within the device.

[0006] In many cases, a multi-point serial bus can be provided to support a combination of high priority low latency communications and low priority communications. When multiple devices coupled to the serial bus are active at the same time and attempt to obtain bus access for transmission initiation, latency may be adversely affected. Degraded latency may result in failure to meet certain application performance constraints. As mobile communication devices continue to include higher levels of functionality, improved serial communication technology is needed to accommodate high priority low latency functionality. Summary of the invention

[0007] Certain aspects of the present disclosure relate to systems, apparatus, methods, and techniques that can alleviate congestion on a multi-purpose multi-drop serial bus. A slave device can be equipped with sequencer logic that can be configured to extend short commands received from a conventional multi-drop serial bus by automatically generating a command sequence that accesses multiple registers in one or more downstream devices and / or initiates actions in the downstream devices.

[0008] In various aspects of the present disclosure, a data communication method performed at a slave device coupled to a serial bus includes: communicating with a bus master through a first interface circuit, the first interface circuit being configured to couple the slave device to a primary serial bus, communicating with one or more downstream devices through a second interface circuit, the second interface circuit being configured to couple the slave device to a plurality of secondary serial buses, and responding to a first command received from the primary serial bus by initiating execution of a preconfiguration sequence, the preconfiguration sequence causing a command sequence to be transmitted through the second interface circuit. The command sequence may be configured to access a register in at least one downstream device.

[0009] In one aspect, the command sequence includes a first command addressed to a register in a first downstream device and a second command addressed to a register in a second downstream device, the first downstream device being coupled to a first auxiliary serial bus, the second downstream device being coupled to a second auxiliary serial bus. In some cases, the command sequence includes a register write command, a register mask write command, or a register read command. In some cases, the command sequence includes a trigger mask write command or a trigger command.

[0010] In one aspect, a first serial bus protocol is used to transmit data at a first data rate over a primary serial bus, and a second serial bus protocol can be used to transmit data at a second data rate greater than the first data rate over a plurality of secondary serial buses. In one example, the primary serial bus operates according to the RFFE protocol.

[0011] In some aspects, the method includes: receiving a second command from a primary serial bus, and initiating transmission of a third command over one of a plurality of secondary serial buses in response to the second command. Transmission of the third command may begin while the second command is received. The method may include: determining a type of the second command based on a command code transmitted in the second command, and starting transmission of the third command after determining the type of the second command and before address information of the second command has been completely received.

[0012] In certain aspects, the method includes managing communications over a plurality of secondary serial buses and selecting a preconfigured sequence from one or more preconfigured sequences using content of a first command before the first command is fully received. Each of the plurality of secondary serial buses may be configured as a point-to-point serial link.

[0013] In various aspects of the present disclosure, a data communication device has: a first interface circuit configured to couple the data communication device to a primary serial bus, a second interface circuit configured to couple the data communication device to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence, the preconfigured sequence causing a command sequence to be transmitted through the second interface circuit. The command sequence can be configured or selected to access a register in at least one device coupled to one of the secondary serial buses. The data communication device can be configured to operate as a slave device.

[0014] In various aspects of the present disclosure, a data communication device has: a module configured to couple the data communication device to a main serial bus for communicating with a bus host through a first interface circuit, a module configured to couple the data communication device to multiple auxiliary serial buses for communicating with one or more downstream devices through a second interface circuit, and a module for executing a preconfiguration sequence, the preconfiguration sequence causing a command sequence to be transmitted through the second interface circuit. The preconfiguration sequence can be executed in response to a first command received from the main serial bus. The command sequence can be configured to access registers in one or more downstream devices. The data communication device can be configured to operate as a slave device.

[0015] In various aspects of the present disclosure, a processor-readable storage medium stores or maintains code for: communicating with a bus master via a first interface circuit configured to couple a slave device to a primary serial bus, communicating with one or more downstream devices via a second interface circuit configured to couple the slave device to a plurality of secondary serial buses, and responding to a first command received from the primary serial bus by initiating execution of a preconfiguration sequence that causes a command sequence to be transmitted via the second interface circuit. The command sequence may be configured to access a register in at least one downstream device.

[0016] In some examples, the command sequence includes a first command addressed to a register in a first downstream device and a second command addressed to a register in a second downstream device, the first downstream device being coupled to a first auxiliary serial bus, and the second downstream device being coupled to a second auxiliary serial bus. The command sequence may include a register write command, a register mask write command, or a register read command. The command sequence may include a trigger mask write command or a trigger command.

[0017] In some examples, a first serial bus protocol is used to transmit data at a first data rate over a primary serial bus, and a second serial bus protocol can be used to transmit data at a second data rate greater than the first data rate over a plurality of secondary serial buses. In some cases, the primary serial bus operates according to the RFFE protocol.

[0018] In some examples, the slave device may receive the second command from the main serial bus and may initiate transmission of a third command over one of the plurality of auxiliary serial buses in response to the second command. Transmission of the third command may begin while the second command is received. In some examples, the slave device may determine the type of the second command based on the command code transmitted in the second command, and may begin transmission of the third command after determining the type of the second command and before the address information of the second command has been completely received.

[0019] In some examples, the slave device can manage communications over multiple auxiliary serial buses. The slave device can select a preconfigured sequence from one or more preconfigured sequences using the content of the first command before the first command has been fully received. Each of the multiple auxiliary serial buses can be configured as a point-to-point serial link. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 An apparatus is shown that employs data links between IC devices and selectively operates according to standard or proprietary protocols.

[0021] Figure 2 A system architecture of an apparatus employing data links between IC devices is shown.

[0022] Figure 3 Included are timing diagrams showing signaling on the serial bus when the serial bus is operating in a single data rate (SDR) mode of operation defined by the I3C specification.

[0023] Figure 4 A system including a data communications link configured to operate according to the SPMI protocol is shown.

[0024] Figure 5 A device configuration for coupling various RF front-end devices using multiple RFFE buses is shown.

[0025] Figure 6 The datagram structure defined by the RFFE and / or SPMI protocols is shown.

[0026] Figure 7 A system employing a serial bus protocol adapted according to certain aspects disclosed herein is shown.

[0027] Figure 8 An example of a command structure for a serial bus protocol adapted according to certain aspects disclosed herein is shown.

[0028] Fig. 9 Actuation of a trigger according to certain aspects disclosed herein is shown.

[0029] Fig.10 Trigger-related commands defined by a serial bus protocol adapted according to certain aspects disclosed herein are shown.

[0030] Fig.11 Power mode commands defined by a serial bus protocol adapted according to certain aspects disclosed herein are shown.

[0031] Fig.12 Shown are read / write commands defined by a serial bus protocol adapted according to certain aspects disclosed herein.

[0032] Fig.13 An example of a pass-through transaction using a serial bus protocol adapted according to certain aspects disclosed herein is shown.

[0033] Fig.14 One example of an apparatus employing processing circuitry that may be adapted according to certain aspects disclosed herein is shown.

[0034] Fig.15 is a flow chart illustrating a method that may be performed by a slave device coupled to a serial bus in accordance with certain aspects disclosed herein.

[0035] Fig.16A first example of a hardware implementation for an apparatus adapted according to certain aspects disclosed herein is shown. DETAILED DESCRIPTION

[0036] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. The detailed description includes specific details for providing a thorough understanding of the various concepts. However, it is clear to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid confusing such concepts.

[0037] Several aspects of the present invention will now be presented with reference to various devices and methods. These devices and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system.

[0038] Overview

[0039] Devices including multiple SoCs and other IC devices typically employ a shared communication interface that may include a serial bus or other data communication link for connecting a processor to a modem and other peripherals. The serial bus or other data communication link may operate according to a plurality of defined standards or protocols. For example, the serial bus may operate according to I2C, I3C, SPMI, and / or RFFE protocols or other protocols. The serial bus may be configured for half-duplex operation. Increased utilization of the serial bus and / or tighter timing constraints imposed to support applications, peripherals, and sensors may result in a need to reduce transmission latency. Transmission latency may include the time required to terminate ongoing transactions on the serial bus, bus turnaround (between transmit mode and receive mode), bus arbitration, or command transmission specified by the protocol.

[0040] High bus latency can limit the capabilities and functionality of serial buses in certain applications. In one example, bus latency considerations may limit the number of sensors that can be coupled via an I3C, RFFE, or SPMI bus. For example, certain applications specify a maximum latency for reading sensor information after an event and / or in response to an interrupt, and may specify a time limit for reading multiple sensors. In another example, bus latency considerations may limit the number of RF devices that can be coupled via an I3C, RFFE, or SPMI bus. Certain operations in RF ICs require very low latency communications. For example, the configuration and reconfiguration of circuits for driving multiple antennas may generate a large number of messages, commands, and signaling for multiple RF components. In many cases, the message may include configuration parameters that will be applied at a time determined by the controlling device. The communication overhead associated with certain protocols for controlling serial buses may also result in congestion and increased latency.

[0041] Advances in RF technology and the introduction of increased capabilities in communications devices have increased pressure on latency. For example, the deployment of radio access technologies such as 5G New Radio defined by the Third Generation Partnership Project (3GPP) and the 802.11ax WLAN standard defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.11 working group may require a 50% reduction in latency at conventional bus clock frequencies, increasing the complexity of the RFFE bus architecture and increasing the likelihood of traffic congestion on the bus. For example, RFFE bus congestion and timing bottlenecks may exacerbate coexistence issues. Increased bus activity may increase bus contention issues with complex RFFE bus timing. Bus contention events may increase when carrier aggregation is supported.

[0042] The serial communication interface realized according to some aspects disclosed herein can be suitable for supporting command extension.The device configured to operate as an expander receives short commands from the main serial bus, and responds by transmitting one or more commands on the point-to-point auxiliary serial interface.In one example, the main serial bus operates according to a protocol defined in a general or standard.The short commands received from the main serial bus can cause the controller or sequencer in the expander to execute a sequence, which causes multiple commands to be transmitted to downstream devices through the point-to-point auxiliary serial interface.The expander can use a pre-configured sequence to enable the system to perform complex operations without considering the congestion of the main serial bus.The auxiliary serial interface can operate using a protocol optimized for time delay and simplicity.For example, the auxiliary serial interface can operate using a simplified datagram structure, minimized protocol overhead, and / or can provide a dedicated communication link for some downstream devices.

[0043] In one example, a radio frequency serial bus (RFSB) interface can be used to provide low latency communications to multiple RF devices. The increased complexity of the RFFE bus architecture configured to support newer radio access technologies, including fourth generation (4G) and fifth generation (5G) wireless communication technologies, may increase the likelihood of traffic congestion on the RFFE bus. The expander may be coupled to the host using the I2C protocol, the I3C protocol, the SPMI protocol, and / or the RFFE protocol, or other suitable protocols. The expander may be operable to relay data between the master and slave devices, thereby enabling a high degree of synchronization between certain slave devices. Multiple RFSB interfaces may be implemented to enable RFFE devices or other low latency devices to communicate within strict time constraints, including where bus throughput, utilization, and / or other operating characteristics are affected by demands from low latency slave devices.

[0044] According to certain aspects of the present disclosure, a data communication device adapted to implement an RFSB protocol has: a first interface circuit configured to couple the data communication device to a primary serial bus, a second interface circuit configured to couple the data communication device to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence, the preconfigured sequence causing a command sequence to be transmitted through the second interface circuit. The command sequence may be configured or selected to access a register in at least one device coupled to one of the secondary serial buses.

[0045] Example of a device using a serial data link

[0046] According to certain aspects, the serial data link can be used to interconnect electronic devices that are subcomponents of the device, such as a cellular phone, a smart phone, a Session Initiation Protocol (SIP) phone, a laptop, a notebook computer, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a Global Positioning System (GPS) device, a smart home device, smart lighting, a multimedia device, a video device, a digital audio player (e.g., an MP3 player), a camera, a game console, an entertainment device, a vehicle component, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), an appliance, a sensor, a security device, a vending machine, a smart meter, a drone, a multi-rotor aircraft, or any other similarly functional device.

[0047] Figure 1An example of an apparatus 100 employing a data communication bus is shown. The apparatus 100 may include a SoC, or processing circuitry 102 having a plurality of circuits or devices 104, 106, and / or 108, which may be implemented in one or more ASICs. In one example, the apparatus 100 may operate as a communication device, and the processing circuitry 102 may include a processing device disposed in an ASIC 104, one or more peripheral devices 106, and a transceiver 108 that enables the apparatus to communicate with a radio access network, a core access network, the Internet, and / or other networks via an antenna 124.

[0048] The ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuits or functions. The processing circuit 102 may be controlled by an operating system, which may provide an application programming interface (API) layer that enables one or more processors 112 to execute software modules residing in the onboard memory 114 or other processor-readable storage devices 122 disposed on the processing circuit 102. The software modules may include instructions and data stored in the onboard memory 114 or the processor-readable storage device 122. The ASIC 104 may access its onboard memory 114, the processor-readable storage device 122, and / or a storage device external to the processing circuit 102. The onboard memory 114, the processor-readable storage device 122 may include a read-only memory (ROM) or a random access memory (RAM), an electrically erasable programmable ROM (EEPROM), a flash card, or any memory device that may be used in a processing system and a computing platform. The processing circuit 102 may include, implement, or have access to a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating the device 100 and / or the processing circuit 102. The local database can be implemented using registers, database modules, flash memory, magnetic media, EEPROM, soft or hard disks, etc. The processing circuit 102 can also be operably coupled to external devices such as an antenna 124, a display 126, operator controls (such as switches or buttons 128, 130 or an external keypad 132), and other components. The user interface module can be configured to operate with the display 126, the external keypad 132, etc. through a dedicated communication link or through one or more serial data interconnects.

[0049] The processing circuit 102 may provide one or more buses 118a, 118b, 120 that enable certain devices 104, 106, and / or 108 to communicate. In one example, the ASIC 104 may include a bus interface circuit 116 that includes a combination of circuits, counters, timers, control logic, and other configurable circuits or modules. In one example, the bus interface circuit 116 may be configured to operate according to a communication specification or protocol defined by a standard. The processing circuit 102 may include or control a power management function that configures and manages the operation of the apparatus 100.

[0050] Figure 2 The system includes a plurality of devices 202 and 2220-222 coupled to a serial bus 220. N Certain aspects of the apparatus 200. Devices 202 and 2220-222 N The devices 202 and 2220-222 may be implemented using one or more semiconductor IC devices, such as an application processor, a SoC, or an ASIC. N The device 2220-222 may include, support, or function as a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, and / or other such components or devices. N One or more of the devices 202 and 2220-222 on the serial bus 220 may be used to control, manage, or monitor the sensor device. N The communication between the two buses is controlled by the bus master 202. Some types of buses can support multiple bus masters 202.

[0051] In one example, the master device 202 may include an interface controller 204 that manages access to the serial bus, configures the slave devices 2220-222 NThe host device 202 may include a configuration register 206 or other storage device 224, and other control logic 212 configured to handle protocols and / or higher-level functions. The control logic 212 may include processing circuits with processing devices such as state machines, sequencers, signal processors, or general-purpose processors. The host 202 includes a transceiver 210 and line drivers / receivers 214a and 214b. The transceiver 210 may include a receiver, a transmitter, and a common circuit, wherein the common circuit may include timing, logic, and storage circuits and / or devices. In one example, the transmitter encodes and transmits data based on the timing in the clock signal 228 provided by the clock generation circuit 208. Other timing clock signals 226 may be used by the control logic 212 and other functions, circuits, or modules.

[0052] At least one device 2220-222 N It can be configured to operate as a slave device on the serial bus 220, and can include circuits and modules supporting displays, image sensors, and / or one or more sensors that control and measure environmental conditions and circuits and modules that communicate with the sensors. In one example, a slave device 2220 configured to operate as a slave device can provide a control function, module or circuit 232, which includes circuits and modules supporting displays, image sensors, and / or one or more sensors that control and measure environmental conditions and circuits and modules that communicate with the sensors. From the device 2220, it can include configuration registers 234 or other storage devices 236, control logic 242, transceiver 240 and line driver / receiver 244a and 244b. Control logic 242 can include processing circuits with processing devices such as state machines, sequencers, signal processors or general processors. Transceiver 240 can include a receiver, a transmitter and a common circuit, wherein the common circuit can include timing, logic and storage circuits and / or devices. In one example, the transmitter encodes and transmits data based on timing in a clock signal 248 provided by a clock generation and / or recovery circuit 246. The clock signal 248 may be derived from a signal received from a clock line 218. Other timing clock signals 238 may be used by the control logic 242 and other functions, circuits, or modules.

[0053] The serial bus 220 may operate according to RFFE, I2C, I3C, SPMI, or other protocols. In some cases, two or more devices 202, 2220-222 N Can be configured to operate as a bus master on the serial bus 220 .

[0054] In some implementations, the serial bus 220 can be operated according to the I3C protocol. Devices that communicate using the I3C protocol can coexist on the same serial bus 220 with devices that communicate using the I2C protocol. The I3C protocol can support different communication modes, including a single data rate (SDR) mode that is compatible with the I2C protocol. The high data rate (HDR) mode can provide a data transfer rate between 6 megabits per second (Mbps) and 16Mbps, and some HDR modes can provide higher data transfer rates. The I2C protocol can comply with the de facto I2C standard to provide a data rate that can be in the range of 100 kilobits per second (kbps) to 3.2Mbps. In addition to data formats and bus control aspects, the I2C and I3C protocols can define electrical and timing aspects for signals transmitted on the 2-wire serial bus 220. In some aspects, the I2C and I3C protocols can define direct current (DC) characteristics that affect certain signal levels associated with the serial bus 220, and / or alternating current (AC) characteristics that affect certain timing aspects of signals transmitted on the serial bus 220. In some examples, data is transmitted on data line 216 of serial bus 220 based on timing information provided in a clock signal transmitted on clock line 218 of serial bus 220. In some cases, data may be encoded in the signaling states, or in the transitions of the signaling states of both data line 216 and clock line 218.

[0055] Figure 3 A timing diagram 300 is included, which shows the signaling on the serial bus when the serial bus is operated in a single data rate (SDR) operating mode defined by the I3C specification. Data transmitted on the first line (data line 302) of the serial bus can be captured using a clock signal transmitted on the second line (clock line 304) of the serial bus. During data transmission, when the clock line 304 is at a high voltage level, the signaling state 312 of the data line 302 is expected to remain constant for the duration of the pulse 314. The transition on the data line 302 when the clock line 304 is at a high voltage level indicates a start condition 306, a stop condition 308, or a repeated start 310.

[0056] On the I3C serial bus, a start condition 306 is defined to allow the current bus master to signal the data to be transmitted. The start condition 306 occurs when the data line 302 changes from high to low and the clock line 304 is high. The bus master can use a stop condition 308 to signal the completion and / or termination of the transmission. When the clock line 304 is high, the data line 302 indicates the stop condition 308 when it changes from low to high. Repeat start 310 can be transmitted by a bus master that wishes to initiate a second transmission when the first transmission is completed. Repeat start 310 is transmitted instead and has the meaning of stop condition 308 followed by start condition 306. Repeat start 310 occurs when the data line 302 changes from high to low while the clock line 304 is high.

[0057] The bus master may transmit an initiator 322 such as a start condition 306 or a repeated start 310 prior to transmitting a broadcast address or a unique address, commands, and / or data of a slave device. Figure 3 A command code transmission 320 by a bus master is shown. An initiator 322 may be followed in the transmission by a reserved address 324 indicating that a command code 326 will follow. For example, the command code 326 may cause the serial bus to transition to a desired operating mode. In some cases, data 328 may be transmitted. The command code transmission 320 may be terminated by a terminator 330 such as a stop condition 308 or a repeated start 310.

[0058] Some serial bus interfaces support signaling schemes that provide higher data rates. In one example, the I3C specification defines multiple high data rate (HDR) modes, including a high data rate, double data rate (HDR-DDR) mode in which data is transmitted on both the rising and falling edges of the clock signal.

[0059] The MIPI Alliance SPMI protocols and standards specify hardware interfaces that can be implemented between a baseband or application processor and peripheral components to support various data communication functions, including those related to power management operations. Figure 4An example of a system 400 including two data communication links 410, 412 is shown, wherein each data communication link 410, 412 is configured as a two-wire serial bus operating according to the SPMI protocol. In one example, the first data communication link 410 can be used to connect the integrated power controller of the application processor 402 with the voltage regulation system in the first power management integrated circuit (PMIC 406), and the second data communication link 412 can be used to connect the integrated power controller of the modem 4041 with the voltage regulation system in the second PMIC 408. The data communication links 410, 412 can be used to accurately monitor and control the processor performance level required for a given workload or application, and dynamically control various power supply voltages in real time based on the performance level. The data communication links 410, 412 can be used to carry other types of data between the application processor 402 and the first PMIC 406 and / or between the modem 4041 and the second PMIC 408. The SPMI data communication link can be implemented as a multi-point serial link that is used to connect various different devices and to carry other types of data. Some SPMI data communication links can be optimized for real-time power management functions. Some SPMI data communication links can be used as a shared bus that provides a high-speed, low-latency connection for devices, where data transmission can be managed according to priorities assigned to different traffic classes.

[0060] exist Figure 4 In the system 400 shown, the application processor 402 can be used as a plurality of data communication links 410, 412, 422, 424, a plurality of peripheral devices 4041-404 N and a host device on one or more PMICs 406. The application processor 402 and the modem 4041 can be coupled to the respective PMICs 406, 408 using a power management interface implemented using an SPMI master 414, 418. The SPMI masters 414, 418 communicate with corresponding SPMI slaves 416, 420 disposed in the PMICs 406, 408 to facilitate real-time control of the PMICs 406, 408. The application processor 402 can be coupled to the peripheral devices 4041-404 using different types of data communication links 422, 424. N For example, the data communication links 422, 424 may operate according to protocols such as RFFE, SPMI, I3C protocols, and the like.

[0061] Figure 5Certain aspects of an apparatus 500 are shown, the apparatus 500 including a plurality of RFFE buses 530, 532, 534 coupled to various RF front-end devices 518, 520, 522, 524, 526, 528. A modem 502 includes an RFFE interface 508 coupling the modem 502 to a first RFFE bus 530. The modem 502 may communicate with a baseband processor 506 and a radio frequency IC (RFIC 512) via one or more communication links 510, 536. The illustrated apparatus 500 may be embodied in one or more of a mobile communication device, a mobile phone, a mobile computing system, a mobile phone, a laptop computer, a tablet computing device, a drone, an appliance, a sensor, a media player, a gaming device, a wearable computing and / or communication device, an appliance, and the like.

[0062] In various examples, the device 500 may be implemented with one or more baseband processors 506, modems 504, RFIC 512, multiple communication links 510, 536, multiple RFFE buses 530, 532, 534, and / or other types of buses. The device 500 may include other processors, circuits, modules, and may be configured for various operations and / or different functions. Figure 5 In the example shown, the modem 504 is coupled to the RF tuner 518 via its RFFE interface 508 and a first RFFE bus 530. The RFIC 512 may include one or more RFFE interfaces 514, 516, controllers, state machines, and / or processors that may configure and control certain aspects of the RF front end. The RFIC 512 may communicate with the PA 520 and the power tracking module 522 via a first RFFE interface in its RFFE interface 514 and a second RFFE bus 530. The RFIC 512 may communicate with a switch 524 and one or more LNAs 526, 528.

[0063] Bus latency can affect the ability of the serial bus to handle high priority, real-time and / or other time-constrained messages. Low latency messages, or messages requiring low bus latency, can be related to sensor states, real-time events generated by devices, and virtualized general purpose input / output (GPIO). In one example, bus latency can be measured as the time it takes for a message to become available for transmission and the delivery of a message or, in some cases, the transmission of a message to begin. Other measures of bus latency can be used. Bus latency typically includes latency that occurs when transmitting higher priority messages, interrupt processing, the time required to terminate a datagram being processed on a serial bus, the time for transmitting a command that causes a bus conversion between a transmission mode and a reception mode, bus arbitration, and / or command transmission specified by a protocol.

[0064] In some examples, the latency-sensitive messages may include coexistence messages. Coexistence messages are transmitted in a multi-system platform to prevent or reduce situations where certain device types affect each other, including, for example, switches 524, LNAs 526, 528, PAs 520, and other types of devices that operate simultaneously in a manner that can generate inter-device interference or may cause damage to one or more active devices through high-power electromagnetic interference. Devices that may interfere with each other may exchange coexistence management (CxM) messages to allow each device to signal upcoming actions that may cause interference or conflicts. CxM messages can be used to manage the operation of shared components including switches 524, LNAs 526, 528, PAs 520, and / or antennas.

[0065] RFFE, SPMI, and certain other protocols that provide communications over a multi-drop serial bus may have certain common features. In one example, the datagram structure used to transmit command, control, and data payloads over a multi-drop serial bus may exhibit some similarities between the protocols. In other examples, similarities may exist between interrupt techniques, address allocation procedures, addresses used to select devices for receiving or transmitting data, clock generation, and management of device priorities.

[0066] Figure 6Datagram structures 600, 620 for register write commands and extended register write commands are shown. The datagram structures 600, 620 include certain elements that may be present in datagram structures defined by the SPMI and / or RFFE protocols. In some cases, the datagram structures 600, 620 can be used to efficiently write data to registers within the addressable register address range of slave devices operating according to the SPMI and / or RFFE protocols. These datagram structures 600, 620 and similar or equivalent datagram structures defined by other protocols can be suitable for use in systems implemented according to certain aspects disclosed herein. The datagram structures 600, 620 begin with the transmission of a two-bit sequence start condition (SSC 602, 622), followed by a four-bit device ID 604, 624. Next, a nine-bit command field 606, 626 is transmitted. In the register write command datagram structure 600, the nine-bit command field 606 includes a three-bit command code 612, a five-bit address field 614, and a parity bit. In the extended register write command datagram structure 620, the nine-bit command field 606 is occupied by an eight-bit command code and a parity bit, and is followed by an address field 628, which carries an eight-bit register address and a parity bit. In the register write command datagram structure 600, the data field 608 carries a single data byte, while in the extended register write command datagram structure 620, the data field 630 carries up to 16 data bytes. Each data byte is transmitted with a parity bit. Bus park signaling 610, 632 terminates the datagram structure 600, 620.

[0067] Although the concepts disclosed herein are applicable to a variety of serial bus protocols and standards, examples of RFFE protocols are often used herein to illustrate certain aspects of the present disclosure. Continuous changes in wireless communication technologies may result in new configurations of RFFE interfaces and increasing complexity of RFFE bus architectures. For example, these types of changes may increase the likelihood of traffic congestion on one or more RFFE buses provided in a communication device. For example, RFFE bus congestion and timing bottlenecks may occur in wireless phones that support the coexistence of 4G and 5G wireless communication technologies. In some implementations, support for carrier aggregation (CA) may increase RFFE bus timing complexity due to increased bus contention events. For example, the BoM may not be able to dynamically transmit a large number of settings to a large number of RFFE devices within the timeline defined for transmitting data frames in a 5G network, including when the number of more modes and specified behaviors of the 5G network increases.

[0068] Certain aspects of the present disclosure relate to providing a slave device including an expander and / or sequencer logic, the expander and / or sequencer logic being configured to enable the slave device to receive a short command from the BoM, the short command causing the slave device to access a register in one or more RF devices. The expander and / or sequencer logic may be configured to execute a sequence in response to a short command. In one example, the expander and / or sequencer logic performs register writes to configure one or more RF devices without further involving the BoM and / or without using a bus that couples the slave device to the BoM. The expander and / or sequencer logic may cause the slave device to read or write a register in the RF device using a serial data link protocol optimized for low-latency communication. The optimized serial bus may be referred to herein as a radio frequency serial bus (RFSB) protocol, although the RFSB protocol may be used for or suitable for use in other types of systems. For example, a slave device including an expander and / or sequencer logic may be suitable for using the RFSB protocol or its derivative protocol to control, manage or service multiple sensor devices to communicate with the sensor device.

[0069] Example of use of RFSB interface

[0070] Figure 7 Certain aspects of a system 700 employing an RFSB protocol in accordance with certain aspects disclosed herein are shown. In the example shown, a slave device 704 is configured to communicate over a serial bus 710 in accordance with the RFFE protocol. For convenience, the serial bus 710 may be referred to as a master serial bus. In some implementations, the serial bus 710 may operate in accordance with the SPMI or I3C protocol. The serial bus 710 shown is a two-wire bus having a clock line (SCLK 712) and a data line (SDATA 714). The serial bus 710 may correspond to Figure 2 Serial bus 220, Figure 4 One or more of the data communication links 410, 412, 422, 424, and / or Figure 5 The RFFE buses 530, 532, 534 are shown.

[0071] The slave device 704 may include a bus interface 716 that enables communication with the BoM device 702 over the serial bus 710. The bus interface 716 may be configurable for use with one or more protocols and may be used as a slave device on the serial bus 710. Some bus protocols support multi-master configurations, and the bus interface 716 may be configurable for operation as a BoM in certain circumstances. When used as a slave device, the bus interface 716 communicates with the corresponding bus interface 708 in the current BoM device 702. The BoM device 702 may be configured to manage and control communications over the serial bus 710.

[0072] The slave device 704 shown includes a sequencer 720 that can execute one or more preconfigured sequences. In one example, the preconfigured sequence can cause the slave device 704 to write and / or read a group of registers in a configuration or predefined order. The group of registers can include the selected registers in one or more RF devices 706a, 706b, 706c, 706d. The sequencer 720 can be implemented using the configuration of combinational logic, registers and / or triggers. In one example, the sequencer 720 includes a microcontroller or other general processing device. In another example, the sequencer 720 includes one or more state machines that can be configurable or programmable. In another example, the sequencer 720 includes a programmable logic controller or another type of logic that can execute a sequence of logic control steps. The sequencer 720 can perform time-driven and / or event-driven sequences. The sequencer 720 can derive time information from a clock signal provided locally. In some cases, the sequencer 720 can obtain time information from a clock signal transmitted on the SCLK 712 of the serial bus 710.

[0073] The slave device 704 can access the group of registers through one or more point-to-point serial buses 730a, 730b, 730c, 730d. For convenience, the point-to-point serial buses 730a, 730b, 730c, 730d can be referred to as auxiliary serial buses. The point-to-point serial buses 730a, 730b, 730c, 730d can be operated according to the RFSB protocol. Each point-to-point serial bus 730a, 730b, 730c, 730d in the system 700 shown includes a clock and data line. The slave device 704 includes a bus interface 718, which includes a circuit that couples the slave device 704 to the point-to-point serial bus 730a, 730b, 730c, 730d. The bus interface 718 operates as a bus master relative to the RF devices 706a, 706b, 706c, 706d. The bus interface 718 can manage communications according to the RFSB protocol. In some cases, the point-to-point serial buses 730a, 730b, 730c, 730d may operate according to I3C, RFFE, SPMI, or other protocols.

[0074] In some implementations, the RF devices 706a, 706b, 706c, 706d can perform operations related to Figure 5One or more of the functions associated with the RF front-end devices 518, 520, 522, 524, 526, 528 shown. In the system 700 shown, each of the RF devices 706a, 706b, 706c, 706d includes a bus interface 722a, 722b, 722c, 722d, which enables communication with the slave device 704 on the corresponding point-to-point serial bus 730a, 730b, 730c, 730d. The bus interface 722a, 722b, 722c, 722d can be configured to be used with the RFSB protocol and / or one or more other protocols. Each bus interface 722a, 722b, 722c, 722d can be used as a slave device on the corresponding point-to-point serial bus 730a, 730b, 730c, 730d. Each bus interface 722a, 722b, 722c, 722d is in communication with the bus interface 716 of the slave device 704 which manages and controls communications over the point-to-point serial bus 730a, 730b, 730c, 730d.

[0075] In the illustrated system 700, each of the RF devices 706a, 706b, 706c, 706d includes a set of registers 724a, 724b, 724c, 724d addressable using the RFSB protocol. The slave device 704 can read and write individual registers and / or read or write a batch of registers located at consecutive addresses using commands provided by the RFSB protocol. In some implementations, some of the registers 724a, 724b, 724c, 724d can be used to configure components such as sensors, RF circuits, and / or analog circuits 726a, 726b, 726c, 726d. In some implementations, some of the registers 724a, 724b, 724c, 724d can be used to maintain state information or data received from the sensors, RF circuits, and / or analog circuits 726a, 726b, 726c, 726d.

[0076] In an example of operation, the BoM device 702 may transmit to the slave device 704 a command to initiate an action involving one or more of the RF devices 706a, 706b, 706c, 706d. The command may cause the sequencer 720 to perform a register access sequence, including a register read and a register write access. The BoM device 702 does not further participate in the register access sequence. In one example, the slave device 704 uses the type and / or content of the command received from the BoM device 702 to select a preconfigured sequence from a plurality of preconfigured sequences to execute. The preconfigured sequence may include or generate a register access sequence when executed.

[0077] Using a sequencer 720 to perform register access sequences can produce certain advantages. For example, the BoM device 702 can configure multiple RF devices 706a, 706b, 706c, 706d by transmitting a single command over the serial bus 710, where the command can be a short command. The use of a single command can reduce the traffic on the busy serial bus 710, including in 4G / 5G wireless communication devices that are experiencing increasing complexity and traffic. The slave device 704 can use the sequencer 720 to extend the short commands transmitted by the BoM device 702 by executing the register programming sequence under internal control without the participation of the serial bus 710 or the BoM device 702. In addition to reducing congestion, when high congestion or high latency is observed on the serial bus 710, the slave device 704 equipped with the sequencer 720 can provide improved performance.

[0078] The use of sequencer 720 can reduce the overall power consumption of the RF module. The current consumed by the operation of serial buses 730a, 730b, 730c, 730d can be significantly less than the current consumed by the same operation on a single RFFE bus. The load provided by each interface coupled to the RFFE bus can increase the current drive of the transmission interface. According to certain aspects of the present disclosure, the RFSB bus can have a point-to-point architecture and can minimize the current consumption due to each register read or write operation.

[0079] In some implementations, a slave device 704 equipped with a sequencer 720 may be deployed as a hub device that receives BoM commands and expands them into a series of register programming commands for multiple downstream RF components on the module. The RF components may include PAs, LNAs, filters, switches, etc. The hub may interpret and expand commands received from a BoM device 702, which may be a modem or an application processor, and may expand the commands into register settings for downstream RF devices 706a, 706b, 706c, 706d.

[0080] In some implementations, one or more of the point-to-point serial buses 730a, 730b, 730c, 730d may operate according to I3C, RFFE, SPMI, or other universal serial bus protocols. When the RFSB protocol currently disclosed is used to couple the RF devices 706a, 706b, 706c, 706d to the slave device 704 equipped with the sequencer 720, timing efficiency, minimized physical space overhead, and simplified design may be obtained. The selection of the protocol for controlling the point-to-point serial buses 730a, 730b, 730c, 730d may be selected based on the configuration of the system 700. For example, the physical layout of the circuits and components and the proximity to another serial bus may indicate which protocol should be used. The capabilities of the RF devices 706a, 706b, 706c, 706d may also be considered when selecting the protocol.

[0081] The RFSB protocol disclosed herein can be used within a SoC device and / or between IC devices. For example, the RFSB protocol can support intra-module communication (within a single RF module) and can support communication between RF modules. According to certain aspects of the present disclosure, the RFSB interface provides optimized and minimized overhead when deployed in intra-module communications that can operate at a faster data rate or a faster effective data rate than other interfaces, where the effective data rate takes into account the effects of protocol overhead and / or bus congestion. The RFSB interface can use a transmission clock rate that is higher in frequency than the clock rate used for the RFFE interface. In one example, the serial bus 710 coupling the BoM device 702 and the slave device 704 may operate according to the RFFE protocol, and the RFSB protocol controlling communications over the point-to-point serial buses 730a, 730b, 730c, 730d may operate at a higher clock frequency than the frequency of the clock signal transmitted on the SCLK 712 of the serial bus 710, thereby ensuring that commands received from the BoM device 702 can be expanded by the slave device 704 and transmitted to the appropriate RF devices 706a, 706b, 706c, 706d in a timely manner.

[0082] The RFSB slave device uses a simplified bus interface that can be manufactured to have a smaller area footprint than a conventional RFFE slave device, thereby providing reduced device cost overhead. For example, the RFSB slave device supports a less complex datagram structure and fewer commands. Because a relatively small number of RF devices 706a, 706b, 706c, 706d can be deployed in an RF module, address overhead can be reduced.

[0083] The RFSB protocol disclosed herein can provide a customized and highly optimized serial interface that can be used to communicate between a slave device 704 equipped with a sequencer 720 and multiple RF devices 706a, 706b, 706c, 706d in an RF module. Register values ​​of multiple RF devices 706a, 706b, 706c, 706d in an RF module can be sent from the slave device 704 to the RF devices 706a, 706b, 706c, 706d through a point-to-point serial interface operating according to the RFSB protocol. The initiating BoM device 702 can benefit from significantly reduced traffic, and the BoM device 702 can experience reduced processing overhead when only short commands are transmitted to the slave device 704 instead of directly writing all register settings of each RF device 706a, 706b, 706c, 706d. The use of the RFSB protocol can provide higher speed, lower implementation cost, and efficient RF module programming timeline. Slave device 704 may be locally programmable to allow for a higher degree of configurability while reducing the overall traffic associated with BoM device 702 .

[0084] Figure 8 An example of a command structure 800 of an RFSB protocol provided in accordance with certain aspects of the present disclosure is shown. In one aspect, the RFSB protocol may define a command structure and an associated datagram structure that are transmitted over a serial bus having a clock line (SBCK 802) and a data line (SBDATA 804). Table 820 shows an example of a command that conforms to the command structure 800. In one example, the RFSB protocol and command structure 800 may be configured to support an RF front-end device. In another example, the RFSB protocol and command structure 800 may be configured to support a sensor network.

[0085] Table 820 defines a portion of the command set corresponding to the bit settings in the command code 822. In the example shown, the command code 822 has a 6-bit value and is transmitted with a parity bit. Certain commands are transmitted with a payload 824, which can carry data, a mask, and / or an address. The number of commands defined for the RFSB interface can be minimized and / or limited to basic commands. The reduced command set can minimize communication and processing overhead in the slave device and / or RF device. Relative to conventional RFFE command and datagram structures, the command and datagram structure can be optimized to minimize frame transmission time and the number of bits transmitted per transaction. Certain downstream devices can be configured to support a subset of the commands defined for the RFSB protocol.

[0086] Command structure 800 illustrates the format of certain global commands that can be transmitted with minimized transmission time. In the example shown, 12 clock cycles are used to transmit global commands. Command frame 808 is transmitted in 7 clock cycles, of which 5 clock cycles are used for control signaling, including SSC 806 and bus parking (BP 812). During the transmission of BP 812, the driver in the transmitting device can transform its output to present a high impedance to SBDATA 804, thereby releasing SBDATA 804 to an undriven state.

[0087] In the illustrated RFSB protocol, the command frame 808 includes a 6-bit command code 810 and a 1-bit parity check 818. In this example, a global command is indicated by a command code 810 whose three most significant bits (MSB 814) are set to logic 0 and whose three least significant bits (C[2:0] 816) define the command. In one example, a global command includes:

[0088] C[2:0]='b010: Reset(PM_STARTUP), where all registers including the three internal power mode registers and the trigger disable register are reset.

[0089] C[2:0] = 'b011: Reset_alt (UDR_RST), where the user defined registers are reset without resetting the power mode registers and the trigger disable register.

[0090] C[2:0]='b01?: The value of address bit 7, where the value of address bit 7 is defined for paging purposes.

[0091] Other command codes for global commands may be defined, and some command codes may be reserved for user-defined use, application-specific use, or future use. Command structure 800 illustrates an example of using the RFSB protocol to support RF front-end operations, although command structure 800 may be used in other applications. Table 820 defines additional commands, including trigger mask commands, trigger commands, power mode commands, register write commands, register mask write commands, and register read commands.

[0092] Certain short commands are defined by the RFSB protocol to manage and / or control triggers. In one example, triggers provide a mechanism for RF front-end control, whereby certain triggers can be used to coordinate the activities of different front-end components. Triggers can be used for a variety of purposes, including beam steering or beamforming, gain setting, antenna path multiplexer control, and the like. In some devices, triggers can be configured, activated, and / or actuated over a serial bus operating in accordance with the RFFE protocol. In a first example, the BoM may transmit a command including a trigger configuration, the trigger configuration including an action associated with the trigger, and wherein receipt of the command causes the trigger to take effect or be applied upon receipt. In the latter example, a trigger configured by a command may be referred to as a self-actuated trigger. In a second example, the BoM transmits a first command that configures one or more triggers. The configuration may define an action associated with the configured trigger and may activate one or more triggers. The BoM may transmit a second command that actuates the activated trigger.

[0093] Fig. 9 A scheme 900 illustrating actuation of a trigger of an activation is shown. In the example shown, configuration information is received as a plurality of data bytes 902, which may be stored in a trigger configuration register 904. The trigger configuration register 904 may be written during a configuration transaction conducted over a serial bus, which may operate in accordance with an RFFE protocol. The contents of the trigger configuration register 904 may be forwarded to one or more target registers using a trigger activation process. The target register may configure or control one or more antennas, interfaces, modems, control circuits, processors, etc. For example, a change in a value stored in a target register may cause a circuit in a slave device to generate a signal, message, interrupt, or other type of event.

[0094] The trigger activation logic 906 can be configured to enable the contents of the trigger configuration register 904 to be transmitted to the corresponding target device in response to a trigger command or trigger actuation signal 910 received from the control device. In conventional systems, one or more trigger actuation commands can be transmitted to trigger the activation of the configuration of at least a portion of the target trigger element 908. The trigger element 908 can include switches, LNAs, PAs, and other types of devices operating concurrently in the RF front end. In one example, the trigger actuation transmission can configure a shielding or gating logic that determines which trigger elements 908 will receive data from the trigger configuration register 904 during the actuation initiated by the trigger actuation signal 910.

[0095] Fig.10Short commands 1000, 1020 defined by the RFSB protocol for managing and / or controlling triggers are shown. The first short command 1000 is defined as a trigger mask command, which can be used to set or clear a mask bit in a trigger actuation circuit. The trigger mask command is initiated by the SSC 1006, which is signaled using the clock line (SBCK 1002) and the data line (SBDATA 1004). The command frame 1008 carries a 6-bit command code ('b001000) followed by a parity bit. The mask frame 1010 is transmitted as a payload and includes 3 bits of mask information transmitted with the parity bit. The trigger mask command is terminated with a bus park signaling (BP 1012).

[0096] The second short command 1020 is defined as a trigger command that can be used to actuate one or more triggers. The trigger command is initiated by the SSC 1026, which is signaled using the clock line (SBCK 1022) and the data line (SBDATA 1024). The command frame 1028 carries a 3-bit command code 1030 (set to 'b011), three trigger bits 1032, followed by a parity bit. The trigger command is terminated with a bus parking signaling (BP 1034). In one example, the RF device generates a clock cycle gating as a trigger signal in response to one or more of the three trigger bits 1032 being set to logic 1. In this example, when all three trigger bits 1032 are set to logic 0, the trigger disable mode is activated. When any one of the three trigger bits 1032 is set to logic 1, the trigger disable mode is disabled. A write command to a trigger-enabled user-defined register can cause both the trigger configuration register 904 and the output register corresponding to the trigger element 908 to be automatically updated. The trigger command is typically a global command that affects all RF devices coupled to the RFSB bus.

[0097] Fig.11 A power mode command 1100 defined by the RFSB protocol for managing and / or controlling the power mode in one or more RF devices is shown. The power mode command 1100 is a short command initiated by the SSC 1106, which is signaled using the clock line (SBCK 1102) and the data line (SBDATA 1104). The command frame 1108 carries a 3-bit command code 1110 (set to 'b010), three power mode bits 1112, followed by a parity bit. The trigger command is terminated with a bus park signaling (BP 1114). The power mode command 1100 is a global command that works on all RF devices coupled to the RFSB bus.

[0098] Fig.12Long commands 1200, 1220, 1240 defined by the RFSB protocol for reading or writing registers are shown. Fig.12 The first long command 1200 in is defined as a register write command, which can be used to configure the value stored in one or more registers. The register write command is a long command that supports batch writes and is initiated by SSC 1202. The register write command includes a command frame 1204, which carries a 3-bit command code ('b100) and a 3-bit identifier 1214, followed by a parity bit. The payload includes an address frame 1206 configured with a register address, which selects the first register to be written. The payload includes one or more data frames 1208, 1210, which include 8 bits of data and a parity bit. The register write command terminates with a bus parking signaling (BP 1212). In the example shown, a byte count defining the number of frames (N) of data in the payload is not provided. As long as there are valid data frames to be transmitted, the register write command will continue. The first data frame 1208 is written to the register at the address identified by the address frame 1206, and after each register write, the address is incremented (e.g., value 0x01) to point to the next register to be written. In some implementations, the address does not wrap around, but stops changing at address 0x7f. If there are additional valid data frames available for transmission, the register at address 0x7F will be overwritten. The register at address 0x7F can be updated indefinitely by a single register write command.

[0099] Fig.12The second long command 1220 in is defined as a register mask write command, which can be used to configure the value stored in one or more registers. The register mask write command is a long command that supports batch writes and is initiated by SSC 1222. The register mask write command includes a command frame 1224, which carries a 3-bit command code ('b101) and a 3-bit identifier 1234, followed by a parity bit. The payload includes an address frame 1226 configured with a register address, which selects the first register to be written. The payload includes a mask frame 1228, followed by a data frame 1230, each frame 1228, 1230 including 8 bits of information and a parity bit. The mask frame 1228 includes a bit that defines whether the bit of the target register will be written by the corresponding bit of the data frame 1230. Multiple pairs of mask and data frames can be carried in the payload. The register mask write command terminates with a bus parking signaling (BP 1232). In the example shown, a byte count of the number of frames defining the data in the payload is not provided. The register mask write command continues as long as there are valid data frames to be transmitted. The bits in the first data frame 1230 that are not masked by the operation of the mask frame 1228 are written to the corresponding bits in the register at the address identified by the address frame 1226, and after each register write, the address is incremented by 0x01 to point to the next register to be written. In some implementations, the address does not wrap around, but stops changing at address 0x7f. If there are additional valid data frames available for transmission, the register at address 0x7F will be overwritten. The register at address 0x7F can be updated indefinitely by a single register mask write command.

[0100] Fig.12 The third long command 1240 in is defined as a register read command, which can be used to read the value stored in the identified register. The register read command is a long command initiated by SSC 1242. The register read command includes a command frame 1244, which carries a 3-bit command code ('b100) and a 3-bit identifier 1254, followed by a parity bit. The payload includes an address frame 1246 configured with a register address, which selects the register to be read. Then, the transmitter provides a bus parking signaling (BP 1248), in which it releases the data line. At time 1250 after the data line is released, the addressed RF device activates its line driver and transmits a data frame 1252, which includes the content of the register to be read together with the parity bit. When the RF device provides a bus parking signaling (BP1256), the register read command terminates.

[0101] Fig.13An example of a pass-through transaction is shown, where an RFFE command transmitted by an RFFE BoM is received by an RFFE slave device that has been adapted according to certain aspects disclosed herein. While an RFFE transaction is ongoing, the RFFE slave device can initiate a register read or write transaction with a downstream RF device.

[0102] The first example involves an RFFE extended register write command 1300 that causes a register write command 1320 to be transmitted by the RFFE slave device to configure the values ​​stored in one or more registers. The RFFE extended register write command 1300 is initiated by the SSC 1302. A device identifier 1304 is transmitted, followed by a command code 1306. An address frame 1308 identifies the first register to be written. One or more data frames 1310, 1312 may be transmitted, and the RFFE extended register write command 1300 is terminated with a bus park signaling (BP 1314).

[0103] The register write command 1320 is initiated by the SSC 1302 at a point in time 1316 after the RFFE extended register write command 1300 has been started. In one example, the register write command 1320 may be initiated after the command code 1306 has been received from the RFFE BoM and the nature of the command has been determined. The RFFE slave device may transmit the SSC 1322, followed by a command frame 1324, and may relay the contents of the address frame 1308 received from the RFFE BoM in an address frame 1326 to select the first register to be written. The payload of the register write command 1320 includes one or more data frames 1328, 1330 received in the RFFE extended register write command 1300. The register write command terminates with a bus park signaling (BP 1332).

[0104] A second example involves a debug mode RFFE extended register read command 1340 that causes a register read command 1360 to be transmitted by the RFFE slave device to read a value stored in a register of the RF device. The RFFE extended register read command 1340 is initiated by the SSC 1342. A device identifier 1344 is transmitted, followed by a command code 1346. Address frames 1348 and 1350 identify the first register to be written. The BoM then provides bus park signaling (BP 1352) to indicate the release of the data line. At a time 1354 after the data line is released, the addressed RFFE slave device activates its line driver and transmits a data frame 1356 including the register contents read from the target RF device. The register read command terminates when the RFFE slave device provides bus park signaling (BP 1358).

[0105] The register read command 1360 may be used to read the value stored in the register identified by the address frames 1348 and 1350 in the RFFE extended register read command 1340. The register read command is initiated by the SSC 1362 provided at a time point 1380 after the start of the RFFE extended register read command 1340. In one example, the register read command 1360 may be initiated after the command code 1346 has been received from the RFFE BoM and the nature of the command has been determined. The register read command includes a command frame 1364, which includes an address frame 1366, which is configured with a register address derived from the contents of the address frames 1348 and 1350 in the RFFE extended register read command 1340. The transmitter then provides bus park signaling (BP 1368) to indicate the release of the data line. At a time 1370 after the data line is released, the addressed RF device activates its line driver and transmits a data frame 1372 including the contents of the identified register. When the RF Device Provides Bus Park Signaling (BP 1374), the Register Read Command 1360 terminates.

[0106] Examples of Processing Circuits and Methods

[0107] Fig.14 1400. It is a diagram showing an example of a hardware implementation of the device 1400. In some examples, the device 1400 can perform one or more functions disclosed herein. According to various aspects of the present disclosure, any part of the elements or any combination of elements disclosed herein can be implemented using a processing circuit 1402. The processing circuit 1402 may include one or more processors 1404 controlled by a certain combination of hardware and software modules. Examples of processors 1404 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform various functions described throughout the present disclosure. One or more processors 1404 may include a dedicated processor that performs a specific function and can be configured, expanded, or controlled by one of the software modules 1416. One or more processors 1404 may be configured by a combination of software modules 1416 loaded during initialization, and further configured by loading or unloading one or more software modules 1416 during operation.

[0108] In the example shown, the processing circuit 1402 can be implemented with a bus architecture, which is generally represented by a bus 1410. Depending on the specific application and overall design constraints of the processing circuit 1402, the bus 1410 may include any number of interconnecting buses and bridges. The bus 1410 links various circuits including one or more processors 1404 and storage devices 1406 together. The storage device 1406 may include a memory device and a mass storage device, and may be referred to as a computer-readable medium and / or a processor-readable medium in this article. The bus 1410 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuits. The bus interface 1408 may provide an interface between the bus 1410 and one or more transceivers 1412a, 1412b. Transceivers 1412a, 1412b may be provided for each networking technology supported by the processing circuit. In some cases, multiple networking technologies may share some or all of the circuit systems or processing modules found in the transceivers 1412a, 1412b. Each transceiver 1412a, 1412b provides a module for communicating with various other devices over a transmission medium. In one example, transceiver 1412a can be used to couple device 1400 to a multi-line bus. In another example, transceiver 1412b can be used to connect device 1400 to a radio access network. Depending on the nature of device 1400, a user interface 1418 (e.g., a keypad, display, speaker, microphone, joystick) may also be provided, and user interface 1418 may be directly or communicatively coupled to bus 1410 via bus interface 1408.

[0109] The processor 1404 may be responsible for managing the bus 1410 and for general processing, which may include the execution of software stored in a computer-readable medium, which may include a storage device 1406. In this regard, the processing circuit 1402 (including the processor 1404) may be used to implement any of the methods, functions, and techniques disclosed herein. The storage device 1406 may be used to store data that is manipulated by the processor 1404 when executing the software, and the software may be configured to implement certain methods disclosed herein.

[0110] One or more processors 1404 in the processing circuit 1402 may execute software. Software should be broadly interpreted to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, processes, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in a computer-readable form in the storage device 1406 or in an external computer-readable medium. The external computer-readable medium and / or the storage device 1406 may include a non-transitory computer-readable medium. Non-transitory computer-readable media include, for example, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM) (including EEPROM), registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. For example, the computer-readable medium and / or storage device 1406 may also include carrier waves, transmission lines, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. The computer-readable medium and / or storage device 1406 may reside in the processing circuit 1402, in the processor 1404, external to the processing circuit 1402, or distributed among multiple entities including the processing circuit 1402. The computer-readable medium and / or storage device 1406 may be embodied in a computer program product. For example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize how to best implement the described functionality presented in this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

[0111] The storage device 1406 may maintain software maintained and / or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules 1416. Each software module 1416 may include instructions and data that, when installed or loaded onto the processing circuit 1402 and executed by the one or more processors 1404, contribute to a runtime image 1414 that controls the operation of the one or more processors 1404. When executed, certain instructions may cause the processing circuit 1402 to perform functions according to certain methods, algorithms, and processes described herein.

[0112] Some of the software modules 1416 may be loaded during initialization of the processing circuit 1402, and these software modules 1416 may configure the processing circuit 1402 to enable execution of the various functions disclosed herein. For example, some of the software modules 1416 may configure the internal devices and / or logic circuits 1422 of the processor 1404, and may manage access to external devices such as transceivers 1412a, 1412b, bus interface 1408, user interface 1418, timers, math coprocessors, etc. The software modules 1416 may include a control program and / or operating system that interacts with interrupt handlers and device drivers and controls access to various resources provided by the processing circuit 1402. Resources may include memory, processing time, access to the transceivers 1412a, 1412b, user interface 1418, etc.

[0113] The one or more processors 1404 of the processing circuit 1402 may be multifunctional, with some of the software modules 1416 being loaded and configured to perform different functions or different instances of the same function. For example, the one or more processors 1404 may be additionally adapted to manage background tasks initiated in response to inputs from the user interface 1418, the transceivers 1412a, 1412b, and the device drivers. In order to support the execution of multiple functions, the one or more processors 1404 may be configured to provide a multitasking environment, wherein each of the multiple functions is implemented as a set of tasks served by the one or more processors 1404 as needed or desired. In one example, the multitasking environment may be implemented using a time-sharing program 1420, which transfers control of the processor 1404 between different tasks, wherein each task returns control of the one or more processors 1404 to the time-sharing program 1420 when any unfinished operation is completed and / or in response to inputs such as interrupts. When a task controls one or more processors 1404, the processing circuit is effectively dedicated to the purpose solved by the function associated with the control task. The time-sharing program 1420 may include an operating system, a main loop that transfers control on a loop basis, functions that allocate control of one or more processors 1404 based on the priority of the functions, and / or an interrupt-driven main loop that responds to external events by providing control of one or more processors 1404 to processing functions.

[0114] Fig.15 1500 is a flow chart of a method that can be performed by a slave device coupled to a master serial bus and multiple slave serial buses. In one example, the master serial bus can operate according to the RFFE protocol. In another example, the master serial bus can operate according to the SPMI protocol. In one example, the master serial bus can operate according to the I3C protocol.

[0115] In box 1502, a slave device can communicate with a bus master through a first interface circuit, and the first interface circuit is configured to couple the slave device to a main serial bus. In box 1504, the slave device can communicate with one or more downstream devices through a second interface circuit, and the second interface circuit is configured to couple the slave device to a plurality of auxiliary serial buses. Each auxiliary serial bus in a plurality of auxiliary serial buses is configured as a point-to-point serial link. With respect to the bus master and the slave device, the downstream device can be regarded as a downstream, so that downstream data can flow from the master device to the slave device and / or from the slave device to the downstream device, and upstream data can flow from the downstream device to the slave device and / or from the slave device to the master device. In box 1506, the slave device can respond to the first command received from the main serial bus by initiating the execution of a preconfiguration sequence, and the preconfiguration sequence causes the command sequence to be transmitted through the second interface circuit. The command sequence can be configured to access a register in at least one downstream device.

[0116] In some cases, the command sequence includes a first command addressed to a register in a first downstream device and a second command addressed to a register in a second downstream device, the first downstream device being coupled to a first auxiliary serial bus, and the second downstream device being coupled to a second auxiliary serial bus. The command sequence may include a register write command, a register mask write command, or a register read command. The command sequence may include a trigger mask write command or a trigger command.

[0117] In some implementations, a serial bus protocol used to transmit data over a primary serial bus (e.g., RFFE, SPMI, I3C, etc.) can operate at a data rate that is lower than the data rate used with a different serial bus protocol to transmit data over multiple secondary serial buses.

[0118] In some examples, the slave device may receive a second command from the main serial bus, and may initiate transmission of a third command over one of the plurality of auxiliary serial buses in response to the second command. The transmission of the third command may begin while the second command is received. The slave device may determine the type of the second command based on the command code transmitted in the second command, and may start transmission of the third command after determining the type of the second command and before the address information of the second command has been completely received.

[0119] In some implementations, a slave device may manage communications over multiple secondary serial buses and may use the content of the first command to select a preconfiguration sequence from one or more preconfiguration sequences before the first command has been completely received.

[0120] Fig.161600 . The processing circuitry typically has one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines, generally represented by processors 1616 . The processing circuitry 1602 may be implemented with a bus architecture, generally represented by bus 1620 . Depending on the specific application and overall design constraints of the processing circuitry 1602 , the bus 1620 may include any number of interconnecting buses and bridges. The bus 1620 links together various circuits, including one or more processors 1616 , modules or circuits 1604 , 1606 , and 1608 , and processor-readable storage media 1618 . One or more bus interface circuits and / or modules 1614 may be provided to support communications over multiple serial buses 1612 . The bus 1620 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, that are well known in the art and therefore will not be described further.

[0121] The processor 1616 may be responsible for general processing, including the execution of software, code, and / or instructions stored on the processor readable storage medium 1618. The processor readable storage medium 1618 may include a non-transitory storage medium. The software, when executed by the processor 1616, causes the processing circuit 1602 to perform the various functions described above for any particular device. The processor readable storage medium may be used to store data manipulated by the processor 1616 when executing the software. The processing circuit 1602 also includes at least one of the modules 1604, 1606, and 1608. The modules 1604, 1606, and 1608 may be software modules running in the processor 1616, one or more hardware modules coupled to the processor 1616, or some combination thereof, resident / stored in the processor readable storage medium 1618. The modules 1604, 1606, and 1608 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0122] In one configuration, the apparatus 1600 includes modules and / or circuits 1604 adapted to manage, configure and / or control bus interface circuits and / or modules 1614, and modules and / or circuits 1606 adapted to process commands received from the BoM and generate and transmit command sequences through the bus interface circuits and / or modules 1614. The apparatus 1600 may include modules and / or circuits 1608 adapted to manage sequencer operations and / or select sequences to be executed.

[0123] In one example, the device 1600 is configured to operate as a data communication device having a first bus interface circuit and / or module 1614 configured to couple the device 1600 to a primary serial bus, a second bus interface circuit and / or module 1614 configured to couple the data communication device to a plurality of secondary serial buses, and a sequencer. The sequencer may be configured to respond to a first command received from the primary serial bus by initiating execution of a preconfiguration sequence that causes a command sequence to be transmitted through the second interface circuit. The command sequence may be configured to access a register in at least one device coupled to one of the secondary serial buses.

[0124] The command sequence may include a first command addressed to a register in a first device and a second command addressed to a register in a second device, the first device being coupled to a first auxiliary serial bus and the second device being coupled to a second auxiliary serial bus. The command sequence may include a register write command, a register mask write command, or a register read command. The command sequence may include a trigger mask write command or a trigger command.

[0125] The first serial bus protocol may be used to transmit data over the primary serial bus at a first data rate, and the second serial bus protocol may be used to transmit data over the plurality of secondary serial buses at a second data rate greater than the first data rate.

[0126] The sequencer may be configured to receive a second command from the main serial bus and initiate transmission of a third command over one of the plurality of auxiliary serial buses in response to the second command. Transmission of the third command may begin while the second command is received. Transmission of the third command may be initiated after determining the type of the second command and before address information of the second command has been completely received.

[0127] The second bus interface circuit and / or module 1614 can be configured to manage communications over multiple auxiliary serial buses and select a preconfigured sequence from one or more preconfigured sequences using the content of the first command before the first command has been fully received. In some cases, each of the multiple auxiliary serial buses is configured as a point-to-point serial link. The main serial bus can operate according to RFFE, SPMI, I3C, or other protocols.

[0128] The processor-readable storage medium 1618 may include instructions that cause the processing circuit 1602 to communicate with a bus master via a first interface circuit configured to couple a slave device to a primary serial bus, communicate with one or more downstream devices via a second interface circuit configured to couple the slave device to a plurality of secondary serial buses, and respond to a first command received from the primary serial bus by initiating execution of a preconfiguration sequence that causes a command sequence to be transmitted via the second interface circuit. The command sequence may be configured to access a register in at least one downstream device.

[0129] The first serial bus protocol can be used to transmit data at a first data rate over a main serial bus, and the second serial bus protocol can be used to transmit data at a second data rate greater than the first data rate over a plurality of auxiliary serial buses. Each of the plurality of auxiliary serial buses can be configured as a point-to-point serial link. In some implementations, the main serial bus can operate according to RFFE, SPMI, I3C, or other protocols.

[0130] The processor readable storage medium 1618 may include instructions that cause the processing circuit 1602 to perform the following operations: receive a second command from the primary serial bus, and initiate transmission of a third command on one of the plurality of secondary serial buses in response to the second command. The transmission of the third command may begin while the second command is received.

[0131] The processor-readable storage medium 1618 may include instructions that cause the processing circuit 1602 to perform the following operations: determine the type of the second command based on the command code transmitted in the second command, and start the transmission of the third command after determining the type of the second command and before the address information of the second command has been completely received.

[0132] The processor readable storage medium 1618 may include instructions that cause the processing circuit 1602 to manage communications over the plurality of secondary serial buses and select a preconfigured sequence from one or more preconfigured sequences using content of the first command before the first command has been completely received.

[0133] It should be understood that the specific order or hierarchy of steps in the disclosed process is an illustration of an exemplary method. It is understood that the specific order or hierarchy of steps in the process can be rearranged based on design preferences. In addition, some steps can be combined or omitted. The accompanying method claims present elements of the various steps in an example order and are not meant to be limited to the specific order or hierarchy presented.

[0134] The previous description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be clear to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but to the full scope consistent with the language claims, wherein unless specifically stated so, references to elements in the singular form are not intended to mean "one and only one", but to mean "one or more". Unless otherwise specifically stated, the term "some" refers to one or more. All structural and functional equivalents of the elements of the various aspects described in this disclosure known or later known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be exclusively for public use, regardless of whether such disclosure is explicitly cited in the claims. Any claim element shall not be interpreted as a module plus function unless the phrase "module for..." is used to expressly describe the element.

Claims

1. A data communication device, comprising: a first interface circuit configured to couple the data communication device to a main serial bus; a second interface circuit configured to couple the data communication device to a plurality of auxiliary serial buses; as well as a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfiguration sequence, the preconfiguration sequence causing a command sequence to be transmitted through the second interface circuit and a first auxiliary serial bus of the plurality of auxiliary serial buses, wherein the command sequence is configured to access one or more registers in a first device using the first auxiliary serial bus, the first auxiliary serial bus providing a first dedicated communication link between the second interface circuit and the first device, wherein the second interface circuit is further configured to: managing communications over the plurality of auxiliary serial buses, Wherein the content of the first command is used to select the preconfigured sequence from one or more preconfigured sequences before the first command has been completely received.

2. A data communication apparatus according to claim 1, wherein the command sequence comprises a first command addressed to a register in the first device and a second command addressed to a register in a second device, the register in the second device being accessed using a second auxiliary serial bus among the plurality of auxiliary serial buses, the second auxiliary serial bus providing a second dedicated communication link between the second interface circuit and the second device. 3 . The data communication device according to claim 1 , wherein the command sequence comprises a register write command, a register mask write command or a register read command. 4 . The data communication device according to claim 1 , wherein the command sequence comprises a trigger mask write command or a trigger command.

5. The data communication device according to claim 1, wherein a first serial bus protocol is used to transmit data on the main serial bus at a first data rate, a second serial bus protocol is used to transmit data on the first auxiliary serial bus at a second data rate greater than the first data rate, and a third serial bus protocol is used to transmit data on a second auxiliary serial bus among the plurality of auxiliary serial buses.

6. The data communication device according to claim 1, wherein the sequencer is further configured to: receiving a second command from the main serial bus; and Initiate transmission of a third command addressed to a register in a second device in response to the second command, access the register in the second device using a second auxiliary serial bus of the plurality of auxiliary serial buses, the second auxiliary serial bus providing a second dedicated communication link between the second interface circuit and the second device, wherein the transmission of the third command begins simultaneously with the receipt of the second command. 7 . The data communication device according to claim 6 , wherein the transmission of the third command is initiated after the type of the second command has been determined and before address information for the second command has been completely received. 8 . The data communication device according to claim 1 , wherein each of the plurality of auxiliary serial buses is configured as a point-to-point serial link.

9. The data communication device of claim 1, wherein the main serial bus is operated according to a radio frequency front end (RFFE) protocol.

10. A method of data communication at a slave device, comprising: communicating with a bus master via a first interface circuit configured to couple the slave device to a master serial bus; communicating with one or more downstream devices via a second interface circuit configured to couple the slave device to a plurality of secondary serial buses; as well as responding to a first command received from the primary serial bus by initiating execution of a preconfiguration sequence that causes a command sequence to be transmitted through the second interface circuit and a first auxiliary serial bus of the plurality of auxiliary serial buses, wherein the command sequence is configured to access one or more registers in a first downstream device using the first auxiliary serial bus, the first auxiliary serial bus providing a first dedicated communication link between the second interface circuit and the first downstream device, wherein the second interface circuit is further configured to: managing communications over the plurality of auxiliary serial buses, Wherein the content of the first command is used to select the preconfigured sequence from one or more preconfigured sequences before the first command has been completely received.

11. The method of claim 10, wherein the command sequence comprises a first command addressed to a register in the first downstream device and a second command addressed to a register in a second downstream device, the register in the second downstream device being accessed using a second auxiliary serial bus of the plurality of auxiliary serial buses, the second auxiliary serial bus providing a second dedicated communication link between the second interface circuit and the second downstream device. 12 . The method of claim 10 , wherein the command sequence comprises a register write command, a register mask write command, or a register read command.

13. The method of claim 10, wherein the command sequence comprises a trigger mask write command or a trigger command.

14. The method of claim 10, wherein a first serial bus protocol is used to transmit data on the main serial bus at a first data rate, a second serial bus protocol is used to transmit data on the first auxiliary serial bus at a second data rate greater than the first data rate, and a third serial bus protocol is used to transmit data on a second auxiliary serial bus among the plurality of auxiliary serial buses.

15. The method according to claim 10, further comprising: receiving a second command from the main serial bus; as well as Initiate transmission of a third command addressed to a register in a second downstream device in response to the second command, access the register in the second downstream device using a second auxiliary serial bus of the plurality of auxiliary serial buses, the second auxiliary serial bus providing a second dedicated communication link between the second interface circuit and the second downstream device, wherein the transmission of the third command begins while the second command is received.

16. The method according to claim 15, further comprising: determining a type of the second command according to a command code transmitted in the second command; as well as The transmission of the third command is initiated after determining the type of the second command and before address information for the second command has been completely received. 17 . The method of claim 10 , wherein each of the plurality of secondary serial buses is configured as a point-to-point serial link.

18. The method of claim 10, wherein the main serial bus is operated according to a radio frequency front end (RFFE) protocol.

19. A processor-readable storage medium comprising code for: communicating with a bus master via a first interface circuit configured to couple a slave device to a master serial bus; communicating with one or more downstream devices via a second interface circuit configured to couple the slave device to a plurality of secondary serial buses; as well as responding to a first command received from the primary serial bus by initiating execution of a preconfiguration sequence that causes a command sequence to be transmitted through the second interface circuit and a first auxiliary serial bus of the plurality of auxiliary serial buses, wherein the command sequence is configured to access one or more registers in a first downstream device using the first auxiliary serial bus, the first auxiliary serial bus providing a first dedicated communication link between the second interface circuit and the first downstream device, wherein the second interface circuit is further configured to: managing communications over the plurality of auxiliary serial buses, Wherein the content of the first command is used to select the preconfigured sequence from one or more preconfigured sequences before the first command has been completely received.

20. The processor-readable storage medium of claim 19, wherein a first serial bus protocol is used to transmit data over the primary serial bus at a first data rate, a second serial bus protocol is used to transmit data over the first secondary serial bus at a second data rate greater than the first data rate, and a third serial bus protocol is used to transmit data over a second secondary serial bus of the plurality of secondary serial buses, and wherein each of the plurality of secondary serial buses is configured as a point-to-point serial link.

21. The processor-readable storage medium of claim 19, further comprising code for: receiving a second command from the main serial bus; and Initiate transmission of a third command addressed to a register in a second downstream device in response to the second command, access the register in the second downstream device using a second auxiliary serial bus of the plurality of auxiliary serial buses, the second auxiliary serial bus providing a second dedicated communication link between the second interface circuit and the second downstream device, wherein the transmission of the third command begins while the second command is received.

22. The processor-readable storage medium of claim 21 , further comprising means for: determining a type of the second command based on a command code transmitted in the second command; and The transmission of the third command is initiated after determining the type of the second command and before address information of the second command has been completely received.

23. A data communication device, comprising: a module for communicating with a bus host, configured to couple the data communication device to a main serial bus; means for communicating with one or more downstream devices, configured to couple the data communication means to a plurality of secondary serial buses; as well as a module for executing a preconfiguration sequence that causes a command sequence to be transmitted by the module for communicating with the one or more downstream devices, wherein the preconfiguration sequence is executed in response to a first command received from the primary serial bus, and wherein the command sequence is configured to access one or more registers in a first downstream device using a first auxiliary serial bus, the first auxiliary serial bus providing a first dedicated communication link between the module for communicating with the one or more downstream devices and the first downstream device, wherein the module for communicating with the one or more downstream devices is further configured to: managing communications over the plurality of auxiliary serial buses, Wherein the content of the first command is used to select the preconfigured sequence from one or more preconfigured sequences before the first command has been completely received.

24. The data communication device of claim 23, wherein a first serial bus protocol is used to transmit data on the main serial bus at a first data rate, a second serial bus protocol is used to transmit data on the first auxiliary serial bus at a second data rate greater than the first data rate, and a third serial bus protocol is used to transmit data on a second auxiliary serial bus among the plurality of auxiliary serial buses, and wherein each of the plurality of auxiliary serial buses is configured as a point-to-point serial link.

25. The data communication device of claim 23, wherein the module for executing the preconfigured sequence is further configured to: Initiate transmission of a third command addressed to a register in a second downstream device in response to a second command received from the primary serial bus, accessing the register in the second downstream device using a second secondary serial bus of the plurality of secondary serial buses, the second secondary serial bus providing a second dedicated communication link between the module for communicating with the one or more downstream devices and the second downstream device, wherein the transmission of the third command begins while the second command is received.

26. The data communication device of claim 25, wherein the module for executing the preconfigured sequence is further configured to: The transmission of the third command is initiated after determining the type of the second command and before address information of the second command has been completely received.

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