Average current estimation circuit and estimation method thereof

Abstract

The application discloses an average current estimation circuit and an estimation method thereof pk , and an integral voltage value VC is obtained by integrating the input current in one period T through an integral circuit. pk The most approximate discharge current I T is selected by a discharge current selection circuit. T The integral voltage value VC is differentiated to obtain a duty cycle signal D_IN, the duty cycle signal D_IN is converted into a duty cycle square wave signal D_OUT by a level conversion circuit in a duty cycle-error conversion circuit, a direct current voltage component is obtained after filtering by a low-pass filter in the duty cycle-error conversion circuit, and finally the average current I AV in the period T is obtained by converting the direct current voltage component into current according to a proportion through a voltage-current conversion circuit.

Description

Technical Field

[0001] The present invention relates to current detection technology, in particular to an average current estimation circuit and an estimation method thereof, and belongs to the technical field of integrated circuits. Background Art

[0002] In many cases, it is necessary to find the average value of a periodically changing current signal within one cycle. Taking the flyback switching power supply as an example, the inductor current waveform is as follows: Figure 1 As shown in the figure, when the power device is turned on, that is, during the time t1, the inductor current rises linearly; when the power device is turned off, that is, during the time t2, the inductor continues to flow and the current charges the load capacitor. However, in some cases, the current waveform is not a regular current waveform, such as the active clamp flyback circuit in the flyback, the current waveform output to the secondary of the transformer is as follows Figure 2 As shown, it can be seen that the current waveform within the period T is continuous but relatively complex, and it is difficult to calculate the average value of the current at this time.

[0003] When average current analysis is required for a current waveform within a specific cycle, the traditional method is to integrate the current within the cycle and then divide it by the entire cycle length to obtain the average current value. This method is relatively complex and often requires the use of multipliers, which increases chip power consumption and greatly increases circuit complexity. In addition, the sampling accuracy depends on the accuracy of the division operation. Summary of the Invention

[0004] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide an average current estimation circuit and an estimation method thereof. The circuit structure is relatively simple, and the current signal is directly sampled to output the current average value within a certain period.

[0005] To achieve the above objectives, the present invention adopts the following technical solutions: an average current estimation circuit, characterized in that it includes a peak current sampling circuit, an integration circuit, a discharge current selection circuit, a discharge circuit, a duty cycle-error conversion circuit, and a voltage-current conversion circuit, wherein the input ends of the peak current sampling circuit and the integration circuit are both connected to an input current signal, the output of the peak current sampling circuit serves as the input signal of the discharge current selection circuit, the output of the discharge current selection circuit and the output of the integration circuit serve as the input signal of the discharge circuit, the output of the discharge circuit serves as the input signal of the duty cycle-error conversion circuit, the output of the duty cycle-error conversion circuit serves as the input signal of the voltage-current conversion circuit, and the voltage-current conversion circuit outputs the estimated average current;

[0006] The peak current sampling circuit is used to sample the peak value I of the input current signal in one cycle. pkand maintain it; including PMOS tubes PM1 to PM6, NMOS tubes NM1 to NM3, inverter INV3, inverter INV4, resistor R1 and capacitor C1; the gate of NMOS tube NM1 is interconnected with the gate of NMOS tube NM2 and the gate of NMOS tube NM3 and connected to the drain of NMOS tube NM1 as the input end of the peak current sampling circuit connected to the input current I_in, the source of NMOS tube NM1, the source of NMOS tube NM2 and the source of NMOS tube NM3 are all grounded, the drain of NMOS tube NM2 is connected to the gate of PMOS tube PM1 and the drain of PMOS tube PM2, the drain of PMOS tube PM1 is grounded, the source of PMOS tube PM1 is connected to the gate of PMOS tube PM2, the drain of PMOS tube PM3 and capacitor C 1 and the gate of the PMOS tube PM5 and the gate of the PMOS tube PM6, the source of the PMOS tube PM2, the source of the PMOS tube PM4, the source of the PMOS tube PM5, the source of the PMOS tube PM6 and the other end of the capacitor C1 are all connected to the power supply VCC, the source of the PMOS tube PM3 is connected to the power supply VCC through the resistor R1, the drain of the PMOS tube PM5 is connected to the drain of the PMOS tube PM4, the drain of the NMOS tube NM3 and the input end of the inverter INV4, the output end of the inverter INV4 is connected to the input end of the inverter INV3 and the gate of the PMOS tube PM4, the output of the inverter INV3 is connected to the gate of the PMOS tube PM3, the drain of the PMOS tube PM6 is the output end of the peak current sampling circuit, and the sampled peak current I is output. pk ;

[0007] The integration circuit is used to integrate the input current signal within one cycle to obtain the integrated voltage value VC, including PMOS tubes PMC1, PMC2 and PMC3, NMOS tube NMC1 and capacitor C CHG The source of the PMOS transistor PMC1 and the source of the PMOS transistor PMC2 are both connected to the power supply VCC, the gate and drain of the PMOS transistor PMC1 are connected to the gate of the PMOS transistor PMC2 and are connected to the input current I_in as the input end of the integration circuit, the drain of the PMOS transistor PMC2 is connected to the source of the PMOS transistor PMC3, and the gate of the PMOS transistor PMC3 is connected to the gate of the NMOS transistor NMC1 and is connected to the charging control signal S CHG , the source of NMOS tube NMC1 is connected to the capacitor C CHG One end of the capacitor is grounded, and the capacitor C CHG The other end is connected to the drain of the NMOS tube NMC1 and the drain of the PMOS tube PMC3 and serves as the output end of the integration circuit to output the integration voltage VC;

[0008] The discharge current selection circuit is used to select the peak current I output by the peak current sampling circuit. pkDischarge current I T ; including PMOS tubes PM_D1~PM_D19, NMOS tubes NM_D1~NM_D8, a resistor R_ref and an operational amplifier OP_D1; the positive terminal of the operational amplifier OP_D1 is connected to the reference voltage Vref, the negative terminal of the operational amplifier OP_D1 is connected to the source of the NMOS tube NM_D1 and one end of the resistor R_ref, the other end of the resistor R_ref is grounded, the gate of the NMOS tube NM_D1 is connected to the output of the operational amplifier OP_D1, the drain of the NMOS tube NM_D1 is connected to the drain and gate of the PMOS tube PM_D1 and is connected to the gates of the PMOS tubes PM_D2~PM_D13. Together, the sources of the PMOS tubes PM_D1 to PM_D13 are connected together and connected to the power supply VCC. The drain of the PMOS tube PM_D2 is connected to the gate of the PMOS tube PM_D14 and the drain of the NMOS tube NM_D2, with the connection point being S1. The drain of the PMOS tube PM_D3 is connected to the source of the PMOS tube PM_D14, and the drain of the PMOS tube PM_D4 is connected to the gate of the PMOS tube PM_D15 and the drain of the NMOS tube NM_D3, with the connection point being S2. The drain of the PMOS tube PM_D5 is connected to the gate of the PMOS tube P The source of PMOS tube PM_D15 and the drain of PMOS tube PM_D6 are connected to the gate of PMOS tube PM_D16 and the drain of NMOS tube NM_D4, with the connection point being S3; the drain of PMOS tube PM_D7 is connected to the source of PMOS tube PM_D16, the drain of PMOS tube PM_D8 is connected to the gate of PMOS tube PM_D17 and the drain of NMOS tube NM_D5, with the connection point being S4; the drain of PMOS tube PM_D9 is connected to the source of PMOS tube PM_D17, and the drain of PMOS tube PM_D10 is connected to the gate of PMOS tube PM_D17. The gate of the OS transistor PM_D18 and the drain of the NMOS transistor NM_D6 are connected at point S5; the drain of the PMOS transistor PM_D11 is connected to the source of the PMOS transistor PM_D18, the drain of the PMOS transistor PM_D12 is connected to the gate of the PMOS transistor PM_D19 and the drain of the NMOS transistor NM_D7, and the connection point is S6; the drain of the PMOS transistor PM_D13 is connected to the source of the PMOS transistor PM_D19, and the drains of the PMOS transistors PM_D14 to PM_D19 are connected together and serve as the discharge current selection circuit discharge current I T The output terminal of the NMOS tubes NM_D2 to NM_D8 are connected together, and the drain of the NMOS tube NM_D8 is connected to the peak current I output by the peak current sampling circuit. pk , the sources of NMOS tubes NM_D2~NM_D8 are all grounded;

[0009] The discharge circuit is used to use the discharge current IT output by the discharge current selection circuit to perform differential operation on the integrated voltage VC output by the integration circuit, and output the duty cycle signal D_IN. It includes a transmission gate composed of an NMOS tube MN_DSC and a PMOS tube MP_DSC, a comparator CMP_DSC, and a capacitor C DSC , PMOS tube M_ps1 and NMOS tube M_ds1 and NMOS tube M_ds2; the gate of the PMOS tube MP_DSC in the transmission gate is connected to the charging control signal S CHG The gate of the NMOS tube MN_DSC in the transmission gate is connected to the charging control signal S CHG The inverse signal of the transmission gate is connected to the integral voltage VC output by the integration circuit, and the output of the transmission gate is connected to the negative terminal of the comparator CMP_DSC and the capacitor C DSC One end of the NMOS tube M_ds2 is connected to the drain of the NMOS tube M_ds2. The gate of the NMOS tube M_ds2 is connected to the gate and drain of the NMOS tube M_ds1 and the drain of the PMOS tube M_ds1 and the drain of the PMOS tube M_ps1. The source of the NMOS tube M_ds1 and the source of the NMOS tube M_ds2 and the capacitor C DSC The other end of the comparator CMP_DSC is grounded, the positive end of the comparator CMP_DSC is connected to the reference voltage Vth, the output of the comparator CMP_DSC is connected to the gate of the PMOS tube M_ps1 and serves as the output end of the discharge circuit, outputting the duty cycle signal D_IN, and the source of the PMOS tube M_ps1 is connected to the discharge current I output by the discharge current selection circuit. T ;

[0010] The duty cycle-error conversion circuit is used to convert the duty cycle signal D_IN generated by the discharge circuit into an error signal representing the average current. It includes two circuits: a level conversion circuit and a low-pass filter. The level conversion circuit converts the input duty cycle signal D_IN into a square wave signal D_OUT. The low-pass filter performs low-pass filtering on the square wave signal D_OUT to obtain an approximate DC voltage V AV; Wherein: the level conversion circuit includes PMOS tubes PM_L1, PM_L2 and PM_L3, NMOS tubes NM_L1 and NM_L2 and inverters INV1 and INV2, the duty cycle signal D_IN is connected to the input end of the inverter INV1 and the drain of the PMOS tube PM_L1, the source of the PMOS tube PM_L1 is connected to the power supply VCC, the output of the inverter INV1 is connected to the input end of the inverter INV2 and the gate of the PMOS tube PM_L1, and the output of the inverter INV2 is connected to the gate of the PMOS tube PM_L2 and the gate of the NMOS transistor NM_L1. The drain of the NMOS transistor NM_L1 is interconnected with the drain of the PMOS transistor PM_L2 and is connected to the gate of the PMOS transistor PM_L3 and the gate of the NMOS transistor NM_L2. The source of the NMOS transistor NM_L1 and the source of the NMOS transistor NM_L2 are both grounded. The source of the PMOS transistor PM_L2 and the source of the PMOS transistor PM_L3 are both connected to the reference voltage Vref. The drain of the PMOS transistor PM_L3 and the drain of the NMOS transistor NM_L2 are interconnected and output a square wave signal D_OUT.The low-pass filter includes control switches φ1 to φ14, capacitors C00, capacitors C01 to C13, operational amplifiers OP_B1, OP_B2, and OP_B3. The square wave signal D_OUT output by the level conversion circuit is connected to one end of the control switch φ1, the other end of the control switch φ1 is connected to one end of the capacitor C00 and one end of the control switch φ2, the other end of the control switch φ2 is connected to one end of the capacitor C01 and one end of the control switch φ3, the other end of the control switch φ3 is connected to one end of the capacitor C02 and one end of the control switch φ4, the other end of the control switch φ4 is connected to one end of the capacitor C05 and one end of the control switch φ5, and the control switch φ5 The other end of the control switch φ6 is connected to one end of the capacitor C03 and one end of the control switch φ6, the other end of the control switch φ6 is connected to one end of the capacitor C04 and the positive end of the operational amplifier OP_B1, the negative end of the operational amplifier OP_B1 is connected to the other end of the capacitor C05 and the output end of the operational amplifier OP_B1 and one end of the control switch φ7, the other end of the control switch φ7 is connected to one end of the capacitor C09 and one end of the control switch φ8, the other end of the control switch φ8 is connected to one end of the capacitor C06 and one end of the control switch φ9, and the other end of the control switch φ9 is connected to the capacitor C One end of 08 is connected to one end of the control switch φ10, the other end of the control switch φ10 is connected to one end of the capacitor C07 and the positive end of the operational amplifier OP_B2, the negative end of the operational amplifier OP_B2 is connected to the other end of the capacitor C06 and the output end of the operational amplifier OP_B2 and one end of the control switch φ11, the other end of the control switch φ11 is connected to one end of the capacitor C10 and one end of the control switch φ12, the other end of the control switch φ12 is connected to one end of the capacitor C13 and one end of the control switch φ13, and the other end of the control switch φ13 is connected to the capacitor C1 1 and one end of the control switch φ14, the other end of the control switch φ14 is connected to one end of the capacitor C12 and the positive end of the operational amplifier OP_B3, the negative end of the operational amplifier OP_B3 is connected to the other end of the capacitor C13 and the output end of the operational amplifier OP_B3, the capacitor C00 and the other ends of the capacitors C01 to C04, the other ends of the capacitors C07 to C09, and the other ends of the capacitors C10 to C12 are all grounded, and the output end of the operational amplifier OP_B3 is also the output end of the low-pass filter, which outputs an approximately DC voltage V; AVThe control ends of the control switches φ1, φ3, φ5, φ7, φ9, φ11, and φ13 are connected to the clock signal, and the control ends of the control switches φ2, φ4, φ6, φ8, φ10, φ12, and φ14 are connected to the inverse signal of the clock signal. The control switches φ1 to φ6, capacitors C00, capacitors C01 to C05, and operational amplifier OP_B1 form a third-order Butterworth filter; the control switches φ7 to φ10, capacitors C06 to C09, and operational amplifier OP_B2 form a second-order Butterworth filter; the control switches φ11 to φ14, capacitors C10 to C13, and operational amplifier OP_B3 form another second-order Butterworth filter;

[0011] The voltage-current conversion circuit is used to convert the approximate DC voltage V output by the duty cycle-error conversion circuit into AV Converted to average current signal I AV , including operational amplifier OP_S1, PMOS tubes PM_S1~PM_S13, NMOS tube NM_S1 and resistor R; the positive terminal of operational amplifier OP_S1 is connected to V AVThe negative terminal of the operational amplifier OP_S1 is connected to the source of the NMOS tube NM_S1 and grounded through the resistor R. The output of the operational amplifier OP_S1 is connected to the gate of the NMOS tube NM_S1. The drain of the NMOS tube NM_S1 is connected to the drain and gate of the PMOS tube PM_S1 and is connected to the gate of the PMOS tube PM_S2, the gate of PM_S3, the gate of PM_S4, the gate of PM_S5, the gate of PM_S6 and the gate of PM_S7. The source of the PMOS tube PM_S1, the PMOS The sources of PM_S2, PM_S3, PM_S4, PM_S5, PM_S6, and PM_S7 are all connected to the power supply VCC. The drain of PMOS tube PM_S2 is connected to the source of PMOS tube PM_S8. The gate of PMOS tube PM_S8 is connected to the connection point S1 in the discharge current selection circuit. The drain of PMOS tube PM_S3 is connected to the source of PMOS tube PM_S9. The gate of PMOS tube PM_S9 is connected to the connection point S2 in the discharge current selection circuit. The drain of the PMOS transistor PM_S4 is connected to the source of the PMOS transistor PM_S10, the gate of the PMOS transistor PM_S10 is connected to the connection point S3 in the discharge current selection circuit, the drain of the PMOS transistor PM_S5 is connected to the source of the PMOS transistor PM_S11, the gate of the PMOS transistor PM_S11 is connected to the connection point S4 in the discharge current selection circuit, the drain of the PMOS transistor PM_S6 is connected to the source of the PMOS transistor PM_S12, and the gate of the PMOS transistor PM_S12 is connected to the connection point S5, the drain of the PMOS transistor PM_S7 is connected to the source of the PMOS transistor PM_S13, the gate of the PMOS transistor PM_S13 is connected to the connection point S6 in the discharge current selection circuit, the drain of the PMOS transistor PM_S8 is connected to the drain of the PMOS transistor PM_S9, the drain of the PMOS transistor PM_S10, the drain of the PMOS transistor PM_S11, the drain of the PMOS transistor PM_S12 and the drain of the PMOS transistor PM_S13 and serve as the output end of the voltage-current conversion circuit, outputting the average current signal I AV .

[0012] Furthermore, in the discharge current selection circuit, the size ratio of the PMOS transistor PM_D1, the PMOS transistor PM_D2, the PMOS transistor PM_D4, the PMOS transistor PM_D6, the PMOS transistor PM_D8, the PMOS transistor PM_D10 and the PM_D12 is 1:2:4:8:16:32.

[0013] Furthermore, in the discharge current selection circuit, the sizes of the PMOS tube PM_D3 and the PMOS tube PM_D1 are exactly the same; the sizes of the PMOS tube PM_D5 and the PMOS tube PM_D4 are exactly the same; the sizes of the MOS tube PM_D7 and the PMOS tube PM_D6 are exactly the same; the sizes of the PMOS tube PM_D9 and the PMOS tube PM_D8 are exactly the same; the sizes of the PMOS tube PM_D11 and the PMOS tube PM_D10 are exactly the same; and the sizes of the PMOS tube PM_D13 and the PMOS tube PM_D12 are exactly the same.

[0014] Furthermore, the charging control signal S in the integration circuit and the discharge circuit CHG It is an external signal generated by the switching power supply and is consistent with the switching signal of the switching power supply power device.

[0015] Furthermore, the capacitor C in the integration circuit CHG and the capacitor C in the discharge circuit DSC The capacitance values ​​of both are equal.

[0016] Furthermore, the reference voltage Vth in the discharge circuit has a value of 0<Vth<+50mV.

[0017] Furthermore, in the duty cycle-error conversion circuit, the frequency of the clock signal connected to the control terminals of the control switches φ1 to φ14 is greater than the frequency of the sampling period current signal of the peak current sampling circuit.

[0018] The average current estimation method of the average current estimation circuit comprises the following steps:

[0019] (1) The peak current sampling circuit samples the peak value I of the input current within a period T pk ;

[0020] (2) The integration circuit integrates the input current within a period T to obtain the integrated voltage VC;

[0021] (3) The discharge current selection circuit selects the peak current I pk The discharge current I T ;

[0022] (4) Using the discharge current I in the discharge circuit T Differentiate the integrated voltage value VC to obtain the duty cycle signal D_IN;

[0023] (5) The level conversion circuit in the duty cycle-error conversion circuit converts the duty cycle signal D_IN into a duty cycle square wave signal D_OUT, which is then filtered by a low-pass filter in the duty cycle-error conversion circuit and converted into a voltage signal. The voltage signal is proportionally restored by the voltage-current conversion circuit to obtain the average current.

[0024] Furthermore, in step (3), the discharge current I T The reference current generated by the reference voltage Vref through the operational amplifier OP_D1 and the resistor R_ref is amplified in different proportions and then added to the peak current I pk Produced after comparison;

[0025] Furthermore, the step (5) specifically includes the following steps:

[0026] (5.1) The high level of the duty cycle signal D_IN is the power supply voltage VCC. The duty cycle signal D_IN is level-converted to obtain the duty cycle square wave signal D_OUT, whose high level is the reference voltage Vref and low level is 0, where Vref < VCC.

[0027] (5.2) The duty cycle square wave signal D_OUT contains the information of the average current. After filtering the high-order components of the duty cycle square wave signal D_OUT through a low-pass filter, the output voltage V that approximately contains only the DC component is obtained. AV , the output voltage represents the information of the average current;

[0028] (5.3) The output voltage V AV Divide by the resistance R in the voltage-current conversion circuit and obtain the output current I after proportional mirroring AV , the output current I AV That is the average current in one current cycle.

[0029] Advantages and significant effects of the present invention: The present invention samples the peak value I of the input current within a period T through a peak current sampling circuit. pk At the same time, the input current within a period T is integrated by the integration circuit to obtain the integrated voltage value VC, and the discharge current selection circuit is used to select the peak current I pk Discharge current I T , in the discharge circuit, the discharge current I T The discharger differentiates the integrated voltage value VC to obtain a duty cycle signal D_IN. The level conversion circuit in the duty cycle-error conversion circuit converts the duty cycle signal D_IN into a duty cycle square wave signal D_OUT. The signal is then filtered by a low-pass filter in the duty cycle-error conversion circuit to obtain a DC voltage component. Finally, the voltage-current conversion circuit converts the signal into a current proportionally to obtain the average current within the period T.

[0030] The average current estimation circuit of the application directly processes the current signal, realizes the estimation of average current with less circuit cost, can get rid of the shackles of traditional multiplier, converts the average current into square wave signals with different duty cycles through a simple charge-discharge circuit, and restores the average current after high-order low-pass filtering. The whole scheme has simple circuit structure, wide application range, and the estimated average current can guarantee high precision. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a common inductance current waveform;

[0032] Figure 2 is an irregular current waveform;

[0033] Figure 3 is a system block diagram of the average current estimation circuit of the application;

[0034] Figure 3-1 is Figure 3 an embodiment of the current peak detection circuit;

[0035] Figure 3-2 is Figure 3 an embodiment of the discharge current selection circuit;

[0036] Figure 3-3 is Figure 3 an embodiment of the integration circuit;

[0037] Figure 3-4 is Figure 3 an embodiment of the discharge circuit;

[0038] Figure 3-5 is Figure 3 an embodiment of the level conversion circuit in the duty cycle-error conversion circuit;

[0039] Figure 3-6 is Figure 3 an embodiment of the low-pass filter in the duty cycle-error conversion circuit;

[0040] Figure 3-7 is Figure 3 an embodiment of the voltage-current conversion circuit;

[0041] Figure 4 is Figure 3-1 a key waveform schematic diagram of the current peak detection circuit;

[0042] Figure 5 is Figure 3-6 a relationship diagram of the amplitude-frequency characteristic of the Butterworth filter with the order of the low-pass filter;

[0043] Figure 6 The input and output waveforms are generated by low-pass filtering of the duty cycle square wave signal generated by the level conversion circuit;

[0044] Figure 7 It is a waveform diagram of the key nodes of the present invention;

[0045] Figure 8 This is a flow chart of the average current estimation method of the present invention. DETAILED DESCRIPTION

[0046] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be noted that the drawings are simplified and intuitive rather than using precise proportions or parameters, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0047] like Figure 3 The average current estimation circuit of the present invention includes a peak current sampling circuit, an integration circuit, a discharge current selection circuit, a discharge circuit, a duty cycle-error conversion circuit, and a voltage-current conversion circuit. The input ends of the peak current sampling circuit and the integration circuit are both connected to the input current signal I_in. The output Ipk of the peak current sampling circuit is the input signal of the discharge current selection circuit. The output I T The output VC of the integration circuit is used as the input signal of the discharge circuit. The output D_IN of the discharge circuit is the input signal of the duty cycle-error conversion circuit. The output V AV is the input signal of the voltage-current conversion circuit, and the voltage-current conversion circuit outputs the estimated average current I AV The input signals of the peak current sampling circuit and the integration circuit are both the periodic current signal I_in to be processed. Taking the switching power supply as an example, this periodic current signal can be simply understood as the inductor current. When the switch is turned on, the input voltage charges the inductor, and the inductor current rises linearly; when the switch is turned off, the inductor current drops linearly to its initial value.

[0048] See Figure 3-1 , an implementation method of peak current sampling in the present invention is given. When the current I_in changes upward, the gate voltage VG of PM2 is pulled down. When I_in reaches its maximum value, VG reaches its minimum value. At this time, the information of VG is stored on capacitor C1. If the current I_in begins to decrease, the charge stored on C1 can only be discharged through R1 and PM3. Since R1 is very large, the discharge speed is much slower than the speed at which the current I_in decreases. By comparing the currents of PM5 and NM3, PM3 is closed at the moment when the C1 capacitor just discharges, cutting off the discharge circuit, latching the maximum current information, and outputting the maximum current in this cycle, namely the peak current I, through PM6. pkIn this embodiment, the accuracy of current sampling can be set by the width-to-length ratio of NM3 to NM1.

[0049] Figure 4 Given Figure 3-1 The voltage or current waveform of the key nodes in the figure, where VG represents the gate voltage of PM3, VM is the voltage across the latch capacitor C1, I_x and I0 are the currents flowing through PM5 and NM3. As the current flowing through the NMOS transistor NM1 gradually increases, the voltage difference Vm across the capacitor C1 connected between the gate of the PMOS transistor PM2 and the power supply also gradually increases, and the gate potential VG of the PMOS transistor PM2 gradually decreases until the current flowing through the NMOS transistor NM1 reaches the maximum, the voltage difference Vm across the capacitor C1 also reaches the maximum value Vm_max, and the gate potential VG of the PMOS transistor PM2 reaches the minimum V L At this time, if the current flowing through the NMOS tube NM1 begins to decrease, the voltage difference across the capacitor C1 will not decrease immediately. It can only slowly release the charge through the larger resistor R1, approximately maintaining it near the Vm_max value, and then slowly decrease. The rate of decrease is determined by the time constant formed by R1 and C1. The turn-off time of PM3 is determined by current comparison. After PM3 is turned off, the charge on C1 remains approximately fixed, I_x also remains unchanged, and the output peak current I pk .

[0050] See Figure 3-2 , gives an implementation of the discharge current selection circuit in the present invention. The reference voltage Vref generates a reference current through the operational amplifier OP_D1 and the resistor R_ref. The reference current is amplified in different proportions between the current mirrors PM_D1~PM_D13 to generate multiple currents, each of which is proportional to the peak current I pk For comparison, in this embodiment, the amplification ratio of the reference current is 1:2:4:8:16:32, that is, the size ratio of PM_D1, PM_D2, PM_D4, PM_D6, PM_D8, PM_D10 and PM_D12 is 1:2:4:8:16:32, the size of PM_D3 and PM_D1 are exactly the same, the size of PM_D5 and PM_D4 are exactly the same, the size of PM_D7 and PM_D6 are exactly the same, the size of PM_D9 and PM_D8 are exactly the same, the size of PM_D11 and PM_D10 are exactly the same, and the size of PM_D13 and PM_D12 are exactly the same. The sizes of NM_D2 to NM_D8 are also exactly the same, completely mirroring the peak current I pk Taking one of the paths as an example, if the current of PM_D2 is less than the maximum peak current I pk , that is, less than the current flowing through NM_D2, the gate of PM_D4 is low, and PM_D4 is turned on. The current in this path increases to the final output current I TThe final output current I T The maximum value is close to the peak current I pk , as the discharge current I T . Discharge current I T Used to discharge the integration circuit Figure 3-4 Middle capacitor C DSC The charge stored on.

[0051] See Figure 3-3 , gives an implementation of the integration circuit of the present invention, the input current I_in is mirrored by the current mirrors PMC1 and PMC2, and then the charging control signal S is generated by the switching power supply and is consistent with the switching signal of the switching power supply. CHG Control capacitor C CHG Perform an integration operation to obtain the integrated voltage VC.

[0052] Figure 3-3 Another implementation scheme, the integral can also be Figure 3-3 The two integrating circuits with the same circuit structure as shown in the figure respectively perform integration operation synchronously through their own capacitors, divided into odd and even cycles. At this time, the charging control signal S CHG The switching signal of the switching power supply needs to pass through the frequency divider to generate odd and even cycles of SCHG1 and SCHG2 ( Figure 7 SCHG1 and SCHG2 in the .

[0053] See Figure 3-4 , gives an implementation of the discharge circuit in the present invention. The integrated voltage VC passes through the transmission gate composed of MP_DSC and MN_DSC, and the gate control signals of MP_DSC and MN_DSC are respectively connected to the charging control signal S CHG and S CHG The inverse signal is sampled to capacitor C DSC On the other hand, the current mirrors M_ds1 and M_ds2 mirror the discharge current I T , for capacitor C DSC To discharge, the comparator CMP_DSC compares C DSC When the voltage is discharged below Vth, M_ps1 is controlled to be turned off, the discharge ends, and a duty cycle signal D_IN is output, where Vth is a positive voltage greater than 0 and less than 50mV.

[0054] Similarly, corresponding to the double integration circuit, the discharge can also be Figure 3-4 The two discharge circuits shown have completely identical discharge circuit structures, and discharge operations are performed synchronously through their respective capacitors in odd and even cycles.

[0055] When the discharge current I TThe integral voltage VC accumulated on the capacitor C DSC After the charge accumulated on the capacitor C is discharged to 0, a square wave signal with a certain duty cycle is generated, and the high level of the duty cycle signal is converted from the power supply voltage to the reference voltage Vref, which needs to use a level conversion circuit. Figure 3-5 An embodiment of the level conversion circuit in the duty cycle-error conversion circuit is given. The power supply voltage of the inverter INV1 and the inverter INV2 is VCC, D_IN is the duty cycle signal, D_OUT is the duty cycle square wave signal, the high level of D_OUT is the reference voltage Vref, and the reference voltage Vref is less than the power supply voltage VCC.

[0056] The duty cycle square wave signal D_OUT contains the information of the average current, more precisely, the greater the duty cycle, the closer the discharge current I T is to the average current in the previous period, when the duty cycle is 100%, it means that the discharge current I T is exactly equal to the average current in the previous period; when the duty cycle is less than 100%, it means that the discharge current I T is greater than the average current in the previous period. By converting the duty cycle square wave signal D_OUT into a voltage signal, a voltage signal representing the average current can be obtained.

[0057] Referring to Figure 3-6 , an embodiment of the low-pass filter in the duty cycle-error conversion circuit in the application is given, which uses a 7th-order Butterworth filter to obtain the maximum roll-off speed of the passband to the stopband.

[0058] Referring to Figure 5 , generally speaking, the higher the order of the Butterworth filter, the faster the roll-off speed. Figure 3-6 The 7th-order Butterworth filter in the application is composed of a 3rd-order Butterworth filter and two 2nd-order Butterworth filters, and in order to obtain a relatively accurate bandwidth, the resistances are realized in the form of switched capacitors, for example, the switches controlled by φ1 and φ2 and C00 constitute an equivalent resistance, the impedance of the equivalent resistance is determined by the product of the frequency of the clock signal connected to φ1 and φ2 and the capacitance value of C00, and the equivalent resistances of other parts are similar. OP_B1, OP_B2 and OP_B3 are necessary components in the active filter, and the final output V AV contains the direct current component of Vin and almost 0 high frequency component. Figure 6 The output waveform of a square wave signal with a certain duty cycle after low-pass filtering is given.

[0059] In Figure 6In the example, a square wave signal with an amplitude of 2V and a duty cycle of 25% can be low-pass filtered to obtain an approximate DC voltage of 0.5V. In fact, ideally, the final output voltage should be equal to D*Vref, where D is the duty cycle.

[0060] Combine Figure 7 The whole operation process of the present invention is analyzed by the key node waveform diagram. Figure 7 The waveforms are shown in Figure 7 for the operation of the six cycles Cycle1 to Cycle6. As can be seen from the previous description, taking the first cycle as an example, the integrator circuit operates on the odd and even cycles in the first cycle Cycle1. Figure 3-3 The capacitor C in the circuit shown CHG The voltage Vcap1 is obtained by charging. In the first cycle Cycle1, the capacitor C CHG The voltage Vcap1 at both ends eventually reaches a maximum value of VC. At the same time, during the entire cycle Cycle1, the current peak sampling circuit obtains the maximum value Ipk of the current signal during the cycle, and selects the discharge current I according to the size of the Ipk value. T In the next cycle Cycle2, the capacitor C CHG The voltage VC on the Figure 3-4 The capacitor C DSC On, and through the discharge current I T C DSC Discharge, Figure 7 The dotted line indicates I AV is the theoretical average current. It can be seen from the figure that if the average current I AV Discharge is carried out, then at the end of the second cycle, that is, at time t3, the capacitor C DSC The voltage across the two ends should just drop to 0, and the peak current in a certain cycle must be greater than or equal to the average current. Therefore, if the discharge current I T The time required for discharge must be less than or equal to the entire cycle T, that is, the duration of t3-t1. Figure 7 Discharge current I T Discharge is carried out, and at time t2 Figure 3-3 The capacitor C DSC The voltage at both ends discharges to 0. When the voltage is discharged to 0, a falling edge signal is generated. A duty cycle square wave is generated during the entire cycle, namely the duty cycle signal D_IN. D_IN is converted into a duty cycle signal D_OUT with a high level as the reference voltage through the level conversion circuit. D_OUT reflects the discharge current I T With the average current I AV It should be noted that in the present invention, C CHGCapacitance and C DSC The capacitance values ​​are exactly the same.

[0061] From the definition of average current, we can get: I AV =(∫ i dt) / T, where i Represents the time-varying current within a period T, where T is the length of a period and the capacitance C The voltage at both ends eventually reaches a maximum value of VC, which can be expressed as: VC = (∫ i dt) / C , here C It means Figure 3-3 Capacitor C in the integral circuit CHG Capacitance or C DSC Capacitance. After the discharge current I T The capacitance is C Capacitor C CHG or C DSC The time required for both ends to discharge to 0 voltage is t1= C * VC / I T ; If I AV If the discharge is carried out, it will just discharge to 0 in the second cycle, then T= C * VC / I AV Therefore, the duty cycle can be expressed as: D = t1 / T = I AV / I T Therefore, the relative ratio of the average current to the discharge current can be expressed by the duty cycle. The duty cycle square wave signal D_OUT is low-pass filtered to obtain a DC component of V AV =D*Vref=(I AV *Vref) / I T , discharge current I T It is generated by dividing the reference voltage by the resistance and then proportionally amplifying it. Therefore, I T =K*Vref / R, where K is the magnification factor, which is a positive integer. So V AV = I AV *R / K.

[0062] V AV Already passed Figure 3-6 The low-pass filter shown is obtained, therefore, I AV =K*V AV / R, this transformation can be achieved through voltage-current conversion. Figure 3-7 , gives an implementation of the voltage-current conversion circuit of the present invention, first through V AV / R generates current through Figure 3-2 The discharge current selection circuit generates the switch control signals S1~S6 to controlFigure 3-7 The control switch is used to adjust the ratio of the current linear multiples. After adding them together, the output current is: K*V AV / R=I AV , at this time the output current is equal to I AV .

[0063] See Figure 8 The present invention also relates to a method for estimating an average current, the method comprising the following steps:

[0064] (1) The peak current sampling circuit samples the peak value I of the input current within a period T pk ;

[0065] (2) The integration circuit integrates the input current within a period T to obtain the integrated voltage VC;

[0066] (3) The discharge current selection circuit selects the peak current I pk The closest discharge current I T ;

[0067] (4) Using the discharge current I in the discharge circuit T Perform differential operation on the integrated voltage value VC to obtain the duty cycle signal D_IN;

[0068] (5) The level conversion circuit in the duty cycle-error conversion circuit converts the duty cycle signal D_IN into a duty cycle square wave signal D_OUT, which is then filtered by a low-pass filter in the duty cycle-error conversion circuit and converted into a voltage signal. The voltage signal is proportionally restored by the voltage-current conversion circuit to obtain the average current.

[0069] Furthermore, in step (3), the discharge current I T The reference current generated by the reference voltage Vref through the operational amplifier OP_D1 and the resistor R_ref is amplified in different proportions and then added to the peak current I pk Produced after comparison;

[0070] Furthermore, the step (5) specifically includes the following steps:

[0071] (5.1) The high level of the duty cycle signal D_IN is the power supply voltage VCC. The duty cycle signal D_IN is level-converted to obtain the duty cycle square wave signal D_OUT, whose high level is the reference voltage Vref and low level is 0, where Vref < VCC.

[0072] (5.2) The duty cycle square wave signal D_OUT contains the information of the average current. After filtering the high-order components of the duty cycle square wave signal D_OUT through a low-pass filter, the output voltage V that approximately contains only the DC component is obtained. AV, the output voltage represents the information of the average current, and the low-pass filter is a high-order Butterworth filter.

[0073] (5.3) The output voltage V AV Divide by the resistance R in the voltage-current conversion circuit and obtain the output current I after proportional mirroring AV , the output current I AV That is the average current in one current cycle.

[0074] The implementation methods described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent replacements and improvements made within the above-mentioned implementation spirit and principles should be included in the scope of protection of the technical solution of the present invention.

Claims

1. An average current estimation circuit, characterized in that: The invention comprises a peak current sampling circuit, an integration circuit, a discharge current selection circuit, a discharge circuit, a duty cycle-error conversion circuit and a voltage-current conversion circuit. The input ends of the peak current sampling circuit and the integration circuit are both connected to the input current signal. The output of the peak current sampling circuit is the input signal of the discharge current selection circuit. The output of the discharge current selection circuit and the output of the integration circuit are jointly used as the input signal of the discharge circuit. The output of the discharge circuit is the input signal of the duty cycle-error conversion circuit. The output of the duty cycle-error conversion circuit is the input signal of the voltage-current conversion circuit. The voltage-current conversion circuit outputs the estimated average current. The peak current sampling circuit is used to sample the peak value I of the input current signal in one cycle. pk and maintain it; including PMOS tubes PM1 to PM6, NMOS tubes NM1 to NM3, inverter INV3, inverter INV4, resistor R1 and capacitor C1; the gate of NMOS tube NM1 is interconnected with the gate of NMOS tube NM2 and the gate of NMOS tube NM3 and connected to the drain of NMOS tube NM1 as the input end of the peak current sampling circuit connected to the input current I_in, the source of NMOS tube NM1, the source of NMOS tube NM2 and the source of NMOS tube NM3 are all grounded, the drain of NMOS tube NM2 is connected to the gate of PMOS tube PM1 and the drain of PMOS tube PM2, the drain of PMOS tube PM1 is grounded, the source of PMOS tube PM1 is connected to the gate of PMOS tube PM2, the drain of PMOS tube PM3 and capacitor C 1 and the gate of the PMOS tube PM5 and the gate of the PMOS tube PM6, the source of the PMOS tube PM2, the source of the PMOS tube PM4, the source of the PMOS tube PM5, the source of the PMOS tube PM6 and the other end of the capacitor C1 are all connected to the power supply VCC, the source of the PMOS tube PM3 is connected to the power supply VCC through the resistor R1, the drain of the PMOS tube PM5 is connected to the drain of the PMOS tube PM4, the drain of the NMOS tube NM3 and the input end of the inverter INV4, the output end of the inverter INV4 is connected to the input end of the inverter INV3 and the gate of the PMOS tube PM4, the output of the inverter INV3 is connected to the gate of the PMOS tube PM3, the drain of the PMOS tube PM6 is the output end of the peak current sampling circuit, and the sampled peak current I is output. pk ; The integration circuit is used to integrate the input current signal within one cycle to obtain the integrated voltage value VC, including PMOS tubes PMC1, PMC2 and PMC3, NMOS tube NMC1 and capacitor C CHG The source of the PMOS transistor PMC1 and the source of the PMOS transistor PMC2 are both connected to the power supply VCC, the gate and drain of the PMOS transistor PMC1 are connected to the gate of the PMOS transistor PMC2 and are connected to the input current I_in as the input end of the integration circuit, the drain of the PMOS transistor PMC2 is connected to the source of the PMOS transistor PMC3, and the gate of the PMOS transistor PMC3 is connected to the gate of the NMOS transistor NMC1 and is connected to the charging control signal S CHG , the source of NMOS tube NMC1 is connected to the capacitor C CHG One end of the capacitor is grounded, and the capacitor C CHG The other end is connected to the drain of the NMOS tube NMC1 and the drain of the PMOS tube PMC3 and serves as the output end of the integration circuit to output the integration voltage VC; The discharge current selection circuit is used to select the peak current I output by the peak current sampling circuit. pk Discharge current I T ; including PMOS tubes PM_D1~PM_D19, NMOS tubes NM_D1~NM_D8, a resistor R_ref and an operational amplifier OP_D1; the positive terminal of the operational amplifier OP_D1 is connected to the reference voltage Vref, the negative terminal of the operational amplifier OP_D1 is connected to the source of the NMOS tube NM_D1 and one end of the resistor R_ref, the other end of the resistor R_ref is grounded, the gate of the NMOS tube NM_D1 is connected to the output of the operational amplifier OP_D1, the drain of the NMOS tube NM_D1 is connected to the drain and gate of the PMOS tube PM_D1 and is connected to the gates of the PMOS tubes PM_D2~PM_D13. Together, the sources of the PMOS tubes PM_D1 to PM_D13 are connected together and connected to the power supply VCC. The drain of the PMOS tube PM_D2 is connected to the gate of the PMOS tube PM_D14 and the drain of the NMOS tube NM_D2, with the connection point being S1. The drain of the PMOS tube PM_D3 is connected to the source of the PMOS tube PM_D14, and the drain of the PMOS tube PM_D4 is connected to the gate of the PMOS tube PM_D15 and the drain of the NMOS tube NM_D3, with the connection point being S2. The drain of the PMOS tube PM_D5 is connected to the gate of the PMOS tube P The source of PMOS tube PM_D15 and the drain of PMOS tube PM_D6 are connected to the gate of PMOS tube PM_D16 and the drain of NMOS tube NM_D4, with the connection point being S3; the drain of PMOS tube PM_D7 is connected to the source of PMOS tube PM_D16, the drain of PMOS tube PM_D8 is connected to the gate of PMOS tube PM_D17 and the drain of NMOS tube NM_D5, with the connection point being S4; the drain of PMOS tube PM_D9 is connected to the source of PMOS tube PM_D17, and the drain of PMOS tube PM_D10 is connected to the gate of PMOS tube PM_D17. The gate of the OS transistor PM_D18 and the drain of the NMOS transistor NM_D6 are connected at point S5; the drain of the PMOS transistor PM_D11 is connected to the source of the PMOS transistor PM_D18, the drain of the PMOS transistor PM_D12 is connected to the gate of the PMOS transistor PM_D19 and the drain of the NMOS transistor NM_D7, and the connection point is S6; the drain of the PMOS transistor PM_D13 is connected to the source of the PMOS transistor PM_D19, and the drains of the PMOS transistors PM_D14 to PM_D19 are connected together and serve as the discharge current selection circuit discharge current I T The gates of NMOS tubes NM_D2 to NM_D8 are connected together, and the drain of NMOS tube NM_D8 is connected to the peak current I output by the peak current sampling circuit. pk , the sources of NMOS tubes NM_D2~NM_D8 are all grounded; The discharge circuit is used to use the discharge current IT output by the discharge current selection circuit to perform differential operation on the integrated voltage VC output by the integration circuit, and output the duty cycle signal D_IN. It includes a transmission gate composed of an NMOS tube MN_DSC and a PMOS tube MP_DSC, a comparator CMP_DSC, and a capacitor C DSC , PMOS tube M_ps1 and NMOS tube M_ds1 and NMOS tube M_ds2; the gate of the PMOS tube MP_DSC in the transmission gate is connected to the charging control signal S CHG The gate of the NMOS tube MN_DSC in the transmission gate is connected to the charging control signal S CHG The inverse signal of the transmission gate is connected to the integral voltage VC output by the integration circuit, and the output of the transmission gate is connected to the negative terminal of the comparator CMP_DSC and the capacitor C DSC One end of the NMOS tube M_ds2 is connected to the drain of the NMOS tube M_ds2. The gate of the NMOS tube M_ds2 is connected to the gate and drain of the NMOS tube M_ds1 and the drain of the PMOS tube M_ds1 and the drain of the PMOS tube M_ps1. The source of the NMOS tube M_ds1 and the source of the NMOS tube M_ds2 and the capacitor C DSC The other end of the comparator CMP_DSC is grounded, the positive end of the comparator CMP_DSC is connected to the reference voltage Vth, the output of the comparator CMP_DSC is connected to the gate of the PMOS tube M_ps1 and serves as the output end of the discharge circuit, outputting the duty cycle signal D_IN, and the source of the PMOS tube M_ps1 is connected to the discharge current I output by the discharge current selection circuit. T ; The duty cycle-error conversion circuit is used to convert the duty cycle signal D_IN generated by the discharge circuit into an error signal representing the average current. It includes two circuits: a level conversion circuit and a low-pass filter. The level conversion circuit converts the input duty cycle signal D_IN into a square wave signal D_OUT. The low-pass filter performs low-pass filtering on the square wave signal D_OUT to obtain an approximate DC voltage V AV ; Wherein: the level conversion circuit includes PMOS tubes PM_L1, PM_L2 and PM_L3, NMOS tubes NM_L1 and NM_L2 and inverters INV1 and INV2, the duty cycle signal D_IN is connected to the input end of the inverter INV1 and the drain of the PMOS tube PM_L1, the source of the PMOS tube PM_L1 is connected to the power supply VCC, the output of the inverter INV1 is connected to the input end of the inverter INV2 and the gate of the PMOS tube PM_L1, and the output of the inverter INV2 is connected to the gate of the PMOS tube PM_L2 and the gate of the NMOS transistor NM_L1. The drain of the NMOS transistor NM_L1 is interconnected with the drain of the PMOS transistor PM_L2 and is connected to the gate of the PMOS transistor PM_L3 and the gate of the NMOS transistor NM_L2. The source of the NMOS transistor NM_L1 and the source of the NMOS transistor NM_L2 are both grounded. The source of the PMOS transistor PM_L2 and the source of the PMOS transistor PM_L3 are both connected to the reference voltage Vref. The drain of the PMOS transistor PM_L3 and the drain of the NMOS transistor NM_L2 are interconnected and output a square wave signal D_OUT.The low-pass filter includes control switches φ1 to φ14, capacitors C00, capacitors C01 to C13, operational amplifiers OP_B1, OP_B2, and OP_B3. The square wave signal D_OUT output by the level conversion circuit is connected to one end of the control switch φ1, the other end of the control switch φ1 is connected to one end of the capacitor C00 and one end of the control switch φ2, the other end of the control switch φ2 is connected to one end of the capacitor C01 and one end of the control switch φ3, the other end of the control switch φ3 is connected to one end of the capacitor C02 and one end of the control switch φ4, the other end of the control switch φ4 is connected to one end of the capacitor C05 and one end of the control switch φ5, and the control switch φ5 The other end of the control switch φ6 is connected to one end of the capacitor C03 and one end of the control switch φ6, the other end of the control switch φ6 is connected to one end of the capacitor C04 and the positive end of the operational amplifier OP_B1, the negative end of the operational amplifier OP_B1 is connected to the other end of the capacitor C05 and the output end of the operational amplifier OP_B1 and one end of the control switch φ7, the other end of the control switch φ7 is connected to one end of the capacitor C09 and one end of the control switch φ8, the other end of the control switch φ8 is connected to one end of the capacitor C06 and one end of the control switch φ9, and the other end of the control switch φ9 is connected to the capacitor C One end of 08 is connected to one end of the control switch φ10, the other end of the control switch φ10 is connected to one end of the capacitor C07 and the positive end of the operational amplifier OP_B2, the negative end of the operational amplifier OP_B2 is connected to the other end of the capacitor C06 and the output end of the operational amplifier OP_B2 and one end of the control switch φ11, the other end of the control switch φ11 is connected to one end of the capacitor C10 and one end of the control switch φ12, the other end of the control switch φ12 is connected to one end of the capacitor C13 and one end of the control switch φ13, and the other end of the control switch φ13 is connected to the capacitor C1 1 and one end of the control switch φ14, the other end of the control switch φ14 is connected to one end of the capacitor C12 and the positive end of the operational amplifier OP_B3, the negative end of the operational amplifier OP_B3 is connected to the other end of the capacitor C13 and the output end of the operational amplifier OP_B3, the capacitor C00 and the other ends of the capacitors C01 to C04, the other ends of the capacitors C07 to C09, and the other ends of the capacitors C10 to C12 are all grounded, and the output end of the operational amplifier OP_B3 is also the output end of the low-pass filter, which outputs an approximately DC voltage V; AV The control ends of the control switches φ1, φ3, φ5, φ7, φ9, φ11, and φ13 are connected to the clock signal, and the control ends of the control switches φ2, φ4, φ6, φ8, φ10, φ12, and φ14 are connected to the inverse signal of the clock signal. The control switches φ1 to φ6, capacitors C00, capacitors C01 to C05, and operational amplifier OP_B1 form a third-order Butterworth filter; the control switches φ7 to φ10, capacitors C06 to C09, and operational amplifier OP_B2 form a second-order Butterworth filter; the control switches φ11 to φ14, capacitors C10 to C13, and operational amplifier OP_B3 form another second-order Butterworth filter; The voltage-current conversion circuit is used to convert the approximate DC voltage V output by the duty cycle-error conversion circuit into AV Converted to average current signal I AV , including operational amplifier OP_S1, PMOS tubes PM_S1~PM_S13, NMOS tube NM_S1 and resistor R; the positive terminal of operational amplifier OP_S1 is connected to V AV The negative terminal of the operational amplifier OP_S1 is connected to the source of the NMOS tube NM_S1 and grounded through the resistor R. The output of the operational amplifier OP_S1 is connected to the gate of the NMOS tube NM_S1. The drain of the NMOS tube NM_S1 is connected to the drain and gate of the PMOS tube PM_S1 and is connected to the gate of the PMOS tube PM_S2, the gate of PM_S3, the gate of PM_S4, the gate of PM_S5, the gate of PM_S6 and the gate of PM_S7. The source of the PMOS tube PM_S1, the PMOS The sources of PM_S2, PM_S3, PM_S4, PM_S5, PM_S6, and PM_S7 are all connected to the power supply VCC. The drain of PMOS tube PM_S2 is connected to the source of PMOS tube PM_S8. The gate of PMOS tube PM_S8 is connected to the connection point S1 in the discharge current selection circuit. The drain of PMOS tube PM_S3 is connected to the source of PMOS tube PM_S9. The gate of PMOS tube PM_S9 is connected to the connection point S2 in the discharge current selection circuit. The drain of the PMOS transistor PM_S4 is connected to the source of the PMOS transistor PM_S10, the gate of the PMOS transistor PM_S10 is connected to the connection point S3 in the discharge current selection circuit, the drain of the PMOS transistor PM_S5 is connected to the source of the PMOS transistor PM_S11, the gate of the PMOS transistor PM_S11 is connected to the connection point S4 in the discharge current selection circuit, the drain of the PMOS transistor PM_S6 is connected to the source of the PMOS transistor PM_S12, and the gate of the PMOS transistor PM_S12 is connected to the connection point S5, the drain of the PMOS transistor PM_S7 is connected to the source of the PMOS transistor PM_S13, the gate of the PMOS transistor PM_S13 is connected to the connection point S6 in the discharge current selection circuit, the drain of the PMOS transistor PM_S8 is connected to the drain of the PMOS transistor PM_S9, the drain of the PMOS transistor PM_S10, the drain of the PMOS transistor PM_S11, the drain of the PMOS transistor PM_S12 and the drain of the PMOS transistor PM_S13 and serve as the output end of the voltage-current conversion circuit, outputting the average current signal I AV .

2. The average current estimation circuit according to claim 1, wherein: In the discharge current selection circuit, the sizes of the PMOS tube PM_D3 and the PMOS tube PM_D1 are exactly the same; the sizes of the PMOS tube PM_D5 and the PMOS tube PM_D4 are exactly the same; the sizes of the MOS tube PM_D7 and the PMOS tube PM_D6 are exactly the same; the sizes of the PMOS tube PM_D9 and the PMOS tube PM_D8 are exactly the same; the sizes of the PMOS tube PM_D11 and the PMOS tube PM_D10 are exactly the same; and the sizes of the PMOS tube PM_D13 and the PMOS tube PM_D12 are exactly the same.

3. The average current estimation circuit according to claim 1, wherein: The charging control signal S in the integration circuit and the discharge circuit CHG It is an external signal generated by the switching power supply and is consistent with the switching signal of the switching power supply power device.

4. The average current estimation circuit according to claim 1, wherein: The capacitor C in the integrating circuit CHG and the capacitor C in the discharge circuit DSC The capacitance values ​​of both are equal.

5. The average current estimation circuit according to claim 1, wherein: The reference voltage Vth in the discharge circuit has a value of 0<Vth<+50mV.

6. The average current estimation circuit according to claim 1, wherein: In the duty cycle-error conversion circuit, the frequency of the clock signal connected to the control terminals of the control switches φ1 to φ14 is greater than the frequency of the sampling period current signal of the peak current sampling circuit.

7. The average current estimation method according to the average current estimation circuit of claim 1, characterized in that: The following steps are involved: (1) The peak current sampling circuit samples the peak value I of the input current within a period T pk ; (2) The integration circuit integrates the input current within a period T to obtain the integrated voltage VC; (3) The discharge current selection circuit selects the peak current I pk The discharge current I T ; (4) Using the discharge current I in the discharge circuit T Differentiate the integrated voltage value VC to obtain the duty cycle signal D_IN; (5) The level conversion circuit in the duty cycle-error conversion circuit converts the duty cycle signal D_IN into a duty cycle square wave signal D_OUT, which is then filtered by a low-pass filter in the duty cycle-error conversion circuit and converted into a voltage signal. The voltage signal is proportionally restored by the voltage-current conversion circuit to obtain the average current.

8. The average current estimation method according to the average current estimation circuit of claim 7, characterized in that: In step (3), the discharge current I T The reference current generated by the reference voltage Vref through the operational amplifier OP_D1 and the resistor R_ref is amplified in different proportions and then added to the peak current I pk Produced after comparison.

9. The average current estimation method according to the average current estimation circuit of claim 7, characterized in that: The step (5) specifically includes the following steps: (5.1) The high level of the duty cycle signal D_IN is the power supply voltage VCC. The duty cycle signal D_IN is level-converted to obtain the duty cycle square wave signal D_OUT, whose high level is the reference voltage Vref and low level is 0, where Vref < VCC. (5.2) The duty cycle square wave signal D_OUT contains the information of the average current. After filtering the high-order components of the duty cycle square wave signal D_OUT through a low-pass filter, the output voltage V that approximately contains only the DC component is obtained. AV , the output voltage represents the information of the average current; (5.3) The output voltage V AV Divide by the resistance R in the voltage-current conversion circuit and obtain the output current I after proportional mirroring AV , the output current I AV That is the average current in one current cycle.

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