Signal testing methods, systems, equipment, storage media, and software products for chips.
By acquiring and testing the input signal timing parameters of the chip and generating a result table, the problem of low chip signal testing efficiency is solved, batch signal testing and circuit optimization are realized, and testing efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-10
- Publication Date
- 2026-05-26
AI Technical Summary
In existing technologies, the signal testing efficiency of chips is relatively low, especially in simulation testing, where different test circuits need to be manually built, resulting in low testing efficiency.
By acquiring all input signals from the chip, the time parameters of each input signal are obtained, and a result table is generated. The time parameters of the input signals are then tested using a test circuit, including extracting parasitic resistance-capacitance network circuits in the circuit unit, generating and using the test circuit to perform signal testing.
This enables batch acquisition and testing of chip input signals, improving the design efficiency of circuit designers, optimizing circuits, and thus improving chip testing efficiency.
Smart Images
Figure CN114371387B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to, but is not limited to, the field of semiconductor technology, and in particular to a signal testing method, system, device, storage medium, and program product for a chip. Background Technology
[0002] With the continuous development of semiconductor technology, the functions of integrated circuits (ICs) in chips are becoming increasingly complex, and their scale is also growing larger. To ensure that ICs meet design requirements, simulation testing is an essential step. Simulation testing typically includes pre-simulation testing and post-simulation testing. Pre-simulation testing targets the Register Transfer Level (RTL) and is used to analyze the correctness of the IC's logic relationships. Post-simulation testing involves the IC's gate delay parameters and the parasitic capacitances of various electronic components to determine whether the IC's timing is correct.
[0003] However, in simulation testing, the chip has multiple input signals, and each input signal usually requires a different test circuit to be built manually, resulting in low testing efficiency. Summary of the Invention
[0004] In view of the above problems, this disclosure provides a signal testing method, system, device, storage medium, and program product for chips to improve chip testing efficiency.
[0005] A first aspect of this disclosure provides a signal testing method for a chip, the chip having multiple input signals, the signal testing method comprising: acquiring all the input signals of the chip; obtaining a time parameter for each input signal; and generating a result table of the time parameters of all the input signals.
[0006] The signal testing method for chips provided in this disclosure has at least the following advantages:
[0007] In the chip signal testing method of this disclosure embodiment, by acquiring all input signals of the chip and obtaining the rise time and fall time of each input signal, a result table of all input signals is obtained, realizing the batch acquisition and testing of chip input signals, thereby improving the design efficiency of circuit designers, facilitating the design of test circuits, and improving testing efficiency.
[0008] In the signal testing method for the chip described above, each input signal corresponds to a set of circuit units, and each set of circuit units includes a driving circuit and at least one load circuit.
[0009] In the signal testing method for the chip described above, obtaining the time parameter of each input signal includes: extracting the parasitic resistance-capacitance network circuit in a set of circuit units corresponding to each input signal; generating a test circuit for each input signal based on the corresponding circuit unit and the parasitic resistance-capacitance network circuit; and testing the corresponding input signal using the test circuit to obtain the time parameter of the input signal.
[0010] In the signal testing method for the chip described above, generating a test circuit for each input signal based on the corresponding circuit unit and the parasitic resistance-capacitance network circuit includes: determining a first replacement unit corresponding to the driving circuit; determining a second replacement unit corresponding to each load circuit; and generating the test circuit based on the first replacement unit, the at least one second replacement unit, and the parasitic resistance-capacitance network circuit.
[0011] In the signal testing method for the chip described above, determining the first replacement unit corresponding to the driving circuit includes: extracting a first-level driving unit in the driving circuit, the first-level driving unit including a first-level logic unit in the driving circuit; and determining the first-level logic unit in the driving circuit as the first replacement unit.
[0012] In the signal testing method for the chip described above, the first-stage logic unit in the driving circuit is an inverter.
[0013] In the signal testing method for the chip described above, determining the second replacement unit corresponding to any one of the at least one load circuit includes: extracting a first-level load unit from the load circuit, wherein the first-level load unit includes a first-level logic unit in the load circuit; and determining the first-level logic unit in the load circuit as the second replacement unit.
[0014] In the signal testing method for the chip described above, the first-level logic unit in the load circuit is a standard logic unit, including inverters, AND gates, OR gates, NOT gates, NAND gates, and NOR gates.
[0015] In the signal testing method for the chip described above, generating the test circuit based on the first replacement unit, the at least one second replacement unit, and the parasitic resistance-capacitance network circuit includes: connecting the first replacement unit and the parasitic resistance-capacitance network circuit through a first port; and connecting the at least one second replacement unit and the parasitic resistance-capacitance network circuit through at least one second port to obtain the test circuit.
[0016] In the signal testing method for the chip described above, the test circuit is used to test the corresponding input signal to obtain the time parameter of the input signal, which includes: inputting the input signal to the test circuit through the input terminal of the first replacement unit; obtaining at least one result signal from the input terminal of at least one second replacement unit of the test circuit; and determining the time parameter of the input signal based on the at least one result signal.
[0017] In the signal testing method for the chip described above, determining the time parameter of the input signal based on the at least one result signal includes: acquiring the time parameter of each result signal; and determining the maximum value among the time parameters of the at least one result signal as the time parameter of the input signal.
[0018] In the signal testing method for the chip described above, extracting the parasitic resistance-capacitance network circuit from a set of circuit units corresponding to each input signal includes: determining a standard parasitic parameter format file; and establishing the parasitic resistance-capacitance network circuit according to the standard parasitic parameter format file.
[0019] A second aspect of this disclosure provides a signal testing system for a chip, the chip having multiple input signals. The signal testing system includes: a first acquisition module for acquiring all the input signals of the chip; a second acquisition module for acquiring time parameters of each input signal; and a processing module for generating a result table from the time parameters of all the input signals.
[0020] The signal testing system for chips provided in this disclosure has at least the following advantages:
[0021] In the chip signal testing system of this embodiment, all input signals are acquired by a first acquisition module, and the timing parameters of each input signal are obtained by a second acquisition module. The processing module generates a result table from the timing parameters of each input signal, thereby realizing batch testing of the chip's input signals, improving the design efficiency of circuit designers, facilitating the design of test circuits, and improving the chip's testing efficiency.
[0022] In the signal testing system for the chip described above, each input signal corresponds to a set of circuit units, and each set of circuit units includes a driving circuit and at least one load circuit.
[0023] The signal testing system for the chip described above, wherein the second acquisition module includes: a first acquisition submodule, configured to extract the parasitic resistance-capacitance network circuit in a set of circuit units corresponding to each input signal; a generation module, configured to generate a test circuit for each input signal based on the corresponding circuit unit and the parasitic resistance-capacitance network circuit; and a testing module, configured to test the corresponding input signal using the test circuit to obtain the time parameter of the input signal.
[0024] A third aspect of this disclosure provides an apparatus comprising: at least one processor and a memory, the memory storing computer-executable instructions; the at least one processor executing the computer-executable instructions stored in the memory, causing the at least one processor to perform the signal testing method described above. The apparatus in this disclosure is used to perform the signal testing method described above, and therefore possesses at least the advantages of the signal testing method described above; specific effects are as described above and will not be repeated here.
[0025] A fourth aspect of this disclosure provides a storage medium storing computer-executable instructions, which, when executed by a processor, implement the signal testing method described above. The storage medium in this disclosure implements the signal testing method described above, and therefore possesses at least the advantages of the aforementioned signal testing method; specific effects are described above and will not be repeated here.
[0026] A fifth aspect of this disclosure provides a program product including a computer program that, when executed by a processor, implements the signal testing method described above. The program product in this disclosure implements the signal testing method described above, and therefore possesses at least the advantages of the aforementioned signal testing method; specific effects are as described above and will not be repeated here. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a flowchart of the signal testing method in the embodiments of this disclosure;
[0029] Figure 2 This is a schematic diagram of an input signal in an embodiment of this disclosure;
[0030] Figure 3 This is another schematic diagram of the input signal in an embodiment of this disclosure;
[0031] Figure 4 This is a schematic diagram of the parasitic resistance-capacitance network circuit in an embodiment of this disclosure;
[0032] Figure 5 This is a schematic diagram of the test circuit in an embodiment of this disclosure;
[0033] Figure 6 This is a schematic diagram of a result signal in an embodiment of this disclosure;
[0034] Figure 7 This is a schematic diagram of another result signal in an embodiment of this disclosure.
[0035] Explanation of reference numerals in the attached figures:
[0036] 10-Drive circuit;
[0037] 11 - The first-level logic unit in the driver circuit;
[0038] 20-Load circuit;
[0039] 21 - The first-level logic unit in the load circuit;
[0040] 30- Parasitic resistance-capacitance network circuit;
[0041] 40 - First Port;
[0042] 50 - Second port. Detailed Implementation
[0043] To address the issue of low testing efficiency for chips, the signal testing method provided in this disclosure acquires all input signals of the chip and obtains the time parameters of each input signal, resulting in a table of time parameters for all input signals. This enables batch acquisition and testing of chip input signals, improving the design efficiency of circuit designers and facilitating the design of test circuits, thereby enhancing chip testing efficiency.
[0044] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0045] A chip includes an integrated circuit (IC) packaged inside, and pins electrically connected to the IC, through which various signals are input and output. For different input signals, the transmission path within the IC and the pins used for input and output can differ. The chip's response speed can be evaluated by testing the time parameters of its input signals, such as rise time, fall time, positive duty cycle, negative duty cycle, period, and frequency. This disclosure uses rise time and fall time as examples for illustration.
[0046] refer to Figure 1 , Figure 1 This is a flowchart of a signal testing method according to an embodiment of the present disclosure. The signal testing method includes the following steps:
[0047] Step S100: Acquire all input signals of the chip.
[0048] The chip includes multiple input signals, all of which are acquired via a script. These input signals can be distinguished by different signal names, such as signal_1, signal_2, signal_3, etc. Each input signal has different input and output pins. Input pins refer to the pins where the input signal is input into the chip, while output pins refer to the pins where the input signal is output from the chip.
[0049] Each input signal can be a square wave signal, with an ideal waveform as shown below. Figure 2 As shown, the waveform has very steep rising and falling edges; the time from low to high and from high to low is both zero. Input signals often struggle to achieve ideal waveforms because they are typically triggered by the rising edge. For example... Figure 3 As shown, the actual waveform takes less than or equal to 10 picoseconds to rise from 10% of the high level to 90% of the high level, in order to make the actual waveform close to the ideal waveform and reduce the influence of the waveform of the input signal itself on the test results. Of course, the type of input signal in this embodiment is not limited; for example, the input signal can also be a slowly varying AC signal.
[0050] Step S200: Obtain the time parameters for each input signal.
[0051] The circuits that each input signal passes through can be different. For example, each input signal corresponds to a set of circuit units, and each set of circuit units includes a driver circuit 10 and at least one load circuit 20. The input signal is transmitted from the corresponding driver circuit 10 to the load circuit 20 through internal circuitry. Due to the influence of pull-up resistors, pull-down resistors, parasitic resistances, and capacitances in each set of circuit units, the driving capability of each set of circuit units differs, resulting in changes in the waveform of the input signal.
[0052] Specifically, the rising edge of the input signal waveform rises smoothly, and the falling edge falls smoothly, resulting in a significant delay in the input signal. By acquiring the time parameters of each input signal, the delay of the input signal can be evaluated, and thus the response speed of the chip can be assessed. The time parameters can include at least one of the rise time and fall time.
[0053] Rise time can refer to the time it takes for a signal to rise from 10% to 90% of its high level, or from 20% to 80% of its high level. Fall time refers to the time it takes for a signal to fall from 90% to 10% of its high level, or from 80% to 20% of its high level. In this embodiment, the example of a rise time of 10% to 90% and a fall time of 90% to 10% is used for illustration.
[0054] Step S300: Generate a result table of time parameters for all input signals.
[0055] For example, a result table is generated from the rise and fall times of all input signals. The result table includes the signal name, rise time (tR), and fall time (tF) for each input signal. Of course, the result table can also include other information, such as the start pin, end pin, force node, measure node, and first-stage logic unit (Driven) in the driver circuit for each input signal.
[0056] After generating the result table, display the result table, or send the result table to a preset device for storage or display for circuit designers' reference. If the rise time and fall time of the input signal are too large and affect the circuit performance, the drive circuit will be redesigned.
[0057] For example, the results table summarizes all the information for each input signal. Referring to Table 1, the rise time of the input signal signal_1 is 2.065ns, the fall time is 1.856ns, the input pin is IN_1, the output pin is OUT_1, the first-level driver unit is DDINVF8, the input terminal is GATE_IN_1, and the output terminal is GATE_OUT_1.
[0058] The rise time of the input signal signal_2 is 1.873ns, the fall time is 1.735ns, the input pin is IN_2, the output pin is OUT_2, the first-level driver unit is DDINVF8, the input terminal is GATE_IN_2, and the output terminal is GATE_OUT_2.
[0059] The rise time of the input signal signal_3 is 1.849ns, the fall time is 1.589ns, the input pin is IN_3, the output pin is OUT_3, the first-level driver unit is GDINVF8, the input terminal is GATE_IN_3, and the output terminal is GATE_OUT_3.
[0060] The rise time of the input signal signal_4 is 1.837ns, the fall time is 1.5ns, the input pin is IN_4, the output pin is OUT_4, the first-level driver unit is KDINVF8, the input terminal is GATE_IN_4, and the output terminal is GATE_OUT_4.
[0061] Among them, DDINVF8, GDINVF8, and KDINVF8 represent three different inverters, which have different sizes and different driving capabilities. Specifically, F8 indicates the number of fingers in the inverter, and DD, GD, and KD are the codes for the inverters.
[0062] Table 1 Results Table
[0063] Signal Name Start Pin End Pin Driven tR(ns) tF(ns) Force Node Measure Node signal_1 IN_1 OUT_1 DDINVF8 2.065 1.856 GATE_IN_1 GATE_OUT_1 signal_2 IN_2 OUT_2 DDINVF8 1.873 1.735 GATE_IN_2 GATE_OUT_2 signal_3 IN_3 OUT_3 GDINVF8 1.849 1.589 GATE_IN_3 GATE_OUT_3 signal_4 IN_4 OUT_4 KDINVF8 1.837 1.5 GATE_IN_4 GATE_OUT_4
[0064] In summary, the chip signal testing method in this embodiment acquires all input signals of the chip and obtains the time parameters of each input signal to obtain a result table. This result table contains the time parameters of all input signals, enabling batch acquisition and testing of chip input signals, improving the design efficiency of circuit designers, facilitating circuit optimization, and thus improving chip testing efficiency.
[0065] In one possible embodiment, obtaining the rise time and fall time of each input signal (step 200) may include the following steps:
[0066] Step S210: Extract the parasitic resistance-capacitance network circuit in a set of circuit units corresponding to each input signal.
[0067] In some possible embodiments, the parasitic resistance-capacitance network circuit for extracting the corresponding set of circuit units for each input signal may include:
[0068] Step S211: Determine the standard parasitic parameter format (SPF) file for the circuit unit. The standard parasitic parameter format file can be a standard parasitic parameter format netlist.
[0069] Each input signal corresponds to a set of circuit units, and each set of circuit units includes a driver circuit 10 and at least one load circuit 20. The input signal passes sequentially through the driver circuit 10, the signal transmission line between the driver circuit 10 and the load circuit 20, and the load circuit 20. Figure 4 As shown, the area indicated at point A is the driving circuit 10, and the areas indicated at points B and C are the load circuits 20. That is, the input signal corresponds to one driving circuit 10 and two load circuits 20. The specific structure of the driving circuit 10 and the load circuit 20 is not shown. Of course, one input signal may also correspond to one load circuit or multiple load circuits. This embodiment does not limit this.
[0070] For ease of description, this embodiment and the following embodiments are described using the example of an input signal corresponding to one driving circuit 10 and two load circuits 20.
[0071] A first port 40 and a second port 50 corresponding to each input signal are determined, thereby determining the circuit unit between the first port 40 and the second port 50. Here, the first port 40 refers to the port in the drive circuit 10 used to output the input signal, such as... Figure 4 As shown at P1, the second port 50 refers to the port in the load circuit 20 used to receive the input signal. The second port 50 is as follows: Figure 4 As shown at points P2 and P3.
[0072] Specifically, by acquiring the circuit and corresponding layout between the first port 40 and the second port 50, LVS (layout vs schematic) extraction is performed on the circuit and layout to obtain a standard parasitic parameter format netlist. The parasitic parameters are extracted by LVS using parasitic parameter extraction tools or EDA software tools, such as Synopsys' Star_RC, to extract the parasitic parameters of the circuit layout. The extraction result is a standard parasitic parameter format netlist.
[0073] For example, after generating the circuit diagram and corresponding layout of the integrated circuit in the chip, the driver circuit 10, load circuit 20, first port 40, and second port 50 are identified. Software is then used to extract the standard parasitic parameter format file between the first port 40 and the second port 50 to establish a parasitic resistance-capacitance network circuit 30. This parasitic resistance-capacitance network circuit 30 includes the parasitic resistance and capacitance of the signal lines connecting the first port 40 and the second port 50. The circuit units within the driver circuit 10 and load circuit 20 are also connected via signal lines. To avoid redundant calculations and affect accuracy, the parasitic resistance and capacitance of the internal connections of the driver circuit 10 and load circuit 20 are removed, i.e., the parasitic resistance and capacitance of the internal connections are ignored. This removal can be achieved using the Skip Cell function in EDA software.
[0074] Step S212: Construct the parasitic resistance-capacitance network circuit 30 according to the standard parasitic parameter format file. For example, the parasitic resistance-capacitance network circuit 30 is as follows: Figure 4 As shown in the dashed box, the parasitic resistance-capacitance network circuit 30 includes three resistors R1, R2, and R3. The first terminals of R1, R2, and R3 are shared, and the second terminal of R1 is connected to the first port 40. Figure 4 In the P1 connection, the second end of R2 is connected to a second port 50, that is... Figure 4 In the P2 connection, the second end of R3 is connected to another second port 50, that is... Figure 4 In the diagram, P3 is connected, and R1, R2, and R3 represent the resistances of the signal lines between the first port 40 and the second port 50, respectively. Figure 4 It also includes a grounding capacitor (not shown).
[0075] Step S220: Generate a test circuit for each input signal based on the corresponding circuit unit and parasitic resistance-capacitance network circuit.
[0076] In some possible examples, generating a test circuit for each input signal (step S230) based on the corresponding circuit unit and parasitic resistance-capacitance network circuit 30 includes:
[0077] Step S231: Determine the first replacement unit corresponding to the drive circuit.
[0078] Specifically, a first-level driving unit is extracted from the driving circuit 10. The input signal is transmitted from the input terminal of the driving circuit 10 through multiple circuit logic units to the first port 40 of the driving circuit 10, which is the output terminal of the driving circuit 10. The first-level driving unit refers to the first unit into which the input signal flows, and this unit is located near the input terminal of the driving circuit 10.
[0079] The first-level driving unit includes the first-level circuit logic unit 11 in the driving circuit, which is an inverter. Referring to Table 1, the inverter serving as the first-level circuit logic unit 11 can have various designs, such as DDINVF8, GDINVF8, and KDINVF8. The driving capability of the inverter can be improved by changing the channel size of the transistors and the number of gate fingers in the inverter.
[0080] After extracting the first-level driving unit, the first-level circuit logic unit in the driving circuit 10 is determined as the first replacement unit. For example, the inverter is determined as the first replacement unit.
[0081] Step S232: Determine the second replacement unit corresponding to each load circuit.
[0082] The load circuit 20 includes multiple load circuits. Determining the second replacement unit corresponding to each load circuit 20, for any one of the at least one load circuit 20, may include:
[0083] A first-level load unit is extracted from the load circuit 20. The first-level load unit includes the first-level logic unit 21 in the load circuit. The input signal is transmitted to the load circuit 20 through the second port 50, that is, the second port 50 of the load circuit 20 is the input terminal of the load circuit 20. The first-level load unit refers to the first-level unit into which the input signal flows, and this unit is close to the second port 50 of the load circuit 20.
[0084] The first-level load unit includes the first-level circuit logic unit 21 in the load circuit. The first-level load unit can be a latch, a D flip-flop, a selector, etc. The first-level circuit logic unit can be a standard cell, including inverters, AND gates, NAND gates, OR gates, NOR gates, AND-OR-NOT, OR-AND, OR-NOT, XOR-NOT, NOT gates, etc. For example, the first-level logic unit 21 in the load circuit is an inverter.
[0085] After extracting the first-level load unit, the first-level circuit logic unit in the load circuit 20 is determined as the second replacement unit. For example, the inverter is determined as the first replacement unit.
[0086] Step S233: Generate a test circuit based on the first replacement unit, at least one second replacement unit, and the parasitic resistance-capacitance network circuit.
[0087] After obtaining the first replacement unit and at least one second replacement unit, a test circuit can be generated based on the first replacement unit, at least one second replacement unit, and the parasitic resistance-capacitance network circuit 30. That is, the first replacement unit and the parasitic resistance-capacitance network circuit 30 are connected through the first port 40; and at least one second replacement unit and the parasitic resistance-capacitance network circuit 30 are connected through at least one second port 50 to obtain the test circuit.
[0088] refer to Figure 5 The output terminal P1 of the first replacement unit is connected to the parasitic resistance-capacitance network circuit 30 through the first port 40. The input terminals P2 and P3 of each second replacement unit are connected to the parasitic resistance-capacitance network circuit 30 through the corresponding second port 50 to form a test circuit. The parasitic resistance-capacitance network circuit 30 includes three resistors R1, R2, and R3, which represent the parasitic resistance of the signal line, and also includes a grounding capacitor (not shown).
[0089] Step S230: Use the test circuit to test the corresponding input signal and obtain the time parameters of the input signal.
[0090] For example, using a test circuit to test a corresponding input signal and obtain the rise and fall times of the input signal includes the following process: inputting a signal to the test circuit through the input terminal of the first replacement unit. Figure 5 As shown, the input terminal of the first substitution unit is a Force Node. The input signal is transmitted from this terminal to the first port 40, i.e., P1, via the first substitution unit 11, and then to the second port 50, i.e., P2 and P3, via the parasitic resistance-capacitor network circuit 30 in the test circuit. After that, it is transmitted to the output terminal of the second substitution unit via the second substitution unit 21.
[0091] After a test signal is input to the test circuit through the input terminal of the first replacement unit, at least one result signal is obtained from the input terminal of at least one second replacement unit of the test circuit. Each input terminal of the second replacement unit corresponds to one result signal, such as... Figure 5 The test circuit shown includes two second substitution units, whose inputs are Measure Node 1 and Measure Node 2, respectively. Correspondingly, this test circuit can acquire two result signals. The waveform of the result signal corresponding to Measure Node 1 is shown below. Figure 6 As shown, the waveform of the result signal corresponding to Measure Node 2 is as follows: Figure 7 As shown.
[0092] After obtaining at least one result signal at the input end of at least one second replacement unit of the test circuit, the rise time and fall time of the input signal are determined according to the at least one result signal. The rise time and fall time of the input signal can be determined according to the result signal.
[0093] Specifically, when there is one result signal, the rise time of this result signal is the rise time of the input signal, and the fall time of this result signal is the fall time of the input signal. When there are multiple result signals, each result signal has a rise time and a fall time. Obtain the rise time and fall time of each result signal. Take the maximum value among all the rise times as the rise time of the input signal, and take the maximum value among all the fall times as the fall time of the input signal. That is, take the worst result as the rise time / fall time of the input signal. If this result fails, the circuit design is redone.
[0094] Specifically, when there are two result signals, according to Figure 6 the waveform of the result signal corresponding to Measure Node 1 as shown, the rise time and fall time of this result signal can be obtained. According to Figure 7 the waveform of the result signal corresponding to Measure Node2 as shown, the rise time and fall time of this result signal can be obtained. Determine the maximum value among the rise times of these two result signals as the rise time of the input signal, and determine the maximum value among the fall times of these two result signals as the fall time of the input signal. As Figure 6 and Figure 7 shown, tR1 < tR2, so the rise time of this input signal is tR2.
[0095] For each input signal in the embodiments of the present disclosure, a test circuit is established through the above process. The test circuits established for different input signals are also different. The above process can be automatically built through a script or a program, which improves the test efficiency.
[0096] The embodiments of the present disclosure also provide a signal test system for a chip. The chip has multiple input signals. The signal test system includes: a first acquisition module, a second acquisition module, and a processing module. Among them, the first acquisition module is used to acquire all the input signals of the chip, the second acquisition module is used to obtain the time parameters of each input signal, and the processing module is used to generate a result table for the time parameters of all the input signals. The time parameters can be rise time, fall time, positive duty cycle, negative duty cycle, period, frequency, etc.
[0097] Each input signal corresponds to a set of circuit units, and each set of circuit units includes a driver circuit and at least one load circuit. The input signal sequentially passes through the driver circuit, the internal circuit between the driver circuit and the load circuit, and the load circuit. Accordingly, the second acquisition module includes:
[0098] The first acquisition submodule is used to extract the parasitic resistance-capacitance network circuit between the first port and the second port in a set of circuit units corresponding to each input signal.
[0099] The generation module is used to generate a test circuit for each input signal based on the corresponding circuit unit and parasitic resistance-capacitance network circuit.
[0100] The test module is used to test the corresponding input signal using the test circuit, and to obtain the rise time and fall time of the input signal.
[0101] In the chip signal testing system of this embodiment, all input signals are acquired by a first acquisition module, and the time parameters of each input signal are obtained by a second acquisition module. The processing module generates a result table from the time parameters of each input signal, thereby realizing batch acquisition and testing of the chip's input signals and improving testing efficiency.
[0102] This disclosure also provides an apparatus, which can be an electronic device, such as a computer or a server. The apparatus may include at least one processor and a memory. The memory stores instructions to be executed by the computer, and may be random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), or erasable programmable read-only memory (EPROM).
[0103] At least one processor executes computer execution instructions stored in memory, causing the at least one processor to perform the signal testing method described above. The processor can be a Central Processing Unit (CPU), a Network Processor (NP), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or other programmable logic devices. The device in this embodiment is used to execute the above-described signal testing method, and therefore possesses at least the advantages of the above-described signal testing method; specific effects are described above and will not be repeated here.
[0104] This disclosure also provides a storage medium storing computer-executable instructions. When a processor executes these instructions, the signal testing method described above is implemented. The storage medium can be a USB flash drive, external hard drive, readable storage device, magnetic disk, or optical disk, or any other medium capable of storing computer-executable instructions. The storage medium in this disclosure implements the above-described signal testing method and therefore possesses at least the advantages of the method. Specific effects are described above and will not be repeated here.
[0105] This disclosure also provides a program product, including a computer program, which, when executed by a processor, implements the signal testing method described above. The program product in this disclosure implements the signal testing method described above, and therefore possesses at least the advantages of the aforementioned signal testing method; specific effects are described above and will not be repeated here.
[0106] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0107] In the description of this specification, references to "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A signal testing method for a chip, characterized in that, The chip has multiple input signals, and the signal testing method includes: All input signals of the chip are obtained by a script. Each input signal corresponds to a set of circuit units. Each set of circuit units includes a driving circuit and at least one load circuit. Obtaining the time parameters of each input signal includes: Extract the parasitic resistance-capacitance network circuit from a set of circuit units corresponding to each input signal; A test circuit for each input signal is generated based on the corresponding circuit unit and the parasitic resistance-capacitance network circuit. The corresponding input signal is tested using the test circuit to obtain the time parameter of the input signal; Generate a result table of time parameters for all the input signals.
2. The signal testing method according to claim 1, characterized in that, Based on the corresponding circuit unit and the parasitic resistance-capacitance network circuit, a test circuit is generated for each input signal, including: Determine the first replacement unit corresponding to the driving circuit; Determine the second replacement unit corresponding to each of the aforementioned load circuits; The test circuit is generated based on the first replacement unit, the at least one second replacement unit, and the parasitic resistance-capacitance network circuit.
3. The signal testing method according to claim 2, characterized in that, Determining the first replacement unit corresponding to the driving circuit includes: Extract a first-level driving unit from the driving circuit, the first-level driving unit including the first-level circuit logic unit in the driving circuit; The first-level circuit logic unit in the driving circuit is determined as the first replacement unit.
4. The signal testing method according to claim 3, characterized in that, The first-level circuit logic unit in the driving circuit is an inverter.
5. The signal testing method according to claim 2, characterized in that, For any one of the at least one load circuits, determining the second replacement unit corresponding to the load circuit includes: Extract a first-level load unit from the load circuit, the first-level load unit including the first-level circuit logic unit in the load circuit; The first-level circuit logic unit in the load circuit is determined as the second replacement unit.
6. The signal testing method according to claim 5, characterized in that, The first-level circuit logic unit in the load circuit is a standard logic unit, including inverters, AND gates, OR gates, NOT gates, NAND gates, and NOR gates.
7. The signal testing method according to claim 2, characterized in that, The test circuit is generated based on the first replacement unit, the at least one second replacement unit, and the parasitic resistance-capacitance network circuit, including: The test circuit is obtained by connecting the first replacement unit and the parasitic resistance-capacitance network circuit through a first port; and by connecting the at least one second replacement unit and the parasitic resistance-capacitance network circuit through at least one second port.
8. The signal testing method according to any one of claims 2-7, characterized in that, Using the test circuit to test the corresponding input signal and obtain the time parameter of the input signal, includes: The input signal is input to the test circuit through the input terminal of the first replacement unit; Acquire at least one result signal from the input terminal of at least one second replacement unit of the test circuit; The time parameter of the input signal is determined based on the at least one result signal.
9. The signal testing method according to claim 8, characterized in that, Determining the time parameter of the input signal based on the at least one result signal includes: Obtain the time parameters for each result signal; The maximum value among the time parameters of the at least one resulting signal is determined as the time parameter of the input signal.
10. The signal testing method according to any one of claims 1-7, characterized in that, Extracting the parasitic resistance-capacitance network circuit from a set of circuit units corresponding to each input signal, including: Determine the standard parasitic parameter format file for the circuit unit; The parasitic resistance-capacitance network circuit is established according to the standard parasitic parameter format file.
11. A signal testing system for a chip, characterized in that, The chip has multiple input signals, and the signal testing system includes: The first acquisition module is used to acquire all the input signals of the chip through a script. Each input signal corresponds to a set of circuit units, and each set of circuit units includes a driving circuit and at least one load circuit. The second acquisition module is used to obtain the time parameters of each of the input signals, including: The first acquisition submodule is used to extract the parasitic resistance-capacitance network circuit in a set of circuit units corresponding to each input signal; A generation module is used to generate a test circuit for each input signal based on the corresponding circuit unit and the parasitic resistance-capacitance network circuit. The test module is used to test the corresponding input signal using the test circuit and obtain the time parameter of the input signal; The first processing module is used to generate a result table of time parameters for all the input signals.
12. A device, characterized in that, include: At least one processor and a memory, the memory storing instructions to be executed by the computer; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the signal testing method according to any one of claims 1-10.
13. A storage medium, characterized in that, The storage medium stores computer execution instructions, and when the processor executes the computer execution instructions, it implements the signal testing method according to any one of claims 1-10.
14. A program product, characterized in that, Includes a computer program that, when executed by a processor, implements the signal testing method according to any one of claims 1-10.