A coprocessor, an electronic device, and an electronic equipment

Abstract

The present application provides a coprocessor, an electronic device, and an electronic equipment. The coprocessor includes: a command FIFO and an operation FIFO; a command fetching module connected to the command FIFO for fetching commands and storing them in the command FIFO; an operation parameter fetching module connected to the operation FIFO for fetching operation parameters and storing them in the operation FIFO; a controller connected to the command fetching module and the operation parameter fetching module respectively, for controlling the command fetching module to fetch the next command after a command is successfully written into the command FIFO, and for controlling the operation parameter fetching module to fetch the operation parameters corresponding to the next command after the operation parameters corresponding to a command are successfully written into the operation FIFO; an algorithm engine connected to the controller and the operation FIFO respectively, for fetching the operation parameters of the command and performing operations after receiving the command. This solution can improve the processing speed exhibited by the coprocessor as a whole, thereby improving the performance of the coprocessor.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and more particularly, to a coprocessor, an electronic device, and an electronic apparatus. Background Art

[0002] Existing encryption and decryption coprocessor architectures often adopt a structure similar to DMA (Direct Memory Access) to improve encryption and decryption performance. The structure is as Figure 1 shown. During operation, under the scheduling of the control module inside the encryption and decryption coprocessor, the data to be encrypted and decrypted is read into the FIFO (First In, First Out, a commonly used first-in, first-out data buffer) at the input end of the encryption and decryption coprocessor, and then the data is sequentially sent from the FIFO at the input end to the corresponding algorithm engines inside the encryption and decryption coprocessor. After the algorithm engines complete the operation, the processed data is written to the specified memory address through the output end.

[0003] However, it is found in actual use that due to the limited processing performance of the algorithm engines, all the data to be encrypted and decrypted for a command has often been stored in the FIFO inside the encryption and decryption coprocessor, but the encryption and decryption algorithm engines have not completed the processing yet, resulting in the situation that the input end of the encryption and decryption coprocessor is often idle. This causes a waste of the performance of the encryption and decryption coprocessor and reduces the processing speed of the encryption and decryption coprocessor. Summary of the Invention

[0004] The purpose of the embodiments of this application is to provide a coprocessor, an electronic device, and an electronic apparatus to improve the performance of the coprocessor.

[0005] The embodiments of this application provide a coprocessor, including: a command FIFO and an operation FIFO; a command fetching module, connected to the command FIFO, for obtaining commands and storing the obtained commands in the command FIFO; an operation parameter fetching module, connected to the operation FIFO, for obtaining operation parameters and storing the obtained operation parameters in the operation FIFO; a controller, respectively connected to the command fetching module and the operation parameter fetching module, for controlling the command fetching module to obtain the next command after a command is successfully written into the command FIFO, and for controlling the operation parameter fetching module to obtain the operation parameters corresponding to the next command after the operation parameters corresponding to a command are successfully written into the operation FIFO; an algorithm engine, respectively connected to the controller and the operation FIFO, for, after receiving the command taken out from the command FIFO by the controller, taking out the operation parameters corresponding to the command from the operation FIFO for operation.

[0006] In the above implementation process, by setting up a command FIFO and an operation FIFO, as well as a command fetching module and an operation parameter fetching module, under the control of the controller, the command fetching module can independently fetch commands and store the commands in the command FIFO. The operation parameter fetching module can also independently fetch operation parameters and write the operation parameters into the operation FIFO. This realizes the independent fetching and storage of commands and operation parameters, enabling, for any given command, the co-processor to pre-fetch the next command or several subsequent commands, as well as the operation parameters corresponding to the next command or several subsequent commands, achieving the effect of data pre-fetching, thereby reducing the situation where the input of the co-processor is in an idle state, improving the overall processing speed of the co-processor, and thus enhancing the performance of the co-processor.

[0007] Further, the controller includes a command sub-controller; wherein: the command sub-controller is respectively connected to the command fetching module and the command FIFO; the command fetching module is specifically configured to send the fetched command to the command sub-controller, so as to write the command into the command FIFO through the command sub-controller; the command sub-controller is configured to write the command into the command FIFO, and after writing the command into the command FIFO, control the command fetching module to fetch the next command.

[0008] In the above implementation process, by setting up a dedicated command sub-controller to control the command fetching of the command fetching module, the reliability of the command fetching control can be effectively ensured. At the same time, having the command sub-controller write the command can ensure that after a command is successfully written into the command FIFO, the fetching of the next command is executed, guaranteeing the sequential writing and fetching of commands.

[0009] Further, the command sub-controller is further configured to, specifically, perform a correctness check on the command transmitted by the command fetching module; if the command is correct, write the command into the command FIFO.

[0010] In the above implementation process, by performing a correctness check on the command transmitted by the command fetching module and writing it into the command FIFO only when the command is correct, the correctness of the subsequent executed commands is ensured.

[0011] Further, the controller includes an operation sub-controller; the operation sub-controller is respectively connected to the operation parameter fetching module and the command FIFO, and is configured to read a command from the command FIFO and send the command to the operation parameter fetching module; the operation parameter fetching module is specifically configured to obtain the operation parameters corresponding to the command according to the command sent by the operation sub-controller.

[0012] In the above implementation process, by setting a dedicated operator controller to control the acquisition of operation parameters by the operation parameter acquisition module, the reliability of the control for the acquisition of operation parameters can be effectively ensured.

[0013] Furthermore, the operation parameters include a key and data; the operation FIFO includes a key FIFO and a data FIFO; the operation parameter acquisition module includes a key acquisition module and a data acquisition module; the operator controller includes a key sub-controller and a data sub-controller; wherein: the key acquisition module is respectively connected to the key sub-controller and the key FIFO, and is used to obtain the key corresponding to the command transmitted by the key sub-controller according to the command and write it into the key FIFO; the data acquisition module is respectively connected to the data sub-controller and the data FIFO, and is used to obtain the data corresponding to the command transmitted by the data sub-controller according to the command and write it into the data FIFO.

[0014] In the actual application process, if the coprocessor is an encryption / decryption coprocessor and the algorithm engine needs to perform encryption / decryption operations, the operation parameters required by the algorithm engine often need to include the data and key specified by the command. In the above implementation process, a dedicated key acquisition module and data acquisition module, a dedicated key sub-controller and data sub-controller, and a dedicated key FIFO and data FIFO are used to respectively implement the acquisition, control, and storage of data and keys, which effectively ensures the reliability of the acquisition and storage of the data and key corresponding to the command.

[0015] Furthermore, the operator controller is specifically used to determine whether there is data correlation between the currently read command and the command currently executed by the algorithm engine; if there is no data correlation, read the command from the command FIFO and send it to the operation parameter acquisition module; if there is data correlation, wait until the command currently executed by the algorithm engine is completed, and then re-determine whether there is data correlation between the currently read command and the next command executed by the algorithm engine.

[0016] In the above implementation process, the data correlation between the command that needs to acquire operation parameters currently and the command currently executed by the algorithm engine is considered. Only when there is no data correlation between the two commands, the operation parameter acquisition operation is executed, thereby ensuring the correctness of the execution of the command queue.

[0017] Further, the controller includes a main controller; the coprocessor further includes an output feedback module; the main controller is respectively connected to the command FIFO, the algorithm engine, and the output feedback module, and is configured to send the command fetched from the command FIFO to the algorithm engine; the output feedback module is respectively connected to the main controller and the algorithm engine, and is configured to, after receiving the output signal after the algorithm engine finishes the operation, feed back a notification signal to the main controller; the notification signal indicates that the command currently executed by the algorithm engine has been executed; the main controller is further configured to, after receiving the notification signal, continue to fetch a command from the command FIFO and send it to the algorithm engine.

[0018] In the above implementation solution, through the output feedback module, it can be ensured that after a command in the algorithm engine is executed, the main controller outputs the next command for the algorithm engine to execute, thereby ensuring the execution reliability of the commands for the algorithm engine and ensuring the normal operation of the coprocessor.

[0019] Further, the command FIFO has a first pointer, a second pointer, and a third pointer; where: the first pointer points to the tail of the command FIFO and is used for writing commands; the second pointer points to the head of the command FIFO and is used for the controller to fetch commands and send them to the algorithm engine; the third pointer points to the command corresponding to the operation parameter that the operation parameter fetching module currently needs to obtain.

[0020] In the above implementation solution, by setting the above three pointers in the command FIFO, only one command FIFO can simultaneously implement the command output for both the operation parameter fetching module and the algorithm engine, without setting multiple command FIFOs, saving hardware costs.

[0021] The embodiment of the present application further provides an electronic device, and the electronic device is internally provided with the coprocessor of any one of the above.

[0022] The embodiment of the present application further provides an electronic equipment, and the electronic equipment is internally provided with the above-mentioned electronic device. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0024] Figure 1 It is a structural schematic diagram of an encryption and decryption coprocessor in the prior art;

[0025] Figure 2 Schematic diagram of the basic structure of a coprocessor provided by an embodiment of the present application;

[0026] Figure 3 Schematic diagram of the structure of a specific coprocessor provided by an embodiment of the present application;

[0027] Figure 4 Schematic diagram of the structure of another specific coprocessor provided by an embodiment of the present application;

[0028] Figure 5 Schematic diagram of the structure of another specific coprocessor provided by an embodiment of the present application;

[0029] Figure 6 Schematic diagram of the structure of a more specific coprocessor provided by an embodiment of the present application;

[0030] Figure 7 Schematic diagram of the structure of a specific optional encryption / decryption coprocessor provided by an embodiment of the present application;

[0031] Figure 8 Schematic diagram of the working process of a command sub - controller provided by an embodiment of the present application;

[0032] Figure 9 Schematic diagram of the working process of a data sub - controller provided by an embodiment of the present application;

[0033] Figure 10 Schematic diagram of the working process of a main controller provided by an embodiment of the present application;

[0034] Figure 11 Schematic diagram of the structure of a command FIFO provided by an embodiment of the present application;

[0035] Figure 12 Space - time diagram when the encryption / decryption coprocessor provided by an embodiment of the present application is working. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application.

[0037] Embodiment 1:

[0038] In order to improve the performance of the coprocessor, a new implementation micro - architecture of the coprocessor is provided in the embodiments of the present application. It can be seen from Figure 2 as shown Figure 2 Schematic diagram of the basic structure of the coprocessor provided in the embodiments of the present application, including: command FIFO, arithmetic FIFO, command fetching module, arithmetic parameter fetching module, controller, and algorithm engine. Among them:

[0039] The command fetching module is connected to the command FIFO. The command fetching module is used to fetch commands and store the fetched commands in the command FIFO.

[0040] The operation parameter fetching module is connected to the operation FIFO, and is used to fetch operation parameters and store the fetched operation parameters in the operation FIFO.

[0041] The controller is respectively connected to the command fetching module and the operation parameter fetching module. In the embodiment of the present application, on the one hand, the controller is used to control the command fetching module to fetch commands. After a command is successfully written into the command FIFO, the controller controls the command fetching module to fetch the next command. On the other hand, the controller is used to control the operation parameter fetching module to fetch the operation parameters corresponding to the next command after the operation parameters corresponding to a command are successfully written into the operation FIFO.

[0042] In a feasible implementation manner of the embodiment of the present application, the controller can take out a command from the command FIFO, send the command to the operation parameter fetching module, and control the operation parameter fetching module to fetch the operation parameters of the command. Then, after the operation parameters corresponding to a command are successfully written into the operation FIFO, the controller continues to control the operation parameter fetching module to fetch the operation parameters corresponding to the next command.

[0043] In another feasible implementation manner of the embodiment of the present application, the controller can send an instruction to the operation parameter fetching module to control the operation parameter fetching module to fetch operation parameters. After receiving the instruction, the operation parameter fetching module takes out a command from the command FIFO and fetches the operation parameters of the command and writes them into the operation FIFO. After the operation parameters corresponding to a command are successfully written into the operation FIFO, the controller continues to send an instruction to the operation parameter fetching module to control the operation parameter fetching module to fetch the operation parameters corresponding to the next command.

[0044] The algorithm engine is respectively connected to the controller and the operation FIFO.

[0045] In the embodiment of the present application, the controller is further used to take out a command from the command FIFO and send it to the algorithm engine for execution. The algorithm engine is used to, after receiving the command taken out from the command FIFO by the controller, take out the operation parameters corresponding to the command from the operation FIFO for calculation.

[0046] In this way, under the control of the controller, the command fetching module can independently fetch commands and store the commands in the command FIFO. The operation parameter fetching module can also independently fetch operation parameters and write the operation parameters into the operation FIFO. This realizes the independent fetching and storing of commands and operation parameters, so that for any command, before the algorithm engine finishes execution, the coprocessor can prefetch the next command or several subsequent commands, as well as the operation parameters corresponding to the next command or several subsequent commands, achieving the effect of data prefetching, thereby reducing the situation where the input of the coprocessor is in an idle state, improving the overall processing speed shown by the coprocessor, and thus improving the performance of the coprocessor.

[0047] It should be noted that in the embodiments of the present application, the structures of the command fetching module and the operation parameter fetching module can both be implemented by all existing known and all possible future circuits that can realize information fetching and placing, which are not limited in the embodiments of the present application. For example, circuits for fetching information such as commands in the input end of an existing encryption and decryption coprocessor can be used for implementation, but this is not a limitation.

[0048] It should also be noted that in the embodiments of the present application, a dedicated sub - controller can be set in the controller to realize the acquisition control of corresponding information, so as to achieve a better control effect.

[0049] For example, see Figure 3 As shown, the controller can include a command sub - controller, and the command sub - controller is respectively connected to the command fetching module and the command FIFO.

[0050] At this time, after the command fetching module fetches a command, it can send the fetched command to the command sub - controller, and then the command is written into the command FIFO through the command sub - controller.

[0051] The command sub - controller can control the command fetching module to fetch the next command after writing the command into the command FIFO and after writing the command into the command FIFO.

[0052] It should be understood that in order to ensure the reliability of the commands written into the command FIFO, and thus ensure the correctness of the processing results of the coprocessor, in the embodiments of the present application, the command sub - controller can first perform a correctness check on the commands transmitted by the command fetching module. If the command is correct, the command is written into the command FIFO, and then the command fetching module is controlled to fetch the next command. If the command is incorrect, the command sub - controller can enter a stop state.

[0053] It should be understood that the above - mentioned method is only an optional implementation method exemplified in the embodiments of the present application. In fact, when setting a command sub - controller in the controller to control command acquisition, it can also be as Figure 4As shown, after the command fetching module obtains a command, the command fetching module can write the command into the command FIFO. After successfully writing the command into the command FIFO, the command fetching module can notify the command sub - controller. And after receiving the notification, the command sub - controller can control the command fetching module to continue obtaining the next command.

[0054] If it is necessary for the command sub - controller to perform the correctness verification of the command, then in the solution shown in the above example, after the command fetching module obtains a command, it can first send the command to the command sub - controller, and then the command sub - controller performs the correctness verification of the command. If the command is correct, it notifies the command fetching module. After receiving the notification from the command sub - controller, the command fetching module writes the command into the command FIFO. If the command is incorrect, the command sub - controller can enter the stop state.

[0055] It should be understood that in the two implementation methods shown in the above example, it can also be the command fetching module that verifies the correctness of the command, and there is no limitation in the embodiments of the present application.

[0056] It should also be understood that in the two implementation methods shown in the above example, it is possible to determine whether the current command is correct by judging whether the content or format of the current command is correct.

[0057] It should also be understood that in the two implementation methods shown in the above example, the command sub - controller can control the command fetching module to obtain a command by sending a command acquisition request to the command fetching module.

[0058] It should also be understood that in practical applications, for a single processing task, the commands to be obtained are usually a command queue (a command queue refers to a group of commands that are continuous in the address space, and the commands in the command queue are executed sequentially). Therefore, when obtaining commands, the command sub - controller can control the command fetching module to obtain commands in sequence according to the command queue.

[0059] It should also be understood that in the two implementation methods shown in the above example, the command sub - controller can also continuously detect whether the command queue is empty. If the command queue is empty, it indicates that all commands have been obtained, and thus the command sub - controller can enter the stop state. On the contrary, if the command queue is not empty, it indicates that there are still commands to be obtained, and thus it can continue to control the command module to obtain commands.

[0060] It should also be noted that, in the embodiments of the present application, the command may include information such as input address, output address, and which algorithm engine to use. The coprocessor can automatically complete data processing according to the information of the command. It should be understood that in actual applications, in some documents, the command is also referred to as a Descriptor. Therefore, whether it is referred to as a command or a descriptor, it should be considered to be within the protection scope of the present application.

[0061] Similarly, in a feasible implementation manner of the embodiments of the present application, reference may be made to Figure 3 As shown, the controller may further include an operator controller. The operator controller is respectively connected to the operation parameter fetching module and the command FIFO.

[0062] The operator controller is used to read the command from the command FIFO and send it to the operation parameter fetching module. The operation parameter fetching module is specifically used to obtain the operation parameters corresponding to the command according to the command sent by the operator controller. Then, after obtaining the corresponding operation parameters, the obtained operation parameters are written into the operation FIFO.

[0063] In another feasible implementation manner of the embodiments of the present application, reference may be made to Figure 5 As shown, the controller may also include an operator controller. The operator controller is connected to the operation parameter fetching module, and the operation parameter fetching module is connected to the command FIFO.

[0064] The operator controller can send an instruction to the operation parameter fetching module to control the operation parameter fetching module to obtain operation parameters. After receiving the instruction, the operation parameter fetching module fetches the command from the command FIFO and retrieves the operation parameters of the command and writes them into the operation FIFO. After the operation parameters corresponding to a command are successfully written into the operation FIFO, the operator controller continues to send an instruction to the operation parameter fetching module to control the operation parameter fetching module to obtain the operation parameters corresponding to the next command.

[0065] It should be understood that in the embodiments of the present application, the operation parameters refer to the information corresponding to the command required by the algorithm engine when executing the command, including but not limited to at least one of information such as the key, data, initial vector, and initial count value corresponding to the executed command.

[0066] It should also be understood that when multiple operation parameters are required, multiple corresponding operation parameter fetching modules may also be set, so that one operation parameter fetching module is used to obtain one type of operation parameter.

[0067] Correspondingly, multiple corresponding operator controllers may also be set, so that each operator controller controls one operation parameter fetching module.

[0068] Correspondingly, there may also be multiple operation FIFOs, so that each operation parameter fetching module is correspondingly connected to an operation FIFO, and different types of operation parameters are written into different operation FIFOs respectively, which is convenient for information management.

[0069] Exemplarily, assuming that the operation parameters include the key corresponding to the command and the data, a key FIFO, a data FIFO, a key fetching module, a data fetching module, a key sub-controller, and a data sub-controller may be set in the coprocessor. Among them:

[0070] The key fetching module is respectively connected to the key sub-controller and the key FIFO, and is used to obtain the key corresponding to the command according to the command transmitted by the key sub-controller and write it into the key FIFO.

[0071] The data fetching module is respectively connected to the data sub-controller and the data FIFO, and is used to obtain the data corresponding to the command according to the command transmitted by the data sub-controller and write it into the data FIFO.

[0072] It should be understood that the specific settings of the operation FIFO, the operation parameter fetching module, and the operation sub-controller can be set according to the functions to be implemented by the coprocessor and the requirements of the algorithm engine, and are not limited in the embodiments of the present application.

[0073] It should be noted that in the embodiments of the present application, before the operation sub-controller reads the command from the command FIFO and sends it to the operation parameter fetching module, it can check whether the command FIFO is empty. If the command FIFO is not empty, the command is read and sent to the operation parameter fetching module. If the command FIFO is empty, it can continue to wait.

[0074] It should also be understood that in the actual application process, in order to ensure the correctness of the algorithm engine's execution of the command queue, it is also necessary to consider the data correlation between the command for obtaining the operation parameters for storage and the command currently executed by the engine. For this reason, the operation sub-controller can also determine whether there is data correlation between the currently read command and the command currently executed by the algorithm engine; if there is no data correlation, the command is read from the command FIFO and sent to the operation parameter fetching module; if there is data correlation, wait until the command currently executed by the algorithm engine is executed, and then re-determine whether there is data correlation between the currently read command and the next command executed by the algorithm engine. In this way, the data correlation between the fetched commands can be effectively avoided from affecting the execution of the commands.

[0075] It should be understood that in the embodiments of the present application, data correlation includes but is not limited to at least one of the situations such as read after write, write after write, and read after write.

[0076] In the embodiments of the present application, the detection of data correlation can be achieved by setting corresponding hardware circuits capable of implementing data correlation detection in the operator controller. In addition, the detection of data correlation can also be achieved by software. For example, the software determines the data correlation between commands. If data correlation occurs, the software adds a flag bit to the command. When the operator controller recognizes this flag bit, it will pause the fetching of commands.

[0077] It should be noted that, in the embodiments of the present application, as Figures 3 to 7 shown, the controller may further include a main controller. The main controller can be respectively connected to the command FIFO and the algorithm engine, so as to fetch commands from the command FIFO and send them to the algorithm engine for operation.

[0078] It should be understood that, in the embodiments of the present application, the above-mentioned main controller and various sub-controllers can be implemented by a separate controller implementation circuit, or can also be implemented by independent modules or chips, and there is no limitation in the embodiments of the present application.

[0079] In the embodiments of the present application, the main controller can also be connected to each sub-controller to control the operation of each sub-controller.

[0080] In the embodiments of the present application, in order to ensure that the algorithm engine executes commands one by one, as shown in Figure 6 shown, the coprocessor may further include an output feedback module.

[0081] The output feedback module is respectively connected to the main controller and the algorithm engine, and is used for feeding back a notification signal to the main controller after receiving the output signal after the algorithm engine finishes the operation. The notification signal is a signal indicating that the command currently executed by the algorithm engine has been executed.

[0082] After receiving the notification signal, the main controller can continue to fetch commands from the command FIFO and send them to the algorithm engine.

[0083] It should be understood that, in the embodiments of the present application, the output feedback module can be implemented by all existing known and all possible future circuits capable of implementing signal feedback, and there is no limitation in the embodiments of the present application.

[0084] It should be understood that in the embodiments of the present application, in order for the controller to control the operation parameter fetching module, the controller needs to fetch commands from the command FIFO. At the same time, in order to ensure the execution of the algorithm engine, the controller also needs to fetch commands from the command FIFO, and the commands fetched twice can be different. Then, in order to ensure that the controller can correctly read the required commands, in a feasible implementation manner of the embodiments of the present application, two command FIFOs can be set. One is dedicated to controlling the operation parameter fetching module, and the other is dedicated to controlling the algorithm engine. Correspondingly, after the command fetching module obtains a command, the command needs to be written into these two command FIFOs to ensure the reliability of the control process.

[0085] In another feasible implementation manner of the embodiments of the present application, only one command FIFO can be set, and three pointers are set in the command FIFO, which are respectively denoted as the first pointer, the second pointer, and the third pointer. Among them:

[0086] The first pointer points to the tail of the command FIFO and is used to write commands.

[0087] The second pointer points to the head of the command FIFO and is used for the controller to fetch commands and send them to the algorithm engine.

[0088] The third pointer points to the command corresponding to the operation parameter that the operation parameter fetching module currently needs to obtain.

[0089] In this way, through the three pointers, the accurate acquisition of commands can be ensured.

[0090] It should be noted that when there are multiple operation parameters, for the third pointer, only one can be set, or multiple can be set. When multiple are set, one third pointer can be correspondingly set for each operation parameter fetching module to achieve more refined control of the operation parameter fetching module.

[0091] It should also be noted that in the embodiments of the present application, in order to facilitate the main controller and each sub - controller in the controller to read commands, the command FIFO can be set inside the controller. Of course, the command FIFO can also be set outside the controller, and the embodiments of the present application do not limit this.

[0092] It should further be noted that in the embodiments of the present application, the algorithm engine can be an encryption / decryption algorithm engine or a data pass - through engine, etc. The embodiments of the present application do not limit the type of the algorithm engine.

[0093] An electronic device is also provided in the embodiments of the present application. A coprocessor provided in the embodiments of the present application is provided inside the electronic device.

[0094] Exemplarily, in the embodiments of the present application, the electronic device may be a module device such as a data processing module or a communication module having a coprocessor, or may also be a systemized device such as a system-on-chip.

[0095] In the embodiments of the present application, an electronic device is further provided, and the electronic device is provided with the electronic device in the embodiments of the present application.

[0096] Exemplarily, in the embodiments of the present application, the electronic device may be a computer host, a server, etc. devices having a coprocessor.

[0097] The coprocessor, electronic device, and electronic device provided in the embodiments of the present application, by setting a command FIFO and an operation FIFO, and setting a command fetching module and an operation parameter fetching module, so that under the control of the controller, the command fetching module can independently obtain commands and store the commands in the command FIFO. And the operation parameter fetching module can also independently obtain operation parameters and write the operation parameters into the operation FIFO. This realizes the independent acquisition and storage of commands and operation parameters, so that for any command, before the algorithm engine finishes execution, the coprocessor can pre-obtain the next command or the next few commands, and the operation parameters corresponding to the next command or the next few commands, achieving the effect of data prefetching, thereby reducing the situation where the input of the coprocessor is in an idle state, improving the overall processing speed of the coprocessor, and thus improving the performance of the coprocessor.

[0098] In addition, the coprocessor, electronic device, and electronic device provided in the embodiments of the present application consider the data correlation between the command for which operation parameters need to be obtained currently and the command currently executed by the algorithm engine, and only perform the operation parameter acquisition operation when there is no data correlation between the two commands, so as to ensure the correctness of the execution of the command queue.

[0099] Embodiment 2:

[0100] Based on Embodiment 1, taking an encryption / decryption coprocessor with the operation parameters being the key and data of the command as an example, the present application is further illustrated by examples.

[0101] See Figure 7 shown, Figure 7 shows the structure of the encryption / decryption coprocessor provided in this embodiment. It includes several modules: a controller, an input end, an algorithm engine, and an output end. The controller is the control core of the encryption / decryption coprocessor, completing the distribution of commands and the management of the entire life cycle. The input end is the input interface of the encryption / decryption coprocessor, completing the reading of commands, data, and keys. The algorithm engine is used to process data with various algorithms. The output end is the output interface of the encryption / decryption coprocessor, completing the writing of data.

[0102] Among them, the controller includes a main controller, a command sub - controller, a data sub - controller, a key sub - controller, and a command FIFO. The main controller completes command distribution and execution, as well as control of starting and stopping each sub - controller. Under the action of the main controller, the command sub - controller retrieves commands and writes them into the command FIFO. Under the action of the main controller, the data sub - controller reads commands from the command FIFO and controls the data pre - fetching module to complete the data pre - fetching function of the command. Under the action of the main controller, the key sub - controller reads commands from the command FIFO and controls the key pre - fetching module to complete the key pre - fetching function of the command. The command FIFO is used to store multiple retrieved commands.

[0103] The input end includes a command fetching module, a data fetching module, a key fetching module, a data FIFO, and a key FIFO. Among them: Under the action of the command sub - controller, the command fetching module retrieves commands from the bus and writes them into the command FIFO. Under the action of the data sub - controller, the data fetching module retrieves data from the bus and writes the data into the data FIFO. Under the action of the key sub - controller, the key fetching module retrieves keys from the bus and writes the keys into the key FIFO.

[0104] The output end has an output feedback module, which can notify the main controller after the algorithm engine finishes operating on a command.

[0105] Each sub - controller in the controller is controlled by the main controller and operates independently. Each sub - controller is described as follows:

[0106] Figure 8 Describes the working process of the command sub - controller. Under the action of the main controller, the command sub - controller sends a command fetching request to the command fetching module at the input end. After the command sub - controller receives the retrieved command, it checks whether the command is correct. If the command is incorrect, it enters the stop state. If the command is correct, it writes the command into the command FIFO. After the command sub - controller writes the command into the command FIFO, it determines whether the command queue is empty. If the command queue is not empty, it continues to fetch the next command. If the command queue is empty, it enters the stop state.

[0107] Figure 9 Describes the working process of the data sub - controller. Under the action of the main controller, the data sub - controller checks whether the command FIFO is empty. If the command FIFO is not empty, it reads a command and sends it to the data fetching module at the input end. The data fetching module at the input end retrieves data from the specified address according to the command content and stores the data in the data FIFO. After all the data of the command have been stored in the data FIFO, the data sub - controller starts to retrieve data for the next command.

[0108] It should be understood that the working process of the key sub - controller is the same as that of the data sub - controller. The only difference is that the object of control is the key fetching module at the input end, and the retrieved is the key instead of the data. Therefore, it will not be elaborated here.

[0109] Figure 10 Describes the working process of the main controller. After the software prepares the command queue, the main controller is started. The main controller starts the command sub - controller, the data sub - controller, and the key sub - controller in sequence. Then, the main controller checks whether the command FIFO is empty. If the command FIFO is empty, it continues to wait. If the command FIFO is not empty, it takes out a command and sends the command to the algorithm engine. After receiving the command, the algorithm engine reads the corresponding data and key from the data FIFO and the key FIFO. If the data and key are read, it starts the operation and writes the result back to the specified address through the output end. When all the data of this command have been processed and written back to the specified address, the output feedback module at the output end will notify the main controller, and the main controller starts to take the next command from the command FIFO and send it to the algorithm engine.

[0110] Figure 11 Describes the structure of the command FIFO. Figure 11 The depth of the command FIFO shown in is 5 (in practical applications, there is no limit to the depth of the command FIFO), that is, it can store up to 5 commands at most (in the figure, CMD0(valid) to CMD4(valid) represent that commands CMD0 to CMD4 are stored, and in valid in the figure represents that no command is stored at this position). The command FIFO has 3 pointers, namely:

[0111] -WrPtr (i.e., the first pointer): Points to the end of the command FIFO, that is, the latest obtained command, for use by the command sub - controller. The command sub - controller writes commands to this address.

[0112] -RdPtr (i.e., the second pointer): Points to the head of the command FIFO, that is, the command currently being processed, for use by the main controller. The main controller takes out commands from this address.

[0113] -PreFetchPtr (i.e., the third pointer): Points to the command that is pre - fetching data and keys at the input end, for use by the data sub - controller and the key sub - controller. The data sub - controller and the key sub - controller read commands from this address.

[0114] In this way, through the three pointers, it ensures the accurate reading and writing of the command FIFO by the command sub - controller, the main controller, the data sub - controller, and the key sub - controller.

[0115] In addition, in this embodiment, to ensure the correct execution of the command queue, data dependencies between commands should be considered when fetching data. Since the commands in the command queue are executed in order, only the read-after-write case needs to be considered in this embodiment.

[0116] For read-after-write, in this embodiment, in the data sub-controller and the key sub-controller, a hardware judgment circuit is added. When there is a read-after-write data dependency between the command pointed to by PreFetchPtr and the command pointed to by RdPtr (i.e., the command currently being executed by the algorithm engine), the hardware judgment circuit can pause fetching the command pointed to by PreFetchPtr from the command FIFO.

[0117] Next, taking a specific example process as an example, the advantages of the coprocessor in this embodiment are illustrated:

[0118] See Figure 12 as shown, Figure 12 which depicts the space-time diagram when the encryption / decryption coprocessor is working. Figure 12 It is assumed in

[0119] See Figure 12 as shown, at time T1, command fetching starts, and at time T3, all commands are executed. Since command fetching, data fetching, key fetching, and command execution are relatively independent, part of the data of command cmd2 has been prefetched when command cmd2 starts to execute (i.e., at time T2). Therefore, the execution time of command cmd2 is shortened. Similarly, the execution times of command cmd3 and command cmd4 are also shortened, thus reducing the overall execution time of the command queue and improving the overall performance of the encryption / decryption coprocessor.

[0120] The embodiments described above are merely illustrative. For example, the division of the units is only a functional division, and there may be other division methods in actual implementation. Also, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed with each other can be through some communication interfaces, and the indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0121] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed over multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0122] Furthermore, in each embodiment of the present application, the modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0123] In this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0124] In this text, "a plurality of" means two or more.

[0125] The above description is only for the embodiments of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A coprocessor, characterized in that, it includes: a command FIFO and an operation FIFO; a command fetching module, connected to the command FIFO, for fetching commands and storing the fetched commands in the command FIFO; an operation parameter fetching module, connected to the operation FIFO, for fetching operation parameters and storing the fetched operation parameters in the operation FIFO; a controller, connected to the command fetching module and the operation parameter fetching module respectively, for controlling the command fetching module to fetch the next command after a command is successfully written into the command FIFO, and for controlling the operation parameter fetching module to fetch the operation parameters corresponding to the next command after the operation parameters corresponding to a command are successfully written into the operation FIFO; an algorithm engine, connected to the controller and the operation FIFO respectively, for taking out the operation parameters corresponding to the command from the operation FIFO for operation after receiving the command taken out by the controller from the command FIFO.

2. The coprocessor according to claim 1, characterized in that, the controller includes a command sub - controller; where: the command sub - controller is connected to the command fetching module and the command FIFO respectively; the command fetching module is specifically configured to send the fetched command to the command sub - controller, so as to write the command into the command FIFO through the command sub - controller; the command sub - controller is configured to write the command into the command FIFO, and after writing the command into the command FIFO, control the command fetching module to fetch the next command.

3. The coprocessor according to claim 2, characterized in that, the command sub - controller is further configured to, the command sub - controller is specifically configured to perform a correctness check on the command transmitted by the command fetching module; if the command is correct, write the command into the command FIFO.

4. The coprocessor according to claim 1, characterized in that, the controller includes an operation sub - controller; the operation sub - controller is connected to the operation parameter fetching module and the command FIFO respectively, for reading the command from the command FIFO and sending it to the operation parameter fetching module; the operation parameter fetching module is specifically configured to obtain the operation parameters corresponding to the command according to the command sent by the operation sub - controller.

5. The coprocessor according to claim 4, characterized in that, the operation parameters include a key and data; the operation FIFO includes a key FIFO and a data FIFO; the operation parameter fetching module includes a key fetching module and a data fetching module; the operation sub - controller includes a key sub - controller and a data sub - controller; where: the key fetching module is connected to the key sub - controller and the key FIFO respectively, for obtaining the key corresponding to the command according to the command transmitted by the key sub - controller and writing it into the key FIFO; The data fetching module is respectively connected to the data sub - controller and the data FIFO, and is used to obtain the data corresponding to the command transmitted by the data sub - controller according to the command, and write it into the data FIFO.

6. The coprocessor according to claim 4, wherein, the operation sub - controller is specifically used for judging whether there is data correlation between the currently read command and the command currently executed by the algorithm engine; if there is no data correlation, it reads the command from the command FIFO and sends it to the operation parameter fetching module; if there is data correlation, it waits for the command currently executed by the algorithm engine to be executed, and then re - judges whether there is data correlation between the currently read command and the next command executed by the algorithm engine.

7. The coprocessor according to claim 1, wherein, the controller includes a main controller; the coprocessor further includes an output feedback module; the main controller is respectively connected to the command FIFO, the algorithm engine and the output feedback module, and is used to send the command fetched from the command FIFO to the algorithm engine; the output feedback module is respectively connected to the main controller and the algorithm engine, and is used to feedback a notification signal to the main controller after receiving the output signal after the algorithm engine finishes the operation; the notification signal indicates that the command currently executed by the algorithm engine has been executed; the main controller is further used to continue to fetch commands from the command FIFO and send them to the algorithm engine after receiving the notification signal.

8. The coprocessor according to any one of claims 1 - 7, wherein, the command FIFO has a first pointer, a second pointer and a third pointer; among them: the first pointer points to the tail of the command FIFO and is used to write commands; the second pointer points to the head of the command FIFO and is used for the controller to fetch commands and send them to the algorithm engine; the third pointer points to the command corresponding to the operation parameter that the operation parameter fetching module currently needs to obtain.

9. An electronic device, wherein, the electronic device is provided with the coprocessor according to any one of claims 1 - 8.

10. An electronic equipment, wherein, the electronic equipment is provided with the electronic device according to claim 9.

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