System on a Chip

Abstract

The present invention relates to a single chip system, comprising a first and a second central processing unit and a first and a second tightly coupled memory. The first central processing unit comprises a first core circuit, a first level 1 memory interface and a first level 2 memory interface. The first tightly coupled memory is directly coupled to the first level 1 memory interface and comprises a first mailbox. The second central processing unit comprises a second core circuit, a second level 1 memory interface and a second level 2 memory interface. The second tightly coupled memory is directly coupled to the second level 1 memory interface and comprises a second mailbox. When the first central processing unit sends a command to the second mailbox in the second tightly coupled memory, the second core circuit directly reads the command from the second mailbox without passing through the second level 2 memory interface.

Description

Technical Field

[0001] The present invention relates to a system on chip (SoC) including a plurality of central processing units (CPUs). Background Art

[0002] In a conventional single-chip system including multiple CPUs, each CPU has its own mailbox for receiving messages or commands from other CPUs. Taking a single-chip system with an Advanced RISC Machine (ARM) architecture as an example, the CPUs can communicate with each other via an advanced extensible interface (AXI) wire, and an interface between the CPU and its own mailbox is an advanced high performance bus (AHB), and the CPU needs to communicate with the mailbox and / or other peripheral registers / memory through the AHB bridge. In the above structure, when the first central processor sends a message to the mailbox of the second central processor through the advanced extensible interface interconnection circuit, and the mailbox sends an interrupt signal to the second central processor to notify the second central processor to read the message, the second central processor needs to send a read command to the mailbox through the advanced high-performance bus bridge that requires interface conversion, and the interface conversion in the advanced high-performance bus bridge means a longer signal delay. That is to say, in the case of frequent communication between multiple central processors, the inefficiency of the single-chip system may be very obvious. Summary of the invention

[0003] Therefore, one of the objectives of the present invention is to provide a single chip system, which designs a mailbox in a primary memory system to solve the above-mentioned problems.

[0004] According to an embodiment of the present invention, a single chip system is disclosed, which includes a first central processing unit, a first tightly coupled memory, a second central processing unit and a second tightly coupled memory. The first central processing unit includes a first core circuit, a first level 1 memory interface and a first level 2 memory interface. The first tightly coupled memory is directly coupled to the first level 1 memory interface, and the first tightly coupled memory includes a first mailbox. The second central processing unit includes a second core circuit, a second level 1 memory interface and a second level 2 memory interface.

[0005] The second tightly coupled memory is directly coupled to the second first-level memory interface, and the second tightly coupled memory includes a second mailbox. When the first central processor sends a command to the second mailbox in the second tightly coupled memory, the second core circuit directly reads the command from the second mailbox without passing through the second second-level memory interface.

[0006] According to another embodiment of the present invention, a single chip system is disclosed, which includes a first central processor, a first tightly coupled memory, a second central processor, a second tightly coupled memory, and a flash memory controller. The first central processor includes a first core circuit, a first level 1 memory interface, and a first level 2 memory interface. The first tightly coupled memory is directly coupled to the first level 1 memory interface, and the first tightly coupled memory includes a first mailbox. The second central processor includes a second core circuit, a second level 1 memory interface, and a second level 2 memory interface. The second tightly coupled memory is directly coupled to the second level 1 memory interface, and the second tightly coupled memory includes a second mailbox. The flash memory controller is used to access a flash memory module outside the single chip system. When the first central processor sends an access command to the second mailbox in the second tightly coupled memory, the second core circuit directly reads the access command from the second mailbox without passing through the second level 2 memory interface; and the second core circuit also sends a command corresponding to the access command to the flash memory controller to control the flash memory controller to access the flash memory module. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a schematic diagram of a single-chip system according to an embodiment of the present invention.

[0008] Figure 2 According to an embodiment of the present invention Figure 1 A flow chart of the operation of the core circuit is shown.

[0009] Figure 3 FIG. 4 is a schematic diagram of a single-chip system according to another embodiment of the present invention.

[0010] Figure 4 According to an embodiment of the present invention Figure 3 A flow chart of the operation of the core circuit is shown.

[0011] Figure 5 FIG. 4 is a schematic diagram of a single-chip system according to another embodiment of the present invention.

[0012]

Explanation of symbols

[0013] 100,300,500: Single chip system

[0014] 102,302: Advanced Scalable Interface Interconnect Circuit

[0015] 110,120,310,320,510,520:CPU

[0016] 112,122,312,322: Core circuit

[0017] 114,124,314,324: Level 1 memory interface

[0018] 116,126,316,326: Secondary memory interface

[0019] 118,128,318,328: A tightly coupled memory and B tightly coupled memory

[0020] 119,129,319,329: mailbox

[0021] 141,151,341,351: Advanced high performance bus to register bridge (decoder)

[0022] 142,152,342,352: Peripheral registers

[0023] 200~210,400~416: Steps

[0024] 304: Service Provider Interface Loader

[0025] 306: Electronically Erasable Rewritable Read-Only Memory

[0026] 502:Host

[0027] 504: Dynamic Random Access Memory

[0028] 506: Flash memory module

[0029] 530: Flash memory controller DETAILED DESCRIPTION

[0030] Certain terms are used in the following embodiments and the scope of the invention patent application to refer to specific system components. As can be understood by those skilled in the art, manufacturers may refer to a component by different names. This document does not intend to distinguish between components with different names but the same functions. In the following embodiments and the scope of the invention patent application, the term "including" is used in an open manner and should be interpreted as "including but not limited to...". The term "coupled" is intended to mean an indirect or direct electrical connection. Therefore, if a first device is coupled to a second device, the connection can be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

[0031] Figure 1 FIG. 1 is a schematic diagram of a single-chip system according to an embodiment of the present invention. Figure 1 As shown, the single-chip system 100 includes a central processing unit 110, a tightly coupled memory (TCM) including a memory space 118 and a mailbox 119 named A tightly coupled memory (ATCM) and B tightly coupled memory (BTCM), an advanced high-performance bus to register bridge (decoder) 141, and a peripheral register 142, wherein the central processing unit 110 includes a core circuit 112, a level one memory interface 114, and a level two memory interface 116. In addition, the single-chip system 110 further includes a central processing unit 120, a tightly coupled memory (including a memory space 128 and a mailbox 129 named A tightly coupled memory and B tightly coupled memory), an advanced high-performance bus to register bridge (decoder) 151, and a peripheral register 152, wherein the central processing unit 120 includes a core circuit 122, a level one memory interface 124, and a level two memory interface 126. In this embodiment, the tightly coupled memory is intended to provide low latency memory for the processor to use without the unpredictability of cache, and the core circuit 112 / 122 can directly access the tightly coupled memory through the first-level memory interface 114 / 124 without going through the second-level memory interface 116 / 126. In one embodiment, the tightly coupled memory can be built into the central processing unit 110 / 120. The single-chip system 100 also includes a bus for communication between the central processing unit 110 and the central processing unit 120, wherein the advanced extensible interface interconnect circuit (AXI interconnect) 102 is used as the bus in this embodiment.

[0032] In the operation of the single-chip system 100, the core circuit 112 can directly access the A tightly coupled memory and the B tightly coupled memory 118 and the mailbox 119 through the primary memory interface 114, but the core circuit 112 needs to access the peripheral register 142 through the secondary memory interface 116, and the secondary memory interface 116 is necessary for the core circuit 112 to access other components through the advanced extensible interface interconnection circuit 102. In this embodiment, the secondary memory interface 116 can be an advanced high-performance bus interface that performs communication protocol conversion and address mapping, wherein the communication protocol conversion and address mapping mean longer signal delays, therefore, by designing the mailbox 119 in the tightly coupled memory and directly accessible by the core circuit 112, the central processor 110 can communicate with other components with higher efficiency. Similarly, the core circuit 122 can directly access the A tightly coupled memory and the B tightly coupled memory 128 and the mailbox 129 via the primary memory interface 124, but the core circuit 122 needs to access the peripheral register 152 via the secondary memory interface 126, and the secondary memory interface 126 is necessary for the core circuit 122 to access other components through the advanced extensible interface interconnect circuit 102. In this embodiment, the secondary memory interface 126 can be an advanced high-performance bus interface that performs communication protocol conversion and address mapping, wherein the communication protocol conversion and address mapping mean longer signal delays, therefore, by designing the mailbox 129 in the tightly coupled memory and directly accessible by the core circuit 122, the central processor 120 can communicate with other components with higher efficiency.

[0033] Specifically, if the CPU 120 needs to send a command to the CPU 110, the core circuit 122 sends the command to the AEI circuit 102 via the primary memory interface 124 and the secondary memory interface 126, and the command from the CPU 120 is stored in the mailbox 119. After the mailbox 119 receives the command from the CPU 120, the mailbox 119 sends an interrupt signal to notify the core circuit 112. After receiving the interrupt signal from the mailbox 119, the core circuit 112 reads the command stored in the mailbox 119 through the primary memory interface 114 to perform an operation corresponding to the command. In this embodiment, because the primary memory interface 114 does not require any temporary register for the core circuit 112 to access the mailbox 119, the core circuit 112 can effectively obtain the command from the CPU 120. Similarly, if the CPU 110 needs to send a command to the CPU 120, the core circuit 112 sends the command to the AEI circuit 102 via the primary memory interface 114 and the secondary memory interface 116, and the command from the CPU 110 is stored in the mailbox 129. After the mailbox 129 receives the command from the CPU 110, the mailbox 129 sends an interrupt signal to notify the core circuit 122. After receiving the interrupt signal from the mailbox 129, the core circuit 122 reads the command stored in the mailbox 129 through the primary memory interface 124 to perform an operation corresponding to the command. In this embodiment, because the primary memory interface 124 does not require any register for the core circuit 122 to access the mailbox 129, the core circuit 122 can effectively obtain the command from the CPU 110.

[0034] Figure 2 According to an embodiment of the present invention Figure 1 A flow chart of the operation of the core circuit is shown.

[0035] Step 200: The process starts.

[0036] Step 202: The core circuit checks whether an interrupt signal is received from the corresponding mailbox.

[0037] Step 204: If the core circuit receives the interrupt signal (ie, interrupt = 1), the process proceeds to step 206; if the core circuit does not receive the interrupt signal (ie, interrupt = 0), the process returns to step 202.

[0038] Step 206: The core circuit performs a memory transaction via the primary memory interface and the mailbox.

[0039] Step 208: The core circuit reads the command stored in the mailbox through the primary memory interface.

[0040] Step 210: The process ends.

[0041] exist Figure 1 In the single-chip system 100 shown, there are two AXI master interfaces and four AXI slave interfaces, and since the maximum frequency of the AXI interconnect circuit 102 is inversely proportional to the number of AXI master interfaces and AXI slave interfaces, the frequency of the single-chip system 100 may be limited. Therefore, in order to increase the frequency of the single-chip system, Figure 3 FIG. 3 shows a single chip system 300 according to an embodiment of the present invention. Figure 3 As shown, the single-chip system 300 includes a central processing unit 310, a tightly coupled memory (which includes a memory space 318 and a mailbox 319 named A tightly coupled memory and B tightly coupled memory), a high-level high-performance bus to register bridge 341, and a peripheral register 342, wherein the central processing unit 310 includes a core circuit 312, a first-level memory interface 314, and a second-level memory interface 316. In addition, the single-chip system 300 further includes a central processing unit 320, a tightly coupled memory (which includes a memory space 328 and a mailbox 329 named A tightly coupled memory and B tightly coupled memory), a high-level high-performance bus to register bridge 351, and a peripheral register 352, wherein the central processing unit 320 includes a core circuit 322, a first-level memory interface 324, and a second-level memory interface 326. In this embodiment, the tightly coupled memory is intended to provide low latency memory for the processor to use without the unpredictability of cache, and the core circuit 312 / 222 can directly access the tightly coupled memory through the first-level memory interface 314 / 324 without going through the second-level memory interface 316 / 326.

[0042] In the operation of the single-chip system 300, when the single-chip system 300 is powered on from a power-off state, a service provider interface (SPI) loader 304 loads program code from an electrically-erasable programmable read-only memory (EEPROM) 306, and the service provider interface loader 304 writes the program code into the A tightly coupled memory of the central processing unit 310 / 320 via the AEUI circuit 302, the secondary memory interface 316 / 326 and the primary memory interface 314 / 324, and then the central processing unit 310 and the central processing unit 320 are enabled. In the above initialization step, since the service provider interface loader 302 will only operate when the single-chip system 300 is powered on, after the single-chip system 300 is initialized, the advanced extensible interface slave interface (SPI AXI slave) of the service provider interface can be used by the central processor 310 / 320 to communicate with the mailbox 329 / 319 through the advanced extensible interface interconnect circuit 302.

[0043] In the single chip system 300, the core circuit 312 can directly access the A tightly coupled memory and the B tightly coupled memory 318 and the mailbox 319 through the primary memory interface 314, but the core circuit 312 needs to access the peripheral register 342 through the secondary memory interface 316, and the secondary memory interface 316 is necessary for the core circuit 312 to access other components through the advanced extensible interface interconnection circuit 302. In this embodiment, the secondary memory interface 316 can be an advanced high-performance bus interface that performs communication protocol conversion and address mapping, wherein the communication protocol conversion and address mapping mean longer signal delays, therefore, by designing the mailbox 319 in the tightly coupled memory that can be directly accessed by the core circuit 312, the central processor 310 can communicate with other components with higher efficiency. Similarly, the core circuit 322 can directly access the A tightly coupled memory and the B tightly coupled memory 328 and the mailbox 329 via the primary memory interface 324, but the core circuit 322 needs to access the peripheral register 352 via the secondary memory interface 326, and the secondary memory interface 316 is necessary for the core circuit 312 to access other components through the advanced extensible interface interconnection circuit 302. In this embodiment, the secondary memory interface 326 can be an advanced high-performance bus interface that performs communication protocol conversion and address mapping, wherein the communication protocol conversion and address mapping mean longer signal delays, therefore, by designing the mailbox 329 in the tightly coupled memory that can be directly accessed by the core circuit 322, the central processor 320 can communicate with other components with higher efficiency.

[0044] Specifically, if the CPU 320 needs to send a command to the CPU 310, the core circuit 322 sends the command to the AEI circuit 302 via the primary memory interface 324 and the secondary memory interface 326, and the command from the CPU 320 is stored in the mailbox 319 via the secondary memory interface 316 and the primary memory interface 314. After the mailbox 319 receives the command from the CPU 320, the mailbox 319 sends an interrupt signal to notify the core circuit 312. After receiving the interrupt signal from the mailbox 319, the core circuit 312 reads the command stored in the mailbox 319 through the primary memory interface 314 to perform the operation corresponding to the command. In this embodiment, because the primary memory interface 314 does not require any temporary register for the core circuit 312 to access the mailbox 319, the core circuit 312 can effectively obtain the command from the CPU 320. Similarly, if the CPU 310 needs to send a command to the CPU 320, the core circuit 312 sends the command to the AEI circuit 302 via the primary memory interface 314 and the secondary memory interface 316, and the command from the CPU 310 is stored in the mailbox 329 via the secondary memory interface 326 and the primary memory interface 324. After the mailbox 329 receives the command from the CPU 310, the mailbox 329 sends an interrupt signal to notify the core circuit 322. After receiving the interrupt signal from the mailbox 329, the core circuit 322 reads the command stored in the mailbox 329 through the primary memory interface 324 to perform the operation corresponding to the command. In this embodiment, because the primary memory interface 324 does not require any temporary register for the core circuit 322 to access the mailbox 329, the core circuit 322 can effectively obtain the command from the CPU 310.

[0045] Figure 4 FIG. 1 is a flowchart of the operation of the core circuit 312 / 322 according to an embodiment of the present invention. Figure 3 In the illustrated embodiment, the process is described as follows.

[0046] Step 400: The process starts.

[0047] Step 402: A core circuit of a source CPU writes a command into a primary memory interface.

[0048] Step 404: The secondary memory interface converts the command into an AEI master control interface of the AEI interconnect circuit.

[0049] Step 406 : If the AESI subordinate interface is ready, the process proceeds to step 408 ; if the AESI subordinate interface is not ready, the process returns to step 404 .

[0050] Step 408: Write the command into a secondary memory interface of a destination CPU.

[0051] Step 410: Write the command into the mailbox of the target CPU via the primary memory interface.

[0052] Step 412: The mailbox sends an interrupt signal to the core circuit of the target CPU.

[0053] Step 414: The core circuit reads the command stored in the mailbox through the primary memory interface.

[0054] Step 416: The process ends.

[0055] exist Figure 3 and Figure 4 In the illustrated embodiment, because the interface between the mailbox 319 / 329 and the AEIC circuit 302 is removed, the number of AEIC slave interfaces becomes smaller, and therefore, the complexity of the AEIC circuit 302 can be reduced to increase the frequency of the single-chip system 300.

[0056] Figure 5 FIG. 5 is a schematic diagram of a single-chip system 500 according to another embodiment of the present invention. Figure 5 As shown, the single-chip system 500 includes a plurality of central processing units 510, 520 and a flash memory controller 530, wherein the single-chip system 500 is coupled to a host 502, a dynamic random access memory (DRAM) and a flash memory module 506. In this embodiment, the single-chip system 500 is used in a solid state drive (SSD), and the solid state drive can be applied to any appropriate electronic device, such as a server. Taking the server including the single-chip system 500 as an example, the host 502 can be a processor in the server.

[0057] Figure 5The central processing unit 510 shown can be implemented by the central processing unit 110 / 310, and the central processing unit 520 can be implemented by the central processing unit 120 / 320, that is, the mailbox of the central processing unit 510 is designed in a tightly coupled memory, and the commands from the central processing unit 520 are stored in the mailbox, and the mailbox can be directly accessed by the core circuit of the central processing unit 510 without performing any communication protocol conversion; similarly, the mailbox of the central processing unit 520 is designed in a tightly coupled memory, and the commands from the central processing unit 510 are stored in the mailbox, and the mailbox can be directly accessed by the core circuit of the central processing unit 520 without performing any communication protocol conversion.

[0058] exist Figure 5 In the illustrated embodiment, the CPU 510 is used to perform operations related to the host 502, and the CPU 520 is used to perform operations related to the flash memory controller 530. Specifically, when the host 502 sends an access command (hereinafter, a write command is referred to as the access command) and corresponding data to the single chip system 500, the CPU 510 writes the received data into the dynamic random access memory 504 and sends a command corresponding to the received write command to the mailbox of the CPU 520, wherein the command sent by the CPU 510 may include a write instruction and a logical address of the data. Then, the CPU 520 obtains the command stored in the mailbox, and the CPU 520 refers to the command to control the flash memory controller 530 to write the data into the flash memory module 506. In one embodiment, the CPU 520 may read the data from the dynamic random access memory 504, and then send the data with a write command to the flash memory controller 530. In another embodiment, the CPU 520 may send a write command with the logical address of the data to the flash memory controller 530 , and then the flash memory controller 530 retrieves the data from the dynamic random access memory 504 based on the received logical address of the data.

[0059] In short, in the single-chip system of the present invention, by designing a mailbox in the primary memory system (i.e., tightly coupled memory), the central processing unit can read commands from the mailbox without performing communication protocol conversion, i.e., the central processing unit can effectively read the command from the mailbox.

[0060] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A single chip system comprising: A first central processing unit, wherein the first central processing unit comprises a first core circuit, a first level 1 memory interface and a first level 2 memory interface; a first tightly coupled memory, wherein the first tightly coupled memory is directly coupled to the first level 1 memory interface, and the first tightly coupled memory includes a first mailbox; A second central processing unit, wherein the second central processing unit includes a second core circuit, a second first-level memory interface and a second second-level memory interface; as well as a second tightly coupled memory, wherein the second tightly coupled memory is directly coupled to the second level 1 memory interface, and the second tightly coupled memory includes a second mailbox; When the first central processor sends a command to the second mailbox in the second tightly coupled memory, the second core circuit directly reads the command from the second mailbox without passing through the second secondary memory interface; The single-chip system further includes a bus for communication between the first central processing unit and the second central processing unit. The second core circuit needs to access the bus via the second second-level memory interface, and the second first-level memory interface is not directly coupled to the bus; and the second second-level memory interface performs a communication protocol conversion when data passes through, and the second first-level memory interface does not perform any communication protocol conversion when the second core circuit reads the second mailbox.

2. The single chip system as claimed in claim 1, characterized in that: The second mailbox is coupled to the bus, and the first CPU sends the command to the second mailbox in the second tightly coupled memory without passing through the second primary memory interface and the second secondary memory interface.

3. The single chip system as claimed in claim 1, characterized in that: The first central processor transmits the command to the second mailbox in the second tightly coupled memory via the second primary memory interface and the second secondary memory interface.

4. The single chip system as claimed in claim 3, characterized in that: The second mailbox is not directly coupled to the bus.

5. The single chip system as claimed in claim 4, characterized in that: When the power of the single-chip system is turned on, a loader reads a program code from a read-only memory and writes the program code into the first tightly coupled memory and the second tightly coupled memory to complete an initialization step of the single-chip system; And after the initialization step is completed, the loader does not use the bus, and the first central processor transmits the command to the second mailbox in the second tightly coupled memory via the bus, the second secondary memory interface and the second primary memory interface.

6. A single chip system comprising: A first central processing unit, wherein the first central processing unit comprises a first core circuit, a first level 1 memory interface and a first level 2 memory interface; a first tightly coupled memory, wherein the first tightly coupled memory is directly coupled to the first level 1 memory interface, and the first tightly coupled memory includes a first mailbox; A second central processing unit, wherein the second central processing unit includes a second core circuit, a second first-level memory interface and a second second-level memory interface; as well as a second tightly coupled memory, wherein the second tightly coupled memory is directly coupled to the second level 1 memory interface, and the second tightly coupled memory includes a second mailbox; as well as a flash memory controller, coupled to the second CPU, for accessing a flash memory module located outside the single-chip system; When the first CPU transmits an access command to the second mailbox in the second tightly coupled memory, the second core circuit directly reads the access command from the second mailbox without passing through the second secondary memory interface; and the second core circuit further transmits a command corresponding to the access command to the flash memory controller to control the flash memory controller to access the flash memory module; The single-chip system further includes a bus for communication between the first central processing unit and the second central processing unit. The second core circuit needs to access the bus via the second second-level memory interface, and the second first-level memory interface is not directly coupled to the bus; and the second second-level memory interface performs a communication protocol conversion when data passes through, and the second first-level memory interface does not perform any communication protocol conversion when the second core circuit reads the second mailbox.

7. The single chip system as claimed in claim 6, characterized in that: The second mailbox is coupled to the bus, and the first CPU sends the command to the second mailbox in the second tightly coupled memory without passing through the second primary memory interface and the second secondary memory interface.

8. The single chip system as claimed in claim 6, characterized in that: The first central processor transmits the command to the second mailbox in the second tightly coupled memory via the second primary memory interface and the second secondary memory interface.

9. The single chip system as claimed in claim 8, characterized in that: The second mailbox is not directly coupled to the bus.

10. The single chip system according to claim 9, characterized in that: When the power of the single-chip system is turned on, a loader reads a program code from a read-only memory and writes the program code into the first tightly coupled memory and the second tightly coupled memory to complete an initialization step of the single-chip system; And after the initialization step is completed, the loader does not use the bus, and the first central processor transmits the command to the second mailbox in the second tightly coupled memory via the bus, the second secondary memory interface and the second primary memory interface.

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