Page buffer, memory device including the same, and operating method thereof

Abstract

This application relates to page buffers, memory devices including the page buffers, and methods of operating the same. A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell via a bit line and is configured to sense a threshold voltage of the memory cell via a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node and to detect defects in the page buffer based on the leakage current value of the sensing node.

Description

Technical Field

[0001] This disclosure generally relates to electronic devices, and more specifically to memory devices and methods of operating the memory devices. Background Technology

[0002] A storage device is a means of storing data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are memory devices that store data only when powered on and lose the stored data when power is interrupted. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0004] Non-volatile memory devices are memory devices whose data is not lost even when power is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0005] According to one aspect of this disclosure, a memory device may be provided, comprising: a page buffer connected to a memory cell via a bit line, the page buffer being configured to sense a threshold voltage of the memory cell via a potential of a sensing node electrically connected to the bit line; a voltage generator configured to generate a test voltage to be applied to the sensing node; and a test controller configured to control the voltage generator to apply the test voltage to the sensing node and to detect defects in the page buffer based on a leakage current value of the sensing node.

[0006] According to another aspect of this disclosure, a method for operating a memory device including a page buffer connected to memory cells via bit lines can be provided, the method comprising: generating a test voltage; applying the test voltage to a sensing node electrically connected to the bit lines in the page buffer to sense a threshold voltage of the memory cell; and detecting a defect in the page buffer based on a leakage current value of the sensing node.

[0007] According to another aspect of this disclosure, a page buffer can be provided, comprising: a first switch connected between a bit line and a common sensing node; a second switch and a third switch connected in series between a power supply node and a sensing node; a fourth switch connected between the common sensing node and the sensing node; and a fifth switch and a sixth switch connected in series between a ground voltage node and the sensing node, wherein the page buffer applies a test voltage to the sensing node through the power supply node by disconnecting the first switch and the sixth switch and turning on the second switch and the third switch, and applies a test voltage to the common sensing node depending on whether the fourth switch is turned on. Attached Figure Description

[0008] Examples of embodiments will now be described more fully below with reference to the accompanying drawings. However, they may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein.

[0009] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between those two elements, or there may be one or more intermediate elements. Throughout the text, similar reference numerals denote similar elements.

[0010] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 This is an example Figure 1 A diagram showing the structure of the memory device.

[0012] Figure 3 This is an example Figure 2 The diagram shows a memory cell array.

[0013] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 2 The diagram shows the page buffer.

[0014] Figure 5A This is a timing diagram illustrating the operation of a page buffer according to an embodiment of the present disclosure.

[0015] Figure 5B This is a timing diagram illustrating the operation of a page buffer according to an embodiment of the present disclosure.

[0016] Figure 6 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0017] Figure 7 This is a block diagram illustrating a memory card system that utilizes a storage device according to an embodiment of the present disclosure.

[0018] Figure 8 This is a block diagram illustrating a solid-state drive (SSD) using a storage device according to an embodiment of the present disclosure.

[0019] Figure 9 This is a block diagram illustrating a user system that utilizes a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0020] The specific structural or functional descriptions disclosed herein are merely illustrative of embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to those presented herein.

[0021] Implementations may provide a memory device with improved page buffer test performance and a method of operating the memory device.

[0022] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0023] Reference Figure 1 The storage device 50 may include a memory device 100 and a memory controller 200 configured to control the operation of the memory device 100. The storage device 50 may be a means for storing data under the control of a host device such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0024] Depending on the host interface, which serves as the communication scheme with the host, the storage device 50 can be manufactured as any of various types of storage devices. For example, the storage device 50 can be implemented using any of the following types of storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), miniature MMC (RS-MMC), micro-MMC, secure digital card (SD), mini SD card, micro SD card, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash memory (CF) card, smart media card (SMC), memory stick, etc.

[0025] Storage device 50 can be manufactured in any of a variety of package types. For example, storage device 50 can be manufactured in any of the following package types: package stack-up (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stack-up package (WSP).

[0026] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array comprising a plurality of memory cells for storing data.

[0027] Each memory cell can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0028] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100.

[0029] A memory block can be a unit used to erase data. In embodiments, the memory device 100 can be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, the case where the memory device 100 is NAND flash memory is assumed and described.

[0030] The memory device 100 receives commands and addresses from the memory controller 200 and accesses the region in the memory cell array selected by the address. That is, the memory device 100 can perform the operation instructed by the command on the region selected by the address. For example, the memory device 100 can perform write (programming) operations, read operations, and erase operations. In a programming operation, the memory device 100 can program data into the region selected by the address. In a read operation, the memory device 100 can read data from the region selected by the address. In an erase operation, the memory device 100 can erase the data stored in the region selected by the address.

[0031] The memory controller 200 can control the overall operation of the storage device 50.

[0032] When power is applied to storage device 50, memory controller 200 can execute firmware (FW). When storage device 100 is a flash memory device, memory controller 200 can execute FW such as flash translation layer (FTL) for controlling communication between host and storage device 100.

[0033] In one implementation, the memory controller 200 may receive data and logical block addresses (LBAs) from the host and convert the LBAs into physical block addresses (PBAs), which represent the addresses of memory cells included in the memory device 100 in which data will be stored.

[0034] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, erase operations, etc., in response to requests from the host. During programming operations, the memory controller 200 can provide programming commands, PBAs, and data to the memory device 100. During read operations, the memory controller 200 can provide read commands and PBAs to the memory device 100. During erase operations, the memory controller 200 can provide erase commands and PBAs to the memory device 100.

[0035] In this implementation, the memory controller 200 can autonomously generate commands, addresses, and data independent of requests from the host, and send these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform background operations such as programming operations for wear leveling and programming operations for garbage collection.

[0036] In this implementation, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices according to an interleaving scheme to improve operational performance. The interleaving scheme can be an operation scheme that allows the operation periods of at least two memory devices 100 to overlap with each other.

[0037] The host can communicate with the storage device 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCIe, High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-off DIMM (LRDIMM).

[0038] Figure 2This is an example Figure 1 A diagram showing the structure of the memory device.

[0039] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130. The control logic 130 may be implemented in hardware, software, or a combination of both. For example, the control logic 130 may be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0040] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz are connected to the read / write circuitry 123 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells may be defined as a physical page. That is, the memory cell array 110 may be configured with a plurality of physical pages. According to an embodiment of the present disclosure, each of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 may include a plurality of dummy cells. One or more dummy cells may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0041] Each memory cell of the memory device can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0042] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read / write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0043] Peripheral circuitry 120 drives memory cell array 110. For example, peripheral circuitry 120 can drive memory cell array 110 to perform programming operations, read operations, and erase operations.

[0044] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include normal word lines and dummy word lines. According to embodiments of this disclosure, row lines RL may further include tubular select lines.

[0045] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0046] Address decoder 121 decodes the block address in the received address ADDR. Address decoder 121 selects at least one memory block from BLK1 to BLKz based on the decoded block address. Address decoder 121 can also decode the row address in the received address ADDR. Address decoder 121 can select at least one word line from the word lines of the selected memory block based on the decoded row address. Address decoder 121 can apply an operating voltage Vop provided by voltage generator 122 to the selected word line.

[0047] During programming, the address decoder 121 can apply a programming voltage to the selected word line and a pass voltage with a level lower than the programming voltage to the unselected word line. During programming verification, the address decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage with a level higher than the verification voltage to the unselected word line.

[0048] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and a read pass voltage at a level higher than the read voltage to the unselected word line.

[0049] According to embodiments of this disclosure, the erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the address ADDR input to the memory device 100 includes a block address. The address decoder 121 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0050] According to embodiments of this disclosure, address decoder 121 can decode a column address in address ADDR sent to it. The decoded column address can be sent to read / write circuitry 123. In an example, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0051] Voltage generator 122 can use the external power supply voltage provided to memory device 100 to generate multiple operating voltages Vop. Voltage generator 122 can operate under the control of control logic 130.

[0052] In this embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operating voltage of the memory device 100.

[0053] In this implementation, voltage generator 122 can generate multiple operating voltages Vop by using an external power supply voltage or an internal power supply voltage. Voltage generator 122 can generate various voltages required by the memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0054] In order to generate multiple operating voltages Vop with various voltage levels, voltage generator 122 may include multiple pump capacitors for receiving internal power supply voltages, and generate multiple operating voltages Vop by selectively activating the multiple pump capacitors under the control of control logic 130.

[0055] The generated multiple voltages Vop can be supplied to the memory cell array 110 by the address decoder 121.

[0056] The read / write circuit 123 includes first page buffers PB1 to m-th page buffers PBm. First page buffers PB1 to m-th page buffers PBm are connected to the memory cell array 110 via corresponding first bit lines BL1 to m-th bit lines BLm. First page buffers PB1 to m-th page buffers PBm operate under the control of control logic 130.

[0057] The first page buffer PB1 to the m-th page buffer PBm communicate with the data input / output circuit 124 to receive the data DATA to be stored through the data input / output circuit 124 and the data line DL.

[0058] During programming, when a programming pulse is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit the data DATA received through the data input / output circuit 124 to the selected memory cell via bit lines BL1 to BLm. The memory cell of the selected memory cell is programmed according to the transmitted data DATA. Memory cells connected to bit lines where a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines where a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification, the first page buffer PB1 to the m-th page buffer PBm read the data DATA stored in the selected memory cell from the selected memory cell via bit lines BL1 to BLm.

[0059] In the read operation, the read / write circuit 123 reads data DATA from the memory cell of the selected page through the bit line BL, and stores the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0060] During the erase operation, the read / write circuit 123 can float the bit line BL. In one embodiment, the read / write circuit 123 may include a column select circuit.

[0061] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 operates under the control of the control logic 130.

[0062] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 outputs data sent from the first page buffer PB1 to the m-th page buffer PBm included in the read / write circuit 123 to the external controller.

[0063] During a read or verification operation, the sensing circuit 125 may generate a reference current in response to the enable bit VRYBIT signal generated by the control logic 130, and output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the read / write circuit 123 with the reference voltage generated by the reference current.

[0064] Control logic 130 can be connected to address decoder 121, voltage generator 122, read / write circuit 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0065] Control logic 130 can control peripheral circuit 120 by generating several signals in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, row address RADD, read / write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to address decoder 121, read / write circuit control signal PBSIGNALS to read / write circuit 123, and enable bit VRYBIT to sensing circuit 125. In addition, control logic 130 can determine whether the verification operation has passed or failed in response to pass signal PASS or failure signal FAIL output by sensing circuit 125.

[0066] In an implementation, control logic 130 may include a test controller 131 and a test information storage device 132.

[0067] Test controller 131 can detect defects in the page buffer included in read / write circuit 123. Test controller 131 can control voltage generator 122 to generate a test voltage to be applied to the sensing node of the page buffer. In one embodiment, voltage generator 122 can generate a power supply voltage based on an external voltage. Voltage generator 122 can generate the test voltage based on either an external voltage or a power supply voltage.

[0068] Test controller 131 can determine the leakage current value of the sensing node based on the potential change of the sensing node after a test voltage is applied. Test controller 131 can detect defects in the page buffer based on the result obtained by comparing the leakage current value with a reference value. For example, when the leakage current value exceeds the reference value, test controller 131 can determine that there is a defect in the page buffer.

[0069] In one embodiment, the operation in which the test controller 131 detects defects in the page buffer by applying a test voltage to the sensing node can be performed during wafer testing. However, the timing of performing the operation to detect defects in the page buffer is not limited to this embodiment.

[0070] When a defect in the page buffer is detected, the test information storage 132 can store information about the memory block including the memory cells connected to the page buffer. The corresponding memory block can be set as a bad block.

[0071] Figure 3 This is an example Figure 2 The diagram shows a memory cell array.

[0072] Reference Figure 3 The first storage block BLK1 to the z-th storage block BLKz are all connected to the first bit line BL1 to the m-th bit line BLm. Figure 3 For ease of description, the components included in the first storage block BLK1 of a plurality of storage blocks BLK1 to BLKz are illustrated, and the components included in each of the other storage blocks BLK2 to BLKz are omitted. It will be understood that each of the other storage blocks BLK2 to BLKz is configured identically to the first storage block BLK1.

[0073] The memory block BLK1 may include multiple cell strings CS1_1 to CS1_m (m is a positive integer). The first cell string CS1_1 to the m-th cell string CS1_m are respectively connected to the first bit line BL1 to the m-th bit line BLm. Each of the first cell string CS1_1 to the m-th cell string CS1_m includes a drain selection transistor DST, multiple memory cells MC1 to MCn (n is a positive integer) connected in series, and a source selection transistor SST.

[0074] The gate terminal of the drain select transistor DST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m is connected to the drain select line DSL1. The gate terminals of the first memory cell MC1 to the n-th memory cell MCn included in each of the first unit strings CS1_1 to the m-th unit string CS1_m are respectively connected to the first word line WL1 to the n-th word line WLn. The gate terminal of the source select transistor SST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m is connected to the source select line SSL1.

[0075] For ease of description, the structure of the unit strings will be described based on the first unit string CS1_1 among multiple unit strings CS1_1 to CS1_m. However, it will be understood that each of the other unit strings CS1_2 to CS1_m is configured in the same way as the first unit string CS1_1.

[0076] The drain terminal of the drain select transistor DST included in the first cell string CS1_1 is connected to the first bit line BL1. The source terminal of the drain select transistor DST included in the first cell string CS1_1 is connected to the drain terminal of the first memory cell MC1 included in the first cell string CS1_1. The first memory cells MC1 to the nth memory cell MCn are connected in series with each other. The drain terminal of the source select transistor SST included in the first cell string CS1_1 is connected to the source terminal of the nth memory cell MCn included in the first cell string CS1_1. The source terminal of the source select transistor SST included in the first cell string CS1_1 is connected to the common source line CSL. In an embodiment, the common source line CSL can be commonly connected to the first memory block BLK1 to the zth memory block BLKz.

[0077] Drain select line DSL1, first word line WL1 to nth word line WLn, and source select line SSL1 are included. Figure 2 In the row line RL shown, the drain selection line DSL1, the first word lines WL1 to the nth word lines WLn, and the source selection line SSL1 are connected by... Figure 2 The address decoder 121 shown is controlled by [the controller / controller]. The common source line CSL can be [controlled / managed / controlled]. Figure 2 The control logic 130 shown is used for control. The first bit line BL1 to the m-th bit line BLm are controlled by... Figure 2 The read / write circuit 123 shown is controlled by this circuit.

[0078] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 2 The diagram shows the page buffer.

[0079] Reference Figure 4The page buffer can be connected to the memory cell via bit line BL. The page buffer may include a first switch S1 to a sixth switch S6 and a latch. The page buffer may additionally include a seventh switch S7 and an eighth switch S8.

[0080] exist Figure 4 In this configuration, the first switch S1 can be connected between the bit line BL and the common sensing node CSO, and the first switch S1 is controlled according to the page buffer signal PB_SENSE.

[0081] The second switch S2 and the third switch S3 can be connected in series between the power supply node and the sensing node SO. The second switch S2 can be controlled according to the data signal QS stored in the latch. The third switch S3 can be controlled according to the precharge signal SA_PRECH_N.

[0082] The fourth switch S4 can be connected between the common sensing node CSO and the sensing node SO, and the fourth switch S4 is controlled according to the sensing transmission signal SA_SENSE.

[0083] The fifth switch S5 and the sixth switch S6 can be connected in series between the ground voltage node and the sensing node SO. The fifth switch S5 can be controlled according to the discharge signal SA_DISCH. The sixth switch S6 can be controlled according to the data signal QS stored in the latch.

[0084] The seventh switch S7 can be connected between the common sensing node CSO and the connection points of the second switch S2 and the third switch S3. The seventh switch S7 can be controlled according to the precharge transmission signal SA_CSOC.

[0085] The eighth switch S8 can be connected between the latch and the ground voltage node, and the eighth switch S8 can be controlled according to the potential value of the sensing node SO.

[0086] In one implementation, a power supply voltage VCORE generated based on an external voltage can be applied to the power node. In another implementation, an external voltage can be applied to the power node. The voltage applied to the power node is not limited to this implementation.

[0087] exist Figure 4In this process, the page buffer can apply a test voltage to the sensing node S0 through the power node for a predetermined time. For example, the page buffer can turn off the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 for a predetermined time, and turn on the second switch S2 and the third switch S3 for a predetermined time. As used herein with respect to a parameter, the term "predetermined" (such as "predetermined time") means that the value of the parameter is determined before it is used in the process or algorithm. In some implementations, the value of the parameter is determined before the process or algorithm begins. In other implementations, the value of the parameter is determined during the process or algorithm, but before it is used in the process or algorithm.

[0088] In another embodiment, the page buffer can apply a test voltage to the sensing node SO and the common sensing node CSO through the power supply node for a predetermined time. For example, the page buffer can turn off the first switch S1, the fifth switch S5, and the sixth switch S6 and turn on the second switch S2, the third switch S3, and the fourth switch S4 for a predetermined time.

[0089] The page buffer can apply a low-level page buffer signal PB_SENSE to the first switch S1 for a predetermined time. The page buffer can apply a low-level pre-charge signal SA_PRECH_N to the third switch S3. The page buffer can apply a low-level sense transmission signal SA_SENSE to the fourth switch S4. The page buffer can apply a low-level or high-level discharge signal SA_DISCH to the fifth switch S5. The page buffer can apply a low-level data signal QS to the second switch S2 and the sixth switch S6. The test voltage can be applied only to the sensing node SO. The data signal QS stored in the latch can be set low before the test voltage is applied to the sensing node SO.

[0090] In this implementation, the page buffer can apply a low-level page buffer signal PB_SENSE to the first switch S1 for a predetermined time. The page buffer can apply a low-level pre-charge signal SA_PRECH_N to the third switch S3. The page buffer can apply a high-level sensing transmission signal SA_SENSE to the fourth switch S4. The page buffer can apply a low-level or high-level discharge signal SA_DISCH to the fifth switch S5. The page buffer can apply a low-level data signal QS to the second switch S2 and the sixth switch S6. In this implementation, the data signal QS stored in the latch before the test voltage is applied to the sensing node SO can be set to a low level. The test voltage can be applied to the sensing node SO and the common sensing node CSO. The data signal QS stored in the latch before the test voltage is applied to the sensing node SO and the common sensing node CSO can be set to a low level.

[0091] In this embodiment, the first switch S1 and the fourth switches S4 through the eighth switches S8 may include NMOS transistors. The second switch S2 and the third switch S3 may include PMOS (i.e., positive metal-oxide-semiconductor) transistors. However, the transistors included in each switch are not limited to this embodiment. PMOS transistors can be used instead of NMOS (i.e., negative metal-oxide-semiconductor) transistors. Conversely, NMOS transistors can be used instead of PMOS transistors.

[0092] Figure 5A This is a timing diagram illustrating the operation of a page buffer according to an embodiment of the present disclosure.

[0093] Reference Figure 5A The page buffer can enter test mode based on requests from outside the memory device. The page buffer can enter test mode during wafer testing. After a predetermined time has elapsed since entering test mode, the page buffer can exit test mode.

[0094] Reference Figure 4 and Figure 5A Before the page buffer enters test mode, the page buffer signal PB_SENSE can be set low. The precharge transfer signal SA_CSOC can be set low. The discharge signal SA_DISCH can be set low. The sense transfer signal SA_SENSE can be set low. The data signal QS stored in the latch can be set low. When the page buffer enters test mode, the precharge signal SA_PRECH_N can be set low.

[0095] During a predetermined time period, a test voltage Vtest, transmitted through the power supply node, can be applied to the sensing node SO. The test voltage Vtest can be an external voltage or a power supply voltage generated based on an external voltage.

[0096] After the page buffer exits test mode, the leakage current value can be determined based on the change in the potential of the sensing node SO. Defects in the page buffer can be detected based on the result obtained from the leakage current value and a reference value.

[0097] For example, when the potential of sensing node SO drops by a constant width or more, it can be determined that a bridge exists between sensing node SO and the ground voltage node. That is, leakage current occurs at sensing node SO due to the bridge, and when the value of the leakage current exceeds the reference value, the data value of sensing node SO is unreliable. Therefore, it can be determined that the corresponding page buffer is defective.

[0098] Figure 5B This is a timing diagram illustrating the operation of a page buffer according to an embodiment of the present disclosure.

[0099] Reference Figure 5B ,and Figure 5A In contrast, the sensing transmission signal SA_SENSE can be set to high when the page buffer enters test mode. Other signals can be set as follows: Figure 5A Set it up as shown in the diagram.

[0100] During a predetermined period, a test voltage Vtest, transmitted via a power supply node, can be applied to the sensing node SO and the common sensing node CSO. The test voltage Vtest can be an external voltage or a power supply voltage generated based on an external voltage.

[0101] After the page buffer exits test mode, the leakage current value can be determined based on the changes in the potential of the sensing node SO and the common sensing node CSO. Defects in the page buffer can be detected based on the results obtained from the leakage current value and a reference value. This can be achieved as follows: Figure 5A The defects of the page buffer are determined as described in the document.

[0102] Figure 6 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0103] Reference Figure 6 In step S601, the memory device can generate a test voltage. The memory device can generate a power supply voltage based on an external voltage input from outside the memory device. The memory device can generate a test voltage based on either an external voltage or a power supply voltage.

[0104] In step S603, the memory device may apply a test voltage to the sensing node of the page buffer. The memory device may apply the test voltage to the sensing node of the page buffer during wafer testing. However, the timing of the test operation is not limited to this. The memory device may autonomously perform the test operation within itself. In various embodiments, test voltages may be applied to both the sensing node and the common sensing node.

[0105] In step S605, the memory device can detect defects in the page buffer based on the leakage current value of the sensing node.

[0106] In step S607, the memory device may manage the memory block corresponding to the page buffer in which a defect is detected as a bad block. The memory block corresponding to the page buffer may be a memory block that includes memory cells connected to the page buffer.

[0107] Figure 7 This is a block diagram illustrating a memory card system for an application storage device according to an embodiment of the present disclosure.

[0108] Reference Figure 7The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0109] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. For example, memory controller 2100 is configured to control read operations, write operations, erase operations, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and a host. Memory controller 2100 is configured to drive firmware for controlling memory device 2200. Memory controller 2100 can be used with reference to... Figure 1 The memory controller 200 described is implemented in the same way.

[0110] For example, memory controller 2100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and error corrector.

[0111] The memory controller 2100 can communicate with an external device via connector 2300. The memory controller 2100 can communicate with the external device (e.g., a host) according to a specific communication protocol. For example, the memory controller 2100 can communicate with the external device via at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (MCM), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0112] For example, memory device 2200 can be implemented by various non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0113] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and memory device 2200 can form memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory (CF) cards, smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC or eMMC), SD cards (SD, mini SD, micro SD or SDHC), and universal flash memory (UFS).

[0114] Figure 8 This is a block diagram illustrating a solid-state drive (SSD) using a storage device according to an embodiment of the present disclosure.

[0115] Reference Figure 8 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0116] According to embodiments of this disclosure, the SSD controller 3210 can be used as a reference. Figure 1 The memory controller 200 is described.

[0117] SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to a signal SIG received from host 3100. For example, the signal SIG can be a signal based on the interface between host 3100 and SSD 3200. For example, the signal SIG can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (MCM), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0118] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. When the power supply from host 3100 is unstable, auxiliary power supply 3230 can provide power to SSD 3200. For example, auxiliary power supply 3230 can be located inside or outside SSD 3200. For instance, auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to SSD 3200.

[0119] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, or temporarily store metadata (e.g., mapping tables) of flash memory modules 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0120] Figure 9 This is a block diagram illustrating a user system that utilizes a storage device according to an embodiment of the present disclosure.

[0121] Reference Figure 9 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0122] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0123] Memory module 4200 can operate as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, application processor 4100 and memory module 4200 can be provided as a single semiconductor package by being packaged based on a stacked package (POP).

[0124] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0125] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send the data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented using a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. For example, storage module 4400 can be provided as a removable drive or external drive such as a memory card in user system 4000.

[0126] For example, storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be used in conjunction with a reference. Figure 1 The memory device 100 described operates in the same manner. The storage module 4400 can be compared with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0127] User interface 4500 may include an interface for inputting data or commands to application processor 4100 or an interface for outputting data to external devices. For example, user interface 4500 may include user input interfaces such as: keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as: liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0128] According to this disclosure, a memory device with improved page buffer test performance and a method of operating the memory device can be provided.

[0129] Although this disclosure has been shown and described with reference to certain examples of embodiments thereof, those skilled in the art will understand that various modifications in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above-described examples of embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0130] In the embodiments described above, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps do not necessarily have to be performed in the described order but can be rearranged. The embodiments disclosed in this specification and drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0131] Furthermore, examples of embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is for the purpose of explaining embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

[0132] Cross-reference to related applications

[0133] This application claims priority to Korean Patent Application No. 10-2020-0134650, filed on October 16, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: A page buffer is connected to a memory cell via a bit line, and the page buffer senses the threshold voltage of the memory cell by the potential of a sensing node electrically connected to the bit line. A voltage generator that generates a test voltage to be applied to the sensing node; as well as A test controller applies the test voltage to the sensing node, disconnects the connection between the sensing node and the bit line while the test voltage is applied, and detects defects in the page buffer based on the leakage current value of the sensing node. After the test voltage is applied to the sensing node, the test controller keeps the sensing node disconnected from the bit line.

2. The memory device according to claim 1, wherein, The test controller determines the leakage current value of the sensing node based on the change in the potential of the sensing node after the test voltage is applied to the sensing node.

3. The memory device according to claim 2, wherein, The test controller detects defects in the page buffer based on the result obtained by comparing the leakage current value of the sensing node with a reference value.

4. The memory device of claim 1, further comprising a test information storage unit that stores information about a memory block including the memory cell connected to the page buffer when a defect of the page buffer is detected.

5. The memory device according to claim 1, wherein, The voltage generator generates a power supply voltage based on an external voltage, and generates the test voltage based on at least one of the external voltage and the power supply voltage.

6. A method for operating a memory device, the memory device including a page buffer connected to a memory cell via bit lines, the method comprising the steps of: Generate test voltage; In the page buffer, the test voltage is applied to a sensing node electrically connected to the bit line to sense the threshold voltage of the memory cell; Disconnect the connection between the sensing node and the bit line when the test voltage is applied to the sensing node; After the test voltage is applied to the sensing node, the connection between the sensing node and the bit line is maintained. as well as Defects in the page buffer are detected based on the leakage current value of the sensing node.

7. The method according to claim 6, wherein, The steps for detecting defects in the page buffer include the following: After the test voltage is applied to the sensing node, the leakage current value of the sensing node is determined based on the change in the potential of the sensing node; and The defect in the page buffer is detected based on the result obtained by comparing the leakage current value of the sensing node with a reference value.

8. The method according to claim 6, wherein, The steps for generating the test voltage include the following: Power supply voltage is generated based on external voltage; and The test voltage is generated based on at least one of the external voltage and the power supply voltage.

9. The method according to claim 6, further comprising the following step: When a defect in the page buffer is detected, information about a memory block including the memory cell connected to the page buffer is stored.

10. A page buffer, the page buffer comprising: A first switch is connected between the bit line and the common sensing node; The second switch and the third switch are connected in series between the power node and the sensing node; A fourth switch is connected between the common sensing node and the sensing node; as well as The fifth and sixth switches are connected in series between the ground voltage node and the sensing node. The page buffer applies a test voltage to the sensing node through the power node by disconnecting the first switch and the sixth switch and turning on the second switch and the third switch, and applies the test voltage to the common sensing node depending on whether the fourth switch is turned on.

11. The page buffer of claim 10, wherein, The page buffer applies an external voltage to the sensing node through the power node and at least one of a power supply voltage generated based on the external voltage as the test voltage.

12. The page buffer of claim 10, wherein, The page buffer: The first switch is controlled by the page buffer signal; The third switch is controlled by a pre-charge signal; The fourth switch is controlled by sensing and transmitting signals; The fifth switch is controlled by a discharge signal; as well as The second switch and the sixth switch are controlled by data signals stored in the latch.

13. The page buffer according to claim 12, wherein, The page buffer: The test voltage is applied to the sensing node within a predetermined time. as well as During the predetermined time period, a low-level pre-charge signal is applied to the third switch, a low-level sensing transmission signal is applied to the fourth switch, and a low-level data signal is applied to the second switch and the sixth switch.

14. The page buffer of claim 12, wherein, The page buffer: The test voltage is applied to the sensing node and the common sensing node within a predetermined time. as well as During the predetermined time period, a low-level pre-charge signal is applied to the third switch, a high-level sensing transmission signal is applied to the fourth switch, and a low-level data signal is applied to the second and sixth switches.

15. The page buffer of claim 10, wherein, The first switch and the fourth to sixth switches include NMOS transistors, and The second switch and the third switch both include PMOS transistors.

Images