Electrical test structure for monitoring side wall fusion distance conditions and its location selection method

Abstract

The present invention provides an electrical test structure for monitoring the distance conditions of spacer fusion, including several test units; the test unit includes at least one test group; the test group includes a first mandrel to be tested and a second mandrel to be tested, and several fins, which are adjacent to each other at a preset interval; the left end of the first mandrel to be tested is provided with a fin cut-off area, and the right end is provided with a first connecting structure; the right end of the second mandrel to be tested is provided with a fin cut-off area, and the left end is provided with a second connecting structure. The electrical test structure of the present invention is easy to prepare, can quickly perform electrical tests to obtain electrical parameters, and efficiently determine the distance conditions of spacer fusion; it is suitable for monitoring the distance of Spacer Merge in the Fin manufacturing process, which is beneficial to improving the efficiency of process monitoring, and provides a solution for breaking through the existing limitations of spacer fusion technology. The position selection method also provided by the present invention can efficiently and intuitively select the placement position of the electrical test structure of the present invention, realize more effective monitoring of the properties of different areas of the chip, and make the test results more accurate and comprehensive.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device testing, design and manufacturing technology, and in particular relates to an electrical test structure for obtaining sidewall fusion distance condition monitoring and a method for selecting a position for placing the electrical test structure on a chip. Background Art

[0002] With the continuous development of large-scale integrated circuit technology, the integration of circuits continues to increase. When the process technology node is less than 28nm, there is a trend that traditional planar MOS devices are gradually replaced by three-dimensional fin field effect transistors (FinFETs) due to the sharp degradation of performance. Compared with planar transistors, FinFETs generally include semiconductor substrates, oxide layers, and gate structures. A protruding structure is formed on the semiconductor substrate. The oxide layer covers the surface of the semiconductor substrate and a part of the sidewall of the protruding structure. The part of the protruding structure that exceeds the oxide layer becomes the fin of the FinFET. The gate structure spans over the fin and covers the top and sidewalls of the fin. The gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer. For FinFET, the top of the fin and the part of the sidewalls on both sides that contact the gate structure become channel regions, that is, there are multiple gates, which is conducive to increasing the drive current and improving device performance.

[0003] The extremely critical step in the FinFET process is the preparation of the Fin. In order to increase the integration density of semiconductor devices, the existing technology uses self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) to prepare Fins. When the FinFET process technology node enters below 7 nanometers, SAQP technology replaces SADP technology, and the process complexity is correspondingly increased by at least one time. In SAQP technology, two Spacers (sidewalls) are deposited on both sides of a Mandrel (core axis), and four Spacers are deposited on both sides of the two Spacers. Generally, four Fins with equal spacing are finally obtained. In practical applications, users inevitably need some Fins with special structures, such as some non-uniform Fins and special Fin Pitch (Fin spacing). Spacer Merge (sidewall fusion) is a key technology for preparing these special Fin structures. By adjusting the distance between the two Mandrels, when the two Spacer1s overlap, the Fin between the mandrels disappears, and a Fin structure with a special pitch (spacing) and number of roots can be prepared. Among them, obtaining the Mandrel distance during Spacer Merge is the key to the success of this technology. At present, the distance condition of Spacer Merge is mainly obtained by optical means. The distance during Spacer Merge is determined by observing the number of Fin roots at different Mandrel distances. This method is time-consuming and cannot be used for large-scale observations or simultaneous testing of a large number of samples. In order to obtain the distance condition of Spacer Merge (i.e., the distance of the core axis during sidewall fusion), the existing method is used, but the overall test efficiency is limited and cannot be continuously optimized, and the process monitoring speed is difficult to further improve. The development of sidewall fusion technology has therefore also had obvious limitations.

[0004] Therefore, there is a great need to study an electrical test structure for monitoring the distance conditions of side wall fusion and a method for selecting the position of the corresponding electrical test structure on the chip, which can be used to obtain electrical parameters through electrical measurement to analyze the distance conditions of side wall fusion, change the existing practice of relying on optical means to obtain the distance conditions of side wall fusion, realize large-area testing, effectively monitor the properties of different areas of the chip, and the test results are accurate and comprehensive, so as to further promote the in-depth development and wide application of semiconductor device testing and manufacturing technology. Summary of the invention

[0005] The present invention is to solve all or part of the problems of the above-mentioned prior art. On one hand, the present invention provides an electrical test structure for monitoring the distance condition of the sidewall fusion, which is suitable for obtaining electrical parameters through electrical measurement to obtain the distance condition of the sidewall fusion. Another aspect of the present invention provides a method for selecting the position of the electrical test structure, and selects a position on the chip to place the electrical test structure provided by the present invention.

[0006] On one hand, the present invention provides an electrical test structure for monitoring the sidewall fusion distance condition, comprising a plurality of test units; the test unit comprises at least one test group, the test group comprises a first and a second mandrel to be tested with adjacent preset spacings, and a plurality of fins made from the first mandrel to be tested and the second mandrel to be tested; the first mandrel to be tested is provided with a fin cut-off area at the left end, and a first connecting structure at the right end; the second mandrel to be tested is provided with a fin cut-off area at the right end, and a second connecting structure at the left end. When the electrical test structure contains more than two test units or test groups, the preset spacings between the first and second mandrels to be tested of different test units may be different; the number of test groups in different test units may be the same or different.

[0007] There are at least two test groups; the first connection structure and the second connection structure respectively connect the first core shaft to be tested and the second core shaft to be tested, and the test groups are connected in parallel. By connecting the test groups in parallel through the first connection structure and the second connection structure, the current value between the first connection structure and the second connection structure at both ends can be measured. The current value is measured for each test unit or each test group, and a curve of the current value changing with the preset spacing of different test units or different test groups can be drawn in the coordinate system. The value of the preset spacing at the time of the mutation is determined by the mutation position of the current value, and this value is used as the distance between adjacent core shafts when the side walls are fused.

[0008] The first connection structure and the second connection structure include metal wires of the M0 metal layer.

[0009] The first mandrel to be tested and the second mandrel to be tested are parallel to each other. That is, the first mandrel to be tested and the second mandrel to be tested in the same test group are parallel to each other, and are parallel to the first mandrel to be tested and the second mandrel to be tested in another test group. The mandrels to be tested arranged in parallel with each other are easier to prepare, which is conducive to simplifying the process, reducing the resources consumed in preparing the test structure, and optimizing the allocation of production resources.

[0010] The electrical test structure also includes a substrate and a lead-out structure connected to the substrate; the test unit is placed on the substrate and electrically connected to the substrate. The test unit is directly placed on the substrate to facilitate the preparation of the electrical test structure and simplify the production of winding and connection structures.

[0011] The electrical test structure further includes a power supply circuit, which is electrically connected to the lead-out structure, the first connection structure and the second connection structure respectively; the power supply circuit includes a voltage source.

[0012] The voltage source is connected to the lead-out structure to provide a reverse bias voltage to the substrate. The voltage source is also connected to the first connection structure and the second connection structure respectively to apply high voltage and low voltage respectively. The electrical test structure includes a power supply circuit that can directly perform electrical testing to obtain electrical parameters for analysis and obtain results without relying on the setting of an external circuit, simplifying the circuit connection structure and test operation. The voltage source can be directly started to power on the test, which is quick and convenient, the test operation is integrated, the efficiency is higher, and it is conducive to reducing the operation deviation caused by the implementation of multiple links.

[0013] Another aspect of the present invention provides a method for selecting and placing positions, which uses the LIoyd algorithm to perform clustering selection on positions, and the specific steps are: S1. Determine the number of test structures required to place a chip to be tested with a length of L and a width of W, which is recorded as n; S2. Randomly select n seed points in the chip to be tested as the center point of the class to be aggregated, and the coordinates of the n seed points are recorded as (x 0,1 ,y 0,1 ), (x 0,2 ,y 0,2 )……(x 0,n ,y 0,n ); S3. Take points evenly on the chip to be tested, and the interval between the points is denoted as d; the chip to be tested is divided into (L×W) / (d 2 ) points; S4. Calculate the distance from each point to the n seeds, assign each point to the nearest neighbor seed point, and cluster; S5. Use the center point of each cluster as the new seed, and the new coordinates are marked as (x 1,1 ,y 1,1 ), (x 1,2 ,y 1,2 )……(x 1,n ,y 1,n ); S6. The seed coordinates after repeating steps S2 to S5 m times are (x m,1 ,y m,1 ), (x m,2 ,y m,2 )···(x m,n ,y m,n ),until , stop repeating, and the final seed coordinates are the location points for selecting the test structures. According to the number of electrical test structures monitored under the sidewall fusion distance conditions required in a specific application, the positions are clustered and selected through the LIoyd algorithm to determine the coordinates of the placement positions of the electrical test structures, and the electrical test structures are evenly placed in different areas of the test chip, which is conducive to the effective monitoring of the properties of different areas of the chip. Characterizing the selected placement positions with the seed coordinates is more intuitive and convenient for guiding actual process operations.

[0014] In S3, the point interval d is determined according to the size of the test structure.

[0015] Compared with the prior art, the main beneficial effects of the present invention are:

[0016] 1. The electrical test structure for monitoring the distance condition of the sidewall fusion of the present invention has a simple structure and is easy to prepare. It can conveniently and quickly conduct electrical tests to obtain electrical parameters. The distance condition of the sidewall fusion can be determined efficiently and accurately through the analysis of the electrical parameters, and multiple sample tests can be completed over a large area. It is suitable for monitoring the distance of the Spacer Merge in the Fin manufacturing process in the FinFET process, which can improve the efficiency of process monitoring and the speed of new technology development, shorten the product maturity cycle, and speed up the product launch. It is very helpful to break through the limitations of the existing sidewall fusion technology and further promote the deep and rapid development of semiconductor testing and manufacturing technology.

[0017] 2. A position selection method of the present invention can efficiently and intuitively select the placement position of the electrical test structure of the present invention, and provides an effective and feasible solution for laying out the electrical test structure of the present invention on a test chip. It is easy to implement in combination with actual processes and is conducive to optimizing test efficiency. It can achieve more effective monitoring of the properties of different areas of the chip, making the test results more accurate and comprehensive, which is conducive to effectively guiding the further improvement of design and process. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a test unit diagram of the first embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of a test group according to Embodiment 1 of the present invention.

[0020] Figure 3 Schematic diagram of the relationship between current and preset spacing in Embodiment 1 of the present invention.

[0021] Figure 4 This is a schematic diagram of a test unit according to the second embodiment of the present invention.

[0022] Figure 5 Schematic diagram of the relationship between the resistor and the preset spacing according to the second embodiment of the present invention.

[0023] Figure 6 Schematic diagram of the relative relationship among the wafer, chip and electrical test structure of the third embodiment of the present invention.

[0024] Figure 7 Schematic diagram of the process of the position selection method according to the third embodiment of the present invention.

[0025] Figure 8 This is a schematic diagram for selecting the placement position of the electrical test structure according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0026] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings. In the drawings, parts with the same structure or function are marked with the same reference numerals, and for the sake of clarity, not all parts shown are marked with the corresponding reference numerals in all drawings when necessary.

[0027] In the following embodiments, operations of the embodiments are described in specific sequences. The description of these sequences is for better understanding of the details in the embodiments and a comprehensive understanding of the present invention, but is not intended to limit the scope of the present invention.

[0028] Embodiment 1

[0029] In the first embodiment of the present invention, in combination with reference Figure 1 and Figure 2 As shown, an exemplary distance condition electrical test structure of spacer fusion includes a substrate, a lead structure bodyPin connecting the substrate, and a plurality of test units electrically connected to the substrate. Figure 1 The test unit of the example is directly arranged on the substrate. For the convenience of description in conjunction with the accompanying drawings, it is taken as an example that each test unit includes two test groups. In actual applications, the electrical test structure can be provided with multiple test units or only one test unit according to the process design or layout design rules. There can also be more or only one test group in the test unit, which is not limited here. In the present embodiment, the first connection structure and the second connection structure that respectively connect the two ends of the test group are comb-shaped pins combPin1 and combPin2, including a number of metal wires located in the M0 metal layer. In order to simplify the drawings, the first connection structure and the second connection structure are illustrated by the entire rectangular M0 figure, and the actual shapes of the first connection structure and the second connection structure are not limited. The test group of the example, such as Figure 2As shown, it includes two mandrels Mandrel to be tested (i.e., a first mandrel to be tested and a second mandrel to be tested) with adjacent preset spacing Mandrel Space, and a plurality of fins Fin made from the mandrels Mandrel to be tested. The attached figure illustrates a plurality of fins Fin made from the mandrel Mandrel to be tested, including the fins Fin on both sides of the mandrel Mandrel to be tested and the fins Fin between them, but does not limit the positions of all fins Fin in practical applications. The preset spacing Mandrel Space of the two test units in the example is a different value. The mandrels Mandrel to be tested are parallel to each other, and the two mandrels Mandrel to be tested in the same test group are parallel to each other. In this embodiment, the mandrels Mandrel to be tested in different test groups are parallel to each other, and the mandrels Mandrel to be tested in different test units are also parallel to each other. The two ends of the test group are the two ends in the extension direction of the mandrel Mandrel to be tested, as shown in the attached figure. Figure 2 The observation angles are respectively the left end and the right end of the mandrel to be measured Mandrel. In this embodiment, the left end of the first mandrel to be measured Mandrel is provided with a fin cutting area Fin Cut; the right end of the other mandrel to be measured Mandrel, that is, the second mandrel to be measured, is provided with a fin cutting area Fin Cut.

[0030] In the present embodiment, in the same test group, the fin cut-off area Fin Cut is respectively arranged at different ends of each mandrel Mandrel to be tested; correspondingly, all the test groups of a test unit are connected in parallel through the first connection structure and the second connection structure (the example pins combPin1 and combPin2). The electrical test structure of the present embodiment also includes a power supply circuit (not shown), which is electrically connected to the lead-out structure bodyPin, the first connection structure combPin1 and the second connection structure combPin2, respectively. The example power supply circuit includes a voltage source, which is connected to the lead-out structure bodyPin to provide a reverse bias voltage to the substrate. The example lead-out structure bodyPin is also a metal wire located in the M0 metal layer. The voltage source also connects the first connection structure and the second connection structure at both ends of the test group, that is, the pins combPin1 and combPin2 apply a high voltage and a low voltage respectively. The current between the pins combPin1 and combPin2 of each test unit is measured respectively. In the example method, a curve of the current value obtained by the test as a function of the preset spacing of different test units is drawn in the coordinate system. As shown Figure 3 As shown, if the measured current value changes suddenly, that is, all the fins Fin between the mandrels to be tested disappear completely, then the preset spacing Mandrel Space corresponding to the test unit is the distance at which Spacer Merge is completed, thereby obtaining the side wall fusion distance condition.

[0031] Embodiment 2

[0032] like Figure 4 As shown, the difference between the second embodiment and the first embodiment is that the first connection structure and the second connection structure of the example are different from the first embodiment in that the pins snakePin1 and snakePin2 are arranged in a snake shape. Figure 4 The strip metal line of the M0 metal layer is also used as an illustration. The resistance between each test unit pin snakePin1 and snakePin2 is measured respectively, and a curve can also be drawn in the coordinate system, such as Figure 5 As shown, the preset spacing value corresponding to the resistance value mutation position is used as the distance between adjacent mandrels to be tested when the sidewalls are fused.

[0033] Embodiment 3

[0034] Embodiment 3 illustrates the method for selecting and placing positions of the present invention. Figure 6 As shown, there are multiple rectangular test chips c on the circular wafer of the example, and the electrical test structure s as shown in the example of the first or second embodiment needs to be placed on the test chip c. The electrical test structures s placed in the example are all electrical test structures with the same structure. The method of selecting the position of this example is as follows: Figure 7 As shown in FIG. 1 , the LIoyd algorithm is used to cluster the positions. The specific steps are as follows: S1. Determine the number of test structures required to place the chip under test with a length of L and a width of W, which is recorded as n; S2. Randomly select n seed points in the chip under test as the center point of the class to be aggregated, and the coordinates of the n seed points are recorded as (x 0,1 ,y 0,1 ), (x 0,2 ,y 0,2 )……(x 0,n ,y 0,n ); S3. Evenly select points on the chip to be tested, and the interval between the points is d; the chip to be tested is divided into (L×W) / (d 2 ) points; S4. Calculate the distance from each point to the n seeds, assign each point to the nearest neighbor seed point, and cluster; S5. Use the center point of each cluster as the new seed, and the new coordinates are marked as (x 1,1 ,y 1,1 ), (x 1,2 ,y 1,2 )……(x 1,n ,y 1,n ); S6. The seed coordinates after repeating steps S2 to S5 m times are (x m,1 ,y m,1 ), (x m,2 ,y m,2 )···(x m,n ,y m,n ),until , stop repeating, and the final seed coordinates are the locations where the test structures are selected. The length L and width W are obtained based on the corresponding measurements of the chip to be tested in actual production. In step S3 of the example, the point spacing d is determined based on the size of the test structure. In the example case, for a test structure s of 20µm×20µm, d can be 20µm. In a specific example, the locations where five and seven electrical test structures are selected are exemplified. Figure 8 shown.

[0035] Some commonly used English nouns or letters used in the present invention for the convenience of narration are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translation or specific letters. It should also be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. For those of ordinary skill in the art, without departing from the principle of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. An electrical test structure for monitoring the side wall fusion distance condition, characterized in that: Includes several test units; The test unit includes at least one test group, which includes a first and a second mandrel to be tested that are adjacent to each other at a preset interval, and a plurality of fins made from the first and the second mandrel to be tested; a fin cutting area is provided at the left end of the first mandrel to be tested, and a first connecting structure is provided at the right end; a fin cutting area is provided at the right end of the second mandrel to be tested, and a second connecting structure is provided at the left end.

2. The electrical test structure for monitoring the side wall fusion distance condition according to claim 1, characterized in that: There are at least two test groups; the first connection structure and the second connection structure respectively connect the first mandrel to be tested and the second mandrel to be tested, and the test groups are connected in parallel or in series.

3. The electrical test structure for monitoring the side wall fusion distance condition according to claim 1, characterized in that: The first connection structure and the second connection structure include metal wires of the M0 metal layer.

4. The electrical test structure for monitoring the side wall fusion distance condition according to claim 1, characterized in that: The first mandrel to be measured and the second mandrel to be measured are parallel to each other.

5. The electrical test structure for monitoring the side wall fusion distance condition according to any one of claims 1 to 4, characterized in that: The electrical test structure further includes a substrate and a lead-out structure connecting the substrate; the test unit is placed on the substrate and electrically connected to the substrate.

6. The electrical test structure for monitoring the side wall fusion distance condition according to claim 5, characterized in that: It also includes a power supply circuit, which is electrically connected to the lead-out structure, the first connection structure and the second connection structure respectively; the power supply circuit includes a voltage source.

7. The electrical test structure for monitoring the side wall fusion distance condition according to claim 6, characterized in that: The voltage source is connected to the lead-out structure to provide a reverse bias voltage to the substrate. The voltage source is also connected to the first connection structure and the second connection structure respectively to apply a high voltage and a low voltage respectively.

8. A method for selecting and placing a position, for selecting and placing a test structure according to any one of claims 1 to 7, characterized in that: The LIoyd algorithm is used to cluster the locations. The specific steps are as follows: S1. Determine the number of test structures required to be placed on the chip to be tested with a length of L and a width of W, denoted as n; S2. Randomly select n seed points in the chip to be tested as the center point of the class to be aggregated, and the coordinates of the n seed points are marked as (x 0,1 ,y 0,1 ), (x 0,2 ,y 0,2 )……(x 0,n ,y 0,n ); S3. Points are evenly taken on the chip to be tested, and the interval between the points is denoted as d; the chip to be tested is divided into (L×W) / (d 2 ) points; S4. Calculate the distance between each point and n seeds, assign each point to the nearest neighbor seed point, and perform clustering; S5. Use the center point of each cluster as a new seed, and the new coordinates are marked as (x 1,1 ,y 1,1 ), (x 1,2 ,y 1,2 )……(x 1,n ,y 1,n ); S6. After repeating steps S2 to S5 m times, the seed coordinates are (xm,1,ym,1), (x m,2 ,y m,2 )···(x m,n ,y m,n ),until , the repetition ends, and the final seed coordinates are the location points for placing the test structure.

9. The method for selecting and placing a position according to claim 8, characterized in that: In S3, the point interval d is determined according to the size of the test structure to be placed.

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