Capacitor structure and manufacturing method thereof

Abstract

The present application provides a capacitor structure and a method for manufacturing the same. The capacitor structure includes: a substrate, a first capacitor contact layer, a lower electrode layer, a capacitor dielectric layer and an upper electrode layer, wherein the first capacitor contact layer array is arranged on the substrate, the lower electrode layer surrounds the side wall of the first capacitor contact layer and extends in the direction of the first capacitor contact layer away from the substrate, the capacitor dielectric layer covers the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the first capacitor contact layer, and the upper electrode layer covers the surface of the capacitor dielectric layer. The capacitor structure and the method for manufacturing the same provided by the present application increase the capacitor area surrounding the side wall of the first capacitor contact layer, thereby increasing the area of ​​the capacitor and reducing the resistance of the double-sided capacitor structure.

Description

Technical Field

[0001] The present application relates to the technical field of memory manufacturing, and in particular to a capacitor structure and a manufacturing method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory commonly used in computers. DRAM is usually arranged in a two-dimensional matrix with a capacitor and a transistor as a unit. The main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. With the continuous evolution of process technology, DRAM integration continues to increase, component size continues to shrink, and the charge storage capacity of capacitors is also facing challenges. At present, most capacitors in DRAM are single-sided capacitor structures. The single-sided capacitor structure limits the increase in capacitance per unit area. In order to increase the storage charge capacity of the capacitor, a double-sided capacitor structure that can increase the surface area of ​​the electrode layer is proposed in the prior art.

[0003] In the existing double-sided capacitor structure, the capacitor is arranged on the capacitor contact layer. Since the contact area between the lower electrode plate and the capacitor contact layer is small and the area of ​​the capacitor is small, the resistance of the double-sided capacitor structure is large. Summary of the invention

[0004] The present application provides a capacitor structure and a manufacturing method thereof, which increases the area of ​​the capacitor and reduces the resistance of the double-sided capacitor structure.

[0005] In a first aspect, the present application provides a capacitor structure, comprising:

[0006] substrate;

[0007] A first capacitor contact layer, arrayed on the substrate;

[0008] A lower electrode layer, surrounding the side wall of the first capacitor contact layer and extending in a direction of the first capacitor contact layer away from the substrate;

[0009] A capacitor dielectric layer, covering the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the first capacitor contact layer;

[0010] The upper electrode layer covers the surface of the capacitor dielectric layer.

[0011] Optionally, also include:

[0012] A second capacitor contact layer, located on an upper surface of the first capacitor contact layer;

[0013] The capacitor dielectric layer covers the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the second capacitor contact layer.

[0014] Optionally, the second capacitor contact layer is electrically connected to the lower electrode layer, and the second capacitor contact layer and the lower electrode layer form a lower electrode.

[0015] Optionally, the upper electrode layer includes an upper electrode material layer and an upper electrode filling layer, the upper electrode material layer covers the surface of the capacitor dielectric layer, and the upper electrode filling layer is located on the upper surface of the upper electrode material layer.

[0016] Optionally, the material of the upper electrode filling layer is polysilicon or silicon germanium.

[0017] In a second aspect, the present application provides a method for manufacturing a capacitor structure, comprising:

[0018] providing a substrate;

[0019] forming a conductive layer on the substrate, and forming a capacitor stacking layer on the conductive layer;

[0020] Patterning the capacitor stack layer and the conductive layer to form at least one capacitor column arranged in an array and a first capacitor contact layer corresponding to the capacitor column one by one;

[0021] Depositing a first electrode layer to cover the sidewalls of the capacitor column and the sidewalls of the first capacitor contact layer;

[0022] removing the capacitor column and retaining the first electrode layer and the first capacitor contact layer;

[0023] Depositing a capacitor dielectric layer to cover the first electrode layer;

[0024] A second electrode layer is deposited to cover the capacitor dielectric layer.

[0025] Optionally, the conductive layer includes a first conductive layer and a second conductive layer, and a material of the second conductive layer is the same as a material of the first electrode layer.

[0026] Optionally, the method further includes:

[0027] The second conductive layer is electrically connected to the first electrode layer, so that the conductive layer and the first electrode layer form a lower electrode.

[0028] Optionally, the capacitor stack layer includes a sacrificial layer and a top support layer, and removing the capacitor column includes:

[0029] Depositing a mask layer to cover the upper surface of the capacitor column, forming a photoresist to cover the mask layer, wherein the photoresist has openings corresponding to the capacitor columns one by one;

[0030] The mask layer, the top supporting layer, and the sacrificial layer are removed along the opening.

[0031] Optionally, the second electrode layer includes an upper electrode material layer and an upper electrode filling layer, and the depositing of the second electrode layer covering the capacitor dielectric layer includes:

[0032] The upper electrode material layer is deposited to cover the surface of the capacitor dielectric layer, and the upper electrode filling layer is deposited to cover the upper surface of the upper electrode material layer.

[0033] The present application provides a capacitor structure and a manufacturing method thereof. The capacitor structure is composed of a substrate, a first capacitor contact layer, a lower electrode layer, a capacitor dielectric layer and an upper electrode layer. The first capacitor contact layer is arranged in an array on the substrate, the lower electrode layer surrounds the side wall of the first capacitor contact layer and extends in the direction of the first capacitor contact layer away from the substrate, the capacitor dielectric layer covers the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the first capacitor contact layer, and the upper electrode layer covers the surface of the capacitor dielectric layer. Since the first capacitor contact layer is arranged in an array on the substrate, the lower electrode layer surrounds the side wall of the first capacitor contact layer, that is, the lower electrode layer surrounds the side wall of the first capacitor contact layer, so the contact area between the lower electrode layer and the first capacitor contact layer can be increased. Since the capacitor dielectric layer covers the upper surface of the substrate except the first capacitor contact layer arranged in an array, and the upper electrode layer covers the surface of the capacitor dielectric layer, compared with the existing capacitor structure in which the capacitor is arranged on the first capacitor contact layer, the capacitor area surrounding the side wall of the first capacitor contact layer is increased in the present application, thereby increasing the area of ​​the capacitor and reducing the resistance of the double-sided capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0035] Figure 1 A schematic diagram of a capacitor structure provided in an embodiment of the present application;

[0036] Figure 2 is a top view of the first capacitor contact layer;

[0037] Figure 3 A schematic diagram of a capacitor structure provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of a method for manufacturing a capacitor structure provided in an embodiment of the present application;

[0039] Figure 5 A schematic structural diagram of a substrate during the formation of a capacitor structure provided in an embodiment of the present application;

[0040] Figure 6 A schematic diagram of the structure of a conductive layer and a capacitor stacking layer in a process of forming a capacitor structure provided in an embodiment of the present application;

[0041] Figure 7 A schematic structural diagram of at least one capacitor column formed in a process of forming a capacitor structure provided in an embodiment of the present application;

[0042] Figure 8 A schematic diagram of a process of patterning a capacitor stack layer and a conductive layer in a process of forming a capacitor structure provided in an embodiment of the present application;

[0043] Fig. 9 A schematic diagram of a structure after a first electrode layer is deposited in a formation process of a capacitor structure provided in an embodiment of the present application;

[0044] Fig.10 A schematic diagram of a structure after removing a capacitor column during the formation process of a capacitor structure provided in an embodiment of the present application;

[0045] Fig.11 A schematic diagram of a structure after removing a first electrode layer on an upper surface of a substrate during formation of a capacitor structure provided in an embodiment of the present application;

[0046] Fig.12 A schematic diagram of a structure after depositing a mask layer and forming a photoresist in the formation process of a capacitor structure provided in an embodiment of the present application;

[0047] Fig.13 A schematic diagram of a process of removing a capacitor column during the formation of a capacitor structure provided in an embodiment of the present application;

[0048] Fig.14 A schematic diagram of the structure after a capacitor dielectric layer is deposited in the formation process of a capacitor structure provided in an embodiment of the present application;

[0049] Fig.15 A schematic diagram of the structure after depositing an upper electrode material layer in the formation process of a capacitor structure provided in an embodiment of the present application;

[0050] Fig.16 A schematic diagram of the structure after depositing an upper electrode filling layer in the formation process of a capacitor structure provided in an embodiment of the present application;

[0051] Fig.17 A schematic diagram of a method for manufacturing a capacitor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] In the existing double-sided capacitor structure, the capacitor is arranged on the capacitor contact layer. Since the contact area between the lower electrode plate and the capacitor contact layer is small, and the area of ​​the capacitor is small, the resistance of the double-sided capacitor structure is large. To solve this problem, the present application provides a capacitor structure, by also arranging the lower electrode layer at a position around the side wall of the first capacitor contact layer, that is, the lower electrode layer surrounds the side wall of the first capacitor contact layer, so that the contact area between the lower electrode layer and the first capacitor contact layer can be increased, and the capacitor dielectric layer is covered on the surface of the lower electrode layer. The capacitor dielectric layer also covers the upper surface of the substrate except the first capacitor contact layer arranged in an array, and the upper electrode layer is covered on the surface of the capacitor dielectric layer. Therefore, compared with the existing capacitor structure, the capacitor area surrounding the side wall of the first capacitor contact layer is increased in the present application, thereby increasing the area of ​​the capacitor and reducing the resistance of the double-sided capacitor structure. The specific structure of the capacitor structure provided by the present application is described in detail through specific embodiments in conjunction with the accompanying drawings.

[0054] The capacitor structure provided by the present application can be applied to semiconductor memory, for example, it can be applied to dynamic random access memory, the dynamic random access memory includes multiple repeated storage units, each storage unit can include a capacitor and a transistor, the gate of the transistor is connected to the word line, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the capacitor, and the capacitor here can use the capacitor structure provided by the present application. The capacitor structure provided by the present application can also be applied to other semiconductor devices, but is not limited to this.

[0055] Figure 1 A schematic diagram of a capacitor structure provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the capacitor structure of this embodiment may include: a substrate 101 , a first capacitor contact layer 102 , a lower electrode layer 103 , a capacitor dielectric layer 104 and an upper electrode layer 105 .

[0056] The material of the substrate 101 may be silicon (Si), germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or may be silicon on insulator or germanium on insulator, or may be other materials.

[0057] Optionally, the substrate 101 has an active region and a trench isolation structure isolating each active region. A semiconductor device may be formed on the active region of the substrate 101 . The semiconductor device may be, for example, a transistor.

[0058] The first capacitor contact layer 102 is arranged in an array on the substrate 101. The array arrangement can be arranged on the substrate 101 at equal intervals or at unequal intervals. The cross section of the first capacitor contact layer 102 can be circular, square, rectangular or other shapes. For example, eight capacitors are arranged on the substrate 101. Figure 2 is a top view of the first capacitor contact layer, such as Figure 2 As shown, Figure 2 The cross section of the first capacitor contact layer 102 shown in the figure is circular, the first capacitor contact layer 102 has a certain height, and the first capacitor contact layer 102 can be a cylindrical structure. It can be understood that the first capacitor contact layer 102 can also be other columnar structures. The material of the first capacitor contact layer 102 can be metal, and the metal can specifically be tungsten (W) or the like.

[0059] Optionally, if a transistor is formed on the active region of the substrate 101 , the first capacitor contact layer 102 is electrically connected to the transistor.

[0060] like Figure 1 As shown, the lower electrode layer 103 surrounds the side wall of the first capacitor contact layer 102 and extends in the direction of the first capacitor contact layer 102 away from the substrate 101. The lower surface of the lower electrode layer 103 is in direct contact with the substrate 101, and the lower electrode layer 103 has a certain height. As an practicable manner, the material of the lower electrode layer 103 can be a compound formed by at least one of a metal nitride and a metal silicide, such as titanium nitride (TiN), titanium silicide (TiSi) or titanium silicon nitride.

[0061] The capacitor dielectric layer 104 covers the upper surface of the substrate 101, the surface of the lower electrode layer 103 and the upper surface of the first capacitor contact layer 102, and the upper electrode layer 105 covers the surface of the capacitor dielectric layer 104. Optionally, the material of the capacitor dielectric layer 104 can be a high-K dielectric material to increase the capacitance value of the capacitor per unit area, including one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or a stack formed by two or more of the group consisting of the above materials. The material of the capacitor dielectric layer 104 can also be silicon oxide or other insulating materials.

[0062] In the present embodiment, since the first capacitor contact layer 102 is arranged in an array on the substrate 101, the lower electrode layer 103 surrounds the side wall of the first capacitor contact layer 102, that is, the lower electrode layer 103 surrounds the side wall of the first capacitor contact layer 102, so the contact area between the lower electrode layer 103 and the first capacitor contact layer 102 can be increased, and since the capacitor dielectric layer 104 covers the upper surface of the substrate 101 except the first capacitor contact layer 102 arranged in an array, and the upper electrode layer 105 covers the surface of the capacitor dielectric layer 104, compared with the existing capacitor structure, the capacitor is arranged on the first capacitor contact layer, and the capacitor area surrounding the side wall of the first capacitor contact layer 102 is increased in the present application, thereby increasing the area of ​​the capacitor and reducing the resistance of the double-sided capacitor structure.

[0063] Further, in an operative manner, the upper electrode layer 105 includes an upper electrode material layer 1051 and an upper electrode filling layer 1052, wherein the upper electrode material layer 1051 covers the surface of the capacitor dielectric layer 104, and the upper electrode filling layer 1052 is located on the upper surface of the upper electrode material layer 1051. As an operative manner, the material of the upper electrode material layer 1051 may be a compound formed by at least one of a metal nitride and a metal silicide, such as titanium nitride (TiN), titanium silicide (TiSi), or titanium silicon nitride.

[0064] The material of the upper electrode filling layer 1052 may be polysilicon or silicon germanium.

[0065] The capacitor structure provided in this embodiment is composed of a substrate, a first capacitor contact layer, a lower electrode layer, a capacitor dielectric layer and an upper electrode layer. The first capacitor contact layer is arranged in an array on the substrate, the lower electrode layer surrounds the side wall of the first capacitor contact layer and extends in the direction of the first capacitor contact layer away from the substrate, the capacitor dielectric layer covers the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the first capacitor contact layer, and the upper electrode layer covers the surface of the capacitor dielectric layer. Since the first capacitor contact layer is arranged in an array on the substrate, the lower electrode layer surrounds the side wall of the first capacitor contact layer, that is, the lower electrode layer surrounds the side wall of the first capacitor contact layer, so the contact area between the lower electrode layer and the first capacitor contact layer can be increased. Moreover, since the capacitor dielectric layer covers the upper surface of the substrate except the first capacitor contact layer arranged in an array, and the upper electrode layer covers the surface of the capacitor dielectric layer, compared with the existing capacitor structure, the capacitor is arranged on the first capacitor contact layer. In this application, the capacitor area surrounding the side wall of the first capacitor contact layer is increased, thereby increasing the area of ​​the capacitor and reducing the resistance of the double-sided capacitor structure.

[0066] Figure 3 A schematic diagram of a capacitor structure provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the capacitor structure of this embodiment is Figure 1On the basis of the capacitor structure shown, further, it can also include: a second capacitor contact layer 106, the second capacitor contact layer 106 is located on the upper surface of the first capacitor contact layer 102, and the shape of the second capacitor contact layer is the same as the shape of the first capacitor contact layer. For example, if the cross section of the first capacitor contact layer 102 is circular, the cross section of the conductive layer is also circular. In this embodiment, the capacitor dielectric layer 104 covers the upper surface of the substrate 101, the surface of the lower electrode layer 103 and the upper surface of the second capacitor contact layer 106. Among them, the material of the second capacitor contact layer 106 can be the same as the material of the lower electrode layer 103. For example, the material of the second capacitor contact layer 106 can be a compound formed by at least one of metal nitride and metal silicide, such as titanium nitride (TiN), titanium silicide (TiSi) or titanium silicon nitride. By adding the second capacitor contact layer 106, on the one hand, the first capacitor contact layer 102 can be prevented from diffusing into the capacitor dielectric layer 104. For example, when the material of the first capacitor contact layer 102 is metal tungsten (W), and the material of the capacitor dielectric layer 104 is silicon oxide, the metal tungsten can be prevented from diffusing into silicon oxide. On the other hand, the second capacitor contact layer 106 can also serve as a lower electrode layer, so the area of ​​the lower electrode layer and the first capacitor contact layer 102 can be increased, further increasing the capacitor area.

[0067] The method for manufacturing the capacitor structure provided by the present application is described in detail below with reference to the accompanying drawings.

[0068] Figure 4 A schematic diagram of a method for manufacturing a capacitor structure provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the method of this embodiment may include:

[0069] S101, first provide a substrate.

[0070] Figure 5 A schematic diagram of the structure of a substrate during the formation of a capacitor structure provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, a substrate 101 is first provided, wherein the material of the substrate 101 can be silicon (Si), germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), and can also be silicon on insulator or germanium on insulator, or can also be other materials.

[0071] Optionally, the substrate 101 has an active region and a trench isolation structure isolating each active region. A semiconductor device may be formed on the active region of the substrate 101 . The semiconductor device may be, for example, a transistor.

[0072] S102, forming a conductive layer on the substrate, and forming a capacitor stacking layer on the conductive layer.

[0073] Figure 6For a schematic diagram of the structure of a conductive layer and a capacitor stacking layer in the process of forming a capacitor structure provided in an embodiment of the present application, see Figure 6 , a conductive layer 201 is formed on the substrate 101 , and a capacitor stacking layer 202 is formed on the conductive layer 201 , wherein the capacitor stacking layer 202 includes a sacrificial layer 2021 and a top supporting layer 2022 .

[0074] S103 , patterning the capacitor stack layer and the conductive layer to form at least one capacitor column arranged in an array and a first capacitor contact layer corresponding to the capacitor column one by one.

[0075] Figure 7 A schematic diagram of the structure of at least one capacitor column formed in the process of forming a capacitor structure provided in an embodiment of the present application. Figure 6 and Figure 7 , the capacitor stack layer 202 and the conductive layer 201 are patterned to form at least one capacitor column 203 arranged in an array and a first capacitor contact layer 102 corresponding to the capacitor column 203 one by one.

[0076] Specifically, Figure 8 A schematic diagram of a process of patterning a capacitor stack layer and a conductive layer in a process of forming a capacitor structure provided in an embodiment of the present application. As an implementable method, the capacitor stack layer 202 and the conductive layer 201 are patterned to form at least one capacitor column 203 arranged in an array and a first capacitor contact layer 102 corresponding to the capacitor column 203 in a one-to-one manner. It can be:

[0077] See also Figure 8 , deposit a mask layer 111 to cover the top support layer 2022 in the capacitor stack layer 202, the mask layer can be a single-layer structure or a multi-layer structure, and the mask layer can include polysilicon, carbon and silicon oxynitride when it is a multi-layer structure, then form a negative photoresist 112 to cover the mask layer 111, then expose and develop, etch downward along the negative photoresist 112, etch to the mask layer 111, and then etch all the way to the substrate 101, forming at least one capacitor column 203 arranged in an array and a first capacitor contact layer 102 corresponding to the capacitor column 203. By utilizing the characteristic that the exposed area of ​​the negative photoresist is retained, a capacitor column structure of a specific shape (such as a circle) can be directly obtained. In other embodiments, a capacitor column of a specific shape can also be obtained by using two patterning processes, and the patterning process includes a self-aligned double patterning process or a reverse self-aligned double patterning process.

[0078] S104 , depositing a first electrode layer to cover the sidewalls of the capacitor column and the sidewalls of the first capacitor contact layer.

[0079] Fig. 9 This is a schematic diagram of a structure after the first electrode layer is deposited in the formation process of a capacitor structure provided in an embodiment of the present application. Fig. 9The first electrode layer 301 is deposited to cover the sidewalls of the capacitor column 203 and the sidewalls of the first capacitor contact layer 102. The first electrode layer 301 can be deposited by atomic layer deposition, and also covers the upper surface of the substrate. The deposition process here can be chemical vapor deposition, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

[0080] S105 , removing the capacitor column and retaining the first electrode layer and the first capacitor contact layer.

[0081] then, Fig.10 This is a schematic diagram of a structure after removing the capacitor column during the formation process of a capacitor structure provided in an embodiment of the present application. Fig.10 , remove the capacitor column 203, retain the first electrode layer 301 and the first capacitor contact layer 102, and when the capacitor column 203 is removed, the first electrode layer 301 on the upper surface of the capacitor column 203 and the first electrode layer 301 on the upper surface of the substrate 101 are also removed accordingly.

[0082] Optional, Fig.11 A schematic diagram of a structure after removing the first electrode layer on the upper surface of the substrate during the formation of a capacitor structure provided in an embodiment of the present application is shown in FIG. Fig.11 , first remove the first electrode layer 301 on the upper surface of the substrate.

[0083] Fig.12 A schematic diagram of a structure after depositing a mask layer and forming a photoresist in the formation process of a capacitor structure provided in an embodiment of the present application is shown in FIG. Fig.12 , the capacitor column 203 can be removed by depositing a mask layer 302 to cover the upper surface of the capacitor column 203, and then forming a photoresist 303 to cover the mask layer 302, wherein the photoresist 303 has openings corresponding to the capacitor columns 203. The deposition process here can be chemical vapor deposition, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

[0084] Fig.13 A schematic diagram of a process of removing a capacitor column during the formation of a capacitor structure provided in an embodiment of the present application is shown in FIG. Fig.13 , remove the mask layer 302, the top support layer 2022 and the sacrificial layer 2021 along the opening to obtain Fig.10 Optionally, the top support layer 2022 may be removed by dry etching, and the sacrificial layer 2021 may be removed by dry etching and wet etching, and the sacrificial layer 2021 may be completely removed by wet etching. It should be noted that Fig.10 In the structure shown, the first electrode layer 301 and Figure 1 Corresponding to the lower electrode layer 103 in , is the lower electrode layer 103 .

[0085] S106, depositing a capacitor dielectric layer to cover the first electrode layer.

[0086] Get as Fig.10 After the structure shown, Fig.14 A schematic diagram of the structure after the capacitor dielectric layer is deposited in the formation process of a capacitor structure provided in an embodiment of the present application, see Fig.14 , a capacitor dielectric layer 104 is deposited to cover the first electrode layer 301 .

[0087] S107, depositing a second electrode layer to cover the capacitor dielectric layer.

[0088] Specifically, the second electrode layer (i.e., Figure 1 The upper electrode layer 105 shown covers the capacitor dielectric layer 104 .

[0089] Specifically, the second electrode layer 304 includes an upper electrode material layer 3041 and an upper electrode filling layer 3042. Fig.15 A schematic diagram of the structure after depositing an upper electrode material layer in the formation process of a capacitor structure provided in an embodiment of the present application is shown in FIG. Fig.15 , depositing the second electrode layer 304 to cover the capacitor dielectric layer 104 may be:

[0090] The upper electrode material layer 3041 is deposited to cover the surface of the capacitor dielectric layer 104. Fig.16 This is a schematic diagram of a structure after depositing an upper electrode filling layer in the formation process of a capacitor structure provided in an embodiment of the present application. Fig.16 , depositing an upper electrode filling layer 3042 to cover the upper surface of the upper electrode material layer 3041. It should be noted that the upper electrode material layer 3041 and Figure 1 The upper electrode material layer 1051 shown corresponds to the upper electrode filling layer 3042. Figure 1 The upper electrode material layer 1052 shown corresponds.

[0091] The manufacturing method of the capacitor structure provided in the present embodiment comprises a substrate, a first capacitor contact layer, a lower electrode layer, a capacitor dielectric layer and an upper electrode layer. The first capacitor contact layer is arranged in an array on the substrate, the lower electrode layer surrounds the side wall of the first capacitor contact layer and extends in the direction of the first capacitor contact layer away from the substrate, the capacitor dielectric layer covers the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the first capacitor contact layer, and the upper electrode layer covers the surface of the capacitor dielectric layer. Since the first capacitor contact layer is arranged in an array on the substrate, the lower electrode layer surrounds the side wall of the first capacitor contact layer, that is, the lower electrode layer surrounds the side wall of the first capacitor contact layer, so the contact area between the lower electrode layer and the first capacitor contact layer can be increased. Moreover, since the capacitor dielectric layer covers the upper surface of the substrate except the first capacitor contact layer arranged in an array, and the upper electrode layer covers the surface of the capacitor dielectric layer, compared with the existing capacitor structure, the capacitor is arranged on the first capacitor contact layer. In the present application, the capacitor area surrounding the side wall of the first capacitor contact layer is increased, thereby increasing the area of ​​the capacitor and reducing the resistance value of the double-sided capacitor structure.

[0092] Furthermore, in the manufacturing process of the above capacitor structure, in another practicable manner, the conductive layer includes a first conductive layer and a second conductive layer, and the material of the second conductive layer is the same as the material of the first electrode layer. After forming a conductive layer on the substrate, the method may further include: electrically connecting the second conductive layer to the first electrode layer, so that the second conductive layer and the first electrode layer form a lower electrode. Fig.17 The process shown is described as an example.

[0093] Fig.17 A schematic diagram of a method for manufacturing a capacitor structure provided in an embodiment of the present application is shown in FIG. Fig.17 As shown, the method of this embodiment may include:

[0094] S201, first provide a substrate.

[0095] S202, forming a conductive layer on the substrate, the conductive layer comprising a first conductive layer and a second conductive layer, the material of the second conductive layer is the same as the material of the first electrode layer, the second conductive layer is electrically connected to the first electrode layer, so that the conductive layer and the first electrode layer form a lower electrode.

[0096] S203 , forming a capacitor stacking layer on the conductive layer.

[0097] S204 , patterning the capacitor stack layer and the conductive layer to form at least one capacitor column arranged in an array and a first capacitor contact layer corresponding to the capacitor column one by one.

[0098] S205 , depositing a first electrode layer to cover the sidewalls of the capacitor column and the sidewalls of the first capacitor contact layer.

[0099] S206 , removing the capacitor column and retaining the first electrode layer and the first capacitor contact layer.

[0100] S207, depositing a capacitor dielectric layer to cover the first electrode layer.

[0101] S208, depositing a second electrode layer to cover the capacitor dielectric layer.

[0102] In this embodiment, the specific process is as follows Figure 4 The process is the same as shown in the figure, which will not be repeated here, and the final result is as follows Figure 3 The capacitor structure shown in the figure, in this embodiment, since the conductive layer includes a first conductive layer and a second conductive layer (ie Figure 3 The second capacitor contact layer 106 in the embodiment of the present invention is made of the same material as the first electrode layer. Figure 4 In the manufacturing method shown in the embodiment, by adding the second conductive layer, on the one hand, the first capacitor contact layer can be prevented from diffusing into the capacitor dielectric layer. For example, when the material of the first capacitor contact layer is metal tungsten (W), the material of the capacitor dielectric layer is silicon oxide, which can prevent the metal tungsten from diffusing into the silicon oxide. On the other hand, the second conductive layer can also be used as the lower electrode layer, so the area of ​​the lower electrode layer and the first capacitor contact layer can be increased, further increasing the capacitor area.

[0103] An embodiment of the present application also provides a memory, which includes any of the above-mentioned capacitor structures.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A capacitor structure, characterized in that: include: substrate; A first capacitor contact layer, arrayed on the substrate; a lower electrode layer, surrounding the side wall of the first capacitor contact layer and extending along the side wall of the first capacitor contact layer away from the substrate, wherein the height of the lower electrode layer is greater than the height of the first capacitor contact layer; a second capacitor contact layer, located on the upper surface of the first capacitor contact layer, the second capacitor contact layer is electrically connected to the lower electrode layer, the second capacitor contact layer and the lower electrode layer form a lower electrode, and the material of the second capacitor contact layer is the same as that of the lower electrode layer; a capacitor dielectric layer, covering and contacting the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the second capacitor contact layer; The upper electrode layer covers the surface of the capacitor dielectric layer.

2. The capacitor structure according to claim 1, characterized in that: The upper electrode layer comprises an upper electrode material layer and an upper electrode filling layer, wherein the upper electrode material layer covers the surface of the capacitor dielectric layer, and the upper electrode filling layer is located on the upper surface of the upper electrode material layer.

3. The capacitor structure according to claim 2, characterized in that: The material of the upper electrode filling layer is polysilicon or silicon germanium.

4. A memory, characterized in that: Comprising a capacitor structure as described in any one of claims 1-3.

5. A method for manufacturing a capacitor structure, characterized in that: include: providing a substrate; forming a conductive layer on the substrate, and forming a capacitor stacking layer on the conductive layer; The conductive layer comprises a first conductive layer and a second conductive layer; Patterning the capacitor stack layer and the conductive layer to form at least one capacitor column arranged in an array and a first capacitor contact layer corresponding to the capacitor column one by one; Depositing a first electrode layer to cover the sidewalls of the capacitor column and the sidewalls of the first capacitor contact layer; removing the capacitor column, retaining the first electrode layer and the first capacitor contact layer, wherein the height of the first electrode layer is greater than the height of the first capacitor contact layer; electrically connecting the second conductive layer to the first electrode layer, so that the conductive layer and the first electrode layer form a lower electrode, and the material of the second conductive layer is the same as that of the first electrode layer; Depositing a capacitor dielectric layer to cover the first electrode layer, wherein the capacitor dielectric layer is in contact with the first electrode layer; A second electrode layer is deposited to cover the capacitor dielectric layer.

6. The method according to any one of claim 5, characterized in that: The capacitor stack layer includes a sacrificial layer and a top support layer, and removing the capacitor column includes: Depositing a mask layer to cover the upper surface of the capacitor column, forming a photoresist to cover the mask layer, wherein the photoresist has openings corresponding to the capacitor columns one by one; The mask layer, the top supporting layer, and the sacrificial layer are removed along the opening.

7. The method according to claim 5, characterized in that The second electrode layer includes an upper electrode material layer and an upper electrode filling layer, and the deposited second electrode layer covers the capacitor dielectric layer, including: The upper electrode material layer is deposited to cover the surface of the capacitor dielectric layer, and the upper electrode filling layer is deposited to cover the upper surface of the upper electrode material layer.

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