Display device and method of manufacturing the same

Abstract

A pixel according to one embodiment of the present application includes: first and second electrodes spaced apart from each other; a first insulating layer having a first etching selectivity; a first insulating pattern having a second etching selectivity; a light emitting element including first and second ends; a second insulating pattern disposed on one region of the light emitting element to expose the first and second ends of the light emitting element and having the second etching selectivity; and third and fourth electrodes electrically connecting the first and second ends of the light emitting element to the first and second electrodes, respectively.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display device and a method of manufacturing the same. Background Technology

[0002] Recently, techniques have been developed for manufacturing ultra-miniature light-emitting elements using materials with reliable inorganic crystal structures and for manufacturing light-emitting devices using these elements. For example, techniques have been developed for manufacturing multiple ultra-miniature light-emitting elements, each with a small size corresponding to a range from nanometers to micrometers, and for forming various light-emitting devices, including pixels of display devices, using these ultra-miniature light-emitting elements. Summary of the Invention

[0003] Technical issues

[0004] The purpose of this disclosure is to provide a display device including a light-emitting element and a method for manufacturing the same.

[0005] Technical solution

[0006] A display device according to an embodiment of the present disclosure includes pixels disposed in a display area. Each pixel includes: a first electrode and a second electrode spaced apart from each other; a first insulating layer disposed on a region of each of the first and second electrodes and in a region between the first and second electrodes, and having a first etch selectivity; a first insulating pattern disposed on the first insulating layer in the region between the first and second electrodes, and having a second etch selectivity; a light-emitting element disposed on the first insulating pattern, and including a first end and a second end; a second insulating pattern having a second etch selectivity and disposed on a region of the light-emitting element, such that the first and second ends of the light-emitting element are exposed; and a third electrode and a fourth electrode configured to electrically connect the first and second ends of the light-emitting element to the first and second electrodes, respectively.

[0007] In this embodiment, the first insulating layer may include a first insulating material. The first insulating pattern and the second insulating pattern may include a second insulating material that is different from the first insulating material.

[0008] In one embodiment, the light-emitting element may be spaced apart from the first insulating layer, and the first insulating pattern is placed between the light-emitting element and the first insulating layer.

[0009] In an embodiment, the first insulating pattern may be disposed on the first insulating layer and only below the light-emitting element and the second insulating pattern.

[0010] In an embodiment, the light-emitting element may be spaced from the first insulating layer by a distance equal to or greater than the thickness of the first insulating pattern.

[0011] In an embodiment, the pixel may further include: a first dam pattern disposed below a region of the first electrode; and a second dam pattern disposed below a region of the second electrode.

[0012] In one embodiment, the first dam pattern may include a first sidewall facing a first end of the light-emitting element. The second dam pattern may include a second sidewall facing a second end of the light-emitting element.

[0013] In one embodiment, a third electrode may be disposed on the first end and extend to the upper part of the first electrode via the upper part of the first sidewall. A fourth electrode may be disposed on the second end of the light-emitting element and extend to the upper part of the second electrode via the upper part of the second sidewall.

[0014] In an embodiment, a pixel may include multiple light-emitting elements comprising light-emitting elements and connected between a first electrode and a second electrode. The multiple light-emitting elements may be configured to be closer to the first electrode than closer to the second electrode.

[0015] In one embodiment, the first electrode may be connected to a first power source. The second electrode may be connected to a second power source.

[0016] In an embodiment, the pixel may further include pixel circuitry connected between the first power source and the first electrode. The display area may include: a circuit layer having circuit elements of the pixel circuitry disposed therein; and a display layer superimposed on the circuit layer, wherein the first electrode, the second electrode, and the light-emitting element are disposed therein.

[0017] A method for manufacturing a display device according to an embodiment of the present disclosure includes the following steps: forming a first electrode and a second electrode on a substrate layer; forming a first insulating layer having a first etch selectivity on the substrate layer such that the first insulating layer covers the first electrode and the second electrode; forming a first insulating material layer having a second etch selectivity on the first insulating layer; supplying a light-emitting element to the substrate layer on which the first insulating material layer is formed, and aligning the light-emitting element between the first electrode and the second electrode; forming a second insulating material layer having a second etch selectivity on the substrate layer such that the second insulating material layer covers the first insulating material layer and the light-emitting element; exposing a first end and a second end of the light-emitting element by etching the first insulating material layer and the second insulating material layer; exposing a region of each of the first electrode and the second electrode by etching the first insulating layer; and forming a third electrode and a fourth electrode configured to electrically connect the first end and the second end of the light-emitting element to the first electrode and the second electrode, respectively.

[0018] In one embodiment, the first insulating layer may be formed of a first insulating material. The first insulating material layer may be formed of a second insulating material that is different from the first insulating material.

[0019] In an embodiment, the second insulating material layer may be formed of a second insulating material.

[0020] In this embodiment, the first insulating material layer and the second insulating material layer can be etched simultaneously. A first insulating pattern can be formed by etching the first insulating material layer, such that the first insulating pattern is disposed below the lower portion of the light-emitting element, including below the lower portions of the first and second ends of the light-emitting element. A second insulating pattern can be formed by etching the second insulating material layer, such that the second insulating pattern is disposed on a region of the light-emitting element other than the first and second ends of the light-emitting element.

[0021] In an embodiment, the method may further include forming a first dam pattern and a second dam pattern on a substrate layer before forming the first electrode and the second electrode.

[0022] In one embodiment, a first electrode may be formed on a first dam pattern, such that a region of the first electrode protrudes through the first dam pattern. A second electrode may be formed on a second dam pattern, such that a region of the second electrode protrudes through the second dam pattern.

[0023] In an embodiment, the step of supplying and aligning the light-emitting elements may include: supplying a plurality of light-emitting elements, including the light-emitting elements, to each pixel region in which a first electrode and a second electrode are formed; and aligning the light-emitting elements between the first electrode and the second electrode by forming an electric field between the first electrode and the second electrode.

[0024] In one embodiment, the light-emitting element can be aligned to be positioned closer to the first electrode than closer to the second electrode.

[0025] In an embodiment, the method may further include forming a circuit layer including pixel circuitry on a substrate layer prior to forming the first electrode and the second electrode.

[0026] Beneficial effects

[0027] In the display device and method of manufacturing the display device according to embodiments of the present disclosure, the light-emitting element can be reliably connected between the first electrode and the second electrode of the pixel. Therefore, the utilization rate of the light-emitting element supplied to each pixel area can be enhanced, and the emission characteristics of the pixel can be stabilized. Attached Figure Description

[0028] Figure 1a and Figure 1b These are perspective views and cross-sectional views of a light-emitting element according to an embodiment of the present disclosure.

[0029] Figure 2a and Figure 2b These are perspective views and cross-sectional views of a light-emitting element according to an embodiment of the present disclosure.

[0030] Figure 3a and Figure 3b These are perspective views and cross-sectional views of a light-emitting element according to an embodiment of the present disclosure.

[0031] Figure 4a and Figure 4b These are perspective views and cross-sectional views of a light-emitting element according to an embodiment of the present disclosure.

[0032] Figure 5 This is a plan view showing a display device according to an embodiment of the present disclosure.

[0033] Figures 6a to 6g The diagrams shown are circuit diagrams of pixels according to embodiments of the present disclosure.

[0034] Figure 7a and Figure 7b Each of these figures is a plan view of pixels according to an embodiment of the present disclosure.

[0035] Figures 8a to 8d Each of the images shows a cross-sectional view of a pixel according to an embodiment of the present disclosure.

[0036] Figure 9 This is a cross-sectional view showing pixels according to an embodiment of the present disclosure.

[0037] Figure 10 This is a plan view showing pixels according to an embodiment of the present disclosure.

[0038] Figures 11a to 11d Each of the images shows a cross-sectional view of a pixel according to an embodiment of the present disclosure.

[0039] Figure 12 This is a cross-sectional view showing an embodiment that does not include pixels of the first insulating pattern.

[0040] Figures 13a to 13j This is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present disclosure.

[0041] Figures 14a to 14c Each of these figures is a plan view of pixels according to an embodiment of the present disclosure. Detailed Implementation

[0042] Because the embodiments of this disclosure can be modified in many different forms, reference will now be made in detail to various embodiments of this disclosure, specific examples of which are illustrated in the accompanying drawings and described below. However, this disclosure is not limited to the following embodiments and can be modified in various ways. Each embodiment described below can be implemented alone or in combination with at least one other embodiment to achieve various combinations of embodiments.

[0043] Some elements not directly related to the features of this disclosure may be omitted in the accompanying drawings to clearly explain this disclosure. Furthermore, the dimensions, scale, etc., of some elements in the drawings may be slightly exaggerated. It should be noted that the same reference numerals are used throughout the drawings to indicate the same or similar elements, and repeated explanations will be omitted.

[0044] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. It will also be understood that when the terms "comprising," "including," "having," etc., are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. Furthermore, when a first component or part is disposed on a second component or part, the first component or part may not only be directly on the second component or part, but a third component or part may also be situated between them. Furthermore, the terms "position," "direction," etc., used in the following description are defined as relative terms, and it should be noted that they may be changed to the opposite position or direction depending on the viewpoint or orientation. Additionally, the singular form may include the plural form, provided it is not specifically mentioned in the sentence.

[0045] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b Both views show perspective and cross-sectional views of a light-emitting element (LD) according to embodiments of the present disclosure. Although Figures 1a to 3b A cylindrical rod-shaped light-emitting element (LD) is shown, but the type and / or shape of the light-emitting element (LD) according to this disclosure are not limited thereto.

[0046] Reference Figure 1a and Figure 1b According to embodiments of the present disclosure, a light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may include a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 continuously stacked in the longitudinal direction.

[0047] In embodiments, the light-emitting element LD can be a rod-shaped light-emitting element (also referred to as a "bar light-emitting diode"). For example, the light-emitting element LD can be manufactured in the form of a rod extending in one direction by means of etching or the like. In the description of embodiments of this disclosure, the term "bar-shaped" includes rod-shaped and strip-shaped shapes (such as cylindrical and prismatic shapes extending in the longitudinal direction (i.e., having an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light-emitting element LD can be greater than the diameter D of the light-emitting element LD (or the width of the cross-section of the light-emitting element LD).

[0048] If the direction along which the light-emitting element LD extends is defined as the longitudinal direction, then the light-emitting element LD may have a first end EP1 and a second end EP2 relative to the longitudinal direction. The first end EP1 and the second end EP2 may be regions including surfaces (e.g., the two bottom surfaces of a cylinder) disposed at opposite ends of the light-emitting element LD relative to the longitudinal direction, and may be regions including not only the surfaces at opposite ends but also the regions formed around those surfaces.

[0049] In embodiments, the light-emitting element (LD) can have small dimensions ranging from nanometers to micrometers. For example, each LD can have a diameter D (or width) and / or length L ranging from nanometers to micrometers. However, in this disclosure, the size of the LD is not limited to this. For example, the size of the LD can be varied in various ways depending on the design conditions of various devices (e.g., display devices employing light-emitting devices using LDs as light sources).

[0050] Either the first semiconductor layer 11 or the second semiconductor layer 13 can be disposed at the first end EP1 of the light-emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 can be disposed at the second end EP2 of the light-emitting element LD.

[0051] The first semiconductor layer 11 may be formed from a first conductive semiconductor layer. For example, the first semiconductor layer 11 may include at least one N-type semiconductor layer. For example, the first semiconductor layer 11 may include an N-type semiconductor layer, which includes any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and is doped with a first conductive dopant such as Si, Ge, or Sn. However, the constituent materials of the first semiconductor layer 11 are not limited to these, and various other materials may be used to form the first semiconductor layer 11.

[0052] The active layer 12 may be disposed on the first semiconductor layer 11 and have a single quantum well or multiple quantum well (MQW) structure. In embodiments, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In embodiments, materials such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may also be used to form the active layer 12.

[0053] The second semiconductor layer 13 may be disposed on the active layer 12 and formed of a second conductive semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second semiconductor layer 13 may include a P-type semiconductor layer comprising at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the materials used to form the second semiconductor layer 13 are not limited to these, and the second semiconductor layer 13 may be formed of various other materials.

[0054] If a voltage with a threshold voltage or greater is applied between opposite ends of the light-emitting element LD (e.g., the first end EP1 and the second end EP2), the light-emitting element LD emits light through the combination of electron-hole pairs in the active layer 12. Since the light emission of the light-emitting element LD can be controlled based on the aforementioned principle, the light-emitting element LD can be used not only as a light source for pixels in a display device, but also as a light source for various light-emitting devices.

[0055] In an embodiment, the light-emitting element LD may further include an insulating film INF disposed on the surface of the light-emitting element LD. The insulating film INF may be formed on the surface of the light-emitting element LD to surround at least the outer peripheral surface of the active layer 12, and may also surround a region of each of the first semiconductor layer 11 and the second semiconductor layer 13. Here, the insulating film INF may expose opposing ends of the light-emitting element LD with different polarities to the outside. For example, the insulating film INF may expose a first end EP1 and a second end EP2 disposed relative to the longitudinal direction of the corresponding opposing ends of the light-emitting element LD (e.g., as shown in the figure). Figure 1a and Figure 1b The exposed light-emitting element LD (the top and bottom surfaces corresponding to the two base sides of the cylinder) is shown instead of covering the first end EP1 and the second end EP2.

[0056] In the embodiments, the insulating film INF may include at least one insulating material selected from silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and titanium dioxide (TiO2), but is not limited thereto. In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed from various known insulating materials.

[0057] In embodiments, the light-emitting element (LD) may include, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF, other additional components. For example, the light-emitting element (LD) may also include at least one phosphor layer, at least one active layer, at least one semiconductor layer, and / or at least one electrode layer disposed at one end of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0058] For example, such as Figure 2a and Figure 2b As shown, the light-emitting element LD may further include at least one electrode layer 14 disposed at one end of the second semiconductor layer 13. For example, the light-emitting element LD may further include an electrode layer 14 disposed at the first end EP1.

[0059] In an embodiment, such as Figure 3a and Figure 3b As shown, the light-emitting element LD may further include at least one electrode layer 15 disposed at one end of the first semiconductor layer 11. For example, the light-emitting element LD may include electrode layers 14 and 15 disposed at the first end EP1 and the second end EP2, respectively.

[0060] Electrode layers 14 and 15 may be contact electrodes configured to connect each light-emitting element (LD) to other circuit elements, lines, and / or electrodes, etc., but this disclosure is not limited thereto. In embodiments, each of electrode layers 14 and 15 may comprise a metal or a metal oxide. For example, each of electrode layers 14 and 15 may be formed individually or in combination of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, or transparent electrode materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). In embodiments, electrode layers 14 and 15 may be substantially transparent or translucent. Thus, light generated from the light-emitting element (LD) can be emitted to the outside after passing through electrode layers 14 and 15.

[0061] The insulating film INF may at least partially surround the outer peripheral surfaces of electrode layers 14 and 15, or it may not surround the outer peripheral surfaces. In other words, the insulating film INF may be formed to selectively cover the surfaces of electrode layers 14 and 15. Furthermore, the insulating film INF may be formed to expose opposite ends of the light-emitting element LD that have different conductivity types (e.g., P-type and N-type, respectively). For example, the insulating film INF may be exposed in at least one region of each of electrode layers 14 and 15 at the first end EP1 and the second end EP2 of the light-emitting element LD. Optionally, in an embodiment, the insulating film INF may not be present in the light-emitting element LD.

[0062] If the insulating film INF is configured to cover the surface of the light-emitting element LD (specifically, the outer peripheral surface of the active layer 12), short circuits between the active layer 12 and at least one electrode (e.g., the first or second electrode of the pixel) can be prevented. Therefore, the electrical stability of the light-emitting element LD can be ensured. In the description of embodiments of this disclosure, the term "connection (or bonding)" may refer to a physical and / or electrical connection (or bonding). Furthermore, the term "connection (or bonding)" may refer to direct or indirect connection (or bonding) and integral or non-integral connection (or bonding).

[0063] Furthermore, the insulating film INF formed on the surface of the light-emitting element (LD) minimizes the occurrence of defects on the LD surface, thereby improving the LD's lifespan and efficiency. Additionally, if the insulating film INF is formed on each LD, undesirable short circuits can be prevented even when multiple LDs are arranged adjacent to each other.

[0064] In embodiments of this disclosure, a surface treatment process may be performed to manufacture the light-emitting element (LD). For example, each LD may be surface-treated such that when multiple LDs are mixed with a fluid solution (or solvent) and then supplied to each emission region (e.g., the emission region of each pixel), the LDs can be uniformly dispersed rather than non-uniformly aggregated in the solution.

[0065] In related non-limiting embodiments, the insulating film INF itself can be formed from a hydrophobic film using a hydrophobic material, or an additional hydrophobic film formed from a hydrophobic material can be formed on the insulating film INF. In embodiments, the hydrophobic material can be a fluorinated material to exhibit hydrophobicity. In embodiments, the hydrophobic material can be applied to the light-emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material can include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. Furthermore, the hydrophobic material can be, for example, Teflon. TM Or Cytop TMCommercially available fluorine-containing materials or equivalent materials.

[0066] The aforementioned light-emitting element (LD) can be used as a light source in different types of light-emitting devices, including pixels of a display device. For example, at least one ultra-small light-emitting element (LD) (e.g., multiple ultra-small light-emitting elements (LDs) each having dimensions ranging from nanometers to micrometers) can be disposed in each pixel area of ​​a display panel for forming a screen of a display device, and the ultra-small light-emitting element (LD) can be used to form the light source (or light source unit) of the corresponding pixel. Furthermore, the application of the light-emitting element (LD) according to this disclosure is not limited to display devices. For example, the light-emitting element (LD) can also be used in other types of devices that require a light source (such as lighting devices).

[0067] Figure 4a and Figure 4b These are perspective and cross-sectional views of a light-emitting element (LD) according to an embodiment of the present disclosure. According to the embodiment, Figure 4a and Figure 4b It shows having with Figures 1a to 3b The light-emitting element (LD) shown has a different structure than other light-emitting element LDs, such as a light-emitting element LD with a core-shell structure. In other words, the type, structure, and / or shape of the light-emitting element LD according to embodiments of this disclosure can be varied in various ways. Figure 4a and Figure 4b In the description of the embodiments, the same reference numerals are used to indicate the same as those in the drawings. Figures 1a to 3b The components of the embodiments are similar to or the same as (or corresponding to) the components, and their detailed descriptions will be omitted.

[0068] Reference Figure 4a and Figure 4b The light-emitting element (LD) according to embodiments of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. In an embodiment, the first semiconductor layer 11 may be disposed in the central region of the light-emitting element LD, and the active layer 12 may be disposed on the surface of the first semiconductor layer 11 to surround at least one region of the first semiconductor layer 11. The second semiconductor layer 13 may be disposed on the surface of the active layer 12 to surround at least one region of the active layer 12.

[0069] The light-emitting element LD may also optionally include an electrode layer 14 configured to surround at least one region of the second semiconductor layer 13 and / or an insulating film INF disposed on the outermost surface of the light-emitting element LD. For example, the light-emitting element LD may also include an electrode layer 14 disposed on the surface of the second semiconductor layer 13 to surround at least one region of the second semiconductor layer 13 and an insulating film INF disposed on the surface of the electrode layer 14 to surround at least one region of the electrode layer 14.

[0070] In this embodiment, an insulating film INF may be disposed on the surface of the light-emitting element LD to cover a portion of the outer peripheral surface of the first semiconductor layer 11 and the outer peripheral surface of the electrode layer 14. The insulating film INF may be formed to be transparent or translucent to meet a predetermined range of transmittance.

[0071] In an embodiment, after forming an insulating film INF to cover the entire outer peripheral surface of the electrode layer 14 included in the light-emitting element LD, the insulating film INF may be partially removed to expose an area of ​​the electrode layer 14 for electrical connection with an electrode (e.g., a first electrode of a pixel, not shown).

[0072] The light-emitting element (LD) according to the foregoing embodiments can be a core-shell light-emitting element (also referred to as a "core-shell light-emitting diode") manufactured by a growth process or the like. For example, the light-emitting element LD can have a core-shell structure comprising a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, an electrode layer 14, and an insulating film INF continuously disposed in a direction from the center to the periphery. Here, the electrode layer 14 and the insulating film INF can be selectively disposed. For example, in an embodiment, the light-emitting element LD may not include at least one of the electrode layer 14 and the insulating film INF.

[0073] In an embodiment, the light-emitting element (LD) may have a pyramidal shape extending in one direction. For example, at least one region of the light-emitting element (LD) may have a hexagonal pyramidal shape.

[0074] If the direction along which the light-emitting element LD extends is defined as the longitudinal direction, then the light-emitting element LD may have a first end EP1 and a second end EP2 relative to the longitudinal direction. In an embodiment, either the first semiconductor layer 11 or the second semiconductor layer 13 (or an electrode layer configured to surround either the first semiconductor layer 11 or the second semiconductor layer 13) is disposed at the first end EP1 of the light-emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 (or an electrode layer configured to surround the other of the first semiconductor layer 11 and the second semiconductor layer 13) may be disposed at the second end EP2 of the light-emitting element LD.

[0075] In embodiments of this disclosure, the light-emitting element LD can be a light-emitting diode (LED) having a core-shell structure and a first end EP1 protruding in a pyramidal shape (e.g., a hexagonal pyramid shape) and having an ultra-small size. For example, the light-emitting element LD can have a shape corresponding to a combination of hexagonal pyramids and hexagonal prisms, and a small size ranging from nanometer to micrometer scale (e.g., width W and / or length L corresponding to nanometer or micrometer scale). Here, the size and shape of the light-emitting element LD can be varied according to the design conditions of various devices (e.g., display devices) that employ the light-emitting element LD as a light source.

[0076] In an embodiment, the opposite ends of the first semiconductor layer 11 may have a shape that protrudes in the longitudinal direction of the light-emitting element LD. In an embodiment, the protruding shapes of the opposite ends of the first semiconductor layer 11 may differ from each other. For example, one end of the opposite ends of the first semiconductor layer 11 located at an upper position may have a pyramidal shape (e.g., a hexagonal pyramid shape), the width of which decreases upwards to converge at a vertex. Furthermore, the other end of the opposite ends of the first semiconductor layer 11 located at a lower position may have a prism shape (e.g., a hexagonal prism shape) with a constant width, but this disclosure is not limited thereto. For example, in another embodiment, the first semiconductor layer 11 may have a cylindrical or stepped cross-section whose width gradually decreases downwards. In other words, the shape of the opposite ends of the first semiconductor layer 11 can be varied in various ways depending on the embodiment.

[0077] The first semiconductor layer 11 can be disposed in the core (i.e., the central (or middle) region of the light-emitting element LD). Furthermore, the light-emitting element LD can have a shape corresponding to the shape of the first semiconductor layer 11. For example, if the first semiconductor layer 11 has a hexagonal pyramid shape at its upper end, the light-emitting element LD can have a hexagonal pyramid shape at its upper end (e.g., the first end EP1).

[0078] The active layer 12 may be configured and / or formed in a shape that surrounds the outer peripheral surface of the first semiconductor layer 11. For example, the active layer 12 may be configured and / or formed in a shape that surrounds the region of the first semiconductor layer 11 except for one end of the first semiconductor layer 11 in the longitudinal direction relative to the light-emitting element LD (e.g., the second end EP2 at the lower position).

[0079] The second semiconductor layer 13 may be disposed and / or formed in a shape that surrounds the outer peripheral surface of the active layer 12, and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, in the case where the first semiconductor layer 11 includes an N-type semiconductor layer, the second semiconductor layer 13 may include a P-type semiconductor layer.

[0080] In an embodiment, the light-emitting element LD may further include an electrode layer 14 surrounding the outer peripheral surface of the second semiconductor layer 13. The electrode layer 14 may be a contact electrode electrically connected to the second semiconductor layer 13, but this disclosure is not limited thereto.

[0081] As described above, the light-emitting element (LD) may have a core-shell structure with opposite ends protruding outwards, and may include a first semiconductor layer 11 disposed in its central portion, an active layer 12 surrounding the first semiconductor layer 11, and a second semiconductor layer 13 surrounding the active layer 12. Furthermore, the light-emitting element (LD) may optionally include an electrode layer 14 surrounding the second semiconductor layer 13. One end of the electrode layer 14 may be disposed at a first end EP1 of the light-emitting element (LD), and one end of the first semiconductor layer 11 may be disposed at a second end EP2 of the light-emitting element (LD).

[0082] The aforementioned light-emitting elements (LDs) can be used as light sources in different types of light-emitting devices, including pixels. For example, at least one ultra-small light-emitting element (LD) (e.g., multiple ultra-small light-emitting elements (LDs) each having dimensions ranging from nanometers to micrometers) can be disposed in each pixel area of ​​the display panel to form the light source (or light source unit) of the corresponding pixel using the ultra-small light-emitting elements (LDs).

[0083] In an embodiment, each pixel may include at least one rod-shaped light-emitting element (LD) or at least one core-shell light-emitting element (LD), or a combination of rod-shaped LD and core-shell LD. In an embodiment, each pixel may include other light-emitting elements having a type and / or shape different from that of the rod-shaped LD or the core-shell LD.

[0084] Figure 5 This is a plan view illustrating a display device according to an embodiment of the present disclosure. In the embodiment, Figure 5 A display device (specifically, a display panel PNL disposed in the display device) is shown as a device that can be used in... Figures 1a to 4b The light-emitting element (LD) described in the embodiments is an example of an electronic device that serves as a light source. For example, each of the pixels PXL in a display panel PNL may have at least one light-emitting element (LD).

[0085] For the sake of explanation, Figure 5 The structure of a display panel PNL according to an embodiment is simply illustrated, with focus on the display area DA. In some embodiments, although not shown, at least one driving circuit (e.g., at least one of a scan driver and a data driver) and / or multiple lines may also be provided in the display panel PNL.

[0086] Reference Figure 5The display panel PNL according to embodiments of the present disclosure may include a substrate layer BSL and a plurality of pixels PXL disposed on the substrate layer BSL. In embodiments, each pixel PXL may be a first-color pixel configured to emit light having a first color (e.g., red), a second-color pixel configured to emit light having a second color (e.g., green), and a third-color pixel configured to emit light having a third color (e.g., blue). The type and / or arrangement structure of the pixels PXL may be varied in various ways depending on the embodiments.

[0087] The display panel PNL and the substrate layer BSL used to form the display panel PNL may include a display area DA for displaying images and a non-display area NDA other than the display area DA. Pixels PXL may be set on the substrate layer BSL in the display area DA.

[0088] In this embodiment, the display area DA can be located in the central area of ​​the display panel PNL, and the non-display area NDA can be located in the peripheral area of ​​the display panel PNL in a manner that surrounds the display area DA. The positions of the display area DA and the non-display area NDA are not limited to this, and their positions can be changed. The display area DA can form a screen on which an image is displayed.

[0089] The substrate layer (BSL) can form the substrate of the display panel (PNL). In embodiments, the substrate layer (BSL) can be a rigid or flexible substrate or film, and there are no particular limitations on the material or properties of the substrate layer (BSL). For example, the substrate layer (BSL) can be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer, and there are no particular limitations on the material and / or properties of the substrate layer (BSL).

[0090] Furthermore, the substrate layer BSL can be transparent, but this disclosure is not limited thereto. For example, the substrate layer BSL can be a transparent, translucent, opaque, or reflective substrate.

[0091] One region of the substrate layer BSL can be defined as a display area DA in which pixels PXL are disposed, and another region of the substrate layer BSL can be defined as a non-display area NDA. For example, the substrate layer BSL may include a display area DA and a non-display area NDA located around the display area DA, wherein the display area DA includes a plurality of pixel regions in which corresponding pixels PXL are formed. Various lines and / or internal circuitry connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0092] Multiple pixels PXL can be distributed and arranged in the display area DA. For example, multiple pixels PXL can be arranged regularly in the display area DA in a stripe or pen-tile (or "five-tile") arrangement. The arrangement structure of pixels PXL is not limited to this, and pixels PXL can be arranged in the display area DA in various structures and / or schemes.

[0093] Each pixel PXL may include at least one light source driven by a predetermined control signal (e.g., a scan signal and a data signal) and / or a predetermined power supply (e.g., a first power supply and a second power supply). In an embodiment, each pixel PXL may include, according to... Figures 1a to 3b In any of the embodiments, at least one light-emitting element LD, for example, is at least one ultra-small rod-shaped light-emitting element LD manufactured by an etching scheme to have a small size ranging from nanometer to micrometer. In the embodiments, each pixel PXL may include, according to Figure 4a and Figure 4b At least one light-emitting element (LD) in the embodiment is, for example, at least one ultra-miniature core-shell light-emitting element (LD) fabricated by a growth scheme to have a small size ranging from nanometer to micrometer. Alternatively, different types of light-emitting elements (LDs) can be used as the light source for the pixel PXL.

[0094] In embodiments, each pixel PXL may be formed of an active pixel. For example, a pixel PXL may also include a light-emitting element (LD) and pixel circuitry configured to control the emission of the light-emitting element LD. However, there are no particular limitations on the type, structure, and / or driving scheme of the pixel PXL that can be applied to the display device according to this disclosure. For example, each pixel PXL may have the same structure as pixels used in passive or active light-emitting display devices having various known structures and / or capable of operating with various known driving schemes.

[0095] Figures 6a to 6g The diagrams shown are circuit diagrams of pixel PXL according to embodiments of the present disclosure. For example, Figures 6a to 6g Different embodiments of the pixel PXL that can be applied to active display devices are shown. However, the types of pixel PXL and display devices to which the embodiments of this disclosure can be applied are not limited thereto. In the embodiments, Figures 6a to 6g Each pixel PXL shown can be set in the PXL position. Figure 5 Any one of the pixels PXL in the display panel PNL. Pixels PXL can have substantially the same or similar structures.

[0096] Reference Figure 6aAccording to embodiments of the present disclosure, a pixel PXL may include a light source unit LSU configured to generate light having a brightness corresponding to a data signal. The pixel PXL may also optionally include a pixel circuit PXC configured to drive the light source unit LSU.

[0097] In an embodiment, the light source unit LSU may include at least one light-emitting element LD connected between a first power supply (or first power source) VDD and a second power supply (or second power source) VSS, for example, multiple light-emitting elements LD. For example, the light source unit LSU may include a first electrode ELT1 (also referred to as a "first pixel electrode" or "first alignment electrode") connected to the first power supply VDD via a pixel circuit PXC and a first power line PL1, a second electrode ELT2 (also referred to as a "second pixel electrode" or "second alignment electrode") connected to the second power supply VSS via a second power line PL2, and multiple light-emitting elements LD connected in parallel to each other in the same direction between the first electrode ELT1 and the second electrode ELT2. In an embodiment, the first electrode ELT1 may be an anode electrode, and the second electrode ELT2 may be a cathode electrode.

[0098] In an embodiment, each of the light-emitting elements (LDs) may include a first terminal (e.g., a P-type terminal) connected to a first power supply VDD via a first electrode ELT1 and / or pixel circuit PXC, and a second terminal (e.g., an N-type terminal) connected to a second power supply VSS via a second electrode ELT2. In an embodiment, the light-emitting elements (LDs) may be connected in parallel in a forward direction between the first electrode ELT1 and the second electrode ELT2. Each of the light-emitting elements (LDs) connected in a forward direction between the first power supply VDD and the second power supply VSS can form an effective light source. The effective light source can form the light source unit (LSU) of pixel PXL.

[0099] In this embodiment, the first power supply VDD and the second power supply VSS can have different potentials to enable the light-emitting element LD to emit light. For example, the first power supply VDD can be set to a high potential, and the second power supply VSS can be set to a low potential. Here, at least during the emission period of pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS can be set to the threshold voltage of the light-emitting element LD or a higher voltage.

[0100] In an embodiment, one end (e.g., the P-type end) of the light-emitting element LD forming each light source unit LSU can be connected to the pixel circuit PXC via one electrode of the light source unit LSU (e.g., the first electrode ELT1 of each pixel PXL), and connected to the first power supply VDD via the pixel circuit PXC and the first power line PL1. The remaining end (e.g., the N-type end) of the light-emitting element LD can be connected to the second power supply VSS via another electrode of the light source unit LSU (e.g., the second electrode ELT2 of each pixel PXL) and the second power line PL2.

[0101] The light-emitting element (LD) can emit light with a brightness corresponding to the driving current supplied to it through the corresponding pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply a driving current corresponding to the grayscale value to be represented in the corresponding frame to the light source unit (LSU). The driving current supplied to the light source unit (LSU) can be divided into portions flowing to the light-emitting elements (LDs) connected in the forward direction. Therefore, each of the light-emitting elements (LDs) can emit light with a brightness corresponding to the current applied to it, such that the light source unit (LSU) can emit light with a brightness corresponding to the driving current.

[0102] In an embodiment, the light source unit LSU may include, in addition to the light-emitting elements LD that form each effective light source, at least one ineffective light source. For example, at least one reverse light-emitting element LDrv may also be connected between the first electrode ELT1 and the second electrode ELT2.

[0103] Each reverse-emitting element (LDrv) and the light-emitting element (LD) forming an effective light source can be connected in parallel between the first electrode ELT1 and the second electrode ELT2, and can be connected between the first electrode ELT1 and the second electrode ELT2 in a direction opposite to that of the light-emitting element LD. For example, the N-type terminal of the reverse-emitting element LDrv can be connected to the first power supply VDD via the first electrode ELT1 and the pixel circuit PXC. The P-type terminal of the reverse-emitting element LDrv can be connected to the second power supply VSS via the second electrode ELT2. Even when a predetermined driving voltage (e.g., a forward driving voltage) is applied between the first electrode ELT1 and the second electrode ELT2, the reverse-emitting element LDrv remains inactive. Therefore, current essentially does not flow through the reverse-emitting element LDrv.

[0104] Furthermore, in an embodiment, at least one pixel PXL may also include at least one invalid light source (not shown) that is not fully connected between the first electrode ELT1 and the second electrode ELT2. For example, at least one pixel PXL may also include at least one invalid light-emitting element disposed in the light source unit LSU and whose first end EP1 and second end EP2 are not fully connected to the first electrode ELT1 and the second electrode ELT2.

[0105] The pixel circuit PXC is connected between the first power supply VDD and the first electrode ELT1 of the light source unit LSU. The pixel circuit PXC can be connected to the scan line Si and data line Dj of the corresponding pixel PXL. For example, if pixel PXL is set on the i-th (i is a positive integer) horizontal line (row) and j-th (j is a positive integer) vertical line (column) of the display area DA, then the pixel circuit PXC of pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0106] In an embodiment, the pixel circuit PXC may include multiple transistors and at least one capacitor. For example, the pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0107] The first transistor T1 can be connected between the first power supply VDD and the light source unit LSU. For example, the first electrode (e.g., the source electrode) of the first transistor T1 can be connected to the first power supply VDD, and the second electrode (e.g., the drain electrode) of the first transistor T1 can be connected to the first electrode ELT1 of the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can control the drive current to be supplied to the light source unit LSU in response to the voltage of the first node N1. In other words, the first transistor T1 can be a drive transistor configured to control the drive current of the pixel PXL.

[0108] A second transistor T2 can be connected between the data line Dj and the first node N1. For example, the first electrode (e.g., the source electrode) of the second transistor T2 can be connected to the data line Dj, and the second electrode (e.g., the drain electrode) of the second transistor T2 can be connected to the first node N1. The gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal SSi with a gate on-state voltage (e.g., a low-level voltage) is supplied from the scan line Si, the second transistor T2 can be turned on to electrically connect the first node N1 to the data line Dj.

[0109] During each frame period, the data signal DSj corresponding to the frame is supplied to the data line Dj, and the data signal DSj is transmitted to the first node N1 through the second transistor T2, which is turned on during the period in which the scan signal SSi with a gate on voltage is supplied. In other words, the second transistor T2 can be a switching transistor configured to transmit each data signal DSj to the inside of the pixel PXL.

[0110] One electrode of the storage capacitor Cst is connected to the first power supply VDD, and the other electrode of the storage capacitor Cst is connected to the first node N1. During each frame period, the storage capacitor Cst can be charged with a voltage corresponding to the data signal DSj to be supplied to the first node N1.

[0111] Although Figure 6a In the present invention, transistors (e.g., first transistor T1 and second transistor T2) included in the pixel circuit PXC have been shown as being formed of P-type transistors, but this disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0112] For example, such as Figure 6b As shown, each of the first transistor T1 and the second transistor T2 can be formed by an N-type transistor. In this case, the gate turn-on voltage for writing the data signal DSj supplied to the data line Dj in each frame cycle to the scan signal SSi of the pixel PXL can be a high-level voltage (also referred to as "gate high voltage"). Similarly, the voltage for turning on the data signal DSj of the first transistor T1 can be a voltage with a voltage similar to that of the second transistor T1. Figure 6a The voltage level is opposite to the level of the embodiment. For example, in Figure 6b In this embodiment, when the grayscale value to be represented increases, a data signal DSj with a higher voltage can be supplied. In this embodiment, the first transistor T1 and the second transistor T2 can be different conductive transistors. For example, one of the first transistor T1 and the second transistor T2 can be a P-type transistor, and the other can be an N-type transistor.

[0113] In this embodiment, the interconnection position between the pixel circuit PXC and the light source unit LSU can be changed. For example, as... Figure 6b As shown, when both the first transistor T1 and the second transistor T2 forming the pixel circuit PXC are N-type transistors, the pixel circuit PXC can be connected between the light source unit LSU and the second power supply VSS, and the storage capacitor Cst can be connected between the first node N1 and the second power supply VSS. However, this disclosure is not limited thereto. For example, in an embodiment, even when the pixel circuit PXC is formed by N-type transistors, the pixel circuit PXC can still be connected between the first power supply VDD and the light source unit LSU.

[0114] Apart from the fact that the connection positions of some circuit elements and the voltage levels of control signals (e.g., scan signal SSi and data signal DSj) change according to the types of the first transistor T1 and the second transistor T2, Figure 6b The pixel PXL shown is similar in construction and operation to Figure 6a The pixels PXL are basically similar. Therefore, the pixel values ​​will be omitted. Figure 6b Detailed description of the pixel PXL.

[0115] The structure of pixel circuits (PXC) is not limited to Figure 6a and Figure 6b The embodiment shown. For example, the construction of the pixel circuit PXC can be similar to... Figure 6c or Figure 6d The embodiments shown are constructed similarly. In other words, the pixel circuit PXC can be formed from known pixel circuits that can have various structures and / or operate through various driving schemes.

[0116] Reference Figure 6c The pixel circuit PXC can also be connected to the sensing control line SCLi and the sensing line SLj. For example, the pixel circuit PXC of pixel PXL, which is located on the i-th horizontal line and j-th vertical line of display area DA, can be connected to the i-th sensing control line SCLi and the j-th sensing line SLj of display area DA. The pixel circuit PXC may also include a third transistor T3. In an embodiment, the sensing line SLj can be omitted, and the characteristics of pixel PXL can be detected by detecting the sensing signal SENj via data line Dj.

[0117] The third transistor T3 is connected between the first transistor T1 and the sensing line SLj. For example, the first electrode of the third transistor T3 can be connected to the first electrode (e.g., the source electrode) of the first transistor T1 connected to the first electrode ELT1, and the second electrode of the third transistor T3 can be connected to the sensing line SLj. If the sensing line SLj is omitted, the second electrode of the third transistor T3 can be connected to the data line Dj.

[0118] In one embodiment, the gate electrode of the third transistor T3 is connected to the sensing control line SCLi. If the sensing control line SCLi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si. During a predetermined sensing period, the third transistor T3 can be turned on by a sensing control signal SCSi having a gate on-state voltage (e.g., a high-level voltage) supplied to the sensing control line SCLi, and thus electrically connect the sensing line SLj to the first transistor T1.

[0119] In an embodiment, the sensing period can be a period in which characteristics (e.g., the threshold voltage of the first transistor T1, etc.) of each pixel PXL disposed in the display area DA are extracted. During the sensing period, the first transistor T1 can be turned on by supplying a predetermined reference voltage capable of turning on the first transistor T1 to the first node N1 via data line Dj and the second transistor T2, or by connecting each pixel PXL to a current source, etc. Furthermore, the third transistor T3 can be turned on by supplying a sensing control signal SCSi having a gate turn-on voltage to the third transistor T3, so that the first transistor T1 can be connected to the sensing line SLj. Thereafter, a sensing signal SENj can be obtained through the sensing line SLj, and the characteristics of each pixel PXL, including the threshold voltage of the first transistor T1, etc., can be detected using the sensing signal SENj. Information about the characteristics of each pixel PXL can be used to convert image data so that characteristic deviations between pixels PXL disposed in the display area DA can be compensated.

[0120] Although Figure 6c An embodiment is shown in which all of the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors, but the invention is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 can be changed to a P-type transistor. Furthermore, although... Figure 6c An embodiment is shown in which the light source unit LSU is connected between the pixel circuit PXC and the second power supply VSS, but this disclosure is not limited thereto. For example, in an embodiment, the light source unit LSU may be connected between the first power supply VDD and the pixel circuit PXC.

[0121] Reference Figure 6d The pixel circuit PXC can be connected not only to the scan line Si of the corresponding horizontal line, but also to at least one other scan line or control line. For example, the pixel circuit PXC of pixel PXL located on the i-th horizontal line of display area DA can also be connected to the (i-1)-th scan line Si-1 and / or the (i+1)-th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to other power supplies. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC may include the first transistor T1 to the seventh transistor T7 and the storage capacitor Cst.

[0122] The first transistor T1 can be connected between the first power supply VDD and the light source unit LSU. For example, the first electrode (e.g., the source electrode) of the first transistor T1 can be connected to the first power supply VDD via the fifth transistor T5 and the first power line PL1, and the second electrode (e.g., the drain electrode) of the first transistor T1 can be connected to an electrode (e.g., the first electrode ELT1) of the light source unit LSU via the sixth transistor T6. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can control the drive current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0123] A second transistor T2 is connected between the data line Dj and the first electrode (e.g., the source electrode) of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line Si. When a scan signal SSi with a gate on-state voltage is supplied from the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal DSj supplied from the data line Dj can be transmitted to the first transistor T1.

[0124] The third transistor T3 can be connected between the second electrode (e.g., the drain electrode) of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line Si. When a scan signal SSi with a gate on-state voltage is supplied from the scan line Si, the third transistor T3 can be turned on to connect the first transistor T1 as a diode. Therefore, during the period in which the scan signal SSi with a gate on-state voltage is supplied, the first transistor T1 can be turned on as a diode, so that the data signal DSj can be continuously supplied from the data line Dj to the first node N1 via the second transistor T2, the first transistor T1, and the third transistor T3. Therefore, the voltage corresponding to the threshold voltage of the data signal DSj and the first transistor T1 is charged into the storage capacitor Cst.

[0125] The fourth transistor T4 is connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the (i-1)th scan line Si-1. When a scan signal SSi-1 with a gate on-state voltage is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 can be turned on, so that the voltage of the initialization power supply Vint can be transmitted to the first node N1.

[0126] In this embodiment, the voltage of the initialization power supply Vint can be the minimum voltage of the data signal DSj or a lower voltage. Before the data signal DSj of the corresponding frame is supplied to each pixel PXL, the first node N1 can be initialized to the voltage of the initialization power supply Vint by a scan signal SSi-1 with a gate on voltage supplied to the (i-1)th scan line Si-1. Therefore, regardless of the voltage of the data signal DSj of the previous frame, during the period when the scan signal SSi with a gate on voltage is supplied to the i-th scan line Si, the first transistor T1 is connected to the diode in the forward direction, so that the data signal DSj of the corresponding frame can be reliably transmitted to the first node N1.

[0127] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emitter control line, for example, the i-th emitter control line Ei. The fifth transistor T5 can be turned off when an emitter control signal ESi with a gate cutoff voltage (e.g., a high-level voltage) is supplied to the emitter control line Ei, and can be turned on under other conditions.

[0128] The sixth transistor T6 is connected between the first transistor T1 and the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The sixth transistor T6 is turned off when an emission control signal ESi with a gate cutoff voltage is supplied to the emission control line Ei, and is turned on under other conditions.

[0129] The fifth transistor T5 and the sixth transistor T6 can control the emission period of pixel PXL. For example, if the fifth transistor T5 and the sixth transistor T6 are turned on, a current path can be formed, allowing the drive current to flow continuously from the first power supply VDD through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light source unit LSU to the second power supply VSS. If the fifth transistor T5 and the sixth transistor T6 are turned off, the current path can be blocked, thus preventing the emission of pixel PXL.

[0130] A seventh transistor T7 is connected between the first electrode (e.g., first electrode ELT1) of the light source unit LSU and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to the scan line used to select the next horizontal line pixel PXL, for example, the (i+1)th scan line Si+1. When a scan signal SSi+1 with a gate on voltage is supplied to the (i+1)th scan line Si+1, the seventh transistor T7 is turned on, allowing the voltage of the initialization power supply Vint to be supplied to the first electrode (e.g., the first pixel electrode ELT1) of the light source unit LSU. In this case, during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode of the light source unit LSU can be initialized.

[0131] The control signal used to control the operation of the seventh transistor T7 can be changed in various ways. For example, in an embodiment, the gate electrode of the seventh transistor T7 can be connected to the scan line of the corresponding horizontal line (i.e., the i-th scan line Si) or the scan line of the previous horizontal line (e.g., the (i-1)-th scan line Si-1). In this case, when a scan signal SSi (or SSi-1) with a gate on-state voltage is supplied to the i-th scan line Si or the (i-1)-th scan line Si-1, the seventh transistor T7 can be turned on, allowing the voltage of the initialization power supply Vint to be supplied to the first electrode of the light source unit LSU. Therefore, during each frame period, pixel PXL can emit light with more uniform brightness in response to the data signal DSj.

[0132] The storage capacitor Cst is connected between the first power supply VDD and the first node N1. The storage capacitor Cst can store a voltage that corresponds to both the data signal DSj applied to the first node N1 and the threshold voltage of the first transistor T1 during each frame period.

[0133] Although Figure 6d In the present disclosure, all of the transistors included in the pixel circuit PXC (e.g., the first transistor T1 to the seventh transistor T7) have been shown as being formed of P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be changed to an N-type transistor.

[0134] Although Figures 6a to 6d An embodiment in which all effective light sources (i.e., light-emitting elements LD) constituting each light source unit (LSU) are connected in parallel with each other is shown, but this disclosure is not limited thereto. For example, in embodiments of this disclosure, such as Figures 6e to 6g As shown, the light source unit (LSU) of each pixel PXL can be constructed to include at least two levels of cascaded structure. Figures 6e to 6g In the following description of the embodiments, the terms "and" will be omitted. Figures 6a to 6dDetailed explanation of components similar to or the same as those in the embodiments (e.g., pixel circuit PXC).

[0135] Reference Figure 6e A light source unit (LSU) may include at least two light-emitting elements connected in series with each other. For example, a light source unit (LSU) may include a first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3, which are connected in series in the forward direction between a first power supply VDD and a second power supply VSS, thus forming each effective light source. In the following text, when referring to a specific light-emitting element among the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, the corresponding light-emitting element will be referred to as "first light-emitting element LD1," "second light-emitting element LD2," or "third light-emitting element LD3." The terms "light-emitting element LD" or "multiple light-emitting elements LD" will be used to arbitrarily refer to at least one of the first light-emitting elements LD1, the second light-emitting element LD2, and the third light-emitting element LD3, or to collectively refer to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3.

[0136] The first end (e.g., P-type end) of the first light-emitting element LD1 is connected to the first power supply VDD via the first electrode (i.e., the first pixel electrode) ELT1 of the light source unit LSU. The second end (e.g., N-type end) of the first light-emitting element LD1 is connected to the first end (e.g., P-type end) of the second light-emitting element LD2 via the first intermediate electrode IET1 (also referred to as the "third pixel electrode").

[0137] The first end (e.g., P-type end) of the second light-emitting element LD2 is connected to the second end of the first light-emitting element LD1. The second end (e.g., N-type end) of the second light-emitting element LD2 is connected to the first end (e.g., P-type end) of the third light-emitting element LD3 via the second intermediate electrode IET2 (also referred to as the "fourth pixel electrode").

[0138] The first end (e.g., the P-type end) of the third light-emitting element LD3 is connected to the second end of the second light-emitting element LD2. The second end (e.g., the N-type end) of the third light-emitting element LD3 is connected to the second power supply VSS via the second electrode (i.e., the second pixel electrode) ELT2 of the light source unit LSU. In this way, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be continuously connected in series between the first electrode ELT1 and the second electrode ELT2 of the light source unit LSU.

[0139] Although Figure 6eThe illustration shows an embodiment in which light-emitting elements (LDs) are connected in a three-stage series structure, but this disclosure is not limited thereto. For example, in embodiments of this disclosure, two light-emitting elements (LDs) may be connected in a two-stage series structure, or four or more light-emitting elements (LDs) may be connected in a four-stage or more series structure.

[0140] When assuming that light-emitting elements (LDs) with the same conditions (e.g., the same size and / or number) produce the same brightness, compared to a light source unit (LSU) with LDs connected in parallel, a light source unit (LSU) with LDs connected in series can increase the voltage applied between the first electrode ELT1 and the second electrode ELT2, and decrease the amount of drive current flowing to the light source unit (LSU). Therefore, when using a light source unit (LSU) with a series structure forming each pixel PXL, the panel current flowing through the display panel (PNL) can be reduced.

[0141] In an embodiment, at least one series stage may include multiple light-emitting elements (LDs) connected in parallel with each other. In this case, the light source unit (LSU) may be formed by a series / parallel combination structure. For example, the light source unit (LSU) may be as follows: Figure 6f or Figure 6g The configuration is shown in the embodiments.

[0142] Reference Figure 6f At least one series stage forming a light source unit (LSU) may include multiple light-emitting elements (LDs) connected in parallel to each other in a forward direction. For example, the light source unit (LSU) may include at least one first light-emitting element (LD1) disposed in a first series stage (also referred to as "first stage" or "first row"), at least one second light-emitting element (LD2) disposed in a second series stage (also referred to as "second stage" or "second row") following the first series stage, and at least one third light-emitting element (LD3) disposed in a third series stage (also referred to as "third stage" or "third row") following the second series stage. Furthermore, at least one of the first, second, and third series stages may include multiple light-emitting elements (LDs) connected in a forward direction.

[0143] Although Figure 6f A light source unit (LSU) formed by light-emitting elements (LDs) arranged in three series stages has already been shown, but this disclosure is not limited thereto. For example, as Figure 6gAs shown, the light source unit (LSU) may include multiple light-emitting elements (LDs) disposed in only two series stages (i.e., a first series stage and a second series stage). For example, the light source unit (LSU) may include at least one first light-emitting element (LD1) and at least one second light-emitting element (LD2). The at least one first light-emitting element (LD1) is disposed in the first series stage and includes a first end (e.g., a P-type end) and a second end (e.g., an N-type end) respectively connected to the first electrode (ELT1) and the intermediate electrode (IET). The at least one second light-emitting element (LD2) is disposed in the second series stage and includes a first end (e.g., a P-type end) and a second end (e.g., an N-type end) respectively connected to the intermediate electrode (IET) and the second electrode (ELT2). Furthermore, at least one of the first series stage and the second series stage may include multiple light-emitting elements (LDs) connected in a forward direction.

[0144] Furthermore, the number of series stages forming the light source unit (LSU) can be varied in various ways. For example, the light source unit (LSU) may include multiple light-emitting elements (LDs) distributed in four or more series stages. Additionally, the number of light-emitting elements (LDs) connected in the forward direction in each series stage can be varied in various ways.

[0145] In this embodiment, it is set in the display area ( Figure 5 The number of light-emitting elements (LDs) included in pixel PXL in the DA can be equal or similar to each other. For example, in the operation of supplying LDs to each pixel PXL, the LDs can be aligned in such a way that the LD ink (or "light-emitting solution") including the LDs is controlled to be uniformly applied to the emission region of each pixel PXL and a uniform electric field is controlled to be applied to each pixel PXL. Therefore, the LDs can be supplied to and aligned relatively uniformly in pixel PXL.

[0146] In an embodiment, such as Figure 6f and Figure 6g As shown, each pixel PXL may further include at least one reverse-emitting element LDrv disposed in at least one cascade stage. For example, at least one of the multiple cascade stages may further include at least one reverse-emitting element LDrv connected in a direction opposite to that of the emitting element LD.

[0147] Even when the reverse-emitting element LDrv is connected to at least one series stage, if at least one effective light source (e.g., the first emitting element LD1, the second emitting element LD2, and / or the third emitting element LD3) is provided and connected in the forward direction to the series stage, the driving current of the pixel PXL can flow continuously through the series stage. Therefore, the light source unit LSU can emit light with a brightness corresponding to the driving current.

[0148] As described in the foregoing embodiments, each light source unit (LSU) may include multiple light-emitting elements (LDs), which are connected in a forward direction between a first power supply (VDD) and a second power supply (VSS) to form a corresponding effective light source. Furthermore, the connection structure between the light-emitting elements (LDs) can be varied in various ways depending on the embodiments. For example, the light-emitting elements (LDs) may be connected in series or in parallel, or in a series / parallel combination structure.

[0149] As described above, the pixel PXL may include a pixel circuit PXC and / or a light source unit LSU, which may have various structures. The structures applicable to the pixel PXL of this disclosure are not limited to those described above. Figures 6a to 6g The embodiments shown are illustrated, and each pixel PXL can have various known structures. For example, each pixel circuit PXC can be formed by a known pixel circuit that can have various structures and / or operate in various driving modes. In the embodiments of this disclosure, each pixel PXL can be constructed in a passive light-emitting display device, etc. In this case, the pixel circuit PXC can be omitted, and each of the first electrode ELT1 and the second electrode ELT2 of the light source unit LSU can be directly connected to the scan line Si, the data line Dj, the first power line PL1, the second power line PL2, or other signal lines or power lines, etc.

[0150] Figure 7a and Figure 7b This is a plan view illustrating a pixel PXL according to a corresponding embodiment of the present disclosure. For example, Figure 7a and Figure 7b It shows that it can be set to Figure 5 Different embodiments of the pixel PXL in the display area DA. For example, Figure 7a An embodiment of a pixel PXL is shown, comprising a first dam pattern BNK1 and a second dam pattern BNK2 disposed beneath a first electrode ELT1 and a second electrode ELT2. Figure 7b An embodiment is shown that excludes the first dam pattern BNK1 and the second dam pattern BNK2.

[0151] According to each embodiment, in Figure 7a and Figure 7b In the diagram, the structure of each pixel PXL is shown with the light source unit LSU of pixel PXL as the center. In an embodiment, each pixel PXL may also optionally include circuit elements connected to the light source unit LSU (e.g., multiple circuit elements forming each pixel circuit PXC).

[0152] also, Figure 7a and Figure 7bAn embodiment is shown in which each light source unit LSU is connected via a first contact hole CH1 and a second contact hole CH2 to predetermined power lines (e.g., first power line PL1 and / or second power line PL2), circuit elements (e.g., at least one circuit element forming a pixel circuit PXC), and / or signal lines (e.g., scan lines Si and / or data lines Dj). However, this disclosure is not limited thereto. For example, in an embodiment, at least one of the first electrode ELT1 and the second electrode ELT2 of each pixel PXL can be directly connected to the predetermined power lines and / or signal lines without using contact holes and / or intermediate lines.

[0153] Reference Figures 5 to 7b According to embodiments of the present disclosure, a pixel PXL may include a first electrode ELT1 and a second electrode ELT2 disposed in each emission region EMA, and at least one light-emitting element LD disposed between the first electrode ELT1 and the second electrode ELT2 (e.g., multiple light-emitting elements LD connected in parallel between the first electrode ELT1 and the second electrode ELT2). Furthermore, the pixel PXL may also include a first electrode line ELI1 (also referred to as a "first connection electrode" or "first alignment line") and a first contact hole CH1 configured to connect the first electrode ELT1 to the pixel circuit PXC and / or the first power line PL1; a second electrode line ELI2 (also referred to as a "second connection electrode" or "second alignment line") and a second contact hole CH2 configured to connect the second electrode ELT2 to the second power line PL2; and a first contact electrode CNE1 (also referred to as a "third electrode") and a second contact electrode CNE2 (also referred to as a "fourth electrode") configured to electrically connect the light-emitting element LD between the first electrode ELT1 and the second electrode ELT2.

[0154] Additionally, pixel PXL may optionally include a first dam pattern BNK1 (also referred to as a "first partition wall") and a second dam pattern BNK2 (also referred to as a "second partition wall") superimposed on the first electrode ELT1 and the second electrode ELT2, respectively. For example, as Figure 7a As shown in the embodiments, the pixel PXL may include a first embankment pattern BNK1 disposed below each first electrode ELT1 and superimposed on a region of the first electrode ELT1, and a second embankment pattern BNK2 disposed below the second electrode ELT2 and superimposed on a region of the second electrode ELT2. Optionally, as Figure 7b As shown in the embodiments, pixel PXL may not include the first dike pattern BNK1 and the second dike pattern BNK2.

[0155] The first dam pattern BNK1 and the second dam pattern BNK2, the first electrode ELT1 and the second electrode ELT2, the light-emitting element LD, and / or the first contact electrode CNE1 and the second contact electrode CNE2, etc., can form the light source unit LSU of pixel PXL.

[0156] The first electrode ELT1 and the second electrode ELT2 can be disposed in each pixel region in which the pixel PXL is disposed and / or formed. For example, the first electrode ELT1 and the second electrode ELT2 can be disposed in the emission region EMA of each pixel PXL.

[0157] In an embodiment, each pixel region may include a pixel circuit region in which circuit elements for forming the corresponding pixel PXL are disposed, and an emission region EMA in which a light source unit LSU of the pixel PXL is disposed. The emission region EMA may be a region in which a light-emitting element LD (specifically, an effective light source completely connected between the first electrode ELT1 and the second electrode ELT2) forming the light source unit LSU of each pixel PXL is disposed. Furthermore, a portion of a predetermined electrode (e.g., the first electrode ELT1 and the second electrode ELT2 and / or the first contact electrode CNE1 and the second contact electrode CNE2) or a portion of an electrode connected to the light-emitting element LD may be disposed in the emission region EMA.

[0158] The emission region EMA may be surrounded by light-blocking and / or reflective dam structures (e.g., pixel-defining layers and / or black matrices), which are formed between pixels PXL to define each pixel region and the emission region EMA formed within that pixel region. For example, dam structures surrounding the emission region EMA may be disposed around the emission region EMA.

[0159] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other. For example, the first electrode ELT1 and the second electrode ELT2 may be arranged in parallel at positions spaced apart from each other by a predetermined distance along the first direction DR1 in each emission region EMA.

[0160] In embodiments, each of the first electrode ELT1 and the second electrode ELT2 may have a strip shape extending in either direction. For example, each of the first electrode ELT1 and the second electrode ELT2 may have a strip shape extending in a second direction DR2 that intersects (e.g., is perpendicular to) the first direction DR1. However, this disclosure is not limited thereto. For example, the shape, orientation, and / or relative arrangement of the first electrode ELT1 and the second electrode ELT2 may be varied in various ways.

[0161] Furthermore, one or more first electrodes ELT1 and second electrodes ELT2 may be disposed in each emission region EMA, and there is no particular limitation on the number of first electrodes ELT1 and second electrodes ELT2 disposed in the emission region EMA. For example, multiple first electrodes ELT1 extending in the second direction DR2 and parallel to each other may be disposed in the emission region EMA. At least one second electrode ELT2 facing each first electrode ELT1 may be disposed in the emission region EMA. For example, a second electrode ELT2 disposed between two first electrodes ELT1 or multiple second electrodes ELT2 respectively corresponding to multiple first electrodes ELT1 may be disposed in the emission region EMA.

[0162] In an embodiment, the first electrode ELT1 can be electrically connected via the first electrode line ELI1 and / or the first contact hole CH1 to a predetermined circuit element (e.g., at least one transistor forming a pixel circuit PXC), a power line (e.g., the first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). In another embodiment, the first electrode ELT1 can be electrically connected via the first electrode line ELI1 and the first contact hole CH1 to a predetermined circuit element disposed below it, and is electrically connected via the circuit element to a first line. The first line may be the first power line PL1 for supplying a first power supply VDD, but this disclosure is not limited thereto. For example, in an embodiment, the first line may be a signal line through which a predetermined first drive signal (e.g., a scan signal, a data signal, or a predetermined control signal) can be supplied.

[0163] In an embodiment, the first electrode ELT1 can be directly connected to a predetermined power line or signal line without passing through the first electrode line ELI1, the first contact hole CH1, and / or circuit elements. In this case, the first electrode ELT1 can be integrally or non-integrally connected to the predetermined power line or signal line.

[0164] In this embodiment, the first electrode ELT1 and the first electrode line ELI1 can extend in different directions in each pixel region. For example, when the first electrode line ELI1 extends in the first direction DR1, the first electrode ELT1 can extend in the second direction DR2, which intersects the first direction DR1.

[0165] In embodiments, the first electrode ELT1 and the first electrode line ELI1 can be integrally connected to each other. For example, the first electrode ELT1 can branch off from the first electrode line ELI1 in at least one direction. When the first electrode ELT1 and the first electrode line ELI1 are integrally connected to each other, the first electrode line ELI1 can be considered as a region of the first electrode ELT1. However, this disclosure is not limited thereto. For example, in embodiments, the first electrode ELT1 and the first electrode line ELI1 can be formed separately from each other and connected to each other through at least one contact hole, via, etc.

[0166] In an embodiment, the second electrode ELT2 can be electrically connected via the second electrode line ELI2 and / or the second contact hole CH2 to a predetermined circuit element (e.g., at least one transistor forming a pixel circuit PXC), a power line (e.g., a second power line PL2), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). For example, the second electrode ELT2 can be electrically connected via the second electrode line ELI2 and the second contact hole CH2 to a second line disposed thereunder. The second line can be the second power line PL2 for supplying a second power supply VSS, but this disclosure is not limited thereto. For example, in an embodiment, the second line can be a signal line through which a predetermined second drive signal (e.g., a scan signal, a data signal, or a predetermined control signal) can be supplied.

[0167] In an embodiment, the second electrode ELT2 can be directly connected to a predetermined power line or signal line without passing through the second electrode line ELI2 and / or the second contact hole CH2. In this case, the second electrode ELT2 can be integrally or non-integrally connected to the predetermined power line or signal line.

[0168] In this embodiment, the second electrode ELT2 and the second electrode line ELI2 can extend in different directions. For example, when the second electrode line ELI2 extends in the first direction DR1, the second electrode ELT2 can extend in the second direction DR2, which intersects the first direction DR1.

[0169] In embodiments, the second electrode ELT2 and the second electrode line ELI2 can be integrally connected to each other. For example, the second electrode ELT2 can branch off from the second electrode line ELI2 in at least one direction. When the second electrode ELT2 and the second electrode line ELI2 are integrally connected to each other, the second electrode line ELI2 can be considered as a region of the second electrode ELT2. However, this disclosure is not limited thereto. For example, in embodiments, the second electrode ELT2 and the second electrode line ELI2 can be formed separately from each other and connected to each other through at least one contact hole, via, etc.

[0170] Here, during the process of forming pixel PXL (specifically, before the alignment of the light-emitting element LD is completed), the first electrodes ELT1 of pixel PXL disposed in the display area DA can be connected to each other, and the second electrodes ELT2 of pixel PXL can be connected to each other. During the alignment operation of the light-emitting element LD, the first electrodes ELT1 and the second electrodes ELT2 can be supplied with a first alignment signal (or a first alignment voltage) and a second alignment signal (or a second alignment voltage), respectively. For example, either the first electrode ELT1 or the second electrode ELT2 can be supplied with an AC alignment signal, and the other of the first electrode ELT1 and the second electrode ELT2 can be supplied with an alignment voltage having a constant voltage level (e.g., ground voltage).

[0171] In other words, during the alignment of the light-emitting elements (LDs), a predetermined alignment signal can be applied to the first electrode ELT1 and the second electrode ELT2, so that an electric field can be formed between the first electrode ELT1 and the second electrode ELT2. The LDs supplied to each pixel region (specifically, the emission region EMA of each pixel PXL) can self-align between the first electrode ELT1 and the second electrode ELT2 through the electric field. After the alignment of the LDs has been completed, the connection between the first electrode ELT1 and / or the connection between the second electrode ELT2 can be disconnected between pixels PXL, so that pixels PXL can be driven individually.

[0172] Each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer or multi-layer structure. For example, each first electrode ELT1 may include at least one reflective electrode layer and optionally also include at least one transparent electrode layer and / or a conductive capping layer. Similarly, each second electrode ELT2 may include at least one reflective electrode layer and optionally also include at least one transparent electrode layer and / or a conductive capping layer.

[0173] The first dam pattern BNK1 and the second dam pattern BNK2 can be selectively disposed below the first electrode ELT1 and the second electrode ELT2. For example, the first dam pattern BNK1 can be disposed below a region of the first electrode ELT1, and the second dam pattern BNK2 can be disposed below a region of the second electrode ELT2.

[0174] The first dam pattern BNK1 can be disposed below each first electrode ELT1 to overlap with the first electrode ELT1. For example, the first dam pattern BNK1 can have a width smaller than the width of each first electrode ELT1 and can be disposed below the first electrode ELT1. Therefore, the first electrode ELT1 can protrude upward in the area where the first dam pattern BNK1 is disposed. The first dam pattern BNK1 can form a reflective dam (also referred to as a "reflective partition wall") together with the first electrode ELT1. For example, each first electrode ELT1 and / or each first dam pattern BNK1 can be formed of a reflective material, or at least one layer of reflective material can be formed on the sidewall of the first electrode ELT1 and / or the first dam pattern BNK1. Therefore, the light emitted from the first end EP1 of the light-emitting element LD facing the first electrode ELT1 can be controlled to travel more effectively in the front direction of the display device.

[0175] The second dam pattern BNK2 can be disposed below the second electrode ELT2 to overlap with a region of the second electrode ELT2. For example, the second dam pattern BNK2 can have a width smaller than the width of the second electrode ELT2 and can be disposed below the second electrode ELT2. Therefore, the second electrode ELT2 can protrude upward in the region where the second dam pattern BNK2 is disposed. The second dam pattern BNK2 together with the second electrode ELT2 can form a reflective dam pattern. For example, each second electrode ELT2 and / or each second dam pattern BNK2 can be formed of a reflective material, or at least one layer of reflective material can be formed on the sidewalls of the second electrode ELT2 and / or the second dam pattern BNK2. Therefore, light emitted from the second end EP2 of the light-emitting element LD facing the second electrode ELT2 can be controlled to travel more effectively in the front direction of the display device.

[0176] In an embodiment, where each pixel PXL includes multiple first electrodes ELT1 and / or second electrodes ELT2, the pixel PXL may include multiple first dam patterns BNK1 and / or second dam patterns BNK2 superimposed on the corresponding first electrodes ELT1 and / or corresponding second electrodes ELT2. For example, the corresponding first dam patterns BNK1 and / or corresponding second dam patterns BNK2 may be arranged as separate patterns that are separate from each other.

[0177] Optionally, in an embodiment, multiple dam patterns, including at least one first dam pattern BNK1 and / or at least one second dam pattern BNK2, can be integrally connected to each other to form a single dam pattern. The single dam pattern may have an uneven surface that protrudes in the height direction in a region corresponding to each first electrode ELT1 and / or each second electrode ELT2. Therefore, since a region of the first electrode ELT1 and / or the second electrode ELT2 protrudes upwards, the light emitted from the light-emitting element LD can be controlled to travel more reliably in the frontal direction of the display device.

[0178] like Figure 7b As shown in the embodiments, the pixel PXL may not include the first dam pattern BNK1 and the second dam pattern BNK2. In this case, the first electrode ELT1 and the second electrode ELT2 may have a substantially planar shape, or may be formed with an uneven surface. For example, the uneven surface can be formed by varying the thickness of each of the first electrode ELT1 and the second electrode ELT2 by region, whereby a region of each of the first electrode ELT1 and the second electrode ELT2 can protrude upward. Therefore, the light emitted from the light-emitting element LD can be controlled to travel more reliably in the front direction of the display device.

[0179] The light-emitting elements (LDs) can be connected in parallel between the first electrode ELT1 and the second electrode ELT2. For example, each light-emitting element (LD) can be disposed between the first electrode ELT1 and the second electrode ELT2 in a first direction DR1 (e.g., in the horizontal direction) and can be electrically connected between the first electrode ELT1 and the second electrode ELT2.

[0180] Although Figure 7a and Figure 7b The illustration shows the light-emitting elements (LDs) uniformly oriented in any direction (e.g., in the first direction DR1), but this disclosure is not limited thereto. For example, at least one of the light-emitting elements (LDs) may be oriented along a diagonal direction between the first electrode ELT1 and the second electrode ELT2. Although in Figure 7a and Figure 7b Not shown, but at least one light-emitting element (i.e., an ineffective light source) that is not fully connected between the first electrode ELT1 and the second electrode ELT2 may also be provided in each emission region EMA and / or its peripheral region.

[0181] In embodiments, each of the light-emitting elements (LDs) can be a light-emitting element made of a material having an inorganic crystal structure and having an ultra-small size (e.g., ranging from nanometer to micrometer scale). For example, such as Figures 1a to 4bAs shown, each light-emitting element (LD) can be an ultra-small light-emitting element with a size ranging from nanometers to micrometers. However, the type and / or size of the light-emitting element (LD) can vary in various ways depending on the design conditions of each light-emitting device (e.g., pixel PXL) that uses the light-emitting element (LD) as a light source.

[0182] In an embodiment, each light-emitting element (LD) may include a first end EP1 facing an adjacent first electrode ELT1 and a second end EP2 facing an adjacent second electrode ELT2. In an embodiment, each of the light-emitting elements (LDs) may be stacked with or not stacked with the adjacent first electrode ELT1 and / or second electrode ELT2. For example, the first end EP1 of the light-emitting element (LD) may be stacked with or not stacked with the adjacent first electrode ELT1. Similarly, the second end EP2 of the light-emitting element (LD) may be stacked with or not stacked with the adjacent second electrode ELT2.

[0183] In an embodiment, the corresponding first end EP1 of the light-emitting element LD can be connected to the first electrode ELT1. The corresponding second end EP2 of the light-emitting element LD can be connected to the second electrode ELT2. For example, the corresponding first end EP1 of the light-emitting element LD can be electrically connected to the first electrode ELT1 through the first contact electrode CNE1. The corresponding second end EP2 of the light-emitting element LD can be electrically connected to the second electrode ELT2 through the second contact electrode CNE2. In an embodiment, at least one of the first end EP1 and the second end EP2 of each of the light-emitting elements LD can directly contact the first electrode ELT1 and / or the second electrode ELT2, and can be electrically connected to the first electrode ELT1 and / or the second electrode ELT2. In this case, the first contact electrode CNE1 and / or the second contact electrode CNE2 can be selectively formed.

[0184] In an embodiment, the light-emitting element (LD) can be prepared in a predetermined solution by diffusion and then supplied to each pixel region (specifically, the emitting region EMA of each pixel PXL) via various methods such as inkjet printing or slot coating. For example, the LD can be mixed with a volatile solvent and supplied to the emitting region EMA of each pixel PXL. Here, if a predetermined alignment voltage (or alignment signal) is applied to the first electrode ELT1 and the second electrode ELT2 of the pixel PXL, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, thereby aligning the LD between the first electrode ELT1 and the second electrode ELT2. After the LD has been aligned, the solvent can be removed by evaporation or other methods. In this way, the LD can be reliably disposed between the first electrode ELT1 and the second electrode ELT2.

[0185] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed on opposite ends of the light-emitting element LD (i.e., the first end EP1 and the second end EP2). Therefore, the light-emitting element LD can be more reliably connected between the first electrode ELT1 and the second electrode ELT2.

[0186] The first contact electrode CNE1 can be disposed on the first end EP1 adjacent to each first electrode ELT1 and at least one light-emitting element LD, such that the first contact electrode CNE1 is superimposed on the first end EP1 of the first electrode ELT1 and the light-emitting element LD. For example, the first contact electrode CNE1 can be disposed on the first end EP1 adjacent to each first electrode ELT1 and multiple light-emitting elements LD, such that the first contact electrode CNE1 is superimposed on the first end EP1 of the first electrode ELT1 and the light-emitting element LD.

[0187] The first contact electrode CNE1 can electrically connect the first electrode ELT1 to the first end EP1 of the light-emitting element LD. Furthermore, the first contact electrode CNE1 can stably fix the first end EP1 of the light-emitting element LD in place. In an embodiment, without forming the first contact electrode CNE1, the first end EP1 of the light-emitting element LD can be configured to overlap with and be directly connected to the adjacent first electrode ELT1.

[0188] The second contact electrode CNE2 can be disposed on the second end EP2 of each second electrode ELT2 and at least one light-emitting element LD adjacent to each second electrode ELT2, such that the second contact electrode CNE2 is superimposed on the second end EP2 of the second electrode ELT2 and the light-emitting element LD. For example, the second contact electrode CNE2 can be disposed on the second end EP2 of each second electrode ELT2 and multiple light-emitting elements LD adjacent to each second electrode ELT2, such that the second contact electrode CNE2 is superimposed on the second end EP2 of the second electrode ELT2 and the light-emitting element LD.

[0189] The second contact electrode CNE2 can electrically connect the second electrode ELT2 to the second terminal EP2 of the light-emitting element LD. Furthermore, the second contact electrode CNE2 can stably fix the second terminal EP2 of the light-emitting element LD in place. In an embodiment, without forming the second contact electrode CNE2, the second terminal EP2 of the light-emitting element LD can be configured to be stacked on top of and directly connected to the adjacent second electrode ELT2.

[0190] Each light-emitting element (LD) connected in the forward direction between the first electrode ELT1 and the second electrode ELT2 can form an effective light source for the corresponding pixel PXL. Such effective light sources can be grouped to form light source units (LSUs) for the corresponding pixel PXL.

[0191] For example, when the voltage of the first power supply VDD (or a predetermined first control signal such as a scan signal or data signal) is applied to the first terminal EP1 of the light-emitting element LD via the first power line PL1, the first electrode ELT1, and / or the first contact electrode CNE1, and the voltage of the second power supply VSS (or a predetermined second control signal such as a scan signal or data signal) is applied to the second terminal EP2 of the light-emitting element LD via the second power line PL2, the second electrode ELT2, and / or the second contact electrode CNE2, the light-emitting element LD, which is connected in the positive direction between the first electrode ELT1 and the second electrode ELT2, can emit light. Therefore, light is emitted from the pixel PXL.

[0192] Figures 8a to 8d and Figure 9 All of these show cross-sectional views of pixel PXL according to embodiments of the present disclosure. For example, Figures 8a to 8d It shows along Figure 7a Different embodiments of the cross-section of pixel PXL intercepted by line I-I'. Figure 9 It shows along Figure 7a An embodiment of the cross-section of pixel PXL intercepted by line II-II'. In this embodiment, it is set in the display area ( Figure 5 Pixels PXL in DA can have substantially the same or similar cross-sectional structures.

[0193] To illustrate the various circuit elements that form the pixel circuit PXC Figures 8a to 8d Any one of the transistors T in the circuit elements is shown, and Figure 9 The circuit elements shown include a storage capacitor Cst and a transistor connected to the first electrode ELT1 (e.g., Figure 6a and Figure 6b The first transistor T1). In the following text, when it is not necessary to separately indicate the first transistor T1, the term "transistor T" may be used to indicate the first transistor T1.

[0194] In the embodiments, the transistors T forming each pixel circuit PXC may have substantially the same or similar structures, but this disclosure is not limited thereto. Furthermore, the structure and / or location of the transistors T and the storage capacitor Cst can be varied in various ways according to the embodiments, and are not limited thereto. Figures 8a to 8d and Figure 9 The structure and / or location of the embodiments.

[0195] Reference Figures 5 to 9According to embodiments of the present disclosure, a pixel PXL and a display device including a pixel PXL may include a circuit layer PCL and a display layer DPL disposed on one surface of a substrate layer BSL. For example, a display area DA may include a circuit layer PCL disposed on one surface of the substrate layer BSL and a display layer DPL disposed on the circuit layer PCL.

[0196] In this embodiment, the circuit elements of the pixel circuit PXC forming each pixel PXL and the various lines connected thereto can be disposed in the circuit layer PCL. Furthermore, the electrodes (e.g., the first electrode ELT1 and the second electrode ELT2) of the light source unit LSU forming each pixel PXL and the light-emitting element LD connected thereto can be disposed in the display layer DPL.

[0197] The circuit layer PCL may include at least one circuit element electrically connected to the light-emitting element LD of each pixel PXL. For example, the circuit layer PCL may include a plurality of transistors T and a storage capacitor Cst disposed in each pixel region and forming the corresponding pixel PXL pixel circuit PXC. In addition, the circuit layer PCL may also include at least one power line and / or signal line connected to each pixel circuit PXC and / or light source unit LSU. For example, the circuit layer PCL may include a first power line PL1, a second power line PL2, and a scan line Si and a data line Dj for each pixel PXL. Here, if the pixel circuit PXC is omitted and the light source unit LSU of each pixel PXL is directly connected to the first power line PL1 and the second power line PL2 (or a predetermined signal line), the circuit layer PCL may be omitted.

[0198] The circuit layer PCL may include multiple insulating layers. For example, the circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and / or a passivation layer PSV that are continuously stacked on one surface of the substrate layer BSL. The circuit layer PCL may also optionally include at least one light-shielding pattern (not shown) disposed under at least some transistors T.

[0199] The buffer layer BFL prevents impurities from diffusing into each circuit element. The buffer layer BFL can be formed as a single layer or as a multilayer having at least two layers. In the case where the buffer layer BFL is formed as a multilayer, the corresponding layers can be formed of the same material or different materials. Various circuit elements, such as transistors T and storage capacitors Cst, as well as various lines connected to the circuit elements, can be disposed on the buffer layer BFL. In embodiments, the buffer layer BFL can be omitted. In this case, at least one circuit element and / or line can be directly disposed on one surface of the substrate layer BSL.

[0200] Each transistor T may include a semiconductor layer SCL (also referred to as a "semiconductor pattern" or "active layer"), a gate electrode GE, and a first transistor electrode TE1 and a second transistor electrode TE2. Although Figures 8a to 9 An embodiment is shown in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor layer SCL, but the present disclosure is not limited thereto. For example, in embodiments of the present disclosure, the first transistor electrode TE1 and / or the second transistor electrode TE2 disposed in at least one transistor T may be integral with the corresponding semiconductor layer SCL.

[0201] The semiconductor layer SCL can be disposed on the buffer layer BFL. For example, the semiconductor layer SCL can be disposed between the gate insulating layer GI and the substrate layer BSL on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region contacting each first transistor electrode TE1, a second region contacting each second transistor electrode TE2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0202] In this embodiment, the semiconductor layer SCL can be a semiconductor pattern formed from polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The channel region of the semiconductor layer SCL can be an intrinsic semiconductor that is an undoped semiconductor pattern. Each of the first and second regions of the semiconductor layer SCL can be a semiconductor pattern doped with a predetermined impurity.

[0203] In an embodiment, the semiconductor layer SCL of the transistor T forming each pixel circuit PXC can be formed of substantially the same or similar materials. For example, the semiconductor layer SCL of the transistor T can be formed of any of the same materials, such as polycrystalline silicon, amorphous silicon, and oxide semiconductor. In an embodiment, some and others of the transistor T may include semiconductor layers SCL formed of different materials. For example, the semiconductor layer SCL of some of the transistor T may be formed of polycrystalline silicon or amorphous silicon, while the semiconductor layer SCL of others of the transistor T may be formed of oxide semiconductor.

[0204] A gate insulating layer GI can be disposed on the semiconductor layer SCL. For example, the gate insulating layer GI can be disposed between the semiconductor layer SCL and the gate electrode GE. The gate insulating layer GI can be formed of a single layer or multiple layers and includes at least one inorganic insulating material and / or an organic insulating material. For example, the gate insulating layer GI may include silicon nitride (SiN) x ), silicon dioxide (SiO) x Various known organic / inorganic insulating materials, such as GI, are used. There are no particular restrictions on the constituent materials of the gate insulating layer GI.

[0205] The gate electrode GE can be disposed on the gate insulating layer GI. For example, the gate electrode GE can be stacked with the semiconductor layer SCL, and the gate insulating layer GI can be disposed between the gate electrode GE and the semiconductor layer SCL. Although Figures 8a to 9 The examples shown all depict a transistor T with a top-gate structure, but in other embodiments, the transistor T may have a bottom-gate structure. In this case, the gate electrode GE may be disposed below the semiconductor layer SCL to be stacked with the semiconductor layer SCL.

[0206] An interlayer insulating layer (ILD) can be disposed on the gate electrode GE. For example, the ILD can be disposed between the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2. The ILD can be formed of a single layer or multiple layers and includes at least one inorganic insulating material and / or an organic insulating material. For example, the ILD can include various known organic / inorganic insulating materials. There are no particular limitations on the constituent materials of the ILD.

[0207] A first transistor electrode TE1 and a second transistor electrode TE2 may be disposed on each semiconductor layer SCL, and at least one interlayer insulating layer ILD is disposed between the first transistor electrode TE1 and the second transistor electrode TE2 and each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on corresponding different ends of the semiconductor layer SCL, and a gate insulating layer GI and an interlayer insulating layer ILD are disposed between the first transistor electrode TE1 and the second transistor electrode TE2 and corresponding different ends of the semiconductor layer SCL. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be connected to a first region and a second region of the semiconductor layer SCL through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD. In an embodiment, either the first transistor electrode TE1 or the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0208] At least one transistor T disposed in the pixel circuit PXC can be connected to at least one pixel electrode. For example, Figures 6a to 6c The first transistor T1 shown is or Figure 6d The sixth transistor T6 and the seventh transistor T7 shown can be electrically connected to the first electrode ELT1 and / or the first electrode line ELI1 of the corresponding pixel PXL through a contact hole (e.g., the first contact hole CH1) through the passivation layer PSV.

[0209] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2 stacked on top of each other. In embodiments, each of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be formed of a single layer or multiple layers. Furthermore, at least one of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be disposed on the same layer as at least one electrode of the first transistor T1 or the semiconductor layer SCL.

[0210] For example, the first capacitor electrode CE1 can be formed of a multilayer electrode, which includes a lower electrode LE disposed on the same layer as the semiconductor layer SCL of the first transistor T1, and an upper electrode UE disposed on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 and electrically connected to the lower electrode LE. The second capacitor electrode CE2 can be formed of a single-layer electrode, which is disposed on the same layer as the gate electrode of the first transistor T1 and is located between the lower electrode LE and the upper electrode UE of the first capacitor electrode CE1.

[0211] This disclosure is not limited thereto. The structure and / or location of each of the first capacitor electrode CE1 and the second capacitor electrode CE2 can be changed in various ways. For example, in an embodiment, either the first capacitor electrode CE1 or the second capacitor electrode CE2 may include at least one conductive patterned layer disposed in a layer different from the layer forming the electrodes of the first transistor T1 (e.g., the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2) and the semiconductor layer SCL.

[0212] In an embodiment, at least one signal line and / or power line connected to each pixel PXL can be disposed on the same layer as the layer of one electrode in each of the circuit elements forming the pixel circuit PXC. For example, the scan line Si of each pixel PXL can be disposed on the same layer as the gate electrode GE. The data line Dj of each pixel PXL can be disposed on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of transistor T. Furthermore, the first power line PL1 and / or the second power line PL2 can be disposed on the same layer as the gate electrode GE of transistor T or the first transistor electrode TE1 and the second transistor electrode TE2. For example, the second power line PL2, used to supply the voltage of the second power supply VSS, can be disposed on the same layer as the gate electrode GE of transistor T, and is electrically connected both through the bridging pattern BRP disposed on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of transistor T and through the second contact hole CH2 passing through the passivation layer PSV to the second electrode line ELI2 and / or the second electrode ELT2 of the light source unit LSU disposed on the passivation layer PSV. However, the structure and / or position of the second power line PL2, etc., can be changed in various ways.

[0213] In an embodiment, the circuit layer PCL may further include at least one conductive layer (not shown) (e.g., any conductive layer in which an electrode of the storage capacitor Cst is disposed and in a layer different from the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2). In this case, at least one line connected to each pixel PXL may be disposed in this conductive layer.

[0214] A passivation layer PSV can be disposed on inline and / or circuit elements including transistor T and storage capacitor Cst. The passivation layer PSV can be formed of a single layer or multiple layers and includes at least one inorganic insulating material and / or an organic insulating material. For example, the passivation layer PSV may include at least one organic insulating layer and substantially planarize the surface of the circuit layer PCL. A display layer DPL can be disposed on the passivation layer PSV.

[0215] The display layer DPL may include a light source unit LSU for each pixel PXL, and optionally include a first electrode line ELI1 and / or a second electrode line ELI2 connected to a first electrode ELT1 and / or a second electrode ELT2 of the light source unit LSU. For example, the display layer DPL may include at least one pair of first electrodes ELT1 and second electrodes ELT2 disposed in the emission region EMA of each pixel PXL and forming each light source unit LSU, at least one light-emitting element LD connected between the first electrode ELT1 and the second electrode ELT2, and a first electrode line ELI1 and a second electrode line ELI2 respectively connected to the first electrode ELT1 and the second electrode ELT2.

[0216] In an embodiment, such as Figures 6a to 7b As shown in the embodiments, each pixel PXL may include a plurality of light-emitting elements (LDs) connected in a forward direction between the first electrode ELT1 and the second electrode ELT2. However, the number of light-emitting elements (LDs) disposed in each pixel PXL is not limited to this, and this can be varied in various ways. For the sake of explanation, in Figures 8a to 9 In the description of the embodiments and other embodiments described below, each embodiment will be explained assuming that each pixel PXL includes multiple light-emitting elements (LDs). It should be noted here that the light-emitting element (LD) disposed in the pixel PXL according to each embodiment can be changed to a single light-emitting element (LD).

[0217] Furthermore, the display layer DPL may optionally include a first embankment pattern BNK1 and a second embankment pattern BNK2 configured to cause corresponding portions of the first electrode ELT1 and the second electrode ELT2 to protrude upwards, and / or a first contact electrode CNE1 and a second contact electrode CNE2 configured to more reliably connect the light-emitting element LD between the first electrode ELT1 and the second electrode ELT2. Additionally, the display layer DPL may also include, for example, at least one conductive layer and / or an insulating layer.

[0218] For example, the display layer DPL may include a first dam pattern BNK1 and a second dam pattern BNK2, a first electrode ELT1 and a second electrode ELT2, a first insulating layer INS1, a first insulating pattern INP1, a light-emitting element LD, a second insulating pattern INP2, a first contact electrode CNE1 and a second contact electrode CNE2, and a second insulating layer INS2, continuously disposed and / or formed on the circuit layer PCL. Furthermore, the display layer DPL may also include an outer cover layer OC disposed on the second insulating layer INS2.

[0219] The first dam pattern BNK1 and the second dam pattern BNK2 may be disposed at spaced-apart positions on a surface of the substrate layer BSL on which the circuit layer PCL is selectively formed. For example, the first dam pattern BNK1 and the second dam pattern BNK2 may be disposed at spaced-apart positions in each pixel region (specifically, each emitter region EMA) on the substrate layer BSL. The first dam pattern BNK1 and the second dam pattern BNK2 may protrude from the surface of the substrate layer BSL on which the circuit layer PCL is formed in the height direction of the substrate layer BSL. In embodiments, the first dam pattern BNK1 and the second dam pattern BNK2 may have substantially the same height, but this disclosure is not limited thereto.

[0220] In an embodiment, the first dam pattern BNK1 may be disposed between the substrate layer BSL and / or the circuit layer PCL and each first electrode ELT1. The first dam pattern BNK1 may be configured to be adjacent to the first end EP1 of the light-emitting element LD. For example, the first dam pattern BNK1 may include a first sidewall SDW1 positioned adjacent to and facing the first end EP1 of the light-emitting element LD.

[0221] In an embodiment, the second dam pattern BNK2 may be disposed between the substrate layer BSL and / or the circuit layer PCL and the second electrode ELT2. The second dam pattern BNK2 may be configured to be adjacent to the second end EP2 of the light-emitting element LD. For example, the second dam pattern BNK2 may include a second sidewall SDW2 positioned adjacent to and facing the second end EP2 of the light-emitting element LD.

[0222] In an embodiment, each of the first dike pattern BNK1 and the second dike pattern BNK2 can have various shapes. In an embodiment, such as... Figure 8a and Figure 8c As shown, the first dam pattern BNK1 and the second dam pattern BNK2 can have a trapezoidal cross-section whose width gradually decreases upwards. In this case, the first sidewall SDW1 of the first dam pattern BNK1 and the second sidewall SDW2 of the second dam pattern BNK2 can both be formed by inclined surfaces that are tilted relative to the substrate layer BSL at an angle within a predetermined range. In the embodiment, as... Figure 8b and Figure 8d As shown, the first embankment pattern BNK1 and the second embankment pattern BNK2 can have a semi-circular or semi-elliptical cross-section whose width gradually decreases upward. In this case, the first sidewall SDW1 of the first embankment pattern BNK1 and the second sidewall SDW2 of the second embankment pattern BNK2 can both be formed by curved surfaces.

[0223] The first electrode ELT1 and the second electrode ELT2, and / or the first insulating layer INS1, disposed on the first embankment pattern BNK1 and the second embankment pattern BNK2, may have shapes corresponding to the first embankment pattern BNK1 and the second embankment pattern BNK2. For example, the first electrode ELT1 may include a first inclined surface ICS1 or a first curved surface CUS1 disposed on the first sidewall SDW1 of the first embankment pattern BNK1 and having a shape corresponding to the shape of the first sidewall SDW1. The second electrode ELT2 may include a second inclined surface ICS2 or a second curved surface CUS2 disposed on the second sidewall SDW2 of the second embankment pattern BNK2 and having a shape corresponding to the shape of the second sidewall SDW2. Similarly, the first insulating layer INS1 may include a third inclined surface ICS3 and a fourth inclined surface ICS4 or a third curved surface CUS3 and a fourth curved surface CUS4 covering the first sidewall SDW1 of the first embankment pattern BNK1 and the second sidewall SDW2 of the second embankment pattern BNK2 and having shapes corresponding to the shapes of the first sidewall SDW1 and the second sidewall SDW2.

[0224] In this disclosure, the shapes of the first dam pattern BNK1 and the second dam pattern BNK2, as well as the predetermined electrodes (e.g., first electrode ELT1 and second electrode ELT2) and / or insulating layers (e.g., first insulating layer INS1) formed on the first dam pattern BNK1 and the second dam pattern BNK2, are not particularly limited and can be varied in various ways according to embodiments. For example, in an embodiment, each of the first dam pattern BNK1 and the second dam pattern BNK2 may have a stepped shape. In an embodiment, at least one of the first dam pattern BNK1 and the second dam pattern BNK2 may be omitted or its position may be changed.

[0225] Each of the first dam pattern BNK1 and the second dam pattern BNK2 may include an insulating material having at least one inorganic and / or organic material. For example, the first dam pattern BNK1 and the second dam pattern BNK2 may include materials containing, for example, silicon nitride (SiN). x ) or silicon dioxide (SiO) x The first dam pattern BNK1 and the second dam pattern BNK2 may comprise at least one inorganic layer of various known inorganic insulating materials and / or a photoresist layer, or may form a single-layer or multi-layer insulator comprising a combination of organic and inorganic materials. In embodiments of this disclosure, the constituent materials of the first dam pattern BNK1 and the second dam pattern BNK2 may be varied in various ways.

[0226] In an embodiment, both the first dam pattern BNK1 and the second dam pattern BNK2 can be used as reflectors. For example, the first dam pattern BNK1 and the second dam pattern BNK2, together with the first electrode ELT1 and the second electrode ELT2 disposed thereon, can be used as reflectors to guide light emitted from each light-emitting element LD in a desired direction (e.g., the front direction of the display panel PNL), thereby enhancing the light efficiency of the pixel PXL.

[0227] The first electrode ELT1 and the second electrode ELT2 forming the pixel electrodes of each pixel PXL can be disposed on the first embankment pattern BNK1 and the second embankment pattern BNK2. In embodiments, the first electrode ELT1 and the second electrode ELT2 can each have a shape corresponding to the first embankment pattern BNK1 and the second embankment pattern BNK2. For example, the first electrode ELT1 and the second electrode ELT2 can each have a first inclined surface ICS1 and a second inclined surface ICS2 or a first curved surface CUS1 and a second curved surface CUS2 corresponding to the first embankment pattern BNK1 and the second embankment pattern BNK2, and can protrude in the height direction of the substrate layer BSL. In embodiments where the first embankment pattern BNK1 and the second embankment pattern BNK2 are not formed, each of the first electrode ELT1 and the second electrode ELT2 can be formed on the passivation layer PSV to have a substantially flat surface, or have a thickness varying by area, such that one region of it can protrude in the height direction of the substrate layer BSL.

[0228] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one metal selected from various metallic materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc., or alloys thereof), conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc antimony oxide (AZO), indium tin zinc oxide (ITZO), tin oxide (SnO2)), and conductive polymers (such as PEDOT), but this disclosure is not limited thereto. For example, each of the first electrode ELT1 and the second electrode ELT2 may include other conductive materials such as carbon nanotubes and graphene. In other words, each of the first electrode ELT1 and the second electrode ELT2 may include at least one of various conductive materials to be conductive, and there are no particular limitations on the constituent materials. Furthermore, the first electrode ELT1 and the second electrode ELT2 can have the same conductive material. Alternatively, the first electrode ELT1 and the second electrode ELT2 can have different conductive materials.

[0229] Each of the first electrode ELT1 and the second electrode ELT2 may be formed of a single layer or multiple layers. For example, each of the first electrode ELT1 and the second electrode ELT2 may include a reflective electrode layer comprising a reflective conductive material. Each of the first electrode ELT1 and the second electrode ELT2 may also selectively include at least one of at least a transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive capping layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0230] In embodiments, the reflective electrode layer may be formed of a conductive material with uniform reflectivity. For example, the reflective electrode layer may include at least one of various metallic materials comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), or alloys thereof, but this disclosure is not limited thereto. In other words, the reflective electrode layer included in each of the first electrode ELT1 and the second electrode ELT2 may be formed of various reflective conductive materials.

[0231] Each of the first electrode ELT1 and the second electrode ELT2, including the reflective electrode layer, enables light emitted from opposite ends (i.e., first end EP1 and second end EP2) of each of the light-emitting elements LDs to travel more reliably in the direction along which the displayed image is viewed (e.g., in the front direction of the display panel PNL). Specifically, if the first electrode ELT1 and the second electrode ELT2 each have a tilted surface or a curved surface (e.g., first tilted surface ICS1 and second tilted surface ICS2 or first curved surface CUS1 and second curved surface CUS2) corresponding to the first dam pattern BNK1 and the second dam pattern BNK2, and are respectively positioned facing the first end EP1 and the second end EP2 of the light-emitting element LD, then light emitted from the first end EP1 and the second end EP2 of each of the light-emitting elements LDs can be reflected by the first electrode ELT1 and the second electrode ELT2, and thus travel more reliably in the front direction of the display panel PNL (e.g., in the upward direction of the substrate layer BSL). This enhances the efficiency of light emitted from the light-emitting element LD.

[0232] Furthermore, the transparent electrode layer can be formed from various transparent conductive materials. For example, the transparent electrode layer may include ITO, IZO, or ITZO, but this disclosure is not limited thereto. In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 can be formed from three layers having a stacked structure of ITO / Ag / ITO. Thus, if each of the first electrode ELT1 and the second electrode ELT2 is formed from a multilayer structure of at least two layers, the voltage drop due to signal delay (RC delay) can be minimized. Therefore, the desired voltage can be efficiently transmitted to the light-emitting element LD.

[0233] Additionally, each of the first electrode ELT1 and the second electrode ELT2 may include a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer. In this case, the reflective electrode layers of the first electrode ELT1 and the second electrode ELT2 can be prevented from being damaged by defects that may occur, for example, during the manufacturing process of the pixel PXL. However, the conductive capping layer may be optionally included in each of the first electrode ELT1 and the second electrode ELT2, and may be omitted depending on the embodiment. Furthermore, the conductive capping layer may be considered as a component of each of the first electrode ELT1 and the second electrode ELT2, or as a separate component disposed on the first electrode ELT1 and the second electrode ELT2.

[0234] The first insulating layer INS1 may be disposed on a region of each of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may be formed to cover a region of each of the first electrode ELT1 and the second electrode ELT2, and may include openings to expose another region of each of the first electrode ELT1 and the second electrode ELT2.

[0235] For example, the first insulating layer INS1 may be disposed on a region of each of the first electrodes ELT1 and the second electrodes ELT2, including a first inclined surface ICS1 and a second inclined surface ICS2 or a first curved surface CUS1 and a second curved surface CUS2, and disposed in the region between the first electrode ELT1 and the second electrode ELT2, exposing another region of each of the first electrode ELT1 and the second electrode ELT2 on a region of each of the first embankment pattern BNK1 and the second embankment pattern BNK2. In an embodiment, the first insulating layer INS1 may be omitted. In this case, the light-emitting element LD may be directly disposed on the passivation layer PSV and / or one end of each of the first electrode ELT1 and the second electrode ELT2.

[0236] In an embodiment, the first insulating layer INS1 may initially be formed to cover the entire surface of the first electrode ELT1 and the second electrode ELT2. After the light-emitting element LD is supplied to the first insulating layer INS1 and aligned thereon, the first insulating layer INS1 may be partially opened to expose a region of each of the first electrode ELT1 and the second electrode ELT2 in an upper region of each of the first embankment pattern BNK1 and the second embankment pattern BNK2. For example, the first insulating layer INS1 may have an opening on the respective upper surface of the first embankment pattern BNK1 and the second embankment pattern BNK2 that exposes a region of each of the first electrode ELT1 and the second electrode ELT2, and at least partially cover the first inclined surface ICS1 and the second inclined surface ICS2 or the first curved surface CUS1 and the second curved surface CUS2 of the first electrode ELT1 and the second electrode ELT2. Optionally, in an embodiment, after the supply and alignment of the light-emitting element LD have been completed, the first insulating layer INS1 may be patterned as a separate pattern that is only partially disposed under the light-emitting element LD.

[0237] After the first electrode ELT1 and the second electrode ELT2 have been formed, the first insulating layer INS1 can be formed to cover the first electrode ELT1 and the second electrode ELT2. Therefore, the first electrode ELT1 and the second electrode ELT2 can be prevented from being damaged during subsequent processes.

[0238] In embodiments, the first insulating layer INS1 may be formed of a single layer or multiple layers and includes at least one inorganic insulating material and / or an organic insulating material. For example, the first insulating layer INS1 may include silicon nitride (SiN) x ), silicon dioxide (SiO) x Various organic / inorganic insulating materials such as aluminum oxide (Al2O3) are used. There are no particular restrictions on the constituent materials of the first insulating layer INS1.

[0239] In an embodiment where the first insulating layer INS1 is formed of an inorganic insulating material, the first insulating layer INS1 may have a shape corresponding to the shape of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may include a third inclined surface ICS3 and a fourth inclined surface ICS4 or a third curved surface CUS3 and a fourth curved surface CUS4 disposed on the first inclined surface ICS1 and the second inclined surface ICS2 or the first curved surface CUS1 and the second curved surface CUS2 of the first electrode ELT1 and the second electrode ELT2.

[0240] The first insulating pattern INP1 can be disposed on the first insulating layer INS1 in the region between the first electrode ELT1 and the second electrode ELT2. For example, the first insulating pattern INP1 can be partially disposed on the first insulating layer INS1 in the region between the first electrode ELT1 and the second electrode ELT2, such that the first insulating pattern INP1 is positioned between the first insulating layer INS1 and the light-emitting element LD.

[0241] In embodiments, the first insulating pattern INP1 may be formed of a single layer or multiple layers and includes at least one inorganic insulating material and / or an organic insulating material. For example, the first insulating pattern INP1 may include silicon nitride (SiN) x ), silicon dioxide (SiO) x Various organic / inorganic insulating materials, such as alumina (Al2O3) and photoresist (PR), are used. There are no particular restrictions on the constituent materials of the first insulating pattern INP1.

[0242] In embodiments of this disclosure, the first insulating pattern INP1 may be formed to have an etch selectivity different from that of the first insulating layer INS1. For example, the first insulating layer INS1 may have a first etch selectivity. The first insulating pattern INP1 may have a second etch selectivity different from the first etch selectivity.

[0243] For example, the first insulating pattern INP1 may include a material different from that of the first insulating layer INS1 (e.g., a material formed of different elements and / or with different composition ratios), and therefore has an etching selectivity different from that of the first insulating layer INS1 relative to a predetermined etching gas. For example, in the case where the first insulating layer INS1 comprises a first insulating material, the first insulating pattern INP1 may have a second insulating material different from the first insulating material. In an embodiment, the first insulating layer INS1 may be made of silicon nitride (SiN). x The first insulating pattern INP1 can be formed from silicon oxide (SiO2). xThe first insulating layer INS1 and the first insulating pattern INP1 are formed. However, this disclosure is not limited thereto, and the constituent materials of the first insulating layer INS1 and the first insulating pattern INP1 can be changed in various ways according to the embodiments.

[0244] In an embodiment, the first insulating pattern INP1 may be formed in the form of a first insulating material layer that first covers the entire surface of the first insulating layer INS1. After the light-emitting element LD is supplied and aligned on the first insulating material layer, the first insulating material layer can be patterned to form the first insulating pattern INP1.

[0245] In an embodiment, the first insulating material layer for forming the first insulating pattern INP1 and the second insulating material layer for forming the second insulating pattern INP2 can be made of the same material, such that if the first insulating material layer is etched together with the second insulating material layer during the etching operation, the first insulating pattern INP1 and the second insulating pattern INP2 can be patterned simultaneously. In this case, the mask used to form the second insulating pattern INP2 by etching the second insulating material layer and the light-emitting element LD can be used as a mask for forming the first insulating pattern INP1. Therefore, the first insulating pattern INP1 can be partially disposed on the first insulating layer INS1 only below the light-emitting element LD and the second insulating pattern INP2. For example, the first insulating pattern INP1 can be disposed below the central region of the light-emitting element LD and superimposed on the second insulating pattern INP2, and can also be disposed below the first end EP1 and the second end EP2 of the light-emitting element LD exposed from the second insulating pattern INP2.

[0246] In other words, the first insulating pattern INP1 can be partially disposed on the first insulating layer INS1, and specifically disposed below the light-emitting element LD. Therefore, each light-emitting element LD can be spaced apart from the first insulating layer INS1, and the first insulating pattern INP1 is disposed between each light-emitting element LD and the first insulating layer INS1.

[0247] In this embodiment, after the alignment of the light-emitting elements (LDs) is completed, the first insulating material layer can be patterned to form a first insulating pattern INP1. In other words, after the first insulating layer INS1 has been covered by the first insulating material layer, the light-emitting elements (LDs) can be supplied and aligned on the first insulating material layer. In this case, each light-emitting element (LD) can be spaced from the first insulating layer INS1 by a distance equal to or greater than the thickness of the first insulating pattern INP1 (or the first insulating material layer). Therefore, it is possible to prevent the first end EP1 and the second end EP2 of each of the light-emitting elements (LDs) from coming into close contact with the first insulating layer INS1.

[0248] Thus, if a spacing distance equal to or greater than the thickness of the first insulating pattern INP1 is ensured between the first insulating layer INS1 and the first end EP1 and the second end EP2 of each of the light-emitting elements LD, the disconnection (or open circuit defect) of the first contact electrode CNE1 and the second contact electrode CNE2 at the first end EP1 and the second end EP2 can be effectively prevented. Therefore, connection failures (e.g., contact failures) of the light-emitting element LD due to the disconnection of the first contact electrode CNE1 and / or the second contact electrode CNE2 can be prevented.

[0249] Each light-emitting element (LD) can be disposed on the first insulating pattern INP1. For example, each pixel PXL may include multiple light-emitting elements (LDs) disposed on the first insulating pattern INP1.

[0250] In an embodiment, light-emitting elements (LDs) can be supplied to each pixel region (specifically, the emission region EMA of each pixel PXL) in which a first insulating layer INS1 and a first insulating material layer are formed, and aligned between a first electrode ELT1 and a second electrode ELT2. For example, multiple light-emitting elements (LDs) can be supplied to the emission region EMA of each pixel PXL via an inkjet printing scheme, a slot coating scheme, or various other schemes, and the light-emitting elements (LDs) can be directionally aligned between the first electrode ELT1 and the second electrode ELT2 by means of predetermined alignment signals (or alignment voltages) respectively applied to the first electrode ELT1 and the second electrode ELT2.

[0251] In one embodiment, at least some of the light-emitting elements (LDs) can be disposed horizontally or diagonally between a pair of adjacent first electrodes ELT1 and second electrodes ELT2, such that each LD is superimposed on the pair of first electrodes ELT1 and second electrodes ELT2 at its opposite ends (i.e., first end EP1 and second end EP2) in the longitudinal direction. In another embodiment, at least some of the light-emitting elements (LDs) can be disposed between a pair of adjacent first electrodes ELT1 and second electrodes ELT2, such that at least some LDs are not superimposed on the first electrodes ELT1 and / or the second electrodes ELT2, and can be electrically connected to the pair of first electrodes ELT1 and second electrodes ELT2 respectively via first contact electrodes CNE1 and second contact electrodes CNE2. In other words, in one embodiment, the light-emitting elements (LDs) can be superimposed on the first electrodes ELT1 and second electrodes ELT2 or not superimposed on the first electrodes ELT1 and second electrodes ELT2, and are electrically connected between the first electrodes ELT1 and second electrodes ELT2 via first contact electrodes CNE1 and second contact electrodes CNE2.

[0252] The second insulating pattern INP2 can be disposed on a region of each of the light-emitting elements LD. For example, the second insulating pattern INP2 can be disposed on a region of each of the light-emitting elements LD such that the first end EP1 and the second end EP2 of each of the light-emitting elements LD are exposed. For example, the second insulating pattern INP2 can be partially disposed on only one region including the central region of each of the light-emitting elements LD.

[0253] Although the second insulating pattern INP2 is formed as an independent pattern in the emission region EMA of each pixel PXL, this disclosure is not limited thereto. According to an embodiment, the second insulating pattern INP2 can be omitted. In this case, one end of each of the first contact electrode CNE1 and the second contact electrode CNE2 can be directly disposed on the upper surface of the light-emitting element LD.

[0254] In embodiments, the second insulating pattern INP2 may be formed of a single layer or multiple layers and includes at least one inorganic insulating material and / or an organic insulating material. For example, the second insulating pattern INP2 may include silicon nitride (SiN) x ), silicon dioxide (SiO) x Various organic / inorganic insulating materials, such as alumina (Al2O3) and photoresist (PR), are used. There are no particular restrictions on the constituent materials of the second insulating pattern INP2.

[0255] After the alignment of the light-emitting element (LD) is completed, a second insulating pattern INP2 is formed on the LD to prevent it from moving away from the alignment position. In embodiments, if there is a space between the first insulating pattern INP1 (or the first insulating material layer used to form the first insulating pattern INP1) and the LD, this space can be filled with the insulating material introduced during the process of forming the second insulating pattern INP2. Therefore, the LD can be supported more stably. In some embodiments, the space may not be completely filled. For example, the second insulating pattern INP2 may be formed only on the LD, or it may be formed both on and under the LD.

[0256] In embodiments of this disclosure, the second insulating pattern INP2 may be formed to have the same etch selectivity as the first insulating pattern INP1. For example, the second insulating pattern INP2 may have a second etch selectivity in the same manner as the first insulating pattern INP1.

[0257] For example, the second insulating pattern INP2 can include a second insulating material in the same manner as the first insulating pattern INP1, and therefore has the same etching selectivity as the first insulating pattern INP1 relative to a predetermined etching gas, etc. For example, the first insulating layer INS1 and the first insulating pattern INP1 are respectively made of silicon nitride (SiN). x ) and silicon dioxide (SiO) x In the case of formation, the second insulating pattern INP2 can be formed from silicon oxide (SiO2). x In an embodiment, the second insulating pattern INP2 may be formed using a different material and / or manufacturing method than the first insulating pattern INP1, and may be formed to have the same etching selectivity as the first insulating pattern INP1 with respect to the same etching gas.

[0258] When the first insulating pattern INP1 and the second insulating pattern INP2 have the same etching selectivity, the first insulating pattern INP1 and the second insulating pattern INP2 can be formed by simultaneously etching the first insulating material layer and the second insulating material layer. Therefore, this can be beneficial for the process of manufacturing pixel PXL.

[0259] The opposite ends of the light-emitting element LD that are not covered by the second insulating pattern INP2 (i.e., the first end EP1 and the second end EP2) can be covered by the first contact electrode CNE1 and the second contact electrode CNE2, respectively. The first contact electrode CNE1 and the second contact electrode CNE2 can be spaced apart from each other. For example, the first contact electrode CNE1 and the second contact electrode CNE2 that are adjacent to each other can be disposed on at least one adjacent first end EP1 and the second end EP2 of the light-emitting element LD at a position spaced apart from each other, and the second insulating pattern INP2 is placed between them.

[0260] In an embodiment, such as Figure 8a and Figure 8b As shown, the first contact electrode CNE1 and the second contact electrode CNE2 can be simultaneously formed on the same surface of the substrate layer BSL. Therefore, the manufacturing process of the pixel PXL and the display device including the pixel PXL can be simplified.

[0261] Here, the positions and relative arrangement of the first contact electrode CNE1 and the second contact electrode CNE2 can be changed in various ways. For example, in the embodiment, such as Figure 8c and Figure 8dAs shown, the first contact electrode CNE1 and the second contact electrode CNE2 can be continuously formed on different layers on one surface of the substrate layer BSL. Furthermore, a third insulating layer INS3 can be disposed between the first contact electrode CNE1 and the second contact electrode CNE2. In an embodiment, the third insulating layer INS3 can be disposed on the first contact electrode CNE1 to completely cover the first contact electrode CNE1, or it can be partially disposed on a region of the first contact electrode CNE1, such that the third insulating layer INS3 is only located between the first contact electrode CNE1 and the second contact electrode CNE2.

[0262] Furthermore, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on the first electrode ELT1 and the second electrode ELT2 to cover the corresponding exposed areas of the first electrode ELT1 and the second electrode ELT2. For example, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on at least some areas of the first electrode ELT1 and the second electrode ELT2 respectively to contact the first electrode ELT1 and the second electrode ELT2 respectively.

[0263] For example, the first contact electrode CNE1 can be disposed on the first end EP1 of the light-emitting element LD, and extends to the upper part of the adjacent first electrode ELT1 via the upper part of the first sidewall SDW1 of the first embankment pattern BNK1 (e.g., the surface of the third inclined surface ICS3 or the third curved surface CUS3 of the first insulating layer INS1). Similarly, the second contact electrode CNE2 can be disposed on the second end EP2 of the light-emitting element LD, and extends to the upper part of the adjacent second electrode ELT2 via the upper part of the second sidewall SDW2 of the second embankment pattern BNK2 (e.g., the surface of the fourth inclined surface ICS4 or the fourth curved surface CUS4 of the first insulating layer INS1).

[0264] Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 can be electrically connected to the first electrode ELT1 and the second electrode ELT2, respectively. Each of the first electrode ELT1 and the second electrode ELT2 can be electrically connected to the first terminal EP1 or the second terminal EP2 adjacent to at least one light-emitting element LD through a corresponding one of the first contact electrode CNE1 and the second contact electrode CNE2.

[0265] In this embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed of various transparent conductive materials. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may include at least one of various transparent conductive materials comprising ITO, IZO, and ITZO, and may be substantially transparent or translucent to meet a predetermined transmittance. Therefore, light emitted from the light-emitting element LD through the first end EP1 and the second end EP2 can be emitted from the display panel PNL through the first contact electrode CNE1 and the second contact electrode CNE2.

[0266] The second insulating layer INS2 may be disposed on the first contact electrode CNE1 and the second contact electrode CNE2. For example, the second insulating layer INS2 may be formed and / or disposed on the entire surface of the display area DA to cover the first dam pattern BNK1 and the second dam pattern BNK2, the first electrode ELT1 and the second electrode ELT2, the first insulating layer INS1, the first insulating pattern INP1, the light-emitting element LD, the second insulating pattern INP2, and the first contact electrode CNE1 and the second contact electrode CNE2 formed in each emission area EMA. The second insulating layer INS2 may include at least one inorganic layer and / or an organic layer.

[0267] In an embodiment, the second insulating layer INS2 may include a thin-film encapsulation layer with a multilayer structure. For example, the second insulating layer INS2 may be formed of a thin-film encapsulation layer with a multilayer structure, the multilayer structure including at least two inorganic insulating layers and at least one organic insulating layer disposed between the at least two inorganic insulating layers. Here, the constituent materials and / or structure of the second insulating layer INS2 can be varied in various ways. In some embodiments, at least one outer cover layer OC and / or encapsulation substrate, etc., may also be disposed on the second insulating layer INS2.

[0268] In the embodiments, both the second insulating layer INS2 and the outer covering layer OC can be formed of a single layer or multiple layers, and include at least one inorganic insulating material and / or an organic insulating material. For example, both the second insulating layer INS2 and the outer covering layer OC can include various known organic / inorganic insulating materials.

[0269] According to the above embodiments, the spacing between the first insulating layer INS1 and the first end EP1 and the second end EP2 of each of the light-emitting elements LD can be ensured by forming a first insulating pattern INP1 (or a first insulating material layer for forming the first insulating pattern INP1). Therefore, disconnection of the first contact electrode CNE1 and the second contact electrode CNE2 can be prevented, so that each light-emitting element LD can be reliably connected between the first electrode ELT1 and the second electrode ELT2 of each pixel PXL.

[0270] Therefore, according to the above embodiments, the utilization rate of the light-emitting element LD supplied to each pixel region (e.g., the utilization rate as each effective light source) can be increased, and the emission characteristics of the pixel PXL can be stabilized. For example, the ratio of the light-emitting element LD supplied to each pixel region electrically connected between the first electrode ELT1 and the second electrode ELT2 can be increased. Therefore, the efficiency of the material used to form the pixel PXL (e.g., the utilization rate of the light-emitting element LD) can be increased, making it possible to reduce the cost of manufacturing the display device and reliably form the light source unit LSU for each pixel PXL.

[0271] Figure 10 This is a plan view illustrating pixel PXL according to an embodiment of the present disclosure, and for example, it illustrates a plan view according to... Figure 7a A modified embodiment of the pixel PXL of the embodiment. Figures 11a to 11d Both are cross-sectional views of pixel PXL according to embodiments of the present disclosure, and for example, show a view along... Figure 10 Different embodiments of the cross-section of pixel PXL intercepted by line III-III'. Figure 12 This is a cross-sectional view showing an embodiment of a pixel excluding the first insulating pattern INP1, and for example, a comparison with a pixel PXL according to a contrasting example excluding the first insulating pattern INP1 is shown. Figure 10 The sectional view corresponding to line III-III'. For example, relative to according to Figure 11a The pixel PXL of the embodiment, Figure 12 The image shown is a pixel PXL based on a comparative example excluding the first insulating pattern INP1. Figures 10 to 12 In the description of the embodiments, the same reference numerals will be used to indicate components that are similar to or the same as those in the previous embodiments (e.g., corresponding components), and their detailed explanations will be omitted.

[0272] Reference Figures 10 to 11d The light-emitting elements (LDs) can be aligned and biased to be positioned closer to one electrode than to the other electrode, which is closer to either the first electrode ELT1 or the second electrode ELT2. For example, most of the light-emitting elements connected between the first electrode ELT1 and the second electrode ELT2 in each pixel PXL (e.g., approximately 70% or more (e.g., 80% or more) of the light-emitting elements LD and LDrv connected between the first electrode ELT1 and the second electrode ELT2 in a forward and / or reverse direction) can be aligned to be positioned closer to the first electrode ELT1 than to the second electrode ELT2, and connected in a forward direction between the first electrode ELT1 and the second electrode ELT2.

[0273] In an embodiment, during the operation of aligning the light-emitting elements (LDs) between the first electrode ELT1 and the second electrode ELT2 to form each light source unit (LSU), the alignment and bias of the LDs supplied to each pixel region (e.g., the emission region EMA of each pixel PXL) in any direction (e.g., the forward direction) can be controlled by adjusting the alignment signal (or alignment voltage) to be applied to the first electrode ELT1 and the second electrode ELT2 or by forming a magnetic field. For example, the LDs can be aligned and biased such that the number of LDs connected in the forward direction between the first electrode ELT1 and the second electrode ELT2 of each pixel PXL can be increased by controlling the alignment signal (or alignment voltage) to be applied to the first electrode ELT1 and the second electrode ELT2 or by forming a magnetic field. In this case, the LDs can be aligned and biased toward either the first electrode ELT1 or the second electrode ELT2 (e.g., the first electrode ELT1).

[0274] Thus, by biasing and / or eccentrically aligning the light-emitting elements (LDs) to increase the number of LDs connected in the positive direction between the first electrode ELT1 and the second electrode ELT2, the utilization rate of the LDs supplied to each pixel area (e.g., the utilization rate as each effective light source) can be increased. Therefore, the cost of manufacturing the display device can be reduced, and each light source unit (LSU) can be reliably formed.

[0275] Furthermore, in the embodiments of this disclosure, since the first insulating pattern INP1 is formed under the light-emitting element LD, even if the light-emitting element LD is eccentrically aligned between the first electrode ELT1 and the second electrode ELT2, the disconnection of the first contact electrode CNE1 and the second contact electrode CNE2 can be effectively prevented. For example, in the embodiments of this disclosure, after the first insulating material layer has been formed to cover the first insulating layer INS1 and the light-emitting element LD has been aligned, a second insulating material layer can be formed on the light-emitting element LD, and then the first insulating pattern INP1 and the second insulating pattern INP2 can be formed by simultaneously etching the first insulating material layer and the second insulating material layer. Therefore, a spacing distance d equal to or greater than the thickness of the first insulating pattern INP1 (or the first insulating material layer) is ensured between the first insulating layer INS1 and the first end EP1 and the second end EP2 of each of the light-emitting elements LD, such that sufficient space can be ensured to form the first contact electrode CNE1 and the second contact electrode CNE2 between the first insulating layer INS1 and the first end EP1 and the second end EP2. Therefore, the disconnection of the first contact electrode CNE1 and the second contact electrode CNE2 can be effectively prevented.

[0276] On the other hand, according to Figure 12In this embodiment, the pixel PXL does not include the first insulating pattern INP1, such that when the light-emitting elements LD are aligned (specifically, eccentrically aligned according to bias alignment), one end of each of the light-emitting elements LD is aligned in close contact with the first insulating layer INS1. For example, the first end EP1 of the light-emitting element LD is aligned in close contact with the first insulating layer INS1, such that no space sufficient to form the first contact electrode CNE1 (e.g., a space for depositing conductive material to form the first contact electrode CNE1) is formed between the first end EP1 and the first insulating layer INS1. In this case, if the first contact electrode CNE1 is formed by sputtering or the like, the conductive material used to form the first contact electrode CNE1 will not be deposited to reliably cover the first end EP1, causing the first contact electrode CNE1 to be disconnected. For example, the conductive material used to form the first contact electrode CNE1 will not reach the area below the first end EP1, causing the first contact electrode CNE1 to be disconnected around the first end EP1. Therefore, the light-emitting element LD is not completely connected between the first electrode ELT1 and the second electrode ELT2, thereby reducing the utilization efficiency of the light-emitting element LD. Furthermore, if a sufficient number of light-emitting elements (LDs) are not connected in the positive direction between the first electrode ELT1 and the second electrode ELT2, the corresponding pixel PXL will be exposed as a dark spot due to the connection failure caused in the light source unit LSU.

[0277] Figures 13a to 13j This is a cross-sectional view sequentially illustrating a method for manufacturing a display device according to embodiments of the present disclosure, and for example, illustrating the manufacturing process including... Figure 10 and Figure 11a An embodiment of a method for displaying a display device with pixels PXL.

[0278] Reference Figures 5 to 13a A circuit layer PCL, including pixel circuits PXC, is formed on the substrate layer BSL in each pixel region. A first dam pattern BNK1 and a second dam pattern BNK2 are formed on the circuit layer PCL. Here, if the circuit layer PCL is omitted, the first dam pattern BNK1 and the second dam pattern BNK2 can be formed directly on one surface of the substrate layer BSL (or a substrate layer BSL on which a buffer layer BFL is formed).

[0279] In embodiments, the first dam pattern BNK1 and the second dam pattern BNK2 can be formed by processes for forming an insulating layer comprising inorganic and / or organic materials and / or by patterning processes (e.g., photoprocessing), or by various types of known processes. In embodiments, the first dam pattern BNK1 and the second dam pattern BNK2 can be formed simultaneously on the same layer (or the same plane) of the substrate layer BSL using the same material, but this disclosure is not limited thereto.

[0280] Reference Figure 13b A first electrode ELT1 and a second electrode ELT2 are formed on a substrate layer BSL on which a first dam pattern BNK1 and a second dam pattern BNK2 are formed. For example, the first electrode ELT1 and the second electrode ELT2 can be formed on the first dam pattern BNK1 and the second dam pattern BNK2, respectively. Here, if the first dam pattern BNK1 and / or the second dam pattern BNK2 are omitted, the first electrode ELT1 and the second electrode ELT2 can be formed directly on one surface of the substrate layer BSL (or a substrate layer BSL on which a circuit layer PCL is formed).

[0281] In one embodiment, a first electrode ELT1 may be formed on a first embankment pattern BNK1, such that a region of it protrudes through the first embankment pattern BNK1. Similarly, a second electrode ELT2 may be formed on a second embankment pattern BNK2, such that a region of it protrudes through the second embankment pattern BNK2.

[0282] In embodiments, the first electrode ELT1 and the second electrode ELT2 can be formed by a process for forming a conductive layer comprising at least one conductive material and / or a patterning process, or by various types of known processes. Each of the first electrode ELT1 and the second electrode ELT2 can be formed by a single layer or multiple layers. For example, each of the first electrode ELT1 and the second electrode ELT2 can be formed by a conductive pattern having a single-layer structure or a conductive pattern having a multi-layer structure comprising a corresponding reflective electrode and a corresponding conductive capping layer. In embodiments, the first electrode ELT1 and the second electrode ELT2 can be formed simultaneously using the same material on the same layer (or the same plane) of the substrate layer BSL, but this disclosure is not limited thereto.

[0283] Reference Figure 13c A first insulating layer INS1 and a first insulating material layer INP1' are formed on the substrate layer BSL and the first electrode ELT1 and the second electrode ELT2. In an embodiment, the first insulating layer INS1 and the first insulating material layer INP1' are formed sequentially and have different etch selectivity. For example, after forming a first insulating layer INS1 with first etch selectivity on the substrate layer BSL to cover the first electrode ELT1 and the second electrode ELT2, a first insulating material layer INP1' with second etch selectivity can be formed on the first insulating layer INS1 to cover the first insulating layer INS1.

[0284] In the embodiments, both the first insulating layer INS1 and the first insulating material layer INP1' can be formed by a deposition process of an insulating layer including inorganic and / or organic insulating materials, or by various types of known processes. Furthermore, the first insulating layer INS1 and the first insulating material layer INP1' can have the same thickness or different thicknesses.

[0285] In this embodiment, the first insulating layer INS1 and the first insulating material layer INP1' can be formed of different materials. For example, the first insulating layer INS1 can be formed of a first insulating material, and the first insulating material layer INP1' can be formed of a second insulating material different from the first insulating material. For example, silicon nitride (SiN) can be deposited on the substrate layer BSL and the first electrode ELT1 and the second electrode ELT2. x The first insulating layer INS1 is formed by depositing silicon oxide (SiO2) on the first insulating layer INS1. x To form the first insulating material layer INP1'.

[0286] Reference Figure 13d At least one light-emitting element (LD), such as multiple light-emitting elements (LDs), can be supplied and aligned between the first electrode ELT1 and the second electrode ELT2 of each pixel PXL. For example, multiple light-emitting elements (LDs) can be supplied to each pixel region (e.g., the emission region EMA of each pixel PXL) on a substrate layer BSL on which the first electrode ELT1 and the second electrode ELT2, a first insulating layer INS1, a first insulating material layer INP1', etc., are formed. Furthermore, by applying a predetermined alignment voltage to the first electrode ELT1 and the second electrode ELT2, an electric field can be formed between the first electrode ELT1 and the second electrode ELT2, thereby aligning the light-emitting elements (LDs) between them. The operation of applying the predetermined alignment voltage to the first electrode ELT1 and the second electrode ELT2 can be performed simultaneously with the supply of the light-emitting elements, or after the supply of the light-emitting elements (LDs).

[0287] In an embodiment, the light-emitting elements (LDs) can be supplied to each pixel region by applying a solution (also referred to as "LED ink") in which multiple light-emitting elements (LDs) are dispersed, to each emitting region EMA of the substrate layer BSL, such as through an inkjet printing scheme or a slot coating scheme. However, the method of supplying the light-emitting elements (LDs) is not limited to the aforementioned method, and the LDs can be supplied to each pixel region in various other ways.

[0288] In an embodiment, a self-aligned electric field for the light-emitting element LD can be formed between the first electrode ELT1 and the second electrode ELT2 by supplying an AC alignment voltage or a constant voltage with a reference potential to each of the first electrode ELT1 and the second electrode ELT2. For example, by applying an AC alignment voltage to the second electrode ELT2 of each of the pixels PXL and supplying a constant voltage with a reference potential (e.g., ground potential) to the first electrode ELT1 of each of the pixels PXL, the light-emitting element LD can be aligned between the first electrode ELT1 and the second electrode ELT2 of each pixel PXL.

[0289] In this embodiment, each light-emitting element LD can be aligned horizontally between the first electrode ELT1 and the second electrode ELT2 of the corresponding pixel PXL. For example, the first end EP1 of each light-emitting element LD can be configured to face the first electrode ELT1. The second end EP2 of each light-emitting element LD can be configured to face the second electrode ELT2.

[0290] In an embodiment, the alignment and bias of the light-emitting element LD supplied to each pixel region in any direction (e.g., the forward direction) can be controlled by adjusting the alignment signal (or alignment voltage) to be applied to the first electrode ELT1 and the second electrode ELT2 or by forming a magnetic field. In this case, the light-emitting element LD can be eccentrically aligned to be positioned closer to either the first electrode ELT1 or the second electrode ELT2 (e.g., the first electrode ELT1). For example, at least some of the light-emitting element LDs can be aligned closer to the first electrode ELT1 such that some of the light-emitting element LDs are in close contact with a region of the first insulating material layer INP1' disposed on the first sidewall SDW1 of the first embankment pattern BNK1.

[0291] Reference Figure 13e A second insulating material layer INP2' is formed on the substrate layer BSL on which the first insulating material layer INP1' and the light-emitting element LD are disposed, to cover the first insulating material layer INP1' and the light-emitting element LD. The second insulating layer INP2' can be formed by a deposition process of an insulating layer including inorganic insulating materials and / or organic insulating materials and a patterning process, or by various types of known processes.

[0292] In an embodiment, the second insulating material layer INP2' may be formed to have the same etch selectivity as the first insulating material layer INP1' (i.e., the second etch selectivity). For example, if the first insulating layer INS1 and the first insulating material layer INP1' are formed of a first insulating material and a second insulating material, respectively, the second insulating material layer INP2' may be formed of the second insulating material, thereby allowing the first insulating material layer INP1' and the second insulating material layer INP2' to have the same etch selectivity. Optionally, in an embodiment, the second insulating material layer INP2' may be formed using a material and / or manufacturing method different from that of the first insulating material layer INP1', and the first insulating material layer INP1' and the second insulating material layer INP2' may be formed to have the same selectivity with respect to the same etching gas.

[0293] Reference Figure 13f The first end EP1 and the second end EP2 of the light-emitting element LD can be exposed by etching the first insulating material layer INP1' and the second insulating material layer INP2'. For example, the first insulating pattern INP1 and the second insulating pattern INP2 can be formed by simultaneously etching the first insulating material layer INP1' and the second insulating material layer INP2' using a predetermined etching gas.

[0294] In an embodiment, when etching the first insulating material layer INP1', the first insulating pattern INP1 can be formed to be disposed below the lower part of the light-emitting element LD, including below the lower parts of the first end EP1 and the second end EP2 of the light-emitting element LD. Furthermore, when etching the second insulating material layer INP2', the second insulating pattern INP2 can be formed to be disposed on some areas of the light-emitting element LD other than the first end EP1 and the second end EP2. Therefore, the first end EP1 and the second end EP2 of the light-emitting element LD can be exposed.

[0295] Reference Figure 13g A region of each of the first electrode ELT1 and the second electrode ELT2 is exposed by etching the first insulating layer INS1. For example, the first insulating layer INS1 can be etched over a region of each of the first dam pattern BNK1 and the second dam pattern BNK2, thereby exposing a region of each of the first electrode ELT1 and the second electrode ELT2.

[0296] Reference Figure 13hA first contact electrode CNE1 is formed on the first terminal EP1 of the light-emitting element LD and the first electrode ELT1, and a second contact electrode CNE2 is formed on the second terminal EP2 of the light-emitting element LD and the second electrode ELT2. In an embodiment, the first contact electrode CNE1 may be configured to electrically connect the first terminal EP1 of the light-emitting element LD to the first electrode ELT1. The second contact electrode CNE2 may be configured to electrically connect the second terminal EP2 of the light-emitting element LD to the second electrode ELT2.

[0297] In one embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed simultaneously. However, this disclosure is not limited thereto. For example, in another embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed sequentially.

[0298] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed by a process of forming a conductive layer comprising at least one identical or different conductive material and / or a patterning process, or by various types of known processes. In an embodiment, at least one transparent electrode material can be used to make each of the first contact electrode CNE1 and the second contact electrode CNE2 substantially transparent. Therefore, light emitted from the light-emitting element LD through the first end EP1 and the second end EP2 can pass through the first contact electrode CNE1 and the second contact electrode CNE2.

[0299] Reference Figure 13i A second insulating layer INS2 is formed on one surface of the substrate layer BSL on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed. In an embodiment, the second insulating layer INS2 can be formed by a deposition process comprising at least one insulating layer including inorganic insulating material and / or organic insulating material, or by various types of known processes.

[0300] Reference Figure 13j An outer cover layer OC is formed on one surface of the substrate layer BSL on which a second insulating layer INS2 is formed. In embodiments, the outer cover layer OC can be formed by a deposition process comprising at least one insulating layer including inorganic and / or organic insulating materials, or by various types of known processes.

[0301] In an embodiment, the outer cover layer OC may be formed of a thin film encapsulation layer comprising a plurality of inorganic insulating layers and at least one organic insulating layer disposed between the inorganic insulating layers. In an embodiment, the outer cover layer OC may be formed as a single layer, or the outer cover layer OC may be omitted. In an embodiment, an encapsulation substrate, etc., may be provided on the substrate layer BSL including the pixel PXL, instead of the outer cover layer OC.

[0302] The pixel PXL (e.g., according to the aforementioned process) can be manufactured according to embodiments of this disclosure. Figure 11a The embodiment of the display panel PNL (pixel PXL).

[0303] Figures 14a to 14c Each shows a plan view of pixel PXL according to an embodiment of the present disclosure. Figures 14a to 14c In the description of the embodiments, the same reference numerals will be used to indicate components that are similar to or the same as those in the previous embodiments, and their detailed explanations will be omitted.

[0304] Reference Figure 14a Each first electrode ELT1 and each second electrode ELT2 can have a circular or annular shape. For example, the second electrode ELT2 can have a circular shape, and the first electrode ELT1 can have an annular shape surrounding each corresponding second electrode ELT2.

[0305] The first dam pattern BNK1 and / or the first contact electrode CNE1 may have a shape corresponding to the shape of each first electrode ELT1. For example, the first dam pattern BNK1 and the first contact electrode CNE1 may have an annular shape formed to overlap with the first electrode ELT1.

[0306] The second dam pattern BNK2 and / or the second contact electrode CNE2 may have a shape corresponding to the shape of each second electrode ELT2. For example, the second dam pattern BNK2 and the second contact electrode CNE2 may have a circular shape formed to overlap with the second electrode ELT2.

[0307] In an embodiment, a plurality of first electrodes ELT1 and / or a plurality of second electrodes ELT2 may be disposed in each pixel region. For example, at least two pairs of first electrodes ELT1 and second electrodes ELT2 may be disposed in each pixel region. For example, a plurality of second electrodes ELT2 may be disposed at positions spaced apart from each other along the second direction DR2. Furthermore, a plurality of first electrodes ELT1 may be disposed on the second direction DR2 to surround each second electrode ELT2.

[0308] In this embodiment, the plurality of first electrodes ELT1 may be connected to each other integrally or non-integrally. For example, the plurality of first electrodes ELT1 may be integrally connected to each other through at least one first connector CNP1.

[0309] In this embodiment, the multiple second electrodes ELT2 can be connected to each other integrally or non-integrally. For example, the multiple second electrodes ELT2 can be spaced apart from each other individually and connected to the main electrode line ELI2_1 through the second contact hole CH2 and the sub-electrode line ELI2_2.

[0310] In an embodiment, the main electrode line ELI2_1 and the secondary electrode line ELI2_2 can form a second electrode line ELI2, and both can be disposed in the same or different layers as the second electrode ELT2. For example, the main electrode line ELI2_1 can be disposed in the same layer as the first electrode ELT1 and the second electrode ELT2. The secondary electrode line ELI2_2 can be disposed in a layer separate from the layers of the first electrode ELT1 and the second electrode ELT2, and at least one insulating layer is disposed therebetween. For example, the secondary electrode line ELI2_2 can be disposed in a layer separate from the layers of the first electrode ELT1 and the second electrode ELT2. Figure 11a The first transistor electrode TE1 and the second transistor electrode TE2 shown in the figure are on the same layer, and are electrically connected to the second electrode ELT2 and the main electrode line ELI2_1 through the second contact hole CH2.

[0311] Reference Figure 14b At least one of the second dam pattern BNK2 and the second contact electrode CNE2 can be formed in an annular shape. For example, the second dam pattern BNK2 can have an annular shape including an opening formed in the region corresponding to each second contact hole CH2, such that the second dam pattern BNK2 does not overlap with the second contact hole CH2.

[0312] Reference Figure 14c The second contact hole CH2 can be disposed in the periphery of the area in which each second embankment pattern BNK2 is formed. In this case, even if the second embankment pattern BNK2 does not include an opening, the second embankment pattern BNK2 may not overlap with the second contact hole CH2.

[0313] As shown in the foregoing embodiments, the corresponding electrodes, embankment patterns, and / or insulating patterns forming the pixel PXL, such as the first electrode ELT1 and / or the second electrode ELT2, can be modified to have various shapes, including circular shapes, in addition to having a strip shape. For example, the first electrode ELT1 and the second electrode ELT2, the first contact electrode CNE1 and the second contact electrode CNE2, the first embankment pattern BNK1 and the second embankment pattern BNK2, and the first insulating pattern INP1 and the second insulating pattern INP2 can all have circular shapes, elliptical shapes, or various polygonal shapes or their corresponding annular shapes. In other words, the shape, size, number, and / or position of the corresponding electrodes, embankment patterns, and / or insulating patterns forming the pixel PXL are not particularly limited and can be changed in various ways according to the embodiments.

[0314] While the concept of this disclosure has been described through detailed embodiments, it should be noted that the above embodiments are merely descriptive and should not be considered limiting. Those skilled in the art will understand that various changes, substitutions, and modifications can be made herein without departing from the scope of the disclosure as defined by the claims.

[0315] The scope of this disclosure is not limited to the detailed description herein, but should be defined by the appended claims. Furthermore, all changes or modifications to this disclosure derived from the meaning and scope of the claims and their equivalents should be construed as including within the scope of this disclosure.

Claims

1. A display device, the display device comprising pixels disposed in a display area, in, The pixels include: The first electrode and the second electrode are spaced apart from each other; A first insulating layer is disposed on a region of each of the first electrode and the second electrode and in the region between the first electrode and the second electrode, and has a first etch selectivity; A first insulating pattern is disposed on the first insulating layer in the region between the first electrode and the second electrode, and has a second etching selectivity; A light-emitting element is disposed on the first insulating pattern and includes a first end and a second end; A second insulating pattern, having the second etching selectivity, is disposed on a region of the light-emitting element such that the first end and the second end of the light-emitting element are exposed; and The third and fourth electrodes are configured to electrically connect the first and second ends of the light-emitting element to the first and second electrodes, respectively.

2. The display device according to claim 1, in, The first insulating layer comprises a first insulating material, and Wherein, the first insulating pattern and the second insulating pattern include a second insulating material that is different from the first insulating material.

3. The display device according to claim 1, wherein, The light-emitting element is spaced apart from the first insulating layer, and the first insulating pattern is placed between the light-emitting element and the first insulating layer.

4. The display device according to claim 1, wherein, The first insulating pattern is disposed on the first insulating layer and only below the light-emitting element and the second insulating pattern.

5. The display device according to claim 1, wherein, The light-emitting element is spaced from the first insulating layer by a distance equal to or greater than the thickness of the first insulating pattern.

6. The display device according to claim 1, wherein, The pixels also include: A first embankment pattern is disposed below a region of the first electrode; and The second embankment pattern is disposed below a region of the second electrode.

7. The display device according to claim 6, in, The first embankment pattern includes a first sidewall facing the first end of the light-emitting element, and The second embankment pattern includes a second sidewall facing the second end of the light-emitting element.

8. The display device according to claim 7, in, The third electrode is disposed on the first end and extends through the upper part of the first sidewall to the upper part of the first electrode, and The fourth electrode is disposed on the second end of the light-emitting element and extends to the upper part of the second electrode via the upper part of the second sidewall.

9. The display device according to claim 1, in, The pixel includes a plurality of light-emitting elements comprising the light-emitting element and connected between the first electrode and the second electrode, and The plurality of light-emitting elements are configured to be closer to the first electrode than to be closer to the second electrode.

10. The display device according to claim 1, in, The first electrode is connected to the first power source, and The second electrode is connected to the second power source.

11. The display device according to claim 10, in, The pixel also includes a pixel circuit connected between the first power source and the first electrode. The display area includes: A circuit layer, wherein circuit elements of the pixel circuit are disposed; and The display layer is stacked on top of the circuit layer, and the first electrode, the second electrode, and the light-emitting element are disposed therein.

12. A method for manufacturing a display device, the method comprising the following steps: A first electrode and a second electrode are formed on the substrate layer; A first insulating layer with a first etch selectivity is formed on the substrate layer, such that the first insulating layer covers the first electrode and the second electrode; A first insulating material layer having a second etching selectivity is formed on the first insulating layer; The light-emitting element is supplied to the substrate layer on which the first insulating material layer is formed, and the light-emitting element is aligned between the first electrode and the second electrode; A second insulating material layer having the second etching selectivity is formed on the substrate layer, such that the second insulating material layer covers the first insulating material layer and the light-emitting element; The first and second ends of the light-emitting element are exposed by etching the first insulating material layer and the second insulating material layer; One region of each of the first and second electrodes is exposed by etching the first insulating layer; as well as A third electrode and a fourth electrode are formed, which are configured to electrically connect the first end and the second end of the light-emitting element to the first electrode and the second electrode, respectively.

13. The method according to claim 12, in, The first insulating layer is formed of a first insulating material, and The first insulating material layer is formed of a second insulating material that is different from the first insulating material.

14. The method according to claim 13, wherein, The second insulating material layer is formed of the second insulating material.

15. The method according to claim 12, in, Simultaneously etch the first insulating material layer and the second insulating material layer. Specifically, a first insulating pattern is formed by etching the first insulating material layer, such that the first insulating pattern is disposed below the lower part of the light-emitting element, including below the lower parts of the first end and the second end of the light-emitting element. Specifically, a second insulating pattern is formed by etching the second insulating material layer, such that the second insulating pattern is disposed on a region of the light-emitting element other than the first end and the second end of the light-emitting element.

16. The method of claim 12, further comprising forming a first dam pattern and a second dam pattern on the substrate layer prior to forming the first electrode and the second electrode.

17. The method according to claim 16, in, The first electrode is formed on the first embankment pattern such that a region of the first electrode protrudes through the first embankment pattern, and The second electrode is formed on the second embankment pattern such that a region of the second electrode protrudes through the second embankment pattern.

18. The method according to claim 12, wherein, The steps of supplying and aligning the light-emitting element include: A plurality of light-emitting elements, including the light-emitting element, are supplied to each pixel region in which the first electrode and the second electrode are formed; and The light-emitting element is aligned between the first electrode and the second electrode by forming an electric field between the first electrode and the second electrode.

19. The method according to claim 18, wherein, The light-emitting element is aligned and positioned closer to the first electrode than closer to the second electrode.

20. The method of claim 12, further comprising forming a circuit layer including pixel circuitry on the substrate layer prior to forming the first electrode and the second electrode.

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