Hall Effect Sensors

Abstract

The present invention relates to Hall effect sensors. The present disclosure relates to semiconductor structures, and more particularly to three-contact Hall sensors, methods of manufacturing, and modes of operation. The structure includes: a plurality of sensing blocks, each of which includes a plurality of contacts; a first switching element connected to a first group of sensing blocks among the plurality of sensing blocks; and a second switching element connected to a second group of sensing blocks among the plurality of sensing blocks.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures and more particularly to Hall effect sensors, methods of fabrication, and modes of operation. Background Art

[0002] Hall effect sensors are used to measure the magnitude of a magnetic field. Their output voltage is proportional to the strength of the magnetic field passing through the sensor. Hall effect sensors can be used in many different applications. These applications include proximity sensing, positioning, speed detection, and current sensing applications. In fact, Hall effect sensors are often used in the automotive industry to time the speed of wheels and axles. These include internal combustion engine ignition timing, tachometers, anti-lock braking systems, and the rotation of brushless DC motors.

[0003] Hall effect sensors can be configured as four separate three-contact vertical Hall (3C-Vhall) elements or five-contact vertical Hall (5C-Vhall) elements. Three-contact vertical Hall (3C-Vhall) elements are often used to achieve better symmetry to improve offset / residual voltage; however, these three-contact elements have low sensitivity due to the voltage drop in the bias supply element, resulting in a low effective voltage applied for sensing. Five-contact vertical (5C-Vhall) elements can eliminate the undesirable voltage drop, but the device is not symmetrical, which can result in larger offset / residual voltages. Summary of the invention

[0004] In one aspect of the present disclosure, a structure includes: a plurality of sense blocks, each of which includes a plurality of contacts; a first switching element coupled to a first group of sense blocks among the plurality of sense blocks; and a second switching element connected to a second group of sense blocks among the plurality of sense blocks.

[0005] In one aspect of the present disclosure, a structure includes: a first plurality of sensing blocks, each of which includes a plurality of contacts; a second plurality of sensing blocks, each of which includes a plurality of contacts; and a fixed connection between the first plurality of sensing blocks and the second plurality of sensing blocks.

[0006] In one aspect of the present disclosure, a method includes: turning on switches for a first sensing block and a third sensing block for a Hall effect sensor, and turning off switches for a second sensing block and a fourth sensing block for the Hall effect sensor; applying a bias voltage between terminals of the third sensing block and the first sensing block; and measuring a voltage drop across the second sensing block and the fourth sensing block. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0008] Figure 1 A circuit diagram of a Hall effect sensor with a switching element according to some aspects of the present disclosure is shown.

[0009] Figure 2A and Figure 2B Representatively shown Figure 1 10 different switching modes of the structure.

[0010] Figure 3A and Figure 3B According to some aspects of the present disclosure Figure 1 The structure and Figure 2A and Figure 2B The corresponding switching mode and the cross-sectional diagram of the related manufacturing process.

[0011] Figure 4 A circuit diagram of a vertical Hall effect sensor with fixed connections according to some aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0012] The present disclosure relates to semiconductor structures and, more specifically, to Hall effect sensors, methods of manufacture, and modes of operation. More specifically, the present disclosure provides a Hall effect sensor having four three-contact vertical Hall elements (e.g., sensing blocks) with fixed connections or switched / alternating connections. For example, the three-contact sensing block may include a switch gate. Advantageously, by using a switch gate, undesirable voltage drops in bias power supply elements can be eliminated to achieve maximum voltage sensitivity (>20%) while maintaining structural symmetry to achieve improved offset / residual voltage (>80%). With respect to the latter advantage, the three-contact vertical Hall element described herein eliminates undesirable voltage drops in power supply bias.

[0013] The sensing blocks and switching elements of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, in general, these methods and tools are used to form structures with micrometer and nanometer sizes. The methods (i.e., techniques) for manufacturing the sensing blocks and switching elements of the present disclosure have been adopted from integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned by performing a photolithography process on top of the wafer. In particular, the manufacture of these sensing blocks and switching elements uses three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) applying a patterned mask on top of the film by photolithographic imaging, and (iii) selectively etching the film with the mask.

[0014] Figure 1A circuit diagram of a vertical Hall effect sensor with a switching element according to some aspects of the present disclosure is shown. More specifically, the circuit 10 includes a plurality of sensing blocks (Hall effect elements) 20, 30, 40, 50 in sequence. In an embodiment, the sensing blocks 20, 30, 40, 50 each include three (3) contacts, such as contact pads. Specifically, the sensing block 20 includes contact pads 22a, 22b, 22c, the sensing block 30 includes contact pads 32a, 32b, 32c, the sensing block 40 includes contact pads 42a, 42b, 42c, and the sensing block 50 includes contact pads 52a, 52b, 52c. The contact pads in each sensing block 20, 30, 40, 50 are disposed in a corresponding well 24, 34, 44, 54. In an embodiment, the contact pads may be n+ contacts and the wells may be N-type wells. The wells 24, 34, 44, 54 may be fabricated using conventional ion implantation processes, as discussed in more detail herein.

[0015] Still refer to Figure 1 , each sense block 20, 30, 40, 50 can be separated or isolated from each other by a deep trench isolation structure or a substrate material of a different conductivity type (representatively shown by reference numeral 52). For example, when the corresponding well 24, 34, 44, 54 is an N-type well, the well 52 can be a P-type well; and vice versa. On the other hand, the deep trench isolation structure 52 can be an oxide, polysilicon, or other insulating material manufactured using conventional photolithography, etching, and deposition methods further described herein.

[0016] In another embodiment, each sensing block 20, 30, 40, 50 includes a switching element, such as a transistor. For example, sensing blocks 20 and 40 include a switching element S1; and sensing blocks 30 and 50 include a switching element S2. Switching element S1 can be a single switch, and switch S2 can be another single switch. Switching elements S1, S2 allow current to flow between sensing blocks 20, 30, 40, 50, as described with respect to Figure 2A and Figure 2B For example, the switching elements S1 , S2 provide current to the corresponding contacts in each sensing block 20 , 30 , 40 , 50 .

[0017] exist Figure 1 , the switch elements S1, S2 and their corresponding contact pads may be connected together by wiring 56. As an example, each corresponding sense block 20, 30, 40, 50 is connected (e.g., coupled) in series at the corresponding contact pads by wiring 56, for example, contact pad 22b is connected to contact pad 32a, contact pad 32b is connected to contact pad 42a, contact pad 42b is connected to contact pad 52a, etc. The wiring 56 also connects the contact pads to the corresponding switch elements S1, S2.

[0018] Figure 2A and Figure 2B Representatively shown Figure 1 The invention relates to a structure 10 of different switching modes. By using switching elements, such as on / off switching elements S1, S2, the voltage drop on the bias power supply element is eliminated, and all the voltage drops are in the sensing terminals to provide maximum voltage sensitivity. Moreover, at the same time, the symmetry of the structure is maintained (e.g., sensing blocks 20 to 40 in the first switching mode and sensing blocks 30 to 50 in the second switching mode).

[0019] With the help of examples and Figure 2A As representatively shown in FIG. 1 , the bias voltage applied to terminals T1 and T3 is grounded, for example, switch element S1 is turned on and switch element S2 is turned off. In this way, current will be forced to flow from sensing block 20 to sensing block 40, and a voltage difference will be sensed between sensing block 30 and sensing block 50. This configuration will then provide maximum sensitivity in sensing block 30 and sensing block 50. On the other hand, as Figure 2B As representatively shown in FIG. 1 , a bias voltage is applied to terminal T2 or T4, switch element S2 is turned on and switch element S1 is turned off. In this way, current will be forced to flow from sensing block 30 to sensing block 50 or from sensing block 50 to sensing block 30, and a voltage difference will be sensed between sensing block 20 and sensing block 40. This configuration will then provide maximum sensitivity in sensing block 20 and sensing block 40.

[0020] Figure 3A and Figure 3B According to some aspects of the present disclosure Figure 1 The structure and Figure 2A and Figure 2B The corresponding switching mode and the cross-sectional diagram of the related manufacturing process. Figure 2A and Figure 2B The arrows in represent the current flow during the corresponding switching modes that have been described herein. Figure 3A In FIG. 1 , the switch element S2 is removed to representatively show that the switch element S1 is turned on and the switch element S2 is turned off; and in FIG. Figure 3B , the switching element S1 is removed to representatively show that the switching element S2 is turned on and the switching element S1 is turned off.

[0021] In manufacturing Figure 1 In the structural method, such as Figure 3A and Figure 3BRepresentatively shown, a well 24, 34, 44, 54 for each respective sense block 20, 30, 40, 50 is formed in a substrate 60. The substrate 60 may be a P-type substrate. The wells 24, 34, 44, 54 may be fabricated using conventional ion implantation processes. For example, the wells 24, 34, 44, 54 may be formed by introducing dopants into the substrate 60 by, for example, ion implantation. The wells 24, 34, 44, 54 may be formed to have an opposite conductivity type to that of the substrate 60.

[0022] In the manufacturing process, for example, an implantation mask can be used to define selected areas exposed for the implantation process. The implantation mask for selectively exposing the areas (e.g., wells 24, 34, 44, 54) can include a layer of photosensitive material (e.g., an organic photoresist layer) applied by a spin coating process, then pre-baked, exposed to light projected through a photomask, baked after exposure, and developed using a chemical developer. The implantation mask has a thickness and stopping power sufficient to prevent the masked areas from receiving a certain dose of implanted ions. Among other suitable examples, the N-well is doped with n-type dopants, such as arsenic (As), phosphorus (P), and Sb; and the P-well is doped with p-type dopants, such as boron (B).

[0023] As an example, a silicidation process can be used to form contacts. Contacts can also be formed using conventional photolithography, etching, and deposition methods known to those skilled in the art. It will be appreciated by those skilled in the art that the silicidation process begins by depositing a thin transition metal layer (e.g., nickel, cobalt, or titanium) on the ion implanted area (e.g., wells 24, 34, 44, 54). After the material is deposited, the structure is heated so that the transition metal reacts with the exposed silicon (or other semiconductor materials described herein) in the active area of ​​the semiconductor device (e.g., the contact area of ​​wells 24, 34, 44, 54) to form a low resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active area (e.g., wells 24, 34, 44, 54). Wiring 56 can be connected to contact pads and a voltage source.

[0024] The isolation region 52 can be a portion of the substrate, for example, a doped material or a deep trench isolation structure having a conductivity type opposite to that of the wells 24, 34, 44, 54. The deep trench isolation structure is formed by conventional photolithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed above the substrate 60 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry (e.g., reactive ion etching (RIE)) is used to form one or more trenches in the substrate 60 through the openings of the resist. After removing the resist using a conventional oxygen ashing process or other known stripping agent, the insulator material can be deposited by any conventional deposition process (e.g., a chemical vapor deposition (CVD) process). Any residual material can be removed by a conventional chemical mechanical polishing (CMP) process.

[0025] Wiring 56 can also be formed by conventional photolithography, etching and deposition. Similar to the deep trench isolation structure, wiring 56 is also formed by a resist formed above the insulator material above the substrate 60, which is exposed to energy (light) to form a pattern (opening). An etching process (such as RIE) with selective chemistry will be used to form one or more grooves in the insulator material to expose the contact pad. After removing the resist, the conductive material can be deposited by any conventional deposition process (such as (CVD) process). Any residual material can be removed by conventional chemical mechanical polishing (CMP) process.

[0026] The switch elements S1 and S2 may be conventional CMOS structures, such as transistors. Any conventional front-end process may be used to manufacture the transistors. For example, conventional CMOS processes may be conventional photolithography, etching, and deposition processes known to those skilled in the art for manufacturing switch devices (e.g., transistors). These processes include gate-first or gate-last (e.g., replacement gate) processes known to those skilled in the art, so that the present disclosure may be fully understood without further explanation.

[0027] Figure 4 A circuit diagram of a vertical Hall effect sensor with fixed connections between sense blocks according to some aspects of the present disclosure is shown. In this embodiment, the circuit 10a includes two structures 100a, 100b, each structure including four sense blocks with three contacts, as also shown in FIG. Figure 1 In this configuration, Figure 1 The switching element is omitted.

[0028] exist Figure 4In the configuration shown, in structure 100a, contacts 22a, 22b, and 22c of sense block 20 are connected together by wiring 56. Similarly, in structure 100a, contacts 42a, 42b, and 42c of sense block 40 are connected together by wiring 56. On the other hand, in structure 100a, contacts 32a, 32b, and 32c of sense block 30 and contacts 52a, 52b, and 52c of sense block 50 are not connected together by wiring. Conversely, in structure 100b, contacts 22a, 22b, and 22c of sense block 20a and contacts 42a, 42b, and 42c of sense block 40a are not connected together by wiring. However, in structure 100b, contacts 32a, 32b, and 32c of sense block 30a and contacts 52a, 52b, and 52c of sense block 50 are connected together by wiring 56.

[0029] Furthermore, the following fixed connections are provided by wiring 56:

[0030] (i) the sensing mass 20 of the structure 100a is directly connected to the sensing mass 30a of the structure 100b;

[0031] (i) the sensing mass 30 of the structure 100a is directly connected to the sensing mass 40a of the structure 100b;

[0032] (i) the sensing mass 40 of the structure 100a is directly connected to the sensing mass 50a of the structure 100b; and

[0033] (i) The sensing mass 50 of the structure 100a is directly connected to the sensing mass 20a of the structure 100b.

[0034] In operation using a fixed connection, current can be forced from sense block 20 to sense block 40 for the upper device 100a to measure the voltage difference between sense element 30 / 40a and sense element 50 / 20a. It should be noted that terminals 30 and 40a are the same terminal in this case because they are electrically connected together. Similarly, when terminals 50 and 20a are electrically connected together, they are the same terminal. In this way, the sense blocks of each structure 100a, 100b are connected together to form a symmetrical structure of higher sensitivity, in which the offset voltage is directly canceled and no switching elements are required.

[0035] The three-contact vertical Hall element can be utilized in system-on-chip (SoC) technology. It will be understood by those skilled in the art that a SoC is an integrated circuit (also referred to as a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, a SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0036] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0037] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: a plurality of sensing blocks, each of which comprises a plurality of contacts; a first switch element coupled to a first group of sensing blocks among the plurality of sensing blocks; as well as A second switching element connected to a second group of sensing blocks among the plurality of sensing blocks, wherein The first switching element is connected to alternating sensing blocks among the plurality of sensing blocks, and the second switching element is connected to another set of alternating sensing blocks among the plurality of sensing blocks, and The first switch element is connected to the first sensing block and the third sensing block, the second switch element is connected to the second sensing block and the fourth sensing block, and the first sensing block to the fourth sensing block are arranged in sequence. 2 . The structure of claim 1 , wherein the plurality of sense blocks is four sense blocks, each sense block comprising three contacts.

3. The structure of claim 2, wherein one of the contacts within each sense block is connected to a bias voltage. The structure according to claim 2 , wherein each of the sensing blocks is connected in series with each other through wiring.

5. The structure of claim 1, wherein each of the sensing blocks comprises wells isolated from each other.

6. The structure of claim 1, wherein the first switching element is different from the second switching element.

7. The structure of claim 1, wherein: When the first switch element is turned on and the second switch element is turned off, current is forced to flow from the first sensing block to the third sensing block or from the third sensing block to the first sensing block, and a voltage difference is sensed between the second sensing block and the fourth sensing block.

8. The structure according to claim 1, wherein when the second switching element is turned on and the first switching element is turned off, current is forced to flow from the second sensing block to the fourth sensing block or current is forced to flow from the fourth sensing block to the second sensing block, and a voltage difference is sensed between the first sensing block and the third sensing block.

9. A semiconductor structure comprising: a first plurality of sensing blocks, each of which comprises a plurality of contacts; a second plurality of sensing blocks, each of which comprises a plurality of contacts; as well as The fixed connection between the first plurality of sensing blocks and the second plurality of sensing blocks, wherein the plurality of contacts comprising three contacts provided for each of the first plurality of sensing blocks and the second plurality of sensing blocks; In the first plurality of sensing blocks, the plurality of contacts in a first set of alternating sensing blocks are connected together, and the plurality of contacts in a second set of alternating sensing blocks are not connected together; as well as In the second plurality of sense blocks, the plurality of contacts in a first set of alternating sense blocks are not connected together, and the plurality of contacts in a second set of alternating sense blocks are connected together.

10. The structure of claim 9, wherein the first plurality of sense blocks is four sense blocks and the second plurality of sense blocks is four sense blocks.

11. The structure of claim 9, wherein: The first group of alternating sensing blocks in the first plurality of sensing blocks and the first group of alternating sensing blocks in the second plurality of sensing blocks are respectively a first sensing block and a third sensing block; as well as The second group of alternating sensing blocks in the first plurality of sensing blocks and the second group of alternating sensing blocks in the second plurality of sensing blocks are second sensing blocks and fourth sensing blocks, respectively.

12. The structure of claim 11, wherein: The first sensing block of the first plurality of sensing blocks is connected to the second sensing block of the second plurality of sensing blocks; The second sensing block of the first plurality of sensing blocks is connected to the third sensing block of the second plurality of sensing blocks; The third sensing block of the first plurality of sensing blocks is connected to the fourth sensing block of the second plurality of sensing blocks; as well as The fourth sensing block of the first plurality of sensing blocks is connected to the first sensing block of the second plurality of sensing blocks.

13. The structure of claim 12, wherein: The first plurality of sensing blocks are connected in series; and The second plurality of sensing blocks are connected together in series. 14 . The structure of claim 10 , wherein each of the sense blocks in the first plurality of sense blocks and the second plurality of sense blocks comprises a well isolated from each other.

15. The structure of claim 14 wherein the wells are isolated from each other by substrate material having a different conductivity type than the wells.

16. A method for operating a semiconductor structure, comprising: turning on switches for a first sensing block and a third sensing block of a Hall effect sensor, and turning off switches for a second sensing block and a fourth sensing block of the Hall effect sensor; applying a bias ground voltage to terminals of the third sensing block and the first sensing block to force current to flow from the first sensing block to the third sensing block; sensing a voltage difference between the second sensing block and the fourth sensing block; as well as A bias voltage is applied to the terminals of the second sensing block and the fourth sensing block so that the switch for the second sensing block is turned on and the switch for the third sensing block is turned off, forcing current to flow between the second sensing block and the fourth sensing block, and sensing a voltage difference between the first sensing block and the third sensing block.

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