A timer control method and related equipment

Abstract

The embodiment of the present invention provides a timer control method and related equipment, by setting the timer time; if the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated, and the timing is restarted; if the timer mode is a custom mode, when the timer reaches a second preset time, a second interrupt is generated, and the timing ends. The present invention can set the time and mode, the minimum unit of timing, and the timing range are configurable.

Description

Technical Field

[0001] The present invention relates to the field of data storage, and in particular to a timer control method and related equipment. Background Art

[0002] In SOC (System on Chip), timers are often indispensable. A timer is a peripheral that allows users to count time by counting clock cycles. The user presets the number of clock cycles they want to wait for, and when the timer counts to this number of clock cycles, an interrupt is generated to indicate the elapsed time to the processor.

[0003] In traditional timers, the timing mode is single, the number of channels is fixed, and the minimum timing unit and range are fixed. Summary of the invention

[0004] The embodiment of the present invention provides a timer control method, by setting the timer time; if the timer mode is a free mode, when the timer reaches the first preset time, a first interrupt is generated, and the timing is restarted; if the timer mode is a custom mode, when the timer reaches the second preset time, a second interrupt is generated, and the timing ends. The present invention can set the time and mode, the minimum unit of timing, and the timing range can be configured.

[0005] In a first aspect, an embodiment of the present invention provides a timer control method, characterized in that the method includes:

[0006] Set the timer time;

[0007] If the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated and the timing is reset;

[0008] If the timer mode is a custom mode, when the timer reaches a second preset time, a second interrupt is generated and the timing ends.

[0009] Furthermore, before the step of setting the timer time, the method further includes:

[0010] Turning off the timer to put the timer in a non-timing state;

[0011] Set the minimum timing unit and timing range of the timer.

[0012] Furthermore, if the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated, and the step of retiming includes:

[0013] The first preset value is used as the first counting initial value, and when the current count of the counter is 0, the counting is continued with the first counting initial value as the counting initial value.

[0014] Further, the timer includes a counter, and if the timer mode is a custom mode, a second interrupt is generated when the timer reaches a second preset time, and the step of timing end includes:

[0015] A second preset value is used as a second counting initial value, and counting is performed with the second counting initial value. When the second counting initial value reaches 0, counting stops.

[0016] In a second aspect, an embodiment of the present invention provides a timer control circuit, the circuit comprising: a bus interface and N timers, and a control and status register interacting with the bus interface.

[0017] Furthermore, the timer is mainly composed of a frequency divider, a counter and a control and status register module.

[0018] Furthermore, the frequency divider is used to control the minimum timing unit and the maximum timing range of the timer, and the counter module is a down counter used to count the number of clock cycles preset by the timer.

[0019] In a third aspect, an embodiment of the present invention provides a timer control device, the device comprising:

[0020] Setting module, used to set the timer time;

[0021] A first judgment module, configured to generate a first interrupt and reset the timing when the timer reaches a first preset time if the timer mode is a free mode;

[0022] The second judgment module is used to generate a second interrupt and end the timing when the timer reaches a second preset time if the timer mode is the custom mode.

[0023] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps in the timer control method provided in the embodiment of the present invention when executing the computer program.

[0024] In a fifth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the timer control method provided in the embodiment of the invention are implemented.

[0025] In an embodiment of the present invention, by setting the timer time; if the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated, and the timing is restarted; if the timer mode is a custom mode, when the timer reaches a second preset time, a second interrupt is generated, and the timing ends. Turn off the timer to put the timer in a non-timing state; set the minimum timing unit and timing range of the timer; set the timer time; if the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated, and the timing is restarted; if the timer mode is a custom mode, when the timer reaches a second preset time, a second interrupt is generated, and the timing ends. The present invention can set the time and mode, and the minimum timing unit and timing range are configurable. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 is a flow chart of a timer control method provided by an embodiment of the present invention;

[0028] Figure 2 is an architecture diagram of a timer control circuit provided by an embodiment of the present invention;

[0029] Figure 3 is a flow chart of another timer control circuit method provided by an embodiment of the present invention;

[0030] Figure 4 It is a structural schematic diagram of a timer control device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] See also Figure 1 , Figure 1 is a flow chart of a timer control method provided by an embodiment of the present invention, such as Figure 1 As shown, the timer control method includes the following steps:

[0033] 101. Set the timer time.

[0034] In the embodiment of the present invention, the above-mentioned timer is one of the basic elements for the normal operation of the communication protocol, and is mainly used for various timing and frame retransmission tasks. The above-mentioned timer may be multiple.

[0035] In the embodiment of the present invention, the above communication protocol is the rules and agreements that must be followed by both entities to complete communication or service. The protocol defines the format used by the data unit, the information and meaning that the information unit should contain, the connection method, and the timing of information sending and receiving to ensure that the data in the network is smoothly transmitted to a certain place. In computer communication, the communication protocol is used to implement the standard between the computer and the network connection. If the network does not have a unified communication protocol, the information transmission between computers cannot be recognized.

[0036] Furthermore, before the step of setting the timer time, the present invention also includes: turning off the timer to put the timer in a non-timing state; and setting the minimum timing unit and timing range of the timer.

[0037] In the embodiment of the present invention, the timer is turned off to put the timer in a non-timing state; and the minimum timing unit and timing range of the timer are set.

[0038] 102. If the timer mode is the free mode, when the timer reaches a first preset time, a first interrupt is generated and the timing is reset.

[0039] In an embodiment of the present invention, the above-mentioned free mode is a mode in which a value preset by the user is used as the initial counting value. When the counter counts to 0, the counter will automatically continue to count with the initial counting value preset by the user. In order to ensure that the current counting is completed smoothly, when the counter is working, after the preset initial counting value is changed, the counter will not immediately restart counting with the new initial counting value. It is necessary to wait until the current counting ends (timing ends) before restarting counting with the new initial counting value.

[0040] Furthermore, if the above-mentioned timer mode is a free mode, then when the above-mentioned timer reaches a first preset time, a first interrupt is generated, and the step of retiming includes: taking the first preset value as the first counting initial value, and when the current count of the above-mentioned counter is 0, continuing to count with the above-mentioned first counting initial value as the counting initial value.

[0041] In an embodiment of the present invention, the timer mode is a free mode, with a first preset value as the first counting initial value. When the current count of the counter is 0, the counter will automatically restart counting with the first preset value as the first counting initial value. To ensure that the current counting is completed smoothly, when the counter is working, after the preset counting initial value is changed, the counter will not restart counting with the new counting initial value immediately. It is necessary to wait until the current counting ends before the new counting initial value can be used to restart counting.

[0042] 103. If the timer mode is the custom mode, when the timer reaches the second preset time, a second interrupt is generated and the timing ends.

[0043] In the embodiment of the present invention, the above-mentioned custom mode is a counter that counts with the initial count value preset by the user, and when the counting is completed, the counting stops. The user needs to turn off the timer and then reconfigure the timer before the timer can work again.

[0044] Furthermore, the above-mentioned timer includes a counter. If the above-mentioned timer mode is a custom mode, a second interrupt is generated when the above-mentioned timer reaches a second preset time. The step of ending the timing includes: taking the second preset value as the second counting initial value, and counting with the above-mentioned second counting initial value, and when the above-mentioned second counting initial value is 0, the counting stops.

[0045] In the embodiment of the present invention, the counter is a down counter, which is used to count the clock cycles preset by the timer. Counting is the simplest and most basic operation, and the counter is a logic circuit that implements this operation. In a digital system, the counter mainly counts the number of pulses to achieve the functions of measurement, counting and control, and also has a frequency division function. The counter is composed of a basic counting unit and some control gates, and the counting unit is composed of a series of various triggers with the function of storing information.

[0046] In an embodiment of the present invention, the above-mentioned timer mode is a custom mode, with the second preset value as the second counting initial value, and counting is performed with the above-mentioned second counting initial value. When the above-mentioned second counting initial value is 0, the counting stops, and the timer needs to be turned off, and then the timer is reconfigured before the timer can work again.

[0047] In an embodiment of the present invention, by setting the timer time; if the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated, and the timing is restarted; if the timer mode is a custom mode, when the timer reaches a second preset time, a second interrupt is generated, and the timing ends. Turn off the timer to put the timer in a non-timing state; set the minimum timing unit and timing range of the timer; set the timer time; if the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated, and the timing is restarted; if the timer mode is a custom mode, when the timer reaches a second preset time, a second interrupt is generated, and the timing ends. The present invention can set the time and mode, and the minimum timing unit and timing range are configurable.

[0048] Optional, see Figure 2 , Figure 2 is a schematic diagram of a timer control circuit provided by an embodiment of the present invention, such as Figure 2 As shown, the circuit includes: a bus interface and N timers, a control and status register interacts with the bus interface, receives a control signal from an external processor, and the external processor can read the timer status through the control and status register. Each timer is mainly composed of a frequency divider, a counter and a control and status register module. The frequency divider is used to control the minimum timing unit and the maximum timing range of the timer, and the counter module is a down counter used to count the preset number of timer cycles.

[0049] In the embodiment of the present invention, the present invention mainly includes a group of bus interfaces and N timers, and N can be set according to requirements.

[0050] In the embodiment of the present invention, the above N is represented by a number and can be 2, 3, 4 or more.

[0051] Furthermore, the timer is mainly composed of a frequency divider, a counter and a control and status register module.

[0052] In the embodiment of the present invention, the frequency divider is used to control the minimum timing unit and the maximum timing range of the timer. For example, in the STM32 timer, the pre-frequency divider is used to divide the timer clock source and output it. The value of the pre-frequency divider is set by the register TIMx_PSC, which is a 16-bit positive integer value.

[0053] In the embodiment of the present invention, the counter is a down counter, which is used to count the clock cycles preset by the timer. Counting is the simplest and most basic operation, and the counter is a logic circuit that implements this operation. In a digital system, the counter mainly counts the number of pulses to achieve the functions of measurement, counting and control, and also has a frequency division function. The counter is composed of a basic counting unit and some control gates, and the counting unit is composed of a series of various triggers with the function of storing information.

[0054] In an embodiment of the present invention, the control and status register is composed of a flag register EFLAGS, an instruction pointer EIP and four control registers. The control and status register interacts with the bus interface and receives control signals from an external processor. The external processor can read the status of the timer through the control and status register.

[0055] Furthermore, the frequency divider is used to control the minimum timing unit and the maximum timing range of the timer, and the counter module is a down counter used to count the number of clock cycles preset by the timer.

[0056] In the embodiment of the present invention, the above counter has two counting modes, a free counting mode and a user-defined mode.

[0057] In the embodiment of the present invention, the above-mentioned free mode uses a value preset by the user as the initial counting value. When the counter counts to 0, the counter will automatically restart counting with the initial counting value preset by the user. In order to ensure that the current counting is completed smoothly, when the counter is working, after the preset initial counting value is changed, the counter will not immediately restart counting with the new initial counting value. It is necessary to wait until the current counting ends (timing ends) before restarting counting with the new initial counting value.

[0058] In the embodiment of the present invention, the user-defined mode is a counter that counts with the initial count value preset by the user, and stops counting after the counting is completed. The user needs to turn off the timer and then reconfigure the timer before the timer can work again.

[0059] In an embodiment of the present invention, it mainly includes a group of bus interfaces and N timers, where N can be set according to requirements. Each timer is mainly composed of a frequency divider, a counter, and a control and status register module. The frequency divider is used to control the minimum timing unit and the maximum timing range of the timer. The counter module is a down counter used to count the number of clock cycles preset by the timer. Here, the counter has two counting modes, a free counting mode and a user-defined mode. The present invention uses a multi-channel design, and multiple timers share a group of bus interfaces, and the number of channels can be configured according to requirements.

[0060] Optional, see Figure 3 , Figure 3 is a flow chart of another timer control method provided by an embodiment of the present invention. Figure 3 As shown, the following steps are included:

[0061] Step S1: Turn off the timer to put the timer in a non-timing state.

[0062] Step S2: Set the minimum timing unit and timing range of the timer.

[0063] Step S3: Set the timing time (initial counting value).

[0064] Step S4: Set the timer counting mode. If it is the free mode, go to step S5; if it is the user-defined mode, go to step S8.

[0065] In the example of the present invention, the above-mentioned free mode uses a value preset by the user as the initial count value. When the counter counts to 0, the counter will automatically restart counting with the initial count value preset by the user. In order to ensure that the current counting is completed smoothly, when the counter is working, after the preset initial count value is changed, the counter will not immediately restart counting with the new initial count value. It is necessary to wait until the current counting ends (timing ends) before restarting counting with the new initial count value.

[0066] In the embodiment of the present invention, the user-defined mode is that the counter counts with the initial count value preset by the user, and the counting stops when the counting is completed. The user needs to turn off the timer and then reconfigure the timer before the timer can work again.

[0067] Step S5: Start the timer, and the timer is in the timing state.

[0068] Step S6: The timer starts timing.

[0069] Step S7: When the timer reaches the preset time, an interrupt is generated, and the timer resets the timing at the preset time.

[0070] Step S8: Start the timer, the timer is in the timing state, and starts timing.

[0071] Step S9: When the timer reaches the preset timing time, an interrupt is generated, the timer stops counting, and the timing ends. If the timing needs to be reset, the process will jump to step S1.

[0072] In an embodiment of the present invention, the timer is turned off to put the timer in a non-timing state; the minimum timing unit and timing range of the timer are set; the timer time is set; if the timer mode is a free mode, a first interrupt is generated when the timer reaches a first preset time, and the timing is restarted; if the timer mode is a custom mode, a second interrupt is generated when the timer reaches a second preset time, and the timing ends. The present invention can set the time and mode, and the minimum timing unit and timing range are configurable.

[0073] Optional, see Figure 4 , Figure 4 is a schematic diagram of the structure of a timer control device provided by an embodiment of the present invention, such as Figure 4 As shown, the device comprises:

[0074] The first setting module 401 is used to set the timer time;

[0075] A first judgment module 402 is used for generating a first interrupt and resetting the timing when the timer reaches a first preset time if the timer mode is a free mode;

[0076] The second judgment module 403 is used to generate a second interrupt and end the timing when the timer reaches a second preset time if the timer mode is the custom mode.

[0077] Furthermore, before the setting module 401 step, the device further includes:

[0078] A closing module, used for closing the timer to put the timer in a non-timing state;

[0079] The second setting module is used to set the minimum timing unit and timing range of the timer.

[0080] Furthermore, the first judgment module 402 is further configured to use a first preset value as a first counting initial value, and when the current count of the counter is 0, continue counting with the first counting initial value as the counting initial value.

[0081] Furthermore, the second judgment module 403 is further configured to use a second preset value as a second counting initial value, and to perform counting with the second counting initial value, and when the second counting initial value reaches 0, the counting stops.

[0082] In an embodiment of the present invention, by setting the timer time; if the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated, and the timing is restarted; if the timer mode is a custom mode, when the timer reaches a second preset time, a second interrupt is generated, and the timing ends. Turn off the timer to put the timer in a non-timing state; set the minimum timing unit and timing range of the timer; set the timer time; if the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated, and the timing is restarted; if the timer mode is a custom mode, when the timer reaches a second preset time, a second interrupt is generated, and the timing ends. The present invention can set the time and mode, and the minimum timing unit and timing range are configurable.

[0083] It should be noted that the timer control device provided in the embodiment of the present invention can be applied to smart phones, computers, servers and other devices that can perform business analysis at the map level.

[0084] The timer control device provided in the embodiment of the present invention can implement each process implemented by the timer control method in the above method embodiment and can achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0085] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the computer program implements the various processes of the timer control method or the application-side timer control method provided in the embodiment of the present invention, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0086] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM).

[0087] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A timer control method, characterized in that: The method comprises: Turn off the timer to put the timer in a non-timing state; Setting the minimum timing unit and timing range of the timer, wherein the timer comprises a counter, wherein the counter comprises a counting unit and a control gate, and wherein the counting unit comprises a trigger having a function of storing information; Set the timer time; If the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated and the timing is reset; If the timer mode is a custom mode, when the timer reaches a second preset time, a second interrupt is generated and the timing ends.

2. The timer control method according to claim 1, characterized in that: If the timer mode is a free mode, when the timer reaches a first preset time, a first interrupt is generated, and the steps of retiming include: The first preset value is used as the first counting initial value, and when the current count of the counter is 0, the counting is continued with the first counting initial value as the counting initial value.

3. The timer control method according to claim 1, characterized in that: If the timer mode is a custom mode, a second interrupt is generated when the timer reaches a second preset time, and the step of timing end includes: A second preset value is used as a second counting initial value, and counting is performed with the second counting initial value. When the second counting initial value reaches 0, counting stops.

4. A timer control circuit, characterized in that: The circuit comprises: a bus interface and N timers as claimed in claim 1, a control and status register interacting with the bus interface, wherein N is a positive integer.

5. The timer control circuit according to claim 4, characterized in that: The timer is composed of a frequency divider, a counter and a control and status register module.

6. The timer control circuit as claimed in claim 5, characterized in that: The frequency divider is used to control the minimum timing unit and the maximum timing range of the timer, and the counter is a down counter used to count the number of clock cycles preset by the timer.

7. A timer control device, characterized in that: The device comprises: A setting module, used for turning off the timer so that the timer is in a non-timing state; Setting the minimum timing unit and timing range of the timer, wherein the timer comprises a counter, wherein the counter comprises a counting unit and a control gate, and wherein the counting unit comprises a trigger having a function of storing information; Set the timer time; A first judgment module, configured to generate a first interrupt and reset the timing when the timer reaches a first preset time if the timer mode is a free mode; The second judgment module is used to generate a second interrupt and end the timing when the timer reaches a second preset time if the timer mode is the custom mode.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps in the timer control method according to any one of claims 1 to 3 when executing the computer program.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the timer control method according to any one of claims 1 to 3 are implemented.

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