Signal amplification in MRAM during read.

Abstract

This invention is entitled "Signal Amplification in MRAM During Read". The invention describes an apparatus and technique for reading MRAM memory cells. In a crosspoint memory array, each conductor, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET and an nMOSFET connected in parallel. When selecting a memory cell to be read, the pMOSFET can be used to pull up the voltage of a first conductor while the nMOSFET is used to pull down the voltage of a second conductor to, for example, 0V. This minimizes the capacitance when the selector is on. Furthermore, when reading the selected memory cell, the parallel nMOSFET of the first conductor can be turned on while the pMOSFET is turned off. The nMOSFET provides higher resistance instead of the reduced resistance of the pMOSFET to amplify the signal at the sensing circuit, thereby allowing accurate sensing of the voltage across the memory cell.

Description

Background Technology

[0001] Memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source.

[0002] An example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, unlike some other memory technologies that use charge to store data. Generally, MRAM comprises a large number of memory cells formed on a semiconductor substrate, where each memory cell represents (at least) one data bit. Data bits are written to the memory cell by changing the magnetization direction of magnetic elements within the cell, and bits are read by measuring the resistance of the memory cell. Low resistance typically indicates a "0" bit, and high resistance typically indicates a "1" bit. Attached Figure Description

[0003] Components with similar numbers refer to common parts in different drawings.

[0004] Figure 1 This is a block diagram of an exemplary implementation of a storage system connected to a host computer.

[0005] Figure 2 yes Figure 1 A block diagram of an exemplary embodiment of the FEP circuit 110.

[0006] Figure 3 yes Figure 1 A block diagram of an exemplary embodiment of the BEP circuit 112.

[0007] Figure 4 yes Figure 1 A block diagram of an exemplary embodiment of the memory package 104.

[0008] Figure 5A This is a block diagram of an example memory system that can implement the techniques described herein.

[0009] Figure 5B Depicting Figure 5A An example drive between row drive 524 and column drive 514.

[0010] Figure 5C An exemplary block diagram of a current driver 575 is depicted.

[0011] Figure 5D Depicting Figure 5CExample of DAC circuit 570.

[0012] Figure 6 This is a block diagram of another example of a memory system that can implement the techniques described herein.

[0013] Figure 7A Depicting Figure 5A or Figure 6 A cross-sectional view of an exemplary memory cell in memory array 502.

[0014] Figure 7B Depicting and Figure 7A A perspective view of an exemplary cross-point memory array 750 with memory cells consistent with memory cells.

[0015] Figure 8A Depicting Figure 7A An exemplary IV curve of the storage element 710.

[0016] Figure 8B Depicting Figure 7A An example IV curve for selector 702.

[0017] Figure 8C Depicting Figure 7A An exemplary IV curve of the memory cell 700.

[0018] Figure 9A An exemplary circuit consistent with the first stage of the crosspoint memory array 750 is depicted.

[0019] Figure 9B Depicting and Figure 9A and Figure 7B An exemplary circuit for the second stage of the crosspoint memory array 750.

[0020] Figure 10A Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is turned on and the nMOSFET is turned off when the voltage on the selected word line WL3_1 is pulled up.

[0021] Figure 10B Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is turned off and the nMOSFET is turned on when a voltage is sensed on the selected word line WL3_1.

[0022] Figure 10C Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is turned on and the nMOSFET is turned on when a voltage is sensed on the selected word line WL3_1.

[0023] Figure 10D Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is turned off and the nMOSFET is turned on when the voltage on the selected bit line BL0 is pulled up.

[0024] Figure 10E Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is off and the nMOSFET is on during the sensing process when the selected bit line BL0 is set to ground.

[0025] Figure 10F Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is turned on and the nMOSFET is turned on during the sensing process when the selected bit line BL0 is set to ground.

[0026] Figure 11A Describes the use of selected memory cells such as Figure 7A A flowchart illustrating an exemplary process in which the memory cell 700 performs a write operation.

[0027] Figure 11B Describes the use of selected memory cells such as Figure 7A A flowchart illustrating an exemplary process by which the memory cell 700 performs a read operation using a single voltage detection.

[0028] Figure 11C Describes the use of selected memory cells such as Figure 7A A flowchart illustrating an exemplary process by which the memory cell 700 performs a read operation using dual voltage detection.

[0029] Figure 12A Depicting Figure 7B and Figure 11B An exemplary implementation of the sensing circuit 564, which is consistent with the process.

[0030] Figure 12B Depicting Figure 7B and Figure 11C Another exemplary implementation of the sensing circuit 564, which is consistent with the process.

[0031] Figure 12C Depicting and Figure 9A An exemplary parallel resistor for the pMOSFET and nMOSFET of the consistent transistor pair Wd3_1.

[0032] Figure 13A Describes the relationship between memory cells and Figure 11AAn exemplary current versus time curve consistent with the writing process.

[0033] Figure 13B Describes the relationship between memory cells and Figure 13A An exemplary curve of consistent voltage versus time.

[0034] Figure 13C Describes the relationship between memory cells and Figure 11B An exemplary current versus time curve consistent with the reading process.

[0035] Figure 13D Describes the relationship between memory cells and Figure 13C An exemplary curve of consistent voltage versus time.

[0036] Figure 13E Describes the relationship between memory cells and Figure 11C The process (steps 1100 to 1108) is consistent with the exemplary current versus time curve.

[0037] Figure 13F Describes the relationship between memory cells and Figure 13E An exemplary curve of consistent voltage versus time.

[0038] Figure 13G Describes the relationship between memory cells and Figure 11C An exemplary current versus time curve consistent with the write-back process (step 1110).

[0039] Figure 13H Describes the relationship between memory cells and Figure 13G An exemplary curve of consistent voltage versus time. Detailed Implementation

[0040] This invention describes an apparatus and technique for reading MRAM memory cells.

[0041] MRAM memory cells include a magnetic switching material that can have different data states based on different magnetization states, each state having a different resistance. The MRAM memory cell can be a two-terminal device that is written to a low-resistance state (e.g., 25 kΩ) by applying a current for approximately 50 nsec in one direction and to a high-resistance state (e.g., 50 kΩ) by applying a current in the opposite direction, which can exceed the current required to write to the low resistance state for approximately 50 nsec; for example, if the critical dimension (CD) is 20 nm and the resistivity-area (RA) product of the memory cell is 10, then this current is 20% higher than the current required to write to the low resistance state. The current senses magnetic changes in the free layer of the memory cell.

[0042] Furthermore, when a number of memory cells are arranged in a crosspoint memory array, each memory cell may include a memory element (e.g., comprising a magnetic switching material) connected in series with a selector such as a bidirectional threshold switch. The selector may be in an on or off state. To write to or read from a particular memory cell, a voltage and / or current signal is applied via the corresponding word line and bit line in contact with the memory cell to set the selector to its on state. This is called selecting the memory cell. Once the selector is in its on state, a voltage and / or current can be applied to the memory element via the corresponding word line and bit line for writing or reading. For example, a "self-reference read" (SRR) may be performed in either direction to AP (high resistance state) or P (low resistance state) by selecting a bit in that direction, reading the bit to generate a level and storing the level, writing the bit in that direction, and reading the bit to compare it with an adjusted stored level. If the SRR is performed to the AP state, such adjustment may be a positive increase in voltage for later comparison, or if the SRR is performed to the P state, such adjustment may be a negative decrease in voltage for later comparison.

[0043] After a write operation, a read operation can be performed to determine the data state of the memory cell. A read operation may involve determining the voltage across the memory cell when a current is applied. One method for reading involves first sensing the voltage, then performing a potentially destructive write operation that ensures the memory cell is in a high-resistance state, followed by a second voltage sensing. If the voltage increases by more than a specified amount, it can be determined that the memory cell was initially in a low-resistance state and was programmed to a high-resistance state through the write operation. In this case, the write operation is destructive. If the voltage increases by less than a specified amount, it can be determined that the memory cell was initially in a high-resistance state and remains in a high-resistance state after the write operation. In this case, the write operation is not destructive.

[0044] To provide bidirectional write capability, both word lines and bit lines connected to the memory cell can include transistors, such as MOSFETs, for delivering voltage and / or current to the memory cell. A MOSFET or metal-oxide-semiconductor field-effect transistor is provided in the on-state when biased with an appropriate gate-to-source voltage (called Von). However, Von can change when the memory cell changes its resistance state. This affects the sensing of the voltage generated from reading the memory cell. This read can occur in a path through a decoder transistor to a global node leading to a sense amplifier (sensing circuit), which passes through a series combination of the decoder transistor and the selected memory bit (cell).

[0045] The technique provided in this paper addresses the aforementioned and other problems. Each bit line and word line is connected to a transistor pair, which includes a pMOSFET (p-channel MOSFET) connected in parallel with an nMOSFET (n-channel MOSFET). Bit lines and word lines are wires. The wires include a first wire connected to a first end (e.g., bottom) of each memory cell and a second wire connected to a second end (e.g., top) of each memory cell. When a memory cell to be read is selected, the voltage of the first wire can be pulled up (increased) to a positive voltage using the pMOSFET, while the voltage of the second wire can be pulled down (decreased) to, for example, 0V using the nMOSFET. - This method minimizes capacitance when the selector is turned on. When the voltage across the selector collapses from Vth (selector) (e.g., 2.2V) to Vhold (selector) (e.g., 1.3V), this turn-on of the selector can cause a transient current through the memory element, resulting in a discharge current through the memory bit when the voltage across it decreases. Such a current, higher than the steady-state read current, may cause premature state changes in the memory element before the read level is reached for comparison with the resulting read level after the bit is written.

[0046] In one option, when reading a selected memory cell, in addition to the pMOSFET used to select and turn on the bit selector connected in series with the memory element, a parallel nMOSFET of the first wire can also be used by turning it on after the selector of the selected memory bit is turned on. The nMOSFET adds resistance to offset the reduced resistance of the pMOSFET, allowing for more accurate sensing of the voltage across the memory cell at the global node via the decoder transistor using the address selection bit provided by the host when the cycle is activated. Therefore, the amplitude of the voltage sensed by the sense amplifier circuit is better maintained. In the above-described type of read operation where the voltage is sensed for the first and second time, the pMOSFET can be turned on (set to be in the on state) along with the nMOSFET each time. During a potentially destructive write operation, the nMOSFET can remain on or off (set to be in the non-conducting state) while the pMOSFET is on. The nMOSFET is then turned on, so that a read after a potentially destructive write has the same conditions as a read before the write, allowing a comparison of the resulting level to determine whether the bit state of the memory element has changed after the write.

[0047] In another option, when the selected memory cell is read, the pMOSFET is off, while the parallel nMOSFET is on. This increases the total resistance of the transistor pair, so that if the memory element changes from a low-resistance state to a high-resistance state (LRS to HRS) after a destructive write, the voltage sensed by the sensing circuit is amplified, and the second read is only performed with the nMOSFET on. In the above-described type of read operation where the first and second sensed voltages are both present (e.g., SRR), the pMOSFET is off each time while the nMOSFET is on. During a potentially destructive write operation, the nMOSFET can remain on or off while the pMOSFET is on.

[0048] Using pMOSFETs instead of nMOSFETs during the initial selection of the memory cell helps reduce capacitance and allows overvoltages across the memory cell to discharge more quickly, thereby reducing the resulting bit error rate (and interference) during the initial read.

[0049] Generally speaking, both writing and reading can be optimized by selecting which one or two transistors of a parallel transistor pair are turned on relative to subsequent read and write operations during the selection period.

[0050] These and other beneficial effects are described below.

[0051] Figure 1 This is a block diagram of an exemplary embodiment of a memory system connected to a host computer. The memory system 100 can implement the techniques proposed herein. Exemplary memory systems include solid-state drives (“SSDs”), memory cards, and embedded memory devices. Other types of memory systems may also be used.

[0052] Figure 1The memory system 100 includes a controller 102, non-volatile memory for storing data disposed in one or more memory packages 104, and local memory 106 such as DRAM or ReRAM. The controller 102 includes front-end processor (FEP) circuitry 110 and one or more back-end processor (BEP) circuits 112. In one approach, the FEP circuitry 110 is implemented on an ASIC, and each BEP circuit 112 is implemented on a separate ASIC. In other approaches, a unified controller ASIC may combine both front-end and back-end functions. The ASIC may be implemented on the same semiconductor, allowing the controller 102 to be fabricated as a system-on-a-chip (SoC). Both the FEP circuitry 110 and the BEP circuitry 112 include their own processors. In one approach, the FEP circuitry 110 and the BEP circuitry 112 are used in a master-slave configuration, where the FEP circuitry 110 is the master and each BEP circuitry 112 is the slave. For example, the FEP circuitry 110 may implement a flash translation layer (FTL) or a media management layer (MML). See also Figure 2 The BEP circuit 112 manages memory operations within the memory package / die based on requests from the FEP circuit 110. For example, the BEP circuit 112 can perform read, erase, and program processes. Additionally, the BEP circuit 112 can perform buffer management, set specific voltage levels required by the FEP circuit 110, perform error correction (ECC), and control the switching mode interface to the memory package. Each BEP circuit 112 can be responsible for its own set of memory packages. Alternatively, the interface can be JEDEC industry standard DDR or LPDDR, such as DDR5 or LPDDR5.

[0053] The memory package 104 may include one or more memory dies. Therefore, the controller 102 is connected to one or more non-volatile memory dies. In one approach, each memory die in the memory package 104 utilizes a storage-class memory (SCM) based on resistive random access memory (such as ReRAM, MRAM, or FeRAM or phase-change memory (PCM)).

[0054] Controller 102 communicates with host 120 via interface 130. The interface can implement protocols such as PCI Express (PCIe) or NVM Express (NVMe) over DDR5 or LPDDR5. To work with memory system 100, host 120 includes a host processor 122, host memory 124, and PCIe interface 126 connected along bus 128. Host memory 124 is physical memory such as DRAM, SRAM, non-volatile memory, or another type of storage device. In this example, host 120 is external to and separate from memory system 100. In one approach, memory system 100 is embedded within host 120.

[0055] Figure 2 yes Figure 1 A block diagram of an exemplary embodiment of the FEP circuit 110. PCIe interface 150 and host 120 ( Figure 1 The host processor 152 communicates with the network on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit, typically between cores within a SoC. The NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communication. The NOC 154 communicates with the memory processor 156, SRAM 160, and DRAM controller 162. The DRAM controller 162 is used to operate and communicate with local memory 106, such as DRAM 106. SRAM 160 is the local RAM memory used by the memory processor 156. The memory processor 156 is used to run FEP circuitry and perform various memory operations. The NOC also communicates with two PCIe interfaces, 164 and 166. Figure 1 In this design, the SSD controller includes two BEP circuits 112; therefore, there are two PCIe interfaces 164 and 166. Each PCIe interface communicates with one of the BEP circuits 112. The number of BEP circuits 112 and PCIe interfaces can vary.

[0056] FEP circuit 110 may also include a flash translation layer (FTL), or more generally a media management layer (MML) 158, which performs memory management (e.g., garbage collection, wear leveling, and load balancing), logic-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and overall operation management of SSDs or other non-volatile storage systems. MML 158 may be integrated as part of memory management that can handle memory errors and interact with the host interface. Specifically, MML may be a module in FEP circuit 110 and may include algorithms in the memory device firmware that translate writes from the host into the die's memory structure (such as...). Figure 5A and Figure 6 Writes to the memory array 502. MML 158 may be necessary because: 1) the memory may have limited endurance; 2) the memory structure may only have multiple pages written to; and / or 3) the memory structure may not need to be written to unless it is erased as a block. MML 158 understands these potential limitations of the memory structure, which may not be visible to the host. Therefore, MML 158 attempts to convert writes from the host into writes to the memory structure.

[0057] Figure 3 yes Figure 1 A block diagram of an exemplary embodiment of the BEP circuit 112. In some methods, the BEP circuit is part of a controller. The BEP circuit includes features for communicating with the FEP circuit 110 (e.g., with...). Figure 2 PCIe interface 200 communicates with one of PCIe interfaces 164 and 166. PCIe interface 200 communicates with two NOCs 202 and 204. In one method, the two NOCs are combined. NOCs 202 and 204 are connected to SRAMs 230 and 260, buffers 232 and 262, processors 220 and 250, and data path controllers 222 and 252, respectively, via XOR engines 224 and 254 and ECC engines 226 and 256 (for performing error correction). The XOR engine allows data to be combined and stored in a manner that allows for recovery in the event of a programming error.

[0058] Data path controllers 222 and 252 are connected to interface modules 228 and 258, respectively, which in this example each communicate with the memory package via four channels. Therefore, NOCs 202 and 204 each have four channels for communicating with the memory package. Each interface 228 / 258 includes four switching mode interfaces (TM interfaces), four buffers, and four schedulers. For each channel, there is one scheduler, buffer, and TM interface. Data path controllers 222 and 252 may include a processor, FPGA, microprocessor, or other type of controller. XOR engines 224 and 254 and ECC engines 226 and 256 are dedicated hardware circuitry such as hardware accelerators. In other approaches, XOR engines 224 and 254 and ECC engines 226 and 256 may be implemented in software. The scheduler, buffers, and TM interfaces are hardware circuitry.

[0059] Figure 4 yes Figure 1 A block diagram of an exemplary embodiment of the memory package 104. The memory package includes a plurality of memory dies 292 connected to a memory bus 294 including data lines and chip enable lines. The memory bus 294 is connected to a switching mode interface 296 for communication with the TM interface of the BEP circuit 112 (see, for example...). Figure 3 The memory package may include a small controller connected to a memory bus and a TM interface, and may have one or more memory dies. In one approach, each memory package includes eight or sixteen memory dies; however, the number of dies may vary. Alternatively, such controllers, ECC, and loss balancing functions may be implemented within each memory chip as an "on-chip" controller with ECC and loss balancing.

[0060] Figure 5A This is a block diagram of an example memory system that can implement the techniques described herein. Memory system 500 includes a memory array 502 having memory cells. For example, the memory cells may be arranged in rows and columns in an interlaced array manner, wherein wires such as word lines extend along the row direction and bit lines extend along the column direction. See, for example, [link to relevant documentation]. Figure 7BThe memory system 500 includes row control circuitry 520, the output of which, 508, is connected to a corresponding word line of the memory array 502. Row control circuitry 520 receives a set of M row address signals and various control signals from system control logic circuitry 560. Row control circuitry may include circuitry such as row decoder 522, row driver 524, and block select circuitry 526 for both read and write operations. The memory system 500 also includes column control circuitry 510, the input / output of which, 506, is connected to a corresponding bit line of the memory array 502. Column control circuitry 510 receives a set of N column address signals and various control signals from system control logic circuitry 560. Column control circuitry may include circuitry such as column decoder 512, column driver 514, block select circuitry 516, and read / write circuitry and I / O multiplexers. See also Figure 5B .

[0061] System control logic circuitry 560 receives data and commands from the host and provides output data and status to the host. In other methods, system control logic circuitry 560 receives data and commands from a separate controller circuit and provides output data to that controller circuit, wherein the controller circuit communicates with the host. System control logic circuitry 560 may include a state machine 561 that provides die-level control for memory operations. In one method, the state machine can be programmed by software. In other methods, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuitry). In yet another method, the state machine is replaced by a microcontroller. System control logic circuitry 560 may also include power control circuitry 562 that controls the power and voltage supplied to rows and columns of memory array 502 during memory operations. System control logic circuitry 560 may include one or more state machines, registers 563, and other control logic for controlling the operation of memory system 500. System control logic circuitry 560 may also include sensing circuitry 564, such as a sense amplifier. The sensing circuitry can be used to read data during operations to determine the data state of memory cells as described herein. See, for example, [link to documentation]. Figure 12B .

[0062] In some methods, all components of the memory system 500 (including the system control logic circuit 560) may be formed as part of a single die. In other methods, some or all of the system control logic circuit 560 may be formed on different dies.

[0063] For the purposes of this document, the phrases “control circuit”, “one or more control circuits”, etc., may include row control circuit 520, column control circuit 510, controller, state machine, microcontroller and / or other control circuits represented by system control logic circuit 560, or other similar circuits for controlling non-volatile memory.

[0064] The memory array 502 may include, for example, a single-level cross-point array or a multi-level cross-point array (Figure 7B). The memory structure may be formed over a single substrate (such as a wafer).

[0065] In one method, memory array 502 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory stages are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory, which is integrally formed in one or more physical stages of memory cells having active regions disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0066] In another approach, memory array 502 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0067] The exact type of memory array architecture or memory cell included in memory array 502 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form the memory structure. Other examples of suitable technologies for the memory cells of memory array 502 include ReRAM (Resistive Random Access Memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of memory array 502 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit-line arrays, etc.

[0068] One example of a ReRAM crosspoint memory includes reversible resistive switching elements arranged in a crosspoint array accessed by X-lines and Y-lines (e.g., word lines and bit lines, respectively). In another approach, the memory cell may include a conductive bridge memory cell. A conductive bridge memory cell can also be referred to as a programmable metallized cell. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory cell can be used as a state-changing element. In some cases, the conductive bridge memory cell may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, ion mobility also increases, leading to a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory cell can have a wide range of programming thresholds across the entire temperature range.

[0069] Magnetoresistive random access memory (MRAM) uses magnetic storage elements to store data. The element is formed of two ferromagnetic plates, each of which can remain magnetized, separated by a thin insulating layer. See also Figure 7A. One of the plates (the reference layer) is a permanent magnet set to a specific polarity, and the other plate (the free layer) has a magnetization that can be changed to match an external field to store the memory. Memory devices are constructed from a grid of such memory cells. In one method for programming, each memory cell is located between a pair of wires arranged at right angles to each other, parallel to the cell, one above and one below. When current flows through the wires, an induced magnetic field is generated. MRAM-based memory methods will be discussed in more detail below.

[0070] Phase-change memories (PCMs) utilize the unique properties of chalcogenide glasses. One method uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by changing the coordination state of germanium atoms using only a laser pulse (or a light pulse from another source). Therefore, the programming dose is the laser pulse. Memory cells can be suppressed by preventing them from receiving light. In other PCM methods, memory cells are programmed via current pulses. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage, light, or other waves.

[0071] The techniques described herein are not limited to a single specific memory structure, memory configuration, or material composition, but encompass many related memory structures within the technical essence and scope as described herein and as understood by one of ordinary skill in the art.

[0072] Can Figure 5AThe components are divided into two parts: the memory array 502 and the peripheral circuitry, including all other components. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory dies allocated to the memory array 502 in the memory system 500. However, this reduces the area of ​​the memory dies available for the peripheral circuitry. Furthermore, the functionality of the system control logic circuitry 560 that can be provided on the chip is limited. Therefore, in the design of the memory dies for the memory system 500, a fundamental trade-off needs to be struck between the amount of dedicated area for the memory array 502 and the amount of dedicated area for the peripheral circuitry.

[0073] In addition, the memory array 502 and peripheral circuitry can be manufactured using different technologies, such as NMOS, PMOS and CMOS.

[0074] To address these issues, the methods described below can... Figure 5A The components are separated onto individually formed dies, and then these dies are bonded together. Specifically, the memory array 502 may be formed on a single die, and some or all of the peripheral circuitry elements (including one or more control circuits) may be formed on separate dies. For example, a memory die may be formed solely of memory cells, such as NAND flash memory, MRAM memory, PCM memory, ReRAM memory, or other memory cell arrays of other memory types. Some or all of the peripheral circuitry (including components such as decoders and sense amplifiers) can then be moved to separate dies. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about CMOS components now moved to separate peripheral circuitry dies that can be optimized for CMOS processing. This provides more space for peripheral components, and additional capabilities that might not be easily bonded can now be combined if peripheral components are confined to the edge of the same die that houses the memory cell array. Two dies can then be bonded together in a bonded multi-die memory circuit, with an array on one die connected to peripheral components on another die. See also Figure 6 .

[0075] Figure 5B Depicting Figure 5AAn exemplary driver between row driver 524 and column driver 514. The driver may include charge pump and regulator circuitry for generating and regulating voltage and current on wires such as word lines and bit lines. The drivers include word line (WL) driver 524a, WL nMOSFET transistor driver 524b, WL pMOSFET transistor driver 524c, and WL isolated transistor driver 524d. Voltage drivers also include bit line (BL) driver 513G, BL nMOSFET transistor driver 513H, BL pMOSFET transistor driver 514c, and BL isolated transistor driver 514d. The WL driver and BL driver may be voltage and / or current drivers. See, for example, [link to relevant documentation]. Figure 5C The driver in the 575.

[0076] Figure 5C An exemplary block diagram of a current driver 575 is depicted. The current driver may be provided as, for example... Figure 5A It is part of the row control circuit 520 and / or column control circuit 510, and may be implemented in different ways. The current driver may be a write current source used to set the desired current and / or voltage to perform tasks, including writing data to memory cells, selecting memory cells, and performing potentially destructive writes to memory cells.

[0077] An exemplary current driver is based on the DAC7811 from Texas Instruments and includes a 12-bit, serial-input, digital-to-analog converter multiplier. The current driver outputs a fixed or varying current based on the digital input. The current driver includes a 12-bit R-2R DAC 570, a DAC register 571, an input latch 572, control logic and an input shift register 574, and a power-on reset circuit 573.

[0078] The inputs to the control logic and input shift registers include NOT (synchronization), SCLK, and SDIN. NOT (synchronization) is a valid low control input. This is the frame synchronization signal used for input data. When synchronization goes low, it powers on the buffers of SCLK and SDIN, and the input shift registers are enabled. Data is loaded into the shift registers on the active edges of the following clocks. The serial interface counts the clock, and data is latched into the shift registers on the 16th active clock edge. SCLK is the serial clock input. By default, the data clock is controlled into the input shift registers on the falling edge of the serial clock input. SDIN is the serial data input. The data clock is controlled into the 16-bit input registers on the active edge of the serial clock input. Upon power-on reset, the data clock is controlled into the shift registers on the falling edge of SCLK. SDO is a serial data output, such as for control logic and input shift registers used to link multiple devices.

[0079] The DAC 570's outputs include RFB, IOUT1, and IOUT2. RFB is the DAC's feedback resistor. IOUT1 is the DAC's current output. VOUT is the output voltage of the current source. IOUT2 ​​is the DAC's analog ground. Exemplary current and voltage outputs are shown in... Figures 13E to 13H Provided by China.

[0080] Figure 5D Depicting Figure 5C Example of a DAC circuit 570. The circuit is digitally controlled based on twelve data bits DB0-DB11, where DB0 is the least significant bit (LSB) and DB11 is the most significant bit (MSB). The circuit includes a set of resistors 581 arranged in series with resistors R, and a set of resistors 582 arranged in parallel with resistors 2R in different branches of the staircase. Additionally, each 2R resistor is connected to a switch in a set of switches 583, which can connect the resistor to either output path IOUT1 or IOUT2 ​​based on the value of the corresponding data bit. The circuit receives a reference voltage Vref, which is used to generate current in the different branches and determine the DAC full-scale current. Based on the data bits, the corresponding current is provided as the output.

[0081] Figure 6 This is a block diagram of another example of a memory system that can implement the techniques described herein. Figure 5AAlternative arrangements can be made, for example, using wafer-to-wafer bonding, to provide bonded die pairs in memory system 600. A control die 611 and a separate memory die 601 are coupled. The control die includes peripheral circuitry, including system control logic circuitry 560, row control circuitry 520, and column control circuitry 510. Additional components, such as functional elements from controller 102, may also be moved to the control circuitry die 611.

[0082] Column control circuitry 510 is coupled to memory array 502 via a conductive path. The conductive path provides electrical connections between column decoder 512, column driver 514, and block select circuitry 516 and the bit lines of memory array 502. The conductive path extends from column control circuitry 510 in control die 611 through pads on control die 611. These pads engage with corresponding pads on memory die 601, which in turn connect to the bit lines of memory array 502. Each bit line of memory array 502 may have a corresponding conductive path connected to column control circuitry 510. Similarly, row control circuitry 520 is coupled to memory array 502 via conductive paths. Each conductive path may correspond to a word line, dummy word line, or selected gate line. Additional electrical paths may also be provided between control die 611 and memory die 601.

[0083] System control logic circuit 560, column control circuit 510, row control circuit 520 and / or controller 102 (or equivalent functional circuit) and Figure 5A All or a subset of other circuits depicted in the diagram or in combination thereof Figure 6 The control circuit chip 611 and Figure 5A Combinations of similar elements can be considered as part of one or more control circuits that perform the functions described herein. Control circuitry may consist solely of hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may include processors, FGAs, ASICs, integrated circuits, or other types of circuitry.

[0084] In the following discussion, memory array 502 is primarily discussed in the context of a cross-point architecture, although much of the discussion can be applied more generally. In a cross-point architecture, a first set of conductors or lines (such as word lines) extends in a first direction relative to the underlying substrate, and a second set of conductors or lines (such as bit lines) extends in a second direction relative to the underlying substrate. Memory cells are located at the intersections of word lines and bit lines. These memory cells at the cross-points can be formed according to any of a variety of techniques, including those described above. The following discussion will focus primarily on methods based on cross-point architectures using MRAM memory cells.

[0085] Figure 7A Depicting Figure 5A or Figure 6 A cross-sectional view of an exemplary memory cell in a memory array 502. Memory cell 700 includes a memory element 710 connected in series with a selector 702. The memory array may consist of a large number of such memory cells. Exemplary memory cell 700 includes a bottom electrode 701 and a top electrode 706 formed of a metal such as titanium (Ti) or titanium nitride (TiN). In this example, the memory element is an MRAM and includes a reference layer 703, a tunnel barrier 704, and a free layer 705. The reference layer may include a ferromagnetic metal, such as a bilayer of CoFeB and CoPt coupled to conductive spacers, which may include, for example, conductive metals such as Ta, W, Ru, CN, TiN, and TaN. The free layer may include a ferromagnetic metal, such as a CoFe or CoFeB alloy, with a thickness of approximately 1-2 nm. An Ir layer may be disposed between the free layer and the tunnel barrier and may be doped with Ta, W, or Mo. The tunnel barrier may include, for example, MgO or other insulating materials. A capping layer such as MgO may be provided over the free layer to increase the anisotropy of the free layer. The resistance of a storage element changes based on its magnetization.

[0086] The top wire is connected to the top end 731 of the memory cell, while the bottom wire is connected to the bottom end 721 of the memory cell. One end is the first end, and the other end is the second end. One of the wires is a word line, and the other is a bit line.

[0087] The selector can be located anywhere relative to the storage element, such as above, below, or to the side of the storage element. In this example, the selector is located below the storage element.

[0088] Memory cells can be bipolar (bidirectional), meaning that applying a voltage of one polarity across their terminals to write (program) them to a high-resistance state (HRS) and applying a voltage of the opposite polarity across their terminals to write them to a low-resistance state (LRS). See, for example, [link to relevant documentation]. Figure 8C Therefore, storage elements can reversibly switch between two or more states. One resistance state can represent binary "0", while another resistance state can represent binary "1". However, more than two data / resistance states can be used in some types of storage element technologies, such as phase-change memory, all of which can be advantageously selected and sensed in this manner.

[0089] The selector may include, for example, bidirectional threshold switching materials. Examples include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te.

[0090] A selector controls access to a storage element. Specifically, in order to apply a voltage or current to a storage element to change its resistance state, the corresponding selector must first switch from a non-conducting state to a conducting state by applying a sufficiently high voltage (e.g., a voltage with an amplitude higher than a threshold voltage). See also Figure 8B .

[0091] The state of a memory cell is based on the relative orientation of the magnetization of the reference layer and the free layer. If the two layers are magnetized in opposite directions, the memory cell will be in an antiparallel (AP) state, a high-resistance state (HRS). If the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) state, a low-resistance state (LRS).

[0092] The magnetization direction is fixed for the reference layer but can be changed for the free layer. Data is written to MRAM memory cells by programming the free layer to have the same or opposite orientation as the reference layer. In one method, such as Figure 7B The array of MRAM memory cells is initialized by setting all memory cells to the LRS. Selected memory cells can then be programmed by placing their free layers in the HRS by reversing the magnetic field to be opposite to that of the reference layer. While the free layers are being programmed, the reference layer maintains its orientation.

[0093] To sense (read) the state of data stored in MRAM, a voltage is applied across the memory cell to determine its resistance state. Voltage or current can be applied across the memory cell in either direction. In one method, voltage is applied by driving a current. See, for example... Figure 13E and Figure 13F .

[0094] One type of MRAM is the vertical spin-transmitted torque (STT) MRAM, where the free layer comprises a switchable magnetization orientation perpendicular to the plane of the free layer. STT is an effect that allows modification of the magnetic layer orientation in a magnetic tunnel junction using spin-polarized currents. Charge carriers (such as electrons) possess a property called spin, which is a small amount of angular momentum inherent to the charge carrier. The current is generally unpolarized (e.g., composed of 50% spin-up and 50% spin-down electrons). A spin-polarized current is a current with more electrons of either spin (e.g., a majority of spin-up electrons or a majority of spin-down electrons). In a write operation, a spin-polarized current is generated by passing a current through a reference layer. If this spin-polarized current is directed into the free layer, angular momentum can be transferred to the free layer, thereby changing its magnetization orientation.

[0095] For antiparallel-to-parallel (AP2P) writing, arrow 741 indicates the electron writing current, such as the direction of electron (e-) movement, and arrow 742 indicates the direction of current (I). For example, in order to... Figure 7A An electron writing current is generated in the direction of the upward arrow 741. Due to the negative charge of the electrons, the voltage of the top conductor 730 is set higher than (+V) the voltage of the bottom conductor 730. Electrons in the electron writing current become spin-polarized as they pass through the reference layer 703. When the spin-polarized electrons tunnel through the tunnel barrier 704, the conservation of angular momentum can cause a spin-transfer torque to be applied to both the free layer 705 and the reference layer 703. If the initial magnetization orientation of the free layer is antiparallel to the reference layer (AP), this torque is insufficient to affect the magnetization direction of the reference layer, but sufficient to switch the magnetization orientation in the free layer to be parallel to the magnetization orientation of the reference layer (P). Then, before and after the electron writing current is turned off, the parallel magnetization will remain stable.

[0096] For parallel-to-antiparallel (P2AP) writing, arrow 743 indicates the electron writing current, such as the direction of electron (e-) movement, and arrow 744 indicates the direction of current (I). If the free layer and reference layer are initially magnetized parallel, an electron writing current with the opposite direction to the above can be applied (e.g., Figure 7A The direction of the magnetization of the free layer (as indicated by the downward arrow 743 in the diagram) is used to switch the magnetization direction of the free layer to become antiparallel to the magnetization direction of the reference layer. In this case, an electron write current is applied from the top conductor 730 to the bottom conductor 720 by applying a higher voltage (+V) on the bottom conductor. This writes the free layer from the P state to the AP state. Therefore, the magnetization of the free layer can be set to either of the two stable orientations based on the direction of the electron write current.

[0097] Data ("0" or "1") in a memory cell can be read by measuring its resistance. LRS can represent a "0" bit, while HRS represents a "1" bit. During a read operation, a read current can be applied across the memory cell, for example, by applying an electronic read current from the bottom wire to the top wire in the AP2P direction, or by applying an electronic read current from the top wire to the bottom wire in the P2AP direction. During a read operation, if the electronic write current is too high, this can interfere with the data stored in the memory cell and alter its state. For example, if the electronic read current uses the P2AP direction, excessive current or voltage in the P2AP direction can switch a memory cell in a low-resistance P state to a high-resistance AP state during the initial read, which is intended to store the level representing the initial bit state at the start of the "read". Because writing to P2AP requires more current, although MRAM memory cells can be read in either direction, the directional nature of the write operation can make one read direction superior to the other to reduce the bit error rate (interference); that is, the P2AP direction.

[0098] To read from or write to a selected memory cell in the memory array, the bit lines and word lines corresponding to the selected memory cell are biased to apply a voltage across the selected memory cell and cause an electron flow. This also applies a voltage to unselected memory cells connected to the array of bit lines and word lines, resulting in current leakage and power consumption. One way to reduce current leakage is to place the selector element in series with each MRAM. For example, a threshold switch selector has high resistance (off or non-conducting) when the bias is held below its threshold voltage and low resistance (conducting or conducting) when the bias is held above its threshold voltage. The threshold switch selector remains on until its current drops below the holding current or the voltage drops below the holding voltage. See also Figure 8B When this occurs, the threshold switch selector returns to the off state until a voltage greater than the threshold voltage (or a current greater than the threshold current) is applied again. Therefore, to program a memory cell at the crossover point, a voltage and / or current sufficient to turn on the associated threshold switch selector and write to the memory cell is applied. Similarly, to read a memory cell, the threshold switch selector must be turned on before the resistance state of the memory cell can be determined. In one approach, the resistance state is determined by applying a read current Iread and detecting the resulting voltage across the bit line and word line of the memory cell (including the memory element and the series-connected selector) and the series-select transistor (entering the global select node of the sense amplifier). For example, the voltage can be detected before and after a potentially destructive write operation as described herein.

[0099] When the threshold switch selector is turned on, the MRAM storage element 710 operates as described, despite a voltage drop across the threshold switch selector. After turning on the threshold switch selector by applying a voltage higher than the threshold voltage, the bias current or voltage should be high enough to exceed the holding current or holding voltage of the threshold switch selector so that the selector remains on during subsequent read or write operations. See also Figures 8A to 8C .

[0100] Figure 7B Depicting and Figure 7A A perspective view of an exemplary crosspoint memory array 750 with consistent memory cells. The memory array may include one or more levels of memory cells. This example includes two levels, namely a first level L1 and a second level L2. More than two levels may also be used. In this simplified example, there are four word lines WL0_1 to WL3_1 on L1, four bit lines BL0 to BL3 on L1 and L2, and four word lines WL0_2 to WL3_2 on L2. Therefore, the bit lines are shared by two adjacent levels. A row of memory cells is associated with each word line, and two columns of memory cells (each of the two columns) are associated with each bit line. See also Figure 9A and Figure 9B Regarding the position of the memory element relative to the selector, the orientation of the memory cell can be the same or different in each layer. That is, the memory cell can be reversed relative to L1 on L2, such that the polarity of the voltage and / or current operation of the bit line is the same for each layer. Alternatively, the memory cell can be oriented the same on both L1 and L2, thus selecting the bit line by taking L1 negative when selecting it for reading and writing P2AP, or taking L2 positive when selecting it for reading and writing P2AP; or reversing the voltage to write AP2P.

[0101] Word lines and bit lines comprise conductive materials such as tungsten or copper, any suitable metal, heavily doped semiconductor materials, conductive silicides, conductive silicide-germanide, or conductive germanide. In this example, the conductors are track-shaped, the word lines extend parallel to each other, and the bit lines extend parallel to each other and perpendicular to the word lines.

[0102] Each memory cell is located at the intersection of the corresponding word line and bit line. For example, memory cell 700 is located at the intersection of WL3_1 and BL3. In order to apply voltage across the memory cell, the control circuit applies voltage across WL3_1 and BL3.

[0103] The examples above illustrate cylindrical or columnar memory cells and track-shaped conductors. However, other options are possible.

[0104] Figures 8A to 8C It depicts current on a logarithmic scale and voltage on a linear scale.

[0105] Figure 8A Depicting Figure 7A An exemplary IV curve of the storage element 710. (As in conjunction with...) Figure 7A The discussion involves switching the bipolar switching memory element from HRS to LRS during AP2P write, for example, by applying a positive voltage across the memory element, and switching the bipolar switching memory element from LRS to HRS during P2AP write, for example, by applying a negative voltage across the memory element.

[0106] The IV curve is used for memory elements separate from the selector. The horizontal axis depicts Vwrite_AP2P, the voltage at which an AP2P write operation occurs, and Vwrite_P2AP, the voltage at which a P2AP write operation occurs. In this example, Vwrite_AP2P is greater than Vwrite_P2AP.

[0107] In an AP2P write operation, the memory element is initially in HRS. As the voltage increases from 0V to Vwrite_AP2P, the current increases, as depicted by curve 800. Figure 8A When a memory cell switches to a low resistance state (LRS), curve 801 depicts the increase in current during a write operation. Subsequently, as the voltage decreases towards 0V, the current also decreases, as depicted by curve 802. Figure 8A ).

[0108] In a P2AP write operation, the memory element is initially in LRS. As the voltage magnitude increases from 0V to Vwrite_P2AP, the current increases, as depicted in curve 803. Figure 8A When a memory cell switches to a high resistance state (HRS), curve 804 depicts the decrease in current during a write operation. Subsequently, as the voltage amplitude decreases toward 0V, the current also decreases, as depicted by curve 805.

[0109] Figure 8B Depicting Figure 7A An exemplary IV curve for selector 702. The IV curve is used for selectors separate from memory cells. The horizontal axis depicts the hold threshold voltage Vhold and the operating threshold voltage Vth. The positive and negative polarities of these voltages are depicted for write operations, which is consistent with... Figure 8A Consistent.

[0110] During an AP2P write operation, as the voltage increases from 0V to Vth, the current increases, as depicted in curve 810. When the voltage increases above Vth, the selector turns on and the current increases abruptly, as depicted in curve 811. Subsequently, curve 812 shows that the voltage can increase or decrease with only small changes in current. This depends on the resistance. In most cases, the current increases linearly with the voltage in the P state, but the AP resistance can decrease as the voltage increases. When the voltage increases above a certain level due to voltage compliance, the current can stop changing. When the AP2P write operation is complete, the voltage can decrease to Vhold, at which point the selector turns off, resulting in a sudden decrease in current (curve 813).

[0111] During an AP2P write operation, as the voltage amplitude increases from 0V to -Vth, the current increases, as depicted in curve 820. When the voltage amplitude increases above -Vth, the selector turns on and the current suddenly increases, as depicted in curve 821. Subsequently, curve 822 shows that the voltage can increase or decrease with only small current changes. When the write operation is complete, the voltage amplitude decreases to Vhold, at which point the selector turns off, resulting in a sudden decrease in current (curve 823).

[0112] Figure 8A Depicting Figure 7A An exemplary IV curve for memory cell 700. The memory cell includes a storage element connected in series with a selector. The state of the memory cell can be changed by turning on the selector and then applying a voltage and / or current designed to change the state of the selector.

[0113] Signals, including voltage and current, are not applied to the memory cells until the selector is turned on. The voltage can be increased after the selector is turned on to provide the appropriate read or write voltage across the memory cells.

[0114] In AP2P operation, as the voltage increases from 0V to Vth, the current increases, as depicted in curve 830. When the voltage increases above Vth, the selector turns on and the current suddenly increases, as depicted in curve 831. The voltage can be further increased to Vwrite_AP2P, as shown in curve 832, at which point a setting operation occurs, causing a sudden increase in current (curve 833). Subsequently, when the write operation is complete, curve 834 shows the voltage decreasing to Vhold, at which point the selector turns off, causing a sudden decrease in current (curve 835).

[0115] In an AP2P write operation, as the voltage increases from 0V to -Vth, the current increases, as depicted in curve 840. When the voltage increases above -Vth, the selector turns on and the current suddenly increases, as depicted in curve 841. The voltage can further increase to Vwrite_P2AP, as shown in curve 842, at which point a write operation occurs, causing the current to suddenly decrease (curve 843). Subsequently, when the write operation is complete, curve 844 shows that the voltage decreases to Vhold, at which point the selector turns off, causing the current to suddenly decrease (curve 845).

[0116] Figure 9A An exemplary circuitry 900 consistent with the first stage of the crosspoint memory array 750 is depicted. Word lines WL0_1 to WL3_1 are shown together with bit lines BL0 to BL3. There are sixteen exemplary memory cells arranged in four rows and four columns, with each row connected to a corresponding word line and each column connected to a corresponding bit line. Each memory cell may be a two-terminal device, with one terminal connected to a first wire and the other terminal connected to a second wire. The wires may be, for example, metal or doped silicon.

[0117] For example, memory cells M00_1, M01_1, M02_1, and M03_1 are connected to WL0_1 and BL0 to BL3, respectively; memory cells M10_1, M11_1, M12_1, and M13_1 are connected to WL1_1 and BL0 to BL3, respectively; memory cells M20_1, M21_1, M22_1, and M23_1 are connected to WL2_1 and BL0 to BL3, respectively; and memory cells M30_1, M31_1, M32_1, and M33_1 are connected to WL3_1 and BL0 to BL3, respectively. M30_1, connected to WL3_1 and BL0, is an exemplary selected memory cell as shown by the dashed line.

[0118] In one approach, each bit line and word line may be terminated in an open circuit as depicted by circular terminals including exemplary terminals 915 and 916 for BL0 and WL3_1, respectively.

[0119] Transistor pairs can be connected to each wire. For example, transistor pairs Wd0_1 to Wd3_1 are connected in series with word lines WL0_1 to WL3_1, respectively, and transistor pairs Bd0 to Bd3 are connected in series with bit lines BL0 to BL3, respectively. Wd0_1 to Wd3_1 can be used to select or deselect the corresponding word lines, and Bd0 to Bd3 can be used to select or deselect the corresponding bit lines. For example, Wd0_1 to Wd3_1 are word line decoder transistors and can be part of row control circuitry 520. For example, Bd0 to Bd3 are bit line decoder transistors and can be part of column control circuitry 510.

[0120] In one approach, each transistor decoder pair includes a pMOSFET (circled on the control gate) connected in parallel with an nMOSFET. For example, Wd0_1 to Wd3_1 include pMOSFETs 940-943 and nMOSFETs 944-947, respectively. Bd0 to Bd3 include nMOSFETs 960-963 and pMOSFETs 964-967, respectively. Transistor pairs for word lines can be connected to a common path 910, while transistor pairs for bit lines can be connected to a common path 920. The common path 910 can be connected, for example, to a WL driver 524a during a write operation. Figure 5B The common path 920 can be connected to the BL driver 513G. The common path can also be connected to the sensing circuit 564, for example, during a read operation. Figure 5A Alternatively, with one wire in the wiring driven at 0V or ground, the other wire can be connected to the sensing circuit 564 during the read operation.

[0121] To select the memory cell M30_1 for writing or reading, Wd3_1 and Bd0 can be provided in the ON state to apply voltage / current to the memory cell. Within transistor pair Wd3_1, one or both of transistors 943 and 947 can be provided in the ON state to connect voltage / current from path 910 to WL3_1 during a write operation, or to sense the voltage on WL3_1 via path 910 during a read operation. Similarly, within transistor pair Bd0, one or both of transistors 960 and 964 can be provided in the ON state to connect voltage / current from path 920 to BL0 during a write operation, or to sense the voltage on BL0 via path 920 during a read operation. Generally, for enhancement-mode transistors, the nMOSFET is ON when a positive gate-to-source voltage is applied, and the pMOSFET is ON when a negative gate-to-source voltage is applied, wherein in both cases, the magnitude of the gate-to-source voltage exceeds the transistor's Vth. See also Figure 10F to Figure 10F .

[0122] The circuit also includes isolation transistors connected to each word line and bit line. For example, WL0_1 through WL3_1 are connected to isolation standby transistors 930-933, respectively. The WL isolation transistors can be provided in the on-state to deliver an isolation standby voltage (e.g., 1.65V) to word lines not selected in write or read operations. In one approach, the WL isolation transistors may be nMOSFETs and have sources connected to a common voltage on path 920. For a selected word line, such as WL3_1, isolation transistor 933 is provided in the off-state to disconnect the isolation voltage from the word line. This allows drive voltage / current or sense voltage to pass through transistor pair Wd3_1 during write or read operations, respectively.

[0123] Similarly, BL0 through BL3 are connected to isolation transistors 950-953, respectively. The BL isolation transistors can be provided in the on-state to deliver an isolation voltage (e.g., 1.65V) to bit lines not selected during write or read operations. In one approach, the BL isolation transistors can be pMOSFETs with sources connected to a common voltage on path 921. The voltage of such path 921 can be the same as the voltage of path 920.

[0124] For the selected bit line BL0, an isolation transistor 950 is provided in a non-conducting state to disconnect the isolation voltage from the bit line. This allows the drive voltage / current or sense voltage to pass through the transistor pair Bd0 during write or read operations, respectively.

[0125] In one method, unselected memory nodes connected to both an unselected word line and an unselected bit line may be biased at their two terminals with equal positive voltages (isolation voltages) during a write operation to prevent unselected memory cells from being written to. An unselected memory cell is a memory cell not selected for a read or write operation. A selected memory cell is a memory cell selected for a read or write operation. The isolation voltage is sufficient to prevent unselected memory cells from being affected by write or read operations on selected memory cells; for example, near the average of the minimum and maximum voltages applied to either WL or BL during active operation, when a cell is not selected, the unselected cell does not have a voltage exceeding Vth (the selector) across its terminals.

[0126] The appropriate control gate voltage (Vcg) for the pMOSFET, nMOSFET, and isolation transistor pairs can be set in either the conducting or non-conducting state by the row decoder control circuit and the column decoder control circuit. Within each transistor pair, the control gate voltage can be controlled independently for the pMOSFET and nMOSFET. The control gate of the nMOSFET and pMOSFET can be controlled individually in each transistor pair, and each transistor can be used to select or deselect the path.

[0127] Figure 9B Depicting and Figure 9A and Figure 7B An exemplary circuit 990 consistent with the second stage of the crosspoint memory array 750. (As in conjunction with...) Figure 7B The bit lines BL0 to BL3 can be shared between the first and second levels of the memory cells. The word line decoder may have a similar arrangement to the first level. Word lines WL0_2 to WL3_2 are shown together with bit lines BL0 to BL3. There are sixteen exemplary memory cells. For example, memory cells M00_2, M01_2, M02_2, and M03_2 are connected to WL0_2 and connected to BL0 to BL3, respectively; memory cells M10_2, M11_2, M12_2, and M13_2 are connected to WL1_2 and connected to BL0 to BL3, respectively; memory cells M20_2, M21_2, M22_2, and M23_2 are connected to WL2_2 and connected to BL0 to BL3, respectively; and memory cells M30_2, M31_2, M32_2, and M33_2 are connected to WL3_2 and connected to BL0 to BL3, respectively. M30_2, connected to WL3_2 and BL0, is an exemplary selected memory cell as shown by the dashed line.

[0128] In one approach, each bit line and word line may be terminated in an open circuit as depicted by circular terminals including exemplary terminals 915a and 916a for BL0 and WL3_2, respectively.

[0129] Transistor pairs can be connected to each wire. For example, transistor pairs Wd0_2 to Wd3_2 are connected in series with word lines WL0_2 to WL3_2, respectively. Wd0_2 to Wd3_2 can be used to select or deselect the corresponding word line, and Bd0 to Bd3 can be used to select or deselect the corresponding bit line. For example, Wd0_2 to Wd3_2 are word line decoder transistors and can be part of the line control circuit 520.

[0130] In one approach, each transistor decoder pair includes a pMOSFET connected in parallel with an nMOSFET. For example, Wd0_2 to Wd3_2 each include pMOSFETs 980-983 and nMOSFETs 984-987. The transistor pairs of the word lines can be connected to a common path 910a. The common path 910a can be connected to the WL driver 524a. Figure 5B For example, it can provide a current source of approximately 30 μA in write operations for 20nm CD MRAM. Alternatively, the common path 910a can be connected to the sensing circuit 564. Figure 5A ), such as providing a current source of approximately 15 μA during read operations.

[0131] To select the memory cell M30_2 for writing or reading, Wd3_2 and Bd0 are provided in an on-state to apply voltage across the memory cell. Within transistor pair Wd3_2, one or both of transistors 983 and 987 can be provided in an on-state to connect voltage / current from path 910a to WL3_2 during a write operation, or to sense the voltage across WL3_2 via path 910a during a read operation. Similarly, within transistor pair Bd0 ( Figure 9A One or both of transistors 960 and 964 can be provided in the on state to connect voltage / current from path 920 to BL0 in a write operation, or to sense the voltage on BL0 at path 920 in a read operation.

[0132] Additionally, WL0_2 through WL3_2 are connected to isolation transistors 970-973, respectively. In one approach, the WL isolation transistors may be nMOSFETs with sources connected to a common voltage on path 920a. For a selected word line, such as WL3_2, isolation transistor 973 is provided in a non-conducting state to disconnect the isolation voltage from the word line. This allows the drive voltage / current or sense voltage to pass through transistor pair WL3_2 during write or read operations, respectively.

[0133] Transistor pairs connected to each wire (e.g., word line or bit line) provide optimized bidirectional write capability. As mentioned at the beginning, both writing and reading can be optimized by providing one or two transistors in the on state. Specifically, when selecting memory cells, a pMOSFET driven by a current source can be used to pull up (increase) the voltage of the first wire, such as WL3_1, to a positive voltage, while an nMOSFET (such as...) can be used... Figure 9AThe nMOSFET 960 in BD0 pulls down (reduces) the voltage of the second wire, such as BL0, to, for example, approximately 0V. This method minimizes capacitance when the selector is turned on using only one transistor in the decoder pair, where the pMOSFET is able to pull the node higher than the nMOSFET because Vth loss is avoided. However, when reading the selected memory cell after the selector is on and the WL voltage is low, in one option, the parallel nMOSFET of the first wire can also be used in parallel or alone. This nMOSFET adds resistance that offsets the reduced resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell. Thus, the amplitude of the voltage sensed by the sensing circuit is maintained (or increased if the nMOSFET is used alone). In another option, when reading the selected memory cell, the pMOSFET is off and the parallel nMOSFET is on. This increases the total resistance of the transistor pair, such that if the MRAM changes from LRS to HRS, the voltage sensed by the sensing circuit is amplified.

[0134] Figure 10A Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is on and the nMOSFET is off when the voltage on the selected word line WL3_1 is pulled up. For example, the pull-up of the word line voltage can occur during the selection process of the decoded bit selector or during the write process. In one method, such as in... Figure 5C In this process, a read current source pull-up voltage is used to select a bit, and a write current source pull-up voltage is used to write a bit; each of these processes utilizes a pMOSFET. Reading can also be performed using a pMOSFET. Alternatively, this can be achieved using both a pMOSFET and an nMOSFET that are both on, to improve the difference signal from the state-changing MRAM to the sense amplifier after a self-reference read (SRR) write. Alternatively, the signal can be further amplified by using an nMOSFET for reading simply by turning off the pMOSFET and turning on the nMOSFET after the selector is on.

[0135] exist Figures 10A to 10C In this configuration, transistor pair Wd3_1 includes a pMOSFET 943 and an nMOSFET 947 connected in parallel. Figures 10A to 10F In this diagram, the control gate, drain, and source of a pMOSFET are denoted as Gp, Dp, and Sp, respectively, while the control gate, drain, and source of an nMOSFET are denoted as Gn, Dn, and Sn, respectively. Furthermore, in some configurations, both pMOSFETs and nMOSFETs can function as pass gates.

[0136] The arrow from common path 910 through the pMOSFET to WL3_1 indicates the current direction from source (Sp) to drain (Dp). As mentioned, the pMOSFET is in the on state when a negative gate-to-source voltage exceeding the transistor's Vth is applied. This can be achieved, for example, by applying 0V to the gate (Gp) and a positive voltage (such as greater than 1V) to the source, assuming Vth is, for example, 1V. When the gate-to-source voltage does not exceed Vth, the nMOSFET is in the off state. This can be achieved, for example, by applying 0V to the gate.

[0137] Figure 10B Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is off and the nMOSFET is on when a voltage is sensed on the selected word line WL3_1. During sensing, the sensing circuit senses the voltage of WL3_1 via common path 910 and transistor pair Wd3_1, and specifically via nMOSFET 947 in this example. For example, the pMOSFET is turned off by applying 3.3V to the gate (Gp). For example, the nMOSFET is turned on by applying 3.3V to the gate (Gn). The arrow from WL3_1 through the nMOSFET to common path 910 indicates the current direction from drain (Dn) to source (Sn).

[0138] Figure 10C Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is turned on and the nMOSFET is turned on when a voltage is sensed on the selected word line WL3_1. During sensing, the sensing circuit senses the voltage of WL3_1 via common path 910 and transistor pair Wd3_1, and specifically via nMOSFET 947 and pMOSFET 943 in this example. For example, the pMOSFET is turned on by applying 0V to the gate (Gp). The voltage on Wd3_1 is a positive voltage at the source of the pMOSFET and is assumed to be high enough to provide |Vgs|>Vth. For example, the nMOSFET is turned on by applying 3.3V to the gate (Gn). The voltage on Wd3_1 is a positive voltage at the drain (Dn) of the nMOSFET and may be lower than the control gate voltage (Gn). In the case of two transistors in parallel, Dp is the same as Sn, and Sp is the same as Dn.

[0139] Figure 10D Depicting Figure 9AThe WL transistor pair Wd3_1 is configured such that the pMOSFET is off and the nMOSFET is on when the selected bit line BL0 (e.g., approximately 0V) is pulled down. For example, the pull-down of the bit line voltage can occur during the selection process of the decoded bit selector, or during the read or write operation of that bit. As mentioned above, the selection or write operation can be bidirectional. Therefore, in one direction, the word line is biased higher than the bit line, and in the opposite direction, the bit line is biased higher than the word line. For example, when the bit line is biased higher, it can be driven by the pMOSFET.

[0140] exist Figures 10D to 10F In this transistor pair Bd0, there are two transistors connected in parallel: a pMOSFET 964 and an nMOSFET 960.

[0141] The arrow from the common path 920 through the nMOSFET to BL0 indicates the current direction from the drain (Dn) to the source (Sn). This can be achieved, for example, by applying 3.3V to the gate of the nMOSFET. For example, the pMOSFET can be turned off by applying 3.3V to the gate.

[0142] Figure 10E Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is off and the nMOSFET is on during a sensing process in which the selected bit line BL0 is set to ground. During one option for sensing, the voltage of BL0 can be grounded at common path 920, for example, set to 0V. The pMOSFET is turned off, for example, by applying 3.3V to the gate, and the nMOSFET is turned on, for example, by applying 3.3V to the gate. The arrow from BL0 through the nMOSFET to common path 920 indicates the current direction from drain (Dn) to source (Sn).

[0143] Figure 10F Depicting Figure 9A The WL transistor pair Wd3_1 is configured such that the pMOSFET is turned on and the nMOSFET is turned on during a sensing process in which the selected bit line BL0 is set to ground. In this option, the pMOSFET is turned on, for example, by applying 0V to the gate, and the nMOSFET is turned on, for example, by applying 3.3V to the gate.

[0144] Figure 11A Describes the use of selected memory cells such as Figure 7AA flowchart of an exemplary process for performing a write operation on memory cell 700. Step 1000 includes driving current via a top wire to set a memory cell in the memory array to the LRS (P) state. Repeating this operation at all memory locations will put all bits in the LRS state. In this method, all memory cells in the memory array are in the same known state. In one method, the bottom wire may be set to a fixed voltage. Step 1001 includes receiving data to be stored in the memory array. For example, the data may be received via a communication interface. Step 1002 includes identifying memory cells to be programmed to the HRS (AP) state based on the data. For example, these may be bits intended to store 1 bit. Step 1003 includes driving current via a bottom wire to select the identified memory cell and program it from the P state to the AP state. In one method, the top wire may be set to a fixed voltage. The top wire and bottom wire involved are related to Figure 7A The memory cell configurations are consistent. See also: Figure 13A and Figure 13B .

[0145] Figure 11B Describes the use of selected memory cells such as Figure 7A A flowchart illustrating an exemplary process by which the memory cell 700 performs a read operation using a single voltage detection. This process can be applied to, for example... Figure 7B L1 or L2. Step 1010 involves initiating the operation of a selector for decoding and turning on the memory cell. A first wire may be connected to a first terminal of the memory cell and connected to a first transistor pair, and a second wire may be connected to a second terminal of the memory cell and connected to a second transistor pair. For example, in Figure 9A In this context, M30_1 is the selected memory cell in L1, the first wire is WL3_1 connected to the first transistor pair Wd3_1, and the second wire is BL0 connected to the second transistor pair Bd0. For example, in... Figure 9B In the L2, M30_2 is the selected memory cell, the first wire is BL0 and is connected to the first transistor pair Bd0, and the second wire is WL3_2 and is connected to the second transistor pair Wd3_2.

[0146] Step 1011 includes selecting a memory cell by pulling up the voltage of the first wire using the pMOSFET of the first transistor pair when the nMOSFET of the first transistor pair is in a non-conducting state and by pulling down the voltage of the second wire using the nMOSFET of the second transistor pair when the pMOSFET of the second transistor pair is in a non-conducting state. Pulling up the voltage of the first wire may involve applying a voltage such as... Figure 13C and Figure 13DThe current Iread is depicted. Pulling down the voltage of the second conductor can involve driving the second conductor to near 0V. This selection can switch the selector of the memory cell from a non-conducting state to a conducting state, as described above. For example, with Figure 8C Consistent, it allows applying a voltage increasing from 0V to Vth (the selector) across memory cells. See also Figure 13C and Figure 13D At t1-t2. Select step 1011 to use a read current source to provide the required voltage and current on the word line and bit line.

[0147] Generally, compared to using the pull-up voltage of an nMOSFET, an MRAM crosspoint array can be selected over a wider selector Vth range by using the pull-up voltage of a pMOSFET, because a pMOSFET can be pulled up close to the positive supply, while an nMOSFET can be pulled up to the positive supply minus its Vth, with a loss range of approximately 1V. If the memory cells have the same orientation in each layer, the pull-up voltage can be the first wire below the first level of the memory cell, and the pull-down voltage can be the second wire above the first level of the memory cell. When an overvoltage is discharged through the memory element, the selector switching causes a transient voltage across the memory cell. The internal series resistance of the memory cell is approximately 20kΩ. The overvoltage is Vth - Vhold, which can be reduced if Vhold increases or if the capacitance and Vth decrease. To minimize the risk of memory element state reversal due to the energy of the overvoltage, the transient duration should be minimized by reducing the capacitance.

[0148] like Figure 7B As shown, bit lines tend to have greater capacitance due to their longer length and placement between two layers, so dissipation time is primarily determined by word line capacitance. Discharge time and read latency can be reduced by decreasing capacitance. One option is to shorten the length and increase the tile line pitch. Another option is to reduce the size of the transistors used to drive the tile lines. Another option is to choose word lines with nMOSFETs and higher-capacitance bit lines with pMOSFETs, since for equivalent drive, the nMOSFETs on the word line can be as small as one-third. By avoiding losses in the drive transistor's Vth, the widest range of permissible Vth for a given power supply can be allowed by using pMOSFETs to pull high and nMOSFETs to pull low. However, these methods have problems. For example, the fabrication of multi-level memory devices is simplified if each memory cell has the same orientation. In this case, one of these levels must use a pMOSFET to pull the word line high, and the other levels must use an nMOSFET to pull the word line low to obtain a higher permissible Vth (selector).

[0149] Selecting using a single nMOSFET or pMOSFET reduces capacitance and allows for a higher Vth, but reduces the signal difference when the memory element changes state. For example, if a memory cell has a resistance of 25kΩ in LRS and 50kΩ in HRS, and the read current Iread is 15μA, the voltage across the memory cell is 375mV in LRS and 750mV in HRS. This results in a signal difference of 375mV across the MRAM between the two states. However, because the voltage at the sensing circuit increases when the memory cell is in HRS, the drain-to-source resistance Rds of the MOSFET decreases from a larger Von. Therefore, the signal difference can be reduced to, for example, 250mV-300mV, making it more difficult to detect changes in the memory cell's state during reads.

[0150] Two options are provided for optimizing the signal at the sensing circuit. The first option (step 1012a) involves using a pMOSFET (e.g., on stage 1) to select a selector with only one transistor for reducing capacitance, allowing a higher Vth, and then turning on the available nMOSFET during readout while keeping the pMOSFET on. In this case, during readout, the increased Von of the pMOSFET is offset by the decreased Von of the nMOSFET, such that the total resistance remains approximately constant and approximately the full signal difference is passed to the sensing circuit.

[0151] The second option (step 1012b) involves using a pMOSFET on stage 1 to select a selector with only one transistor for reducing capacitance, allowing a higher Vth, and then turning on the available nMOSFET during the read operation while turning off the pMOSFET after the selector is turned on, thus using only one transistor for selection to reduce capacitance during the turn-on period. The pMOSFET is selected to allow a wider range of Vth (selector) during selection. Then, after selection, it is switched to an nMOSFET used only for reading and level storage during the first read of the SRR. The higher resistance of the nMOSFET causes a higher signal at the sensing circuit. This method is suitable when the resistance-area (RA) product of the memory cell is relatively low (e.g., five or lower). If RA is relatively high (e.g., or greater), the signal at the sensing circuit may become too high, exceeding the range of the sensing circuit or the power supply. In this case, turning both on may be preferred.

[0152] In the first option, step 1012a includes changing the nMOSFET to an on state and keeping the pMOSFET on state in the first transistor pair. In one method, after the selection of a memory cell and during preparation for reading the memory cell, the control circuit is configured to change the nMOSFET from a non-on state to an on state and keep the pMOSFET on state.

[0153] In the second option, step 1012b includes, in the first transistor pair, changing the pMOSFET to a non-conducting state and keeping the nMOSFET on state after the selector is turned on. For consistency, the same options should be used for the first and second reads before and after the destructive write to the SRR. In one method, after the memory cell is selected and while preparing to read the memory cell, the control circuit is configured to change the pMOSFET from an on state to a non-conducting state and turn the nMOSFET on state.

[0154] Common step 1013 includes detecting the voltage Vread on the first wire via the first transistor and comparing it with a reference voltage Vref. See also Figure 12A An exemplary sensing circuit. See also: Figure 13C and Figure 13D At t2-t3.

[0155] Figure 11C Describes the use of selected memory cells such as Figure 7A The flowchart illustrates an exemplary process in which the memory cell 700 performs a read operation using dual voltage detection. Steps 1100, 1101, 1102a, and 1102b correspond to... Figure 11B Steps 1010, 1011, 1012a, and 1012b. See also... Figure 13E and 13F The selection in step 1101 occurs at t1-t2.

[0156] The first option involves steps 1102a, 1104a, and 1106a, while the second option involves steps 1102b, 1104b, and 1106b.

[0157] In this dual-voltage sensing method, a first voltage is detected at step 1103, and a second voltage is detected at step 1107. Specifically, common step 1103 includes detecting and storing the first voltage on the first wire via a first transistor pair. For example, the first voltage Vread1 can be stored... Figure 12B In the first capacitor C1 of the sensing circuit. See also Figure 13E and Figure 13F At t2-t3.

[0158] In the first option, step 1104a includes changing the nMOSFET to a non-conducting state and keeping the pMOSFET on in the first transistor pair. In one method, after the detection of a first voltage and in preparation for a potentially destructive write to a memory cell, the control circuit is configured to change the nMOSFET from an on state to a non-conducting state and keep the pMOSFET on.

[0159] In the second option, step 1104b includes changing the nMOSFET to a non-conducting state and keeping the pMOSFET in a conducting state in the first transistor pair. In one method, after the detection of the first voltage and in preparation for a potentially destructive write to the memory cell, the control circuit is configured to change the nMOSFET from a non-conducting state to a conducting state and keep the pMOSFET in a conducting state.

[0160] Common step 1105 includes performing a potentially destructive write to the memory cell via the first transistor. This write operation ensures the memory cell is in HRS (Higher Responsibility State). If the memory cell is already in HRS, the write is non-destructive. However, if the memory cell is in LRS (Low Responsibility State), the write is destructive because it alters the data state of the memory cell. See also: Figure 13E And at t3-t5 in Figure 13F.

[0161] In the first option, step 1106a includes changing the nMOSFET to an on state and keeping the pMOSFET on state in the first transistor pair. In one method, after a potentially destructive write to a memory cell and while preparing for detection of a second voltage, the control circuit is configured to change the nMOSFET from a non-on state to an on state and keep the pMOSFET on state.

[0162] In the second option, step 1106b includes changing the pMOSFET to a non-conducting state and keeping the nMOSFET on in the first transistor pair. In one method, after a potentially destructive write to a memory cell and while preparing for detection of a second voltage, the control circuit is configured to change the pMOSFET from an on state to a non-conducting state and keep the nMOSFET on.

[0163] Common step 1107 includes detecting a second voltage (Vread2) on the first wire via the first transistor pair. For example, the second voltage can be provided to... Figure 12B The inverting input (-) of the comparator 1201 in the sensing circuit.

[0164] Common step 1108 includes determining whether the second voltage exceeds the first voltage by a specified amount. In one approach, a second capacitor C2 stores an offset voltage Voffset, which can be added to Vread1 by connecting C1 and C2 in series using switch 1202. The combined input Vread1 + Voffset is then provided to the non-inverting input of a comparator for comparison with Vread2. In step 1105, by adding the offset voltage, it is possible to more reliably determine whether a memory cell has switched from LRS to HRS.

[0165] Based on step 1108, proceed to step 1109a or 1109b. Step 1109a deduces that the memory cell stores a low-resistance data state when the second voltage exceeds the first voltage by a specified amount, and step 1109b deduces that the memory cell stores a high-resistance data state when the second voltage does not exceed the first voltage by a specified amount. Step 1110 describes the write-back process after step 1109a, wherein memory cells whose states have been altered due to the destructive write process are restored to their initial states. See also... Figure 13G and Figure 13H .

[0166] Figure 12A Depicting Figure 7B and Figure 11B An exemplary implementation of the sensing circuit 564, consistent with the process, is provided. The sensing circuit includes a comparator 1201. When switch 1210 is closed, a reference voltage Vref is provided to the inverting input, and a detection voltage Vread on the common path 1204 is provided to the non-inverting input. Vref can be set to a level between the expected voltage V_LRS of the LRS memory cell and the expected voltage V_HRS of the HRS memory cell. Therefore, the output of the comparator indicates the data state of the memory cell.

[0167] Figure 12B Depicting Figure 7B and Figure 11C Another exemplary implementation of the process-consistent sensing circuit 564. (See also: [link to example implementation]). Figure 11CThe sensing circuit may include a first capacitor C1 storing a first voltage Vread1 on the selected memory cell and a second capacitor C2 storing an offset voltage Voffset. In one example, Vread1 is 375mV in LRS and 750mV in HRS, and Voffset is 100mV-150mV. Before sensing, C1 can be charged to Voffset by applying the corresponding voltages across nodes 1207 and 1208 and closing switches 1205 and 1206 (making them conduct). These switches can then be opened (making them de-conducting) to maintain Voffset in C2.

[0168] Node 1204 can be connected to Figure 9A The common path 910. During sensing, the common path is connected to a selected word line, such as WL3_1, via transistor pair Wd3_1. This allows the voltage of the word line to be delivered to node 1204. Switch 1203 is closed while switch 1202 is open to provide Vread1 across C1. Subsequently, switch 1203 is opened to disconnect C1 from the word line. Then, switch 1202 is closed to provide C2 in series with C1. In one approach, C2 is connected to the non-inverting input of comparator 1201. To obtain Vread2, switch 1209 is closed while switch 1203 is open to connect node 1204 to the inverting input of the comparator. Alternatively, a capacitor may be connected to the same end of the capacitor associated with the stored level voltage. For example, if SRR is P2AP, when the capacitor is used in the sense amplifier, the other end of the capacitor can be driven positive to boost the voltage of stage 1 by approximately 150mV. Alternatively, for example, if the SRR is P2AP, the other terminal of the capacitor can be driven negative to shift the storage voltage of stage 1 by -150mV. Alternatively, if the SRR is AP2P, the slab direction can be reversed.

[0169] Figure 12C Depicting and Figure 9AAn exemplary parallel resistance is provided for the pMOSFET and nMOSFET of the consistent transistor pair Wd3_1. When the pMOSFET and nMOSFET are in the ON state, they have resistances Rp and Rn, respectively, and the total resistance Rt of the transistor pair is defined as: 1 / Rt = 1 / Rp + 1 / Rn. As described above, in the first option, when both transistors are in the ON state, the decreased resistance Rp of the pMOSFET (indicated by the down arrow) can be canceled out by the increased resistance Rn of the nMOSFET (indicated by the up arrow). This preserves the signal amplitude. In the second option, which increases the signal amplitude, when the pMOSFET is in the OFF state and the nMOSFET is in the ON state, the decreased resistance Rp of the pMOSFET is replaced by the increased resistance Rn of the nMOSFET. Therefore, when the nMOSFET is in the ON state, the decreased resistance of the pMOSFET caused by the selection of the memory cell is canceled out by the resistance of the nMOSFET. Additionally, when the nMOSFET is in the ON state, the decreased resistance of the pMOSFET caused by the selection of the memory cell is replaced by the resistance of the nMOSFET.

[0170] Figure 13A Describes the relationship between memory cells and Figure 11A An exemplary current versus time curve consistent with the writing process. Figure 13B Describes the relationship between memory cells and Figure 13A A consistent voltage versus time exemplary curve. Memory cell selection occurs between t1 and t2. Consistent with step 1000, a current Iread is driven on one of the wires until the selector resistor switches to a lower level at t2. At this point, if the memory cell is in LRS, the voltage drops to the level of curve 1300. Alternatively, if the memory cell is in HRS, the voltage is maintained at the level of curve 1301. If a write operation is required, the selection process can be performed using the write current; however, bit endurance can be improved by always using the read current for selection and then increasing the current to the write current. The LRS memory cell switches to HRS at t3, and the process ends at t4.

[0171] Figure 13C Describes the relationship between memory cells and Figure 11B An exemplary current versus time curve consistent with the reading process. Figure 13D Describes the relationship between memory cells and Figure 13CA consistent voltage versus time exemplary curve. Memory cell selection occurs between t1 and t2. Consistent with step 1011, a current Iread is driven on one of the wires, lower than Iwrite, until the selector resistor switches to a lower level at t2. At this point, the voltage drops to a certain level based on whether the memory cell is in LRS or HRS and based on the configuration of the transistor pair. Specifically, for LRS, voltages of curves 1305, 1305a, and 1305b are obtained if only the pMOSFET is on, both the nMOSFET and pMOSFET are on, or only the nMOSFET is on. For HRS, voltages of curves 1306, 1306a, and 1306b are obtained if only the pMOSFET is on, both the nMOSFET and pMOSFET are on, or only the nMOSFET is on. Consistent with step 1013, voltage Vread detection occurs between t2 and t3, and the process ends at t3.

[0172] Figure 13E Describes the relationship between memory cells and Figure 11C The process (steps 1100 to 1108) is consistent with the exemplary current versus time curve. Figure 13F Describes the relationship between memory cells and Figure 13E An exemplary voltage versus time curve. Memory cell selection occurs between t1 and t2. During this period, the memory cell is driven with a fixed current (called Iread) of, for example, 15 μA, while the voltage ramps up to, for example, Vth = 3V to select the memory cell. At t2, the selector changes from its non-conducting state to its lower-resistance on state, causing the voltage to drop toward Vhold (selector). Between t2 and t3, if the memory cell is in HRS (AP state) or LRS (P state), the curves represent the voltages across the memory cell, V_HRS or V_LRS. Specifically, for LRS, the voltages obtained are curves 1311, 1311a, and 1311b if only the pMOSFET is on, both the nMOSFET and pMOSFET are on, or only the nMOSFET is on. For HRS, the voltages obtained are curves 1310, 1310a, and 1310b if only the pMOSFET is on, both the nMOSFET and pMOSFET are on, or only the nMOSFET is on. Vread1 can be detected from t2 to t3.

[0173] From t3 to t5, a potentially destructive write is performed by driving a higher fixed current Iwrite (e.g., 30 μA). From t3 to t4, curve 1312 represents the memory cell in HRS, and curve 1313 represents the memory cell in LRS. At t4, memory cells in LRS switch to HRS during the destructive write, or memory cells in HRS remain in HRS. From t5 to t6, the current decreases to Iread, and Vread2 is obtained for comparison with Vread1. Specifically, the voltages of curves 1320, 1320a, and 1320b are obtained if only the pMOSFET is on, both the nMOSFET and pMOSFET are on, or only the nMOSFET is on. The data state of the memory cell is determined at t6, which is accomplished by comparing the level at t6 with the level stored during the first read and increasing it by 150 mV (Voffset).

[0174] Figure 13G Describes the relationship between memory cells and Figure 11C An exemplary current versus time curve consistent with the write-back process (step 1110). Figure 13H Describes the relationship between memory cells and Figure 13G An exemplary voltage versus time curve. A current Iwrite passes through the memory cell and may have an amplitude of, for example, 30 μA. This current is driven to perform an AP2P write to a target cell in the AP state. At t1-t2, Iwrite is applied, and the voltage ramps up from 0V to, for example, -3V to select the memory cell, and the voltage remains at -3V from t2 to t3. -3V may be the Vth of the selector. At t3, the AP-state cell switches to the P state, causing the voltage amplitude to drop. The process ends at t4.

[0175] In one method, the apparatus includes: a control circuit configured to be connected to a crosspoint memory array, the crosspoint memory array including memory cells and a first transistor pair, the memory cells being disposed between a first conductor and a second conductor and including a storage element connected in series with a threshold switch selector, the first transistor pair including a pMOSFET and an nMOSFET connected in parallel and connected to the first conductor; the control circuit being configured to select a memory cell by using a voltage pulled up to the first conductor by the pMOSFET when the nMOSFET is in a non-conducting state; and the control circuit being configured to subsequently read the memory cell when the pMOSFET is in a non-conducting state and the nMOSFET is in a conducting state.

[0176] In another method, the method includes: switching a threshold switch selector of a memory cell from a high-resistance state to a low-resistance state, wherein a first wire is connected to a first terminal of the memory cell and a second wire is connected to a second terminal of the memory cell, and a first transistor pair including a pMOSFET and an nMOSFET connected in parallel is connected to the first wire, the switching including setting the voltage of the first wire using the pMOSFET while keeping the nMOSFET in a non-conducting state; and when the threshold switch selector is in the low-resistance state, sensing a first voltage on the first wire via the first transistor pair when the pMOSFET is in a non-conducting state and the nMOSFET is in a conducting state.

[0177] In another method, the apparatus includes: a crosspoint memory array including memory cells, each memory cell including an MRAM connected in series with a threshold switch selector; a first conductor connected to a first terminal of the memory cell; a second conductor connected to a second terminal of the memory cell; a first transistor pair including a pMOSFET and an nMOSFET connected in parallel and connected to the first conductor; a second transistor pair including a pMOSFET and an nMOSFET connected in parallel and connected to the second conductor; and control circuitry configured to pull up a voltage on the first conductor via the pMOSFET of the first transistor pair instead of the nMOSFET and pull down a voltage on the second conductor via the nMOSFET of the second transistor pair instead of the pMOSFET to select the memory cell, and the control circuitry configured to first sense a voltage on the first conductor via the nMOSFET of the first transistor pair instead of the pMOSFET to read the memory cell.

[0178] The specific embodiments of the invention described above have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The methods described were chosen to best elucidate the principles of the invention and its practical application, thereby enabling others skilled in the art to optimally use the invention in various ways with various modifications suitable for the contemplated particular purpose. The scope of the invention is intended to be defined by the appended claims.

Claims

1. An apparatus for reading memory cells, comprising: A control circuit configured to be connected to a crosspoint memory array, the crosspoint memory array including memory cells and a first transistor pair, the memory cells being disposed between a first wire and a second wire and including a storage element connected in series with a threshold switch selector, the first transistor pair including a pMOSFET and an nMOSFET connected in parallel and connected to the first wire; The control circuit is configured to select the memory cell for a read operation by using the voltage of the first wire pulled up by the pMOSFET when the nMOSFET is in a non-conducting state. and The control circuit is configured to subsequently read the memory cell during the read operation when the pMOSFET is in a non-conducting state and the nMOSFET is in a conducting state.

2. The apparatus according to claim 1, wherein: When the nMOSFET is in the ON state, the reduced resistance of the pMOSFET caused by selecting the memory cell is replaced by the resistance of the nMOSFET.

3. The apparatus according to claim 1, wherein: The control circuit is configured to detect the voltage on the first wire via the first transistor pair to read the memory cell when the pMOSFET is in a non-conducting state and the nMOSFET is in a conducting state.

4. The apparatus according to claim 1, wherein: Following the selection of the memory cell and when ready to read the memory cell, the control circuit is configured to change the nMOSFET from a non-conducting state to a conducting state and the pMOSFET from a conducting state to a non-conducting state.

5. The apparatus of claim 1, wherein, in order to read the memory unit, the control circuit is configured to: Before performing a potentially destructive write to the memory cell, a first voltage on the first wire is detected via the first transistor pair when the pMOSFET is in a non-conducting state and the nMOSFET is in a conducting state; After the potentially destructive write to the memory cell is performed, a second voltage on the first wire is detected via the first transistor pair when the pMOSFET is in a non-conducting state and the nMOSFET is in a conducting state. as well as The data state of the memory cell is determined based on the first voltage and the second voltage.

6. The apparatus according to claim 5, wherein: Following the detection of the first voltage and in preparation for the potentially destructive write to the memory cell, the control circuit is configured to change the nMOSFET from an on state to an off state and the pMOSFET from an off state to an on state.

7. The apparatus according to claim 5, wherein: After the potentially destructive write to the memory cell and during the detection of the second voltage, the control circuit is configured to change the nMOSFET from a non-conducting state to a conducting state and the pMOSFET from a conducting state to a non-conducting state.

8. The apparatus according to claim 5, wherein: The control circuit is configured to keep the pMOSFET in the on state and the nMOSFET in the off state during the potentially destructive write to the memory cell.

9. The apparatus according to claim 5, wherein: The control circuit is configured to determine the data state as a low-resistance data state when the second voltage exceeds the first voltage by a specified amount, and to determine the data state as a high-resistance data state when the second voltage does not exceed the first voltage by a specified amount.

10. The apparatus of claim 5, wherein the control circuit comprises: A first capacitor, configured to store the first voltage; A second capacitor, configured to store an offset voltage; A switch configured to connect the first capacitor and the second capacitor in series; and A comparator configured to compare the second voltage with the voltage across the first and second capacitors connected in series.

11. The apparatus according to claim 1, further comprising: A second transistor pair, comprising a pMOSFET and an nMOSFET connected in parallel and configured to connect the second wire to the control circuit, wherein the control circuit is configured to select the memory cell by pulling down the voltage of the second wire using the nMOSFET of the second transistor pair when the pMOSFET of the second transistor pair is in a non-conducting state.

12. A method for a storage device, comprising: Switching a threshold switch selector of a memory cell from a high-resistance state to a low-resistance state, wherein a first wire is connected to a first terminal of the memory cell and a second wire is connected to a second terminal of the memory cell, and a first transistor pair including a pMOSFET and an nMOSFET connected in parallel is connected to the first wire, the switching including setting the voltage of the first wire using the pMOSFET while keeping the nMOSFET in a non-conducting state; as well as When the threshold switch selector remains in the low resistance state caused by the switching, a first voltage on the first wire is sensed via the first transistor pair when the pMOSFET is in the off state and the nMOSFET is in the on state.

13. The method of claim 12, further comprising: After sensing the first voltage, a potentially destructive write to the memory cell is performed to ensure that the memory cell is in a high-resistance state; After the potentially destructive write is performed, a second voltage on the first wire is sensed via the first transistor pair when the pMOSFET is in a non-conducting state and the nMOSFET is in a conducting state; as well as The first voltage is compared with the second voltage.

14. The method of claim 12, further comprising: After the first voltage is sensed, a potentially destructive write to the memory cell is performed to ensure that the memory cell is in a high-resistance state; After the potentially destructive write is performed, a second voltage on the first wire is sensed via the first transistor pair when the pMOSFET is in a non-conducting state and the nMOSFET is in a conducting state; as well as The sum of the first voltage and the second voltage is compared.

15. The method of claim 14, further comprising: After the first voltage is sensed and before the potentially destructive write to the memory cell, the nMOSFET is changed from an on state to an off state and the pMOSFET is changed from an off state to an on state. as well as After the potentially destructive write to the memory cell and before the sensing of the second voltage, the nMOSFET is changed from a non-conducting state to a conducting state and the pMOSFET is changed from a conducting state to a non-conducting state.

16. A storage device, comprising: A crosspoint memory array, the crosspoint memory array including memory cells, the memory cells including MRAM connected in series with a threshold switch selector; A first wire is connected to a first end of the memory cell; A second wire is connected to a second end of the memory cell; The first transistor pair includes a pMOSFET and an nMOSFET connected in parallel and is connected to the first wire; The second transistor pair includes a pMOSFET and an nMOSFET connected in parallel and is connected to the second wire; and A control circuit, wherein the control circuit is configured to pull up the voltage of the first wire via the pMOSFET of the first transistor pair instead of the nMOSFET and pull down the voltage of the second wire via the nMOSFET of the second transistor pair instead of the pMOSFET to select the memory cell, and the control circuit is configured to sense the voltage of the first wire for the first time via the nMOSFET of the first transistor pair instead of the pMOSFET to read the memory cell.

17. The storage device according to claim 16, wherein: In order to sense the voltage of the first conductor for the first time, the control circuit is configured to pull down the voltage of the second conductor.

18. The storage device according to claim 16, wherein: In order to read the memory cell, the control circuit is configured to sense the voltage of the first wire a second time via the nMOSFET of the first transistor pair instead of the pMOSFET, and to perform a potentially destructive write to the memory cell after the first time and before the second time.

19. The storage device according to claim 18, wherein: In order to perform the potentially destructive write to the memory cell, the control circuit is configured to pull up the voltage of the first wire via the pMOSFET of the first transistor pair instead of the nMOSFET.

20. The storage device according to claim 18, wherein: In order to read the memory cell, the control circuit is configured to determine whether the voltage of the first wire has increased by more than a specified amount due to the potentially destructive write.

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