Electrostatic discharge protection circuit and semiconductor circuit

Abstract

The present invention provides an electrostatic discharge protection circuit and a semiconductor circuit for a semiconductor element. The semiconductor element has a first drain / source electrode and a second drain / source electrode, and is surrounded by a deep well. The electrostatic discharge protection circuit includes a control circuit and a discharge circuit. The control circuit is electrically connected between the first drain / source electrode and the power supply terminal, has a control terminal electrically connected to the deep well, and generates a control signal. The discharge circuit is electrically connected between the first drain / source electrode and the power supply terminal and is controlled by the control signal. When an electrostatic discharge event occurs on the first drain / source electrode, the control circuit generates a control signal according to the potential state of the deep well and the potential state of the first drain / source electrode, and the discharge circuit provides a discharge path between the first drain / source electrode and the power supply terminal according to the control signal. The electrostatic discharge protection circuit provided by the present invention does not have a capacitor-resistor circuit used in the prior art, and thus occupies a smaller area.

Description

Technical Field

[0001] The present invention relates to a semiconductor circuit, and more particularly to an electrostatic discharge protection circuit. Background Art

[0002] With the development of semiconductor processes for integrated circuits, the size of semiconductor elements has been reduced to the sub-micron stage to improve the performance and computing speed of integrated circuits. However, the reduction in element size has led to some reliability problems, especially the most significant impact on the electrostatic discharge (ESD) protection ability of integrated circuits. When the element size is reduced due to advanced process technologies, the ESD protection ability is also greatly reduced, resulting in a significant reduction in the ESD tolerance of the elements. Therefore, an electrostatic discharge protection circuit is needed to protect the elements from being damaged by electrostatic discharge. However, traditional electrostatic discharge protection circuits include a capacitor-resistor circuit, which occupies a large area and is not conducive to the miniaturization of integrated circuit size. Summary of the Invention

[0003] An embodiment of the present invention provides an electrostatic discharge protection circuit for use in a semiconductor element. The semiconductor element has a first drain / source electrode and a second drain / source electrode and is surrounded by a deep well. The electrostatic discharge protection circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain / source electrode of the semiconductor element and a power supply terminal and has a first control terminal. The first control terminal is electrically connected to the deep well, and the first control circuit generates a first control signal. The first discharge circuit is electrically connected between the first drain / source electrode and the power supply terminal and is controlled by the first control signal. When an electrostatic discharge event occurs on the first drain / source electrode, the first control circuit generates a first control signal based on the potential state of the deep well and the potential state of the first drain / source electrode, and the first discharge circuit provides a first discharge path between the first drain / source electrode and the power supply terminal according to the first control signal.

[0004] An embodiment of the present invention provides a semiconductor circuit. The semiconductor circuit includes a semiconductor element, a first control circuit, and a first discharge circuit. The semiconductor element is formed in a well and has a first drain / source electrode and a second drain / source electrode. The well is surrounded by a deep well. The well has a first conductivity type, and the deep well has a second conductivity type different from the first conductivity type. The electrostatic discharge protection circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain / source electrode and a power supply terminal and has a first control terminal. The first control terminal is electrically connected to the deep well, and the first control circuit generates a first control signal. The first discharge circuit is electrically connected between the first drain / source electrode and the power supply terminal and is controlled by the first control signal. When an electrostatic discharge event occurs on the first drain / source electrode, the first control circuit generates the first control signal according to a potential state of the deep well and a potential state of the first drain / source electrode, and the first discharge circuit provides a first discharge path between the first drain / source electrode and the power supply terminal according to the first control signal. Description of the Drawings

[0005] Figure 1A Shows a semiconductor circuit according to an embodiment of the present invention.

[0006] Figure 1B Shows a semiconductor circuit according to another embodiment of the present invention.

[0007] Figure 2A Shows a structural cross-sectional view of a transistor according to an embodiment of the present invention.

[0008] Figure 2B Shows a structural cross-sectional view of a transistor according to another embodiment of the present invention.

[0009] Figure 3 Shows a semiconductor circuit according to another embodiment of the present invention.

[0010] Reference Numerals:

[0011] 1: Semiconductor Circuit

[0012] 10: Semiconductor Element

[0013] 11: Electrostatic Discharge Protection Circuit

[0014] 12, 13: Diodes

[0015] 20: Substrate

[0016] 21: N-Type Deep Well

[0017] 22: P-Type Well

[0018] 23: N-Type Doped Region (Drain Region)

[0019] 24: N-type doped region (source region)

[0020] 25: N-type doped region

[0021] 26: Gate dielectric layer

[0022] 27: Gate layer

[0023] 28: N-type doped region

[0024] 110, 110’: Control circuit

[0025] 111, 111’: Discharge circuit

[0026] 112: Inverter

[0027] 113: Control circuit

[0028] 114: Discharge circuit

[0029] 115, 300: Inverter

[0030] CE20, CE21: Contact electrode

[0031] D: Drain electrode

[0032] G: Gate electrode

[0033] GND: Ground voltage

[0034] L21: Boundary

[0035] N110, N111, N113, N114, N300: N-type transistor

[0036] ND10, ND11: Node

[0037] P110, P113, P300, P301: P-type transistor

[0038] S: Source electrode

[0039] S10, S10', S11: Control signal

[0040] T10: Power supply terminal

[0041] T11, T14: Control terminal

[0042] T12, T15, T30: Input terminal

[0043] T13, T16, T31: Output terminal

[0044] VDD: High operating voltage

[0045] VSS: Low operating voltage Detailed Embodiment

[0046] To make the above objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is specifically given below, and detailed descriptions are provided in conjunction with the accompanying drawings as follows.

[0047] Figure 1A It shows a semiconductor circuit according to an embodiment of the present invention. Refer to Figure 1A , the semiconductor circuit 1 includes a semiconductor element 10, an electrostatic discharge protection circuit 11, and diodes 12-13. In Figure 1A the embodiment, the semiconductor element 10 is an N-type transistor, which has a gate electrode G, a drain electrode D, and a source electrode S. In the following text, the transistor will be used as an example of the semiconductor element 10 to illustrate each embodiment. Figure 2A It shows a cross-sectional view of the structure of the transistor 10.

[0048] Refer to Figure 2A , the transistor 10 is formed on a substrate 20, where the conductive type of the substrate 20 is P-type. An N-type deep well 21 is formed in the substrate 20, where L21 represents the boundary between the N-type deep well 21 and the substrate 20. In the deep well 21, a P-type well 22 and an N-type doped region 25 are formed. Two N-type doped regions 23 and 24 are formed in the well 22, and a gate dielectric layer 26 is formed on the substrate 20 and between the doped regions 23 and 24. In this embodiment, the position where the N-type doped region 25 is formed in the deep well 21 is close to the N-type doped region 23. A gate layer 27 is formed on the gate dielectric layer 26, where the gate layer 27 is a metal layer or a polysilicon layer. The doped regions 23 and 24 and the gate layer 27 form the transistor 10. As Figure 1A and Figure 2A shown, the doped region 23 serves as the drain region of the transistor 10, and the contact electrode electrically connected to the doped region 23 serves as the drain electrode D. The doped region 24 serves as the source region of the transistor 10, and the contact electrode electrically connected to the doped region 24 serves as the source electrode S. The contact electrode electrically connected to the gate layer 27 serves as the gate electrode G. In an embodiment of the present invention, a contact electrode CE20 is electrically connected to the doped region 25. When the semiconductor circuit 1 is in the normal operation mode, a high operating voltage VDD is provided to the contact electrode CE20; when the semiconductor circuit 1 is in the abnormal operation mode, the high operating voltage VDD is not provided to the contact electrode CE20, that is, the potential state of the contact electrode CE20 is floating. According to Figure 2A the cross-sectional view, it can be known that the transistor 10 is formed within the deep well 21. Specifically, the transistor 10 is surrounded by the deep well 21. Figure 1A The boundary L21 is shown in Figure 2A which surrounds the transistor 10 to schematically show

[0049] Refer to againFigure 1A The cathode of diode 12 is electrically connected to the drain electrode D of transistor 10, and its anode is electrically connected to power supply terminal T10. The cathode of diode 13 is electrically connected to the source electrode S of transistor 10, and its anode is electrically connected to power supply terminal T10. When semiconductor circuit 1 is in the normal operation mode, a low operating voltage VSS or a ground voltage GND is provided to power supply terminal T10 (hereinafter, the low operating voltage VSS will be taken as an example to illustrate the embodiments of the present invention); when semiconductor circuit 1 is in the abnormal operation mode, no voltage is provided to power supply terminal T10, that is, the potential state of power supply terminal T10 is floating.

[0050] Refer to Figure 1A With Figure 2A The electrostatic discharge protection circuit 11 is electrically connected to the drain electrode D and includes a control circuit 110 and a discharge circuit 111. The control circuit 110 has a control terminal T11, which is electrically connected to the contact electrode CE20 at node ND10. In this embodiment, the control circuit 110 includes an inverter 112. The inverter 112 has an input terminal T12 and an output terminal T13, and the input terminal T12 is electrically connected to the control terminal T11 of the control circuit 11. The inverter 112 includes a P-type transistor P110 and an N-type transistor N110. The gate of transistor P110 is electrically connected to the input terminal T12, its source is electrically connected to the drain electrode D of transistor 10, and its drain is electrically connected to the output terminal T13. The gate of transistor N110 is electrically connected to the input terminal T12, its drain is electrically connected to the output terminal T13, and its source is electrically connected to power supply terminal T10. The discharge circuit 111 includes an N-type transistor N111. The gate of transistor N111 is electrically connected to the output terminal T13 of the inverter 112, its drain is electrically connected to the drain electrode D of transistor 10, and its source is electrically connected to power supply terminal T10. Based on the circuit structure of the control circuit 110 and the connection of transistor 10, the control circuit 110 generates a control signal S10 according to the potential state of the deep well 21 and based on the potential state of the drain electrode D or the potential state of the power supply terminal T10. For related descriptions, please refer to the following text.

[0051] When the semiconductor circuit 1 is in an abnormal operation mode, the high operating voltage VDD is not provided to the contact electrode CE20, and no voltage is provided to the power terminal T10, that is, the potential states of both the contact electrode CE20 and the power terminal T10 are floating. Since the input terminal T12 of the inverter 112 is electrically connected to the node ND10 through the control terminal T11 and the contact electrode CE20, the input terminal T12 is also in a floating state, causing the transistor P110 to conduct and the transistor N110 to turn off. When an electrostatic discharge event occurs at the drain electrode D, the potential of the drain electrode D instantaneously increases. Through the conducting transistor P110, the output terminal T13 is in a high potential state, that is, the control signal S10 has a high voltage level. The transistor N111 conducts according to this high voltage level control signal S10, creating a discharge path between the drain electrode D and the power terminal T10. The electrostatic charge on the drain electrode D is conducted to the power terminal T10 through this discharge path, thereby protecting the circuit or components coupled to the transistor 10 from damage by electrostatic charge.

[0052] In this embodiment, when the semiconductor circuit 1 is in an abnormal operation mode and an electrostatic discharge event occurs at the drain electrode D, due to the conduction of the transistor N111 and the connection structure of the diode 13 (its anode is electrically connected to the power terminal T10 and its cathode is electrically connected to the source electrode S), another discharge path is formed between the power terminal T10 and the source electrode S. Therefore, when an electrostatic discharge event occurs at the drain electrode D, the electrostatic charge on the drain electrode D can be conducted not only to the power terminal T10 but also to the source electrode S.

[0053] When the semiconductor circuit 1 is in a normal operation mode, the high operating voltage VDD is provided to the contact electrode CE20 and the low operating voltage VSS is provided to the power terminal T10, that is, the contact electrode CE20 is in a high potential state and the power terminal T10 is in a low potential state. In the normal operation mode, since the input terminal T12 of the inverter 112 is electrically connected to the node ND10 through the control terminal T11 and the contact electrode CE20, the input terminal T12 is in a high potential state, causing the transistor N110 to conduct and the transistor P110 to turn off. The output terminal T13 is in a low potential state based on the low operating voltage VSS, that is, the control signal S10 has a low voltage level. The transistor N111 turns off according to this low voltage level control signal S10. In the normal operation mode, since the transistor N111 is turned off, there is no discharge path between the drain electrode D and the power terminal T10, that is, the aforementioned discharge path is blocked.

[0054] In other embodiments, the electrostatic discharge protection circuit 11 is also electrically connected to the source electrode S. In this embodiment, as Figure 2BAs shown, an N-type doped region 28 is further formed in the deep well 21, and a contact electrode CE21 is electrically connected to the doped region 28. When the semiconductor circuit 1 is in the normal operation mode, a high operating voltage VDD is provided to the contact electrode CE21; when the semiconductor circuit 1 is in the abnormal operation mode, the high operating voltage VDD is not provided to the contact electrode CE21, that is, the potential state of the contact electrode CE21 is floating. In this embodiment, the position where the N-type doped region 28 is formed in the deep well 21 is close to the N-type doped region (source region) 24. Refer to Figure 1B , the electrostatic discharge protection circuit 11 further includes a control circuit 113 and a discharge circuit 114. The control circuit 113 has a control terminal T14, which is electrically connected to the contact electrode CE21 at the node ND11. The control circuit 113 includes an inverter 115. The inverter 115 has an input terminal T15 and an output terminal T16, and the input terminal T15 is electrically connected to the control terminal T14 of the control circuit 113. The inverter 115 includes a P-type transistor P113 and an N-type transistor N113. The gate of the transistor P113 is electrically connected to the input terminal T15, its source is electrically connected to the source electrode S of the transistor 10, and its drain is electrically connected to the output terminal T16. The gate of the transistor N113 is electrically connected to the input terminal T15, its drain is electrically connected to the output terminal T16, and its source is electrically connected to the power supply terminal T10. The discharge circuit 114 includes an N-type transistor N114. The gate of the transistor N114 is electrically connected to the output terminal T16 of the inverter 115, its drain is electrically connected to the source electrode S of the transistor 10, and its source is electrically connected to the power supply terminal T10. Based on the circuit architecture of the control circuit 113 and the connection of the transistor 10, the control circuit 113 generates a control signal S11 according to the potential state of the deep well 21 and based on the potential state of the source electrode S or the potential state of the power supply terminal T10. For related descriptions, please refer to the following text.

[0055] When the semiconductor circuit 1 is in the abnormal operation mode, the high operating voltage VDD is not provided to the contact electrode CE21, and no voltage is provided to the power supply terminal T10, that is, the potential states of both the contact electrode CE21 and the power supply terminal T10 are floating. Since the input terminal T15 of the inverter 115 is electrically connected to the contact electrode CE21 through the control terminal T14 and the node ND11, therefore, the input terminal T15 is also in a floating state, causing the transistor P113 to conduct and the transistor N113 to turn off. When an electrostatic discharge event occurs on the source electrode S, the potential of the source electrode S instantaneously increases. Through the conducting transistor P113, the output terminal T16 is in a high potential state, that is, the control signal S11 has a high voltage level. The transistor N114 conducts according to this high voltage level control signal S11, such that there is a discharge path between the source electrode S and the power supply terminal T10. The electrostatic charge on the source electrode S is conducted to the power supply terminal T10 through this discharge path, thereby protecting the circuit or components coupled to the transistor 10 from being damaged by electrostatic charges.

[0056] In this embodiment, when the semiconductor circuit 1 is in an abnormal operation mode and an electrostatic discharge event occurs on the source electrode S, since the transistor N114 is turned on and the connection structure of the diode 12 (its anode is electrically connected to the power supply terminal T10 and its cathode is electrically connected to the drain electrode D), another discharge path is formed between the power supply terminal T10 and the drain electrode D. Therefore, when an electrostatic discharge event occurs on the source electrode S, the electrostatic charge on the source electrode S can be conducted not only to the power supply terminal T10 but also to the drain electrode D.

[0057] When the semiconductor circuit 1 is in a normal operation mode, a high operating voltage VDD is provided to the contact electrode CE21 and a low operating voltage VSS is provided to the power supply terminal T10, that is, the contact electrode CE21 is in a high potential state and the power supply terminal T10 is in a low potential state. In the normal operation mode, since the input terminal T15 of the inverter 115 is electrically connected to the contact electrode CE21 through the control terminal T14 and the node ND11, the input terminal T15 is in a high potential state, causing the transistor N113 to be turned on and the transistor P113 to be turned off. The output terminal T16 is in a low potential state based on the low operating voltage VSS, that is, the control signal S11 has a low voltage level. The transistor N114 is turned off according to the control signal S11 with this low voltage level. In the normal operation mode, since the transistor N114 is turned off, there is no discharge path between the source electrode S and the power supply terminal T10, that is, the aforementioned discharge path is blocked.

[0058] In other embodiments, the electrostatic discharge protection circuit electrically connected to the drain electrode D of the transistor 10 has other circuit structures. Refer to Figure 1A and Figure 3 and Figure 1A compared with Figure 3 the control circuit 110' of the electrostatic discharge circuit 11 in Figure 3 further includes an inverter 300. The inverter 300 has an input terminal T30 and an output terminal T31, and the input terminal T30 is electrically connected to the output terminal T13 of the inverter 112. The inverter 300 includes a P-type transistor P300 and an N-type transistor N300. The gate of the transistor P300 is electrically connected to the input terminal T30, its source is electrically connected to the drain electrode D of the transistor 10, and its drain is electrically connected to the output terminal T31. The gate of the transistor N300 is electrically connected to the input terminal T30, its drain is electrically connected to the output terminal T31, and its source is electrically connected to the power supply terminal T10. In addition, based on the structure of the control circuit 110', Figure 3 the discharge circuit 111' of the electrostatic discharge circuit 11 in Figure 1A includes a P-type transistor P301 instead of the N-type transistor N111 in Figure 3, the gate of transistor P301 is electrically connected to the output terminal T31 of inverter 300, its source is electrically connected to the drain electrode D of transistor 10, and its drain is electrically connected to power supply terminal T10.

[0059] Referring to the foregoing description of Figure 1A In the abnormal operation mode, the high operating voltage VDD is not provided to contact electrode CE20, and no voltage is provided to power supply terminal T10, that is, the potential states of both contact electrode CE20 and power supply terminal T10 are floating. When an electrostatic discharge event occurs at drain electrode D, the output terminal T13 of inverter 112 is in a high potential state. According to the high potential state of output terminal T13, transistor N300 is turned on, and transistor P300 is turned off. Through the turned-on transistor N300, output terminal T31 is at a low voltage level based on the floating state of power supply terminal T10, that is, control signal S10’ has a low voltage level. Transistor P301 is turned on according to this low voltage level control signal S10’, so that a discharge path is formed between drain electrode D and power supply terminal T10. The electrostatic charge on drain electrode D is conducted to power supply terminal T10 through this discharge path, thereby protecting the circuit or components coupled to transistor 10 from being damaged by electrostatic charges.

[0060] In this embodiment, when semiconductor circuit 1 is in the abnormal operation mode and an electrostatic discharge event occurs at drain electrode D, due to the conduction of transistor P301 and the connection structure of diode 13 (its anode is electrically connected to power supply terminal T10, and its cathode is electrically connected to source electrode S), another discharge path is formed between power supply terminal T10 and source electrode S. Therefore, when an electrostatic discharge event occurs at drain electrode D, the electrostatic charge on drain electrode D can be conducted not only to power supply terminal T10, but also to source electrode S.

[0061] Similarly, referring to the foregoing description of Figure 1A When semiconductor circuit 1 is in the normal operation mode, the high operating voltage VDD is provided to contact electrode CE20 and the low operating voltage VSS is provided to power supply terminal T10, that is, contact electrode CE20 is in a high potential state, and power supply terminal T10 is in a low potential state. In the normal operation mode, output terminal T13 is in a low potential state. According to the low potential state of output terminal T13, transistor P300 is turned on, and transistor N300 is turned off. Through the turned-on transistor P300, output terminal T31 is at a high voltage level based on the potential of drain electrode D when transistor 10 operates, that is, control signal S10’ has a high voltage level. Transistor P301 is turned off according to this high voltage level control signal S10’. In the normal operation mode, since transistor P301 is turned off, there is no discharge path between drain electrode D and power supply terminal T10, that is, the aforementioned discharge path is blocked.

[0062] According to the above embodiments, the electrostatic discharge protection circuit of the present invention does not have a capacitor-resistor circuit used in the prior art, and thus occupies a smaller area.

[0063] Although the present invention has been disclosed above in its preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the patent application.

Claims

1. An electrostatic discharge protection circuit, characterized in that, For a semiconductor device having a first drain / source electrode and a second drain / source electrode and surrounded by a deep well, comprising: A first control circuit electrically connected between the first drain / source electrode of the semiconductor device and a power supply terminal and having a first control terminal, wherein the first control terminal is electrically connected to the deep well and the first control circuit generates a first control signal; and A first discharge circuit electrically connected between the first drain / source electrode and the power supply terminal and controlled by the first control signal; Wherein, when an electrostatic discharge event occurs on the first drain / source electrode, the first control circuit generates the first control signal according to a potential state of the deep well and a potential state of the first drain / source electrode, and the first discharge circuit provides a first discharge path between the first drain / source electrode and the power supply terminal according to the first control signal.

2. The electrostatic discharge protection circuit according to claim 1, wherein The first control circuit includes: A first inverter electrically connected between the first drain / source electrode and the power supply terminal and having a first input terminal and a first output terminal; Wherein the first input terminal is electrically connected to the first control terminal; and Wherein the first inverter selectively determines a voltage of the first output terminal based on the potential state of the first drain / source electrode or a potential state of the power supply terminal according to the potential state of the deep well, and the first control circuit generates the first control signal according to the voltage of the first output terminal.

3. The electrostatic discharge protection circuit according to claim 2, wherein When the electrostatic discharge event occurs on the first drain / source electrode, the first inverter generates the first control signal based on the potential state of the first drain / source electrode to control the discharge circuit to provide the first discharge path.

4. The electrostatic discharge protection circuit according to claim 3, wherein The electrostatic discharge event occurs during a floating state of the potential state of the deep well.

5. The electrostatic discharge protection circuit according to claim 2, wherein When the semiconductor device is in a normal operation mode, the first inverter generates the first control signal based on the potential state of the power supply terminal to control the discharge circuit to block the first discharge path.

6. The electrostatic discharge protection circuit according to claim 5, wherein During the normal operation mode, the deep well receives an operating voltage.

7. The electrostatic discharge protection circuit according to claim 2, wherein, The first inverter includes: A first P-type transistor having a control electrode electrically connected to the first input terminal, a first electrode electrically connected to the first drain / source electrode, and a second electrode electrically connected to the first output terminal; and A first N-type transistor having a control electrode electrically connected to the first input terminal, a first electrode electrically connected to the first output terminal, and a second electrode electrically connected to the power supply terminal.

8. The electrostatic discharge protection circuit according to claim 7, wherein, The first discharge circuit includes: A second N-type transistor having a control electrode electrically connected to the first output terminal, a first electrode electrically connected to the first drain / source electrode, and a second electrode electrically connected to the power supply terminal.

9. The electrostatic discharge protection circuit according to claim 2, characterized in that, The first control circuit further includes: A second inverter electrically connected between the first drain / source electrode and the power supply and having a second input terminal and a second output terminal; Wherein the second input terminal is electrically connected to the first output terminal; and Wherein the second inverter selectively generates the first control signal based on the potential state of the first drain / source electrode or the potential state of the power supply terminal according to the voltage of the first output terminal.

10. The electrostatic discharge protection circuit according to claim 1, characterized in that, Further comprising: A second control circuit, electrically connected between the second drain / source electrode of the semiconductor element and the power supply terminal, and having a second control terminal, wherein the second control terminal is electrically connected to the deep well, and the second control circuit generates a second control signal; and A second discharge circuit, electrically connected between the second drain / source electrode and the power supply terminal, and controlled by the second control signal; Wherein, when the electrostatic discharge event occurs on the second drain / source electrode, the second control circuit generates the second control signal according to the potential state of the deep well and a potential state of the second drain / source electrode, and the second discharge circuit provides a second discharge path between the second drain / source electrode and the power supply terminal according to the second control signal.

11. The electrostatic discharge protection circuit according to claim 1, wherein Further comprising: A diode, having an anode terminal electrically connected to the power supply terminal and a cathode terminal electrically connected to the second drain / source electrode; Wherein, when the electrostatic discharge event occurs on the first drain / source electrode, a second discharge path is formed between the power supply terminal and the second drain / source electrode via the diode.

12. A semiconductor circuit, characterized in that, Comprising: A semiconductor element, formed in a well, and having a first drain / source electrode and a second drain / source electrode, wherein the well is surrounded by a deep well, the well has a first conductivity type, and the deep well has a second conductivity type different from the first conductivity type; A first control circuit, electrically connected between the first drain / source electrode and a power supply terminal, and having a first control terminal, wherein the first control terminal is electrically connected to the deep well, and the first control circuit generates a first control signal; and A first discharge circuit, electrically connected between the first drain / source electrode and the power supply terminal, and controlled by the first control signal; Wherein, when an electrostatic discharge event occurs on the first drain / source electrode, the first control circuit generates the first control signal according to a potential state of the deep well and a potential state of the first drain / source electrode, and the first discharge circuit provides a first discharge path between the first drain / source electrode and the power supply terminal according to the first control signal.

13. The semiconductor circuit according to claim 12, characterized in that, The first control circuit includes: A first inverter, electrically connected between the first drain / source electrode and the power supply terminal, and having a first input terminal and a first output terminal; Wherein the first input terminal is electrically connected to the first control terminal; and Wherein the first inverter selectively determines a voltage of the first output terminal based on the potential state of the first drain / source electrode or a potential state of the power supply terminal according to the potential state of the deep well, and the first control circuit generates the first control signal according to the voltage of the first output terminal.

14. The semiconductor circuit according to claim 13, wherein, When the electrostatic discharge event occurs on the first drain / source electrode, the first inverter generates the first control signal based on the potential state of the first drain / source electrode to control the discharge circuit to provide the first discharge path.

15. The semiconductor circuit according to claim 14, wherein, The electrostatic discharge event occurs during a floating state of the potential state of the deep well.

16. The semiconductor circuit according to claim 13, wherein, When the semiconductor device is in a normal operation mode, the first inverter generates the first control signal based on the potential state of the power supply terminal to control the discharge circuit to block the first discharge path.

17. The semiconductor circuit according to claim 16, wherein, In the normal operation mode, the deep well receives an operating voltage.

18. The semiconductor circuit according to claim 13, wherein, The first inverter includes: a first P-type transistor having a control electrode electrically connected to the first input terminal, a first electrode electrically connected to the first drain / source electrode, and a second electrode electrically connected to the first output terminal; and a first N-type transistor having a control electrode electrically connected to the first input terminal, a first electrode electrically connected to the first output terminal, and a second electrode electrically connected to the power supply terminal.

19. The semiconductor circuit according to claim 18, wherein, The first discharge circuit includes: a second N-type transistor having a control electrode electrically connected to the first output terminal, a first electrode electrically connected to the first drain / source electrode, and a second electrode electrically connected to the power supply terminal.

20. The semiconductor circuit according to claim 13, wherein, The first control circuit further includes: a second inverter electrically connected between the first drain / source electrode and the power supply terminal and having a second input terminal and a second output terminal; wherein the second input terminal is electrically connected to the first output terminal; and wherein the second inverter selectively generates the first control signal based on the potential state of the first drain / source electrode or the potential state of the power supply terminal according to the voltage at the first output terminal.

21. The semiconductor circuit according to claim 12, wherein, Further included is: a second control circuit electrically connected between the second drain / source electrode of the semiconductor device and the power supply terminal and having a second control terminal, wherein the second control terminal is electrically connected to the deep well and the second control circuit generates a second control signal; and a second discharge circuit electrically connected between the second drain / source electrode and the power supply terminal and controlled by the second control signal; wherein, when an electrostatic discharge event occurs at the second drain / source electrode, the second control circuit generates the second control signal according to the potential state of the deep well and the potential state of the second drain / source electrode, and the second discharge circuit provides a second discharge path between the second drain / source electrode and the power supply terminal according to the second control signal.

22. The semiconductor circuit according to claim 12, wherein Further included is: a diode having an anode terminal electrically connected to the power supply terminal and a cathode terminal electrically connected to the second drain / source electrode; wherein, when an electrostatic discharge event occurs at the first drain / source electrode, a second discharge path is formed between the power supply terminal and the second drain / source electrode via the diode.

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