Device integration scheme using bulk semiconductor substrates

Abstract

The present invention relates to a device integration scheme utilizing bulk semiconductor substrates having a <111> crystal orientation, and discloses structures including devices such as transistors integrated on bulk semiconductor substrates and methods of forming structures including devices such as transistors integrated on bulk semiconductor substrates. The bulk semiconductor substrate contains a single crystalline semiconductor material having a diamond lattice structure and a <111> crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer composed of a III-V compound semiconductor material.

Description

TECHNICAL FIELD

[0001] The present invention relates to semiconductor device fabrication and integrated circuits, and more particularly, to structures including devices (e.g., transistors) integrated on bulk semiconductor substrates and methods of forming structures including devices (e.g., transistors) integrated on bulk semiconductor substrates. BACKGROUND

[0002] High voltage power electronic devices, such as high electron mobility transistors, can be fabricated using III-V compound semiconductors to take advantage of their material properties, such as carrier mobilities greater than that of silicon. III-V compound semiconductors include Group III elements (aluminum, gallium, indium) and Group V elements (nitrogen, phosphorus, arsenic, antimony). High electron mobility transistors can include heterojunctions between crystalline III-V compound semiconductor materials with different bandgaps, such as between binary gallium nitride and ternary aluminum gallium nitride. During operation, a two-dimensional electron gas forms near the interface at the heterojunction and defines the channel of the high electron mobility transistor.

[0003] Integration of high electron mobility transistors with field effect transistors or heterojunction bipolar transistors formed on the same chip from complementary metal-oxide-semiconductor (CMOS) processing has proven to be a complex process. Integration can be achieved through wafer bonding or through the use of engineered or hybrid substrates whose properties make the process of integrating high electron mobility transistors with these other types of transistors very complex.

[0004] There is a need for structures including devices (e.g., transistors) integrated on bulk semiconductor substrates and methods of forming structures including devices (e.g., transistors) integrated on bulk semiconductor substrates. SUMMARY

[0005] In one embodiment of the invention, a structure includes a bulk semiconductor substrate composed of a single crystalline semiconductor material having a diamond crystalline lattice structure and a <111> crystal orientation. The bulk semiconductor substrate has a first device region and a second device region. The structure includes a first transistor located in the first device region of the bulk semiconductor substrate and a second transistor located in the second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate and the layer stack includes a layer composed of a III-V compound semiconductor material.

[0006] In one embodiment of the invention, a method includes providing a bulk semiconductor substrate composed of a single crystalline semiconductor material having a diamond crystalline lattice structure and a <111> crystal orientation. The method also includes forming a first transistor in a first device region of the bulk semiconductor substrate, forming a layer stack including a layer composed of a III-V compound semiconductor material in a second device region of the bulk semiconductor substrate, and forming a second transistor using the layer stack. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate various embodiments of the application and, together with the general description of the application given above and the detailed description of the embodiments given below, serve to explain various embodiments of the present application. In the drawings, like reference numerals indicate the same elements throughout the various drawings.

[0008] Figures 1 to 6 is a cross-sectional view of a structure for a continuous manufacturing phase of a processing method according to an alternative embodiment of the present invention.

[0009] Figure 3A is a cross-sectional view of a structure for a portion of a continuous manufacturing phase of a processing method according to an alternative embodiment of the present invention. Figure 3

[0010] Figure 7 is a cross-sectional view of a structure for a continuous manufacturing phase of a processing method according to an alternative embodiment of the present invention.

[0011] Figure 8 and Figure 9 are cross-sectional views of a structure for a continuous manufacturing phase of a processing method according to alternative embodiments of the present invention.

[0012] Figure 10 is a cross-sectional view of a structure for a continuous manufacturing phase of a processing method according to an alternative embodiment of the present invention.

[0013] MAIN COMPONENT SYMBOL EXPLANATION

[0014] 10 semiconductor substrate

[0015] 12 top surface

[0016] 14 shallow trench isolation region

[0017] 16 device region

[0018] 18 device region

[0019] 20 device region

[0020] 22 gate conductor layer, layer

[0021] 24 gate dielectric layer, layer

[0022] 26 hard mask ​

[0023] 29 side wall, trench side wall

[0024] 30 trench

[0025] 31 side wall, trench side wall

[0026] 32 surface

[0027] 34 sidewall spacer

[0028] 35 top surface

[0029] 36 layer stack

[0030] 37 side wall

[0031] 40 source / drain region

[0032] 42 field effect transistor, transistor

[0033] 44 bipolar junction transistor, transistor

[0034] 46 collector

[0035] 48 emitter

[0036] 50 base layer

[0037] 52 gate electrode

[0038] 54 transistor

[0039] 56 source region

[0040] 58 drain region

[0041] 60 interconnect structure

[0042] 62 dielectric layer

[0043] 64 contact

[0044] 66 metal line

[0045] 68 opening

[0046] 76 buffer layer, layer

[0047] 78 channel layer, layer

[0048] 80 spacer layer, layer

[0049] 82 barrier layer, layer. DETAILED DESCRIPTION

[0050] REFERENCE Figure 1According to embodiments of the present invention, a semiconductor substrate 10 is provided that includes a single crystalline semiconductor material, such as single crystalline silicon. The semiconductor substrate 10 has a top surface 12, which can be planar. The semiconductor substrate 10 is a bulk substrate that includes a single crystalline semiconductor material, such as single crystalline silicon. In one embodiment, the single crystalline semiconductor material of the semiconductor substrate 10 can have a diamond crystal lattice structure with a <111> crystal orientation as specified by Miller indices. In one embodiment, the semiconductor substrate 10 can include single crystalline silicon having a diamond lattice structure with a <111> crystal orientation. For a semiconductor substrate 10 having a <111> crystal orientation, the (111) crystallographic plane is parallel to the top surface 12 of the semiconductor substrate 10, and the

[111] crystallographic direction is perpendicular to the (111) plane. The (100) crystallographic axe is not located in the plane of the top surface 12. The semiconductor substrate 10 can be characterized as a non-silicon-on-insulator substrate (i.e., a non-SOI substrate) that lacks the buried oxide layer characteristics of a silicon-on-insulator (SOI) substrate. In one embodiment, the semiconductor substrate 10 can be composed entirely of a semiconductor material having a <111> crystal orientation.

[0051] A shallow trench isolation region 14 is formed extending from the top surface 12 of the semiconductor substrate 10 into the semiconductor substrate 10. The shallow trench isolation region 14 can include a dielectric material deposited by chemical vapor deposition into a trench etched in the semiconductor substrate 10, and polished and deglazed. The dielectric material included in the shallow trench isolation region 14 can include silicon dioxide, silicon nitride, silicon carbide, silicon rich silicon dioxide, or a combination of two or more of these materials. The shallow trench isolation region 14 can extend to a depth dl into the semiconductor substrate 10 relative to the top surface 12. The shallow trench isolation region 14 surrounds and defines a plurality of device regions 16, 18, 20. In one embodiment, the top surface 12 in the device region 18 can be coplanar with the top surface 12 in the device region 16, and can also be coplanar with the top surface 12 in the device region 20.

[0052] A gate conductor layer 22 composed of doped polysilicon (i.e., doped poly) and a gate dielectric layer 24 composed of an electrical insulator, such as silicon dioxide, are formed on the semiconductor substrate 10. These layers 22, 24 are formed on the top surface 12 of all of the device regions 16, 18, 20.

[0053] A hard mask 26 can be formed over the layers 22, 24 on the semiconductor substrate 10 and patterned to include openings generally over the device region 18. The hard mask 26 can be composed of a dielectric material, such as silicon nitride, and can be patterned by a photolithography and etching process. Segments of the gate conductor layer 22 and the gate dielectric layer 24 exposed by the openings in the hard mask 26 can be removed by an etching process, such as a reactive ion etching process, which can expose the top surface 12 of the semiconductor substrate 10 in the device region 18.

[0054] Subsequently, trenches 30 in the semiconductor substrate 10 are formed at locations of the openings in the hard mask 26 by etching using another etching process, such as a reactive ion etching process. The trenches 30 can extend to a trench bottom at a surface 32 of the semiconductor substrate 10 and can have side faces or sidewalls 29, 31. The trenches 30 can be surrounded by the shallow trench isolation regions 14 defining the device region 18. The surface 32 can be located in the semiconductor substrate 10 at a depth d2 relative to the top surface 12, which is greater than the depth dl of the shallow trench isolation regions 14. The hard mask 26 protects segments of the gate conductor layer 22 and the gate dielectric layer 24 in the device regions 16 and 20 during the etching process. In an embodiment, the surface 32 can be planar and free of topography. In an embodiment, the top surface 12 can be planar, the surface 32 can be planar, and the planes of the top surface 12 and the surface 32 can be parallel.

[0055] Referring to Figure 2 , where like reference numerals refer to like features in Figure 1 , at a subsequent fabrication stage of the processing method, sidewall spacers 34 are formed adjacent to the sidewalls 29, 31 of the trenches 30. The sidewall spacers 34 can extend from the top surface 12 of the semiconductor substrate 10 to the surface 32 at the bottom of the trenches 30. The sidewall spacers 34 can be formed by depositing a liner layer composed of a dielectric material, such as silicon nitride, and etching the deposited liner layer using an anisotropic etching process, such as a reactive ion etching process.

[0056] Referring to Figure 3 , Figure 3A , where like reference numerals refer to like features in Figure 2Similar features in the semiconductor substrate 10 and the layer stack 36 can be formed by similar processes. In one embodiment, the layer stack 36 can include at least one crystalline layer composed of a III-V compound semiconductor material. In one embodiment, the layer stack 36 can include at least one crystalline layer composed of a binary III-V compound semiconductor material. In one embodiment, the layer stack 36 can include at least one crystalline layer composed of a ternary III-V compound semiconductor material. In one embodiment, the layer stack 36 can include a polycrystalline layer composed of different III-V compound semiconductor materials. In one embodiment, the layer stack 36 can include at least one crystalline layer composed of a binary III-V compound semiconductor material and at least one crystalline layer composed of a ternary III-V compound semiconductor material. In one embodiment, the layer stack 36 can include one or more crystalline layers containing a gallium nitride or a ternary III-V compound semiconductor material based on gallium nitride (e.g., aluminum gallium nitride). In one embodiment, the layer stack 36 can include one or more crystalline layers containing gallium and nitrogen.

[0057] The layer stack 36 can be formed by an epitaxial growth process. Each layer of the layer stack 36 can have a single crystalline crystal structure, or, alternatively, a substantially single crystalline crystal structure with varying degrees of crystal defectivity. The <111> crystal orientation of the semiconductor material (e.g., single crystalline silicon) of the semiconductor substrate 10 can facilitate epitaxial growth of the III-V compound semiconductor material (e.g., gallium nitride) of the layer stack 36 with low crystal defectivity by closer lattice matching than a substrate with a <100> crystal orientation. Specifically, the atoms with <111> crystal orientation on the surface plane of the semiconductor substrate 10 are arranged in a hexagonal pattern, which can reasonably lattice match the crystal structure of one or more compound semiconductor materials in the layer stack 36 (e.g., the wurtzite crystal structure of gallium nitride (based on a binary hexagonal close-packed crystal system).

[0058] In one embodiment, layer stack 36 can be formed by a selective epitaxial growth process in which semiconductor material is not formed on dielectric surfaces, such as hard mask 26 and sidewall spacers 34. In one embodiment, layer stack 36 can be formed by a non-selective epitaxial growth process in which semiconductor material is deposited and patterned by photolithography and etching processes. In one embodiment, sidewalls 37 of layer stack 36 can be located adjacent to and spaced apart from trench sidewalls 29, 31, in which case trench 30 can be substantially filled with layer stack 36. In a representative embodiment, layer stack 36 has sidewalls 37 that slope inwardly away from trench sidewalls 29, 31 to define, for example, a trapezoidal shape and space sidewalls 37 away from trench sidewalls 29, 31. In one embodiment, sidewalls 37 can converge at a top surface 35 of layer stack 36, which can be coplanar or substantially coplanar with top surface 12 of semiconductor substrate 10. Isolation regions (not shown) may be formed at the top surface 35 of the layer stack 36 by masked implantation of, for example, nitrogen or argon.

[0059] In one embodiment, if Figure 3A As shown, layer stack 36 may include a buffer layer 76, a channel layer 78, a spacer layer 80, and a barrier layer 82. Layers 76, 78, 80, 82 may be formed sequentially using an epitaxial growth process (e.g., metal organic chemical vapor deposition). Each of layers 76, 78, 80, 82 may have a single crystal structure, or, alternatively, a substantially single crystal structure with varying degrees of crystal defectivity. One or more of layers 76, 78, 80, 82 may include multiple sublayers having varying compositions or doping. Buffer layer 76 may include a III-V compound semiconductor material, such as gallium nitride, tailored in terms of material composition, doping, and / or layer thickness to accommodate the lattice mismatch between the material of semiconductor substrate 10 and the material of channel layer 78. Channel layer 78, disposed above buffer layer 76, may include a III-V compound semiconductor material, such as gallium nitride. Spacer layer 80 and barrier layer 82 are disposed above channel layer 78, with spacer layer 80 located between channel layer 78 and barrier layer 82. Spacer layer 80 can be thin and can comprise a III-V compound semiconductor, such as aluminum nitride. Barrier layer 82 can comprise a III-V compound semiconductor, such as aluminum gallium nitride, aluminum nitride, or indium aluminum nitride, having a heterointerface with channel layer 78 of a different composition. The material properties of spacer layer 80, barrier layer 82, and channel layer 78 contribute to the generation of a two-dimensional electron gas at the heterointerface, which is filled with highly mobile and abundant electrons, during device operation.

[0060] refer to Figure 4 , wherein similar reference numerals denote Figure 3Similar features in the semiconductor substrate 10 can be processed in subsequent fabrication stages of the processing method. The dielectric layer 38 can be deposited and patterned by photolithography and etching processes to cover the layer stack 36 in the device region 18. After deposition and patterning of the dielectric layer 38, the hard mask 26 is removed from the device region 16 by an etching process to expose the gate conductor layer 22 and the gate dielectric layer 24.

[0061] The gate conductor layer 22 and the gate dielectric layer 24 can be subsequently patterned by photolithography and etching processes to define a gate structure of a field effect transistor 42 in the device region 16. During patterning, the gate conductor layer 22 and the gate dielectric layer 24 are removed from the device region 20. Additional elements of the field effect transistor 42 can be fabricated by a complementary metal-oxide-semiconductor (CMOS) process to form a device structure in the device region 16 of the semiconductor substrate 10. The field effect transistor 42 can further include source / drain regions 40 and a channel region below the gate structure. The channel region and the source / drain regions 40 of the field effect transistor 42 comprise respective portions of the single-crystalline semiconductor material of the semiconductor substrate 10. The source / drain regions 40 are at least partially located below the top surface 12, and the channel region is typically located below the top surface 12 between the source / drain regions 40. The patterned gate conductor layer 22 and the gate dielectric layer 24 comprised in the gate structure of the field effect transistor 42 can be positioned as device layers on and above the top surface 12 of the semiconductor substrate 10. In one embodiment, the patterned gate dielectric layer 24 comprised in the gate structure of the field effect transistor 42 can be positioned as a device layer directly on the top surface 12 of the semiconductor substrate 10.

[0062] A bipolar junction transistor 44 can be fabricated as a device structure in the device region 20 of the semiconductor substrate 10. The bipolar junction transistor 44 can include a plurality of terminals in the form of a collector electrode 46, an emitter electrode 48, and a base layer 50 disposed between the collector electrode 46 and the emitter electrode 48 defined in the semiconductor substrate 10. In an alternative embodiment, a collector-up bipolar junction transistor can be formed in which the emitter electrode is disposed as a terminal in the semiconductor substrate 10. The emitter electrode 48 and the base layer 50 can be positioned as device layers on and above the top surface 12 of the semiconductor substrate 10. In one embodiment, the base layer 50 can be positioned as a device layer directly on the top surface 12 of the semiconductor substrate 10. The collector electrode 46 comprises a portion of the semiconductor material of the semiconductor substrate 10 that can be at least partially and preferably entirely located in the semiconductor substrate 10 below the top surface 12. The base layer 50 can comprise a single-crystal semiconductor material (e.g., silicon germanium) epitaxially grown on the top surface 12 of the semiconductor substrate 10. In one embodiment, the collector electrode 46 and the emitter electrode 48 can comprise an n-type semiconductor material and the base layer 50 can comprise a p-type semiconductor material to define an NPN transistor. The bipolar junction transistor 44 can be formed from a bipolar complementary metal-oxide (BiCMOS) process, which is a variant of a CMOS process.

[0063] The field effect transistor 42 and the bipolar junction transistor 44 constitute different types or classes of transistor structures. The difference between the field effect transistor 42 and the bipolar junction transistor 44 is that only majority charge carriers flow in the field effect transistor 42, whereas both majority and minority charge carriers can flow in the bipolar junction transistor 44. Neither the field effect transistor 42 nor the bipolar junction transistor 44 includes any silicon carbide layer in their respective structures and thus are free of silicon carbide. Both the field effect transistor 42 and the bipolar junction transistor 44 are formed on a semiconductor material having the same <111> crystal orientation as the semiconductor material used to form the layer stack 36.

[0064] Reference is made to Figure 5 wherein like reference numerals refer to like features in Figure 4 At a subsequent fabrication stage of the processing method, the transistor 54 is formed as a device structure using the layer stack 36. To this end, the dielectric layer 38 is patterned in the device region 18 by a lithography and etching process to define an opening forming the gate electrode 52 of the transistor 54. The gate electrode 52 can be composed of a metal (e.g., metal nitride) that is deposited and patterned by the lithography and etching process to define a given shape. The source region 56 and the drain region 58 of the transistor 54 can be formed by patterning an opening in the dielectric layer 38 with a lithography and etching process and then forming a metal (e.g., metal nitride) in the patterned opening. Metal atoms from the source region 56 and the drain region 58 can diffuse into the layer stack 36.

[0065] Transistor 54 is not formed from a CMOS process and can therefore be considered a non-CMOS transistor. In one embodiment, transistor 54 can be a high electron mobility transistor (HEMT). In one embodiment, transistor 54 can be a metal insulator semiconductor high electron mobility transistor (MISHEMT). In one embodiment, transistor 54 can be a metal oxide semiconductor high electron mobility transistor (MOSHEMT).

[0066] Although the <111> crystal orientation of the semiconductor material (e.g., single crystalline silicon) of semiconductor substrate 10 enables epitaxial growth of the III-V compound semiconductor material of layer stack 36 with a low crystal defect rate, field effect transistor 42 and / or bipolar junction transistor 44 can exhibit non-optimized electrical performance due to the <111> crystal orientation as compared to comparable transistors formed on semiconductor substrates of other crystal orientations. Many structural and electronic properties of single crystalline semiconductor substrates are highly anisotropic and depend on the orientation of the crystal. Nonetheless, the implementation of semiconductor substrate 10 with a <111> crystal orientation allows transistor 54 to be integrated on the same semiconductor substrate 10 as field effect transistor 42 and / or bipolar junction transistor 44 without the need for complex fabrication processes such as wafer bonding or the use of engineered or hybrid substrates (e.g., SOI substrates with one or more crystal orientations for device layers), which can be considered an acceptable tradeoff for the inferior electrical performance.

[0067] Reference is made to Figure 6 , where like reference numerals refer to like features in Figure 5 , at subsequent fabrication stages of the processing method, mid- and post- stage processes including formation of contacts, vias, and wiring for interconnect structure 60 located above semiconductor substrate 10 and over transistors 42, 44, 54. Various metallization levels of interconnect structure 60 can be formed, such as a first metallization (M1) level, which are coupled with field effect transistor 42, bipolar junction transistor 44, and transistor 54 through contact levels. In this regard, interconnect structure 60 can include one or more dielectric layers 62, metallization levels having metal lines 66, and contact levels having contacts 64 coupling metal lines 66 to field effect transistor 42, bipolar junction transistor 44, and transistor 54.

[0068] Reference is made to Figure 7 , and according to alternative embodiments, sidewalls 37 of layer stack 36 can co-extend with trench sidewalls 29, 31, in which case trench 30 can be completely filled by layer stack 36. Growth conditions can be selected to impart a given shape to layer stack 36. Processing can continue as described in connection with Figures 4 to 6 .

[0069] Reference is made toFigure 8 And according to alternative embodiments, the trench 30, the layer stack 36, and the transistor 54 can be formed entirely after the formation of the field effect transistor 42 and the bipolar junction transistor 44 is completed. In this regard, one or more dielectric layers 62 can be formed and patterned to provide openings 68 that define a path to the top surface 12 of the semiconductor substrate 10 in the device region 18. In representative embodiments, the openings 68 are formed prior to the formation of the contacts 64 and the metal lines 66. In one embodiment, the openings 68 can be formed after the formation of the contacts 64 that are coupled to the contact level of the field effect transistor 42 and the bipolar junction transistor 44. In one embodiment, the openings 68 can be formed after the formation of the metal lines 66 of the first metallization level and the contacts 64 that couple the metal lines 66 to the contact level of the field effect transistor 42 and the bipolar junction transistor 44.

[0070] Referring to Figure 9 where like reference numerals refer to like features in Figure 8 , at a later stage of the processing method, the trench 30 is subsequently formed in the semiconductor substrate 10 at the location of the openings 68 in the one or more dielectric layers 62. The sidewall spacers 34, the layer stack 36, and the transistor 54 are subsequently formed using the channel trench 30 in the semiconductor substrate 10. After the formation of the transistor 54, the openings 68 can be refilled with a dielectric material, and the interconnect structure 60 can be completed by forming the contacts 64 and the metal lines 66 that are coupled to the transistor 54.

[0071] Referring to Figure 10 And according to alternative embodiments, the layer stack 36 can be formed on the top surface 12 of the semiconductor substrate 10 without the need for the prior formation of the trench 30. By forgoing the trench formation, the layer stack 36 and the transistor 54 formed using the layer stack 36 can be located in the same plane as the field effect transistor 42 and the bipolar junction transistor 44. More specifically, the layer stack 36, the gate structure of the field effect transistor 42, and the emitter 48 and the base layer 50 of the bipolar junction transistor 44 can be located on the top surface 12, which can be considered to provide a common plane for the transistors 42, 44, 54.

[0072] The above-described methods are used in the fabrication of integrated circuit chips. The integrated circuit chips produced by such methods can be distributed by the fabricant in raw wafer form (e.g., as a single wafer having a plurality of unpackaged chips), as bare chips, or in packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads for mounting to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier having one or more of a ceramic, glass, or organic substrate, with or without internal leads). In any case, the chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product, or as a final product.

[0073] Terms modified by approximate language referenced herein, such as "about," "approximately," and "substantially," are not limited to the precise value specified. Approximate language can correspond to the precision of the instrument used to measure the value, + / - 10% of the specified value unless otherwise dependent on the precision of the instrument.

[0074] References herein to terms such as "vertical," "horizontal," and the like are to establish a frame of reference rather than to limit. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction that is perpendicular to the horizontal plane, as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0075] A feature that is "connected," or "coupled," to another feature can be directly connected or coupled to the other feature or coupled thereto through one or more intermediate features. If no intermediate feature is present, a feature can be "directly connected," or "directly coupled," to, or in contact with, another feature. If at least one intermediate feature is present, a feature can be "indirectly connected" or "indirectly coupled" to, or in contact with, another feature. A feature that is on or in contact with another feature can be directly on or in direct contact with the other feature, or, conversely, one or more intermediate features can be present. If no intermediate feature is present, a feature can be directly on or in direct contact with another feature. If at least one intermediate feature is present, a feature can be indirectly on or in contact with another feature.

[0076] The description of various embodiments of the present application is provided for illustrative purposes and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application of the technology found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: Bulk semiconductor substrate, comprising a diamond crystal lattice structure and <111> a single crystal semiconductor material in a crystal orientation, wherein the bulk semiconductor substrate has a first device region and a second device region; a first complementary metal oxide semiconductor (CMOS) transistor disposed in the single crystalline semiconductor material in the first device region of the bulk semiconductor substrate; as well as A non-complementary metal oxide semiconductor transistor is located in the second device region of the bulk semiconductor substrate, the non-complementary metal oxide semiconductor transistor including a layer stack located on the single crystalline semiconductor material of the bulk semiconductor substrate, and the layer stack includes a layer composed of a III-V compound semiconductor material.

2. The semiconductor structure according to claim 1, wherein The single crystal semiconductor material is single crystal silicon.

3. The semiconductor structure according to claim 1, wherein The III-V compound semiconductor material includes gallium nitride.

4. The semiconductor structure according to claim 1, wherein The III-V compound semiconductor material of the layer stack has a substantially single-crystalline crystal structure.

5. The semiconductor structure according to claim 1, wherein The bulk semiconductor substrate has a top surface, and the first complementary metal oxide semiconductor transistor is a field effect transistor including a source / drain region in the bulk semiconductor substrate and at least partially below the top surface. The semiconductor structure according to claim 5 , wherein: The bulk semiconductor substrate has a third device region comprising the single crystalline semiconductor material and further comprises: A bipolar junction transistor is located in the third device region of the bulk semiconductor substrate, the bipolar junction transistor including a terminal located in the bulk semiconductor substrate and at least partially below the top surface.

7. The semiconductor structure according to claim 1, wherein The bulk semiconductor substrate has a top surface, and the first complementary metal oxide semiconductor transistor is a bipolar junction transistor including a terminal located in the bulk semiconductor substrate and at least partially below the top surface.

8. The semiconductor structure according to claim 1, wherein The bulk semiconductor substrate has a third device region comprising the single crystalline semiconductor material and further comprises: a second complementary metal oxide semiconductor transistor located in the third device region of the bulk semiconductor substrate; The first complementary metal oxide semiconductor transistor and the second complementary metal oxide semiconductor transistor are of different transistor types.

9. The semiconductor structure according to claim 1, wherein The bulk semiconductor substrate has a top surface, and the layer stack is located on the top surface of the bulk semiconductor substrate.

10. The semiconductor structure according to claim 9, wherein The top surface of the bulk semiconductor substrate is planar in the first device region and in the second device region, and the first complementary metal oxide semiconductor transistor includes a device layer on the top surface of the bulk semiconductor substrate.

11. The semiconductor structure according to claim 1, wherein The bulk semiconductor substrate has a first surface and a trench extending from the first surface into the bulk semiconductor substrate, and the layer stack is located on the bulk semiconductor substrate within the trench.

12. The semiconductor structure according to claim 11, wherein The bulk semiconductor substrate has a second surface located at the bottom of the trench, and the layer stack is located on the second surface.

13. The semiconductor structure of claim 11 , further comprising: a shallow trench isolation region located in the bulk semiconductor substrate, wherein the shallow trench isolation region is laterally located between the first device region and the second device region; Wherein, the trench extends to a deeper depth in the bulk semiconductor substrate relative to the first surface than the shallow trench isolation region.

14. The semiconductor structure according to claim 11, wherein The trench includes a plurality of sidewalls and further includes: A spacer is located on each of the plurality of sidewalls, wherein the spacer is composed of a dielectric material.

15. The semiconductor structure of claim 1 , further comprising: An interconnect structure is located above the bulk semiconductor substrate, the interconnect structure including a plurality of first contacts coupled to the first complementary metal oxide semiconductor transistor and a plurality of second contacts coupled to the non-complementary metal oxide semiconductor transistor.

16. The semiconductor structure of claim 1, further comprising: A shallow trench isolation region is located in the bulk semiconductor substrate, and the shallow trench isolation region is laterally located between the first device region and the second device region.

17. A method of forming a semiconductor structure, comprising: Provided by having a diamond crystal lattice structure and <111> A bulk semiconductor substrate composed of a crystal-oriented single-crystal semiconductor material; forming a first complementary metal oxide semiconductor (CMOS) transistor in a first device region of the bulk semiconductor substrate, wherein the first device region comprises the single crystalline semiconductor material; forming a layer stack comprising a layer consisting of a III-V compound semiconductor material in a second device region of the bulk semiconductor substrate, wherein the second device region comprises the single crystalline semiconductor material; and A non-complementary metal oxide semiconductor transistor is formed using the layer stack.

18. The method according to claim 17, wherein The single crystal semiconductor material is single crystal silicon, and the III-V compound semiconductor material is gallium nitride.

19. The method according to claim 17, further comprising: forming a trench extending from the first surface into the bulk semiconductor substrate to the second surface at a bottom of the trench; Wherein, the layer stack is located on the second surface of the bulk semiconductor substrate within the trench.

20. The method of claim 17, further comprising: forming shallow trench isolation regions in the bulk semiconductor substrate; The shallow trench isolation region is laterally located between the first device region and the second device region.

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