Semiconductor device with stepped multi-stack transistor structure

Abstract

A semiconductor device having a stepped multi-stack transistor structure is provided. The semiconductor device includes a substrate; a first transistor formed above the substrate, the first transistor including a first channel group of a plurality of first nanosheets, a first gate structure surrounding the first nanosheets, and a first source / drain region and a second source / drain region at both ends of the first channel group; and a second transistor formed in a vertical direction above the first transistor, the second transistor including a second channel group of a plurality of second nanosheets, a second gate structure surrounding the second nanosheets, and a third source / drain region and a fourth source / drain region at both ends of the second channel group, wherein the first channel group has a width greater than a width of the second channel group, wherein a number of the first nanosheets is less than a number of the second nanosheets, and wherein a sum of effective channel widths of the first nanosheets is substantially equal to a sum of effective channel widths of the second nanosheets.

Description

[0001] This application is based on and claims priority to U.S. Provisional Application No. 63 / 086,781, filed October 2, 2020, with the United States Patent and Trademark Office, and U.S. Non-Provisional Application No. 17 / 146,136, filed January 11, 2021, with the United States Patent and Trademark Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The apparatus and method consistent with the exemplary embodiments of the inventive concept relates to a semiconductor device, and more specifically, to a multi-stacked transistor having a stepped structure. Background Technology

[0003] To improve the performance and miniaturization of semiconductor devices, fin field-effect transistors (finFETs) were introduced. In a finFET, the channel structure protrudes from the substrate to form an elongated fin-shaped channel region, and the gate structure hangs over the fins to surround the upper surface and two side surfaces of the channel region. However, finFETs have a small effective channel width (W) that limits the amount of current flowing through the elongated fin-shaped channel region. eff Furthermore, current leakage occurs through the contact of the elongated fin channel region with the bottom surface of the silicon (Si) substrate, further limiting the performance of the finFET.

[0004] To address the aforementioned issues with the finFET channel structure, nanosheets have been introduced. Nanosheets have various names, such as multi-bridged channel FET (MBCFET), nanobundle, nanoribbon, and stacked channel device.

[0005] Figure 1 Nanosheet structures for semiconductor devices in the relevant field are shown. Figure 1 The nanosheet structure 100 shown includes a plurality of nanosheet channel layers 110 stacked vertically on a substrate 105 in a stacked manner in the D3 direction. Hereafter, the term "nanosheet channel layer" will be referred to as "nanosheet layer". The nanosheet layers 110, which serve as channels formed through the nanosheet structure 100 and function as transistors, are completely surrounded by a gate structure 115, except at the open ends formed on the two opposite sides of the gate structure 115 where source / drain regions will grow to complete the nanosheet structure 100 as a single nanosheet transistor (such as a metal-oxide-semiconductor FET (MOSFET)). That is, unlike conventional planar FETs or finFETs, Figure 1 The nanosheet structure enables a single transistor to have multiple channels between the source and drain regions. Figure 1In this diagram, the source / drain regions are intentionally omitted from the nanosheet structure 100, solely to illustrate how the nanosheet layer 110 penetrates the gate structure 115 in the D2 direction, which is the channel length direction of the nanosheet structure 100.

[0006] The substrate 105 may be a bulk substrate of a semiconductor (e.g., Si), the nanosheet layer 110 may also be formed of Si, and the gate structure 115 may be formed of a conductor metal and a gate dielectric layer. The conductor metal may be tungsten (W) or aluminum (Al), and the dielectric may include silicon oxide (SiO) or a metal silicate for electrical insulation from the nanosheet layer 110.

[0007] Multiple nanosheets 110 may each have the same width in the D1 direction and the same length in the D2 direction perpendicular to the D1 direction. It is known that nanosheets 110 provide not only increased device density gain but also increased W formed therefrom. eff A semiconductor device that allows a larger amount of current to flow through multiple nanosheet layers 110 between the source and drain regions.

[0008] However, even if transistors are formed from multiple channel layers like nanosheet layer 110, the techniques for reducing the size of a single transistor are limited.

[0009] The information disclosed in this background section was already known to the inventors prior to implementing the embodiments of this application, or it is technical information acquired during the process of implementing the embodiments. Therefore, it may contain information that does not form prior art known to the public. Summary of the Invention

[0010] The inventive concept provides a semiconductor device with a stepped nanosheet structure having different channel widths between the nanosheet layers.

[0011] According to an embodiment, a semiconductor device is provided, which may include: a substrate; a first transistor formed above the substrate, the first transistor including a first channel group of a plurality of first nanosheets, a first gate structure surrounding the first nanosheets, and a first source / drain region and a second source / drain region at both ends of the first channel group; a second transistor formed vertically above the first transistor, the second transistor including a second channel group of a plurality of second nanosheets, a second gate structure surrounding the second nanosheets, and a third source / drain region and a fourth source / drain region at both ends of the second channel group; and a source / drain contact structure connected to the second source / drain region through a space in which the fourth source / drain region is not vertically superimposed with the second source / drain region, wherein the second source / drain region has a width larger than the width of the fourth source / drain region, such that the fourth source / drain region is vertically superimposed only on a portion of the second source / drain region.

[0012] According to an embodiment, a semiconductor device is provided, which may include: a substrate; a first transistor formed above the substrate, the first transistor including a first channel group of a plurality of first nanosheet layers, a first gate structure surrounding the first nanosheet layers, and a first source / drain region and a second source / drain region at both ends of the first channel group; and a second transistor formed above the first transistor in a vertical direction, the second transistor including a second channel group of a plurality of second nanosheet layers, a second gate structure surrounding the second nanosheet layers, and a third source / drain region and a fourth source / drain region at both ends of the second channel group, wherein the first channel group has a width greater than the width of the second channel group, wherein the number of first nanosheet layers is less than the number of second nanosheet layers, and wherein the sum of the effective channel widths of the first nanosheet layers is substantially equal to the sum of the effective channel widths of the second nanosheet layers.

[0013] According to an embodiment, a semiconductor device is provided, which may include: a substrate; a first transistor formed on the substrate, the first transistor including at least two first channel layers and a first source / drain region and a second source / drain region; a second transistor stacked on top of the first transistor in a vertical direction, the second transistor including at least two second channel layers and a third source / drain region and a fourth source / drain region; and a source / drain contact structure connected to the second source / drain region through a space in the fourth source / drain region that is not overlapped with the second source / drain region in the vertical direction, wherein the second source / drain region is partially overlapped with the fourth source / drain region in the vertical direction, and wherein at least one of the at least two first channel layers is partially overlapped with any one of the at least two second channel layers in the vertical direction.

[0014] The structural characteristics of the semiconductor device disclosed in the above embodiments enable the acquisition of at least a greater space for direct and straight connections between the source / drain contact structure included in the semiconductor device and the source / drain region of the transistor. Attached Figure Description

[0015] Example embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 This illustrates nanosheet structures for semiconductor devices in the relevant field;

[0017] Figure 2A A multi-stacked nanosheet structure according to an embodiment is shown;

[0018] Figure 2B The following is illustrated according to an embodiment: Figure 2A Semiconductor devices constructed from multi-stacked nanosheet structures;

[0019] Figure 3A An exploded perspective view of a semiconductor device including a multi-stacked nanosheet structure according to an embodiment is shown;

[0020] Figure 3B The following is shown according to the embodiment. Figure 3A A cross-sectional view of a semiconductor device taken by line I-I' in the diagram;

[0021] Figure 3C The following is shown according to the embodiment. Figure 3A A cross-sectional view of a semiconductor device taken by line II-II' in the diagram;

[0022] Figure 3D The following is shown according to the embodiment. Figure 3A A cross-sectional view of a semiconductor device taken by line III-III' in the diagram;

[0023] Figure 3E The following is shown according to the embodiment. Figure 3A A cross-sectional view of a semiconductor device taken by line IV-IV' in the diagram;

[0024] Figure 3F It is formed Figure 3A A schematic diagram of an inverter, a portion of a semiconductor device, is shown in the figure.

[0025] Figure 4 A perspective view of an inverter structure included in a semiconductor device having a multi-stacked nanosheet structure, according to an embodiment, is shown.

[0026] Figures 5A to 5C A corresponding diagram of a cross-section of another semiconductor device comprising a multi-stacked nanosheet structure according to an embodiment is shown;

[0027] Figure 6 A hybrid nanosheet structure according to an embodiment is shown.

[0028] Figure 7 A schematic plan view of a semiconductor module according to an embodiment is shown; and

[0029] Figure 8 A schematic block diagram of an electronic system according to an embodiment is shown. Detailed Implementation

[0030] The embodiments described herein are exemplary embodiments, and therefore the inventive concept is not limited thereto and can be implemented in various other forms. Each embodiment provided in the following description does not exclude its relation to one or more features of another example or embodiment also provided herein or not provided herein but consistent with the inventive concept. For example, even if a matter described in a particular example or embodiment is not described in a different example or embodiment, such matter may be understood to be related to or combined with a different example or embodiment, unless otherwise stated in its description. Furthermore, it should be understood that all descriptions of the principles, aspects, examples, and embodiments of the inventive concept are intended to cover equivalents of their structure and function. Moreover, these equivalents should be understood to include not only currently known equivalents but also equivalents to be developed in the future, i.e., all devices invented to perform the same function, regardless of their structure. For example, the MOSFET described herein may take the form of different types or forms of transistors, provided that the inventive concept can be applied to them.

[0031] It will be understood that when an element, component, layer, pattern, structure, region, etc., of a semiconductor device (hereinafter collectively referred to as "element") is described as being "above," "on," "below," "under," "connected to," or "bonded to" another element of the semiconductor device, the element may be directly above, above, below, under, or directly connected to or directly bonded to the other element, or there may be intermediate elements present. In contrast, when an element of a semiconductor device is described as being "directly above," "above," "below," "under," "under," "connected to," or "directly bonded to" another element of the semiconductor device, no intermediate elements are present. Throughout this disclosure, the same reference numerals refer to the same elements.

[0032] For ease of description, spatial relative terms such as “above,” “over,” “on,” “upper,” “below,” “below,” “under,” “lower,” etc., as shown in the figure, are used to describe the relationship between one element and another (or other elements). It will be understood that, in addition to the orientation depicted in the figure, the spatial relative terms are intended to cover different orientations of the semiconductor device during use or operation. For example, if the semiconductor device in the figure were flipped, an element described as “below” or “under” other elements would then be positioned “above” said other elements. Thus, the term “below” can cover both upper and lower orientations. The semiconductor device may be otherwise positioned (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0033] It will be understood that although the terms first, second, third, fourth, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, even if an element is described as "second" in the claims but not as "first" in the specification or claims, the "second" element can still be distinguished from another element, and the "second" element described in the specification can be referred to as the "first" element in the claims.

[0034] As used herein, when a statement such as “at least one of…” follows a list of elements, it modifies the entire list of elements, but not individual elements within that list. For example, the statement “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0035] It will be understood that although the terms first, second, third, fourth, etc., may be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the inventive concept, the first element discussed below may be referred to as the second element.

[0036] Numerous embodiments are described herein with reference to cross-sectional views as schematic illustrations of examples (and intermediate structures). Thus, variations in the illustrated shapes are expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments should not be construed as limited to the specific shapes of the areas shown herein, but will include shape deviations, for example, due to manufacturing processes. For instance, an injection area shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from an injection area to a non-injection area. Similarly, the buried region formed by injection results in some injection in the area between the buried region and the surface through which the injection occurs. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the inventive concept. Furthermore, the dimensions and relative sizes of layers and regions may be exaggerated in the figures for clarity.

[0037] It will be understood beforehand that some elements shown in the accompanying drawings without reference numerals or characters are elements included in conventional semiconductor devices and are well known in the art. For example, dielectric layers are disposed in corresponding locations within the semiconductor device to insulate adjacent elements. These dielectric layers may be formed of silicon or silicon compounds (such as SiO, SiO2, silicon nitride (SiN)), but are not limited thereto. It will also be understood that, for the sake of brevity, some elements common to conventional semiconductor devices may be omitted in the following description and accompanying drawings.

[0038] According to an embodiment, Figure 1 The nanosheet structure 100 shown can also be stacked vertically to form a multi-stacked nanosheet structure, thereby achieving increased device density gain.

[0039] Figure 2A A multi-stacked nanosheet structure comprising two sets of nanosheet layers is shown according to an embodiment. The multi-stacked nanosheet structure 200A shown in FIG2 includes a first channel group 210 of a plurality of first nanosheet layers and a second channel group 220 of a plurality of second nanosheet layers stacked vertically in a stacked manner on a substrate 205 in the D3 direction, and an isolation layer 230 is located between the first channel group 210 of the plurality of first nanosheet layers and the second channel group 220 of the plurality of second nanosheet layers.

[0040] Each of the first channel group 210 and the second channel group 220 can be connected with Figure 1 The nanosheets 110 shown employ substantially the same structure. Therefore, each first nanosheet of the first channel group 210 can have the same width and the same length as each second nanosheet of the second channel group 220. Furthermore, the first channel group 210 and the second channel group 220 can have the same number of nanosheets, for example, as... Figure 2A The three shown.

[0041] and Figure 1 Similar to the nanosheets 110, the first nanosheets of the first channel group 210 are completely surrounded by the first gate structure 215, except that the lower source / drain regions will grow in the first gate structure 215 to construct the lower transistor. Figure 2B At the opening ends on two opposite sides of the first transistor 201, and the second nanosheets of the second channel group 220 are completely surrounded by the second gate structure 225, except that the upper source / drain regions will be grown in the second gate structure 225 to construct the upper transistor ( Figure 2B The lower transistor (202) is located at the openings on two opposite sides of the second transistor (202). Here, according to the embodiment, the lower transistor may be one of a p-type MOSFET (PMOS) and an n-type MOSFET (NMOS), and the upper transistor may be the other of an NMOS and a PMOS.

[0042] Using this multi-stacked nanosheet structure, semiconductor devices constructed from it can achieve improved density gain.

[0043] Figure 2B The following is illustrated according to an embodiment: Figure 2A Semiconductor devices constructed from nanosheet structures.

[0044] Reference Figure 2B Semiconductor device 200B includes and Figure 2A The first channel group 210 (not shown) and the second channel group 220 (not shown) of the multi-stacked nanosheet structure 200A are identical. Additionally, the semiconductor device 200B has a first source / drain region 211 and a second source / drain region 212 formed at the two ends of the first nanosheet layer in the D2 direction of the first channel group that are not surrounded by the first gate structure 215, thereby constituting a first transistor 201 that may be an NMOS. Furthermore, the semiconductor device 200B has a third source / drain region 213 and a fourth source / drain region 214 formed at the two ends of the second nanosheet layer in the D2 direction of the second channel group that are not surrounded by the second gate structure 225, thereby constituting a second transistor 202 that may be a PMOS. These two MOSFETs can form an inverter circuit commonly used in semiconductor devices.

[0045] Semiconductor device 200B also includes a first source / drain contact structure 221, a second source / drain contact structure 222, a third source / drain contact structure 223, and a fourth source / drain contact structure 224 to connect the first source / drain region 211 to the fourth source / drain region 214 to internal circuit elements and / or power supplies (not shown), respectively. The first source / drain contact structure 221, the second source / drain contact structure 222, the third source / drain contact structure 223, and the fourth source / drain contact structure 224 may include, but are not limited to, conductive materials such as conductive metallic materials such as cobalt (Co), tungsten (W), ruthenium (Ru), or combinations thereof. The source / drain contact structures 221 to 224 may extend from other back-end process (BEOL) elements (such as a metal pattern (not shown) formed over a transistor) to connect to the first source / drain region 211 to the fourth source / drain region 214, respectively. However, according to the embodiment, because the first transistor 201 is vertically stacked with the second transistor 202, which has substantially the same shape as described above, the first source / drain contact structure 221 and the second source / drain contact structure 222 can be bent to connect respectively to the first source / drain region 211 and the second source / drain region 212 of the first transistor 201, which are respectively formed below the third source / drain region 213 and the fourth source / drain region 214 of the second transistor 202, as shown below. Figure 2B As shown in the image.

[0046] According to an embodiment, the first source / drain contact structure 221 and the second source / drain contact structure 222 can be connected from below. In this case, the metal pattern that connects the first source / drain region 211 and the second source / drain region 212 to the first source / drain contact structure 221 and the second source / drain contact structure 222 respectively can be buried in the substrate 205.

[0047] When the first source / drain contact structure 221 and the second source / drain contact structure 222 need to be as follows Figure 2B When the bending shown or the need to connect to the metal pattern embedded in the substrate 205 to connect with the first source / drain region 211 and the second source / drain region 212 of the first transistor 201 are present, Figure 2B The semiconductor device 220B shown may require additional metal patterns in the BEOL structure to increase the metal spacing, or the metal patterns may need to be buried in the substrate 205, which would increase the size of the semiconductor device and / or add more complexity to the manufacturing process of the semiconductor device. Therefore, the embodiments described below provide an improved multi-stacked transistor structure.

[0048] Figure 3A An exploded perspective view of a semiconductor device comprising a multi-stacked nanosheet structure according to an embodiment is shown.

[0049] Figure 3B It shows along Figure 3A A cross-sectional view of a semiconductor device taken by line I-I'. Figure 3C It shows along Figure 3A A cross-sectional view of a semiconductor device taken from line II-II'. Figure 3D It shows along Figure 3A A cross-sectional view of a semiconductor device taken from line III-III'. Figure 3E It shows along Figure 3A A cross-sectional view of a semiconductor device taken by line IV-IV'. Figure 3F It is formed as described later. Figure 3A The diagram shows a schematic of an inverter circuit, which is a part of a semiconductor device.

[0050] Reference Figures 3A to 3D The semiconductor device 300 according to the embodiment includes a semiconductor device with a semiconductor device 30 ... Figure 2A The formation Figure 2B The semiconductor device 200B has a multi-stacked nanosheet structure substantially similar to that of the semiconductor device 200A. Therefore, the semiconductor device 300 includes a first transistor 301 and a second transistor 302. The first transistor 301 includes a first channel group 310 comprising a plurality of first nanosheet layers, and the second transistor 302 includes a second channel group 320 comprising a plurality of second nanosheet layers vertically stacked above the first transistor 301 in the D3 direction. Furthermore, each first nanosheet layer is completely surrounded by a first gate structure 315, and each second nanosheet layer is completely surrounded by a second gate structure 325. Additionally, the first nanosheet layers are vertically stacked in a stacked manner above the substrate 305 in the D3 direction. The first nanosheet layers and... Figure 1The nanosheets 110 shown all have substantially the same width W1 in the D1 direction and substantially the same length L1 in the D2 direction. The second nanosheet and... Figure 1 The nanosheets 110 shown all have substantially the same width W2 in the D1 direction and substantially the same length L2 in the D2 direction.

[0051] However, the semiconductor device 300 differs from the multi-stacked nanosheet structure 200A and the semiconductor device 200B in the following ways.

[0052] First, according to an embodiment, the first nanosheet layer of the first channel group 310 has a wider width than the second nanosheet layer of the second channel group 320, allowing the semiconductor device 300 to have a stepped multi-stacked nanosheet structure. Here, although Figures 3A to 3C It is shown that the first nanosheets all have the same width W1 and the second nanosheets all have the same width W2, which is smaller than the width W1, but the inventive concept is not limited thereto. According to an embodiment, the first channel group 310 and the second channel group 320 can be configured such that the width of the nanosheet with the largest width among the second nanosheets is smaller than the width of the nanosheet with the smallest width among the first nanosheets.

[0053] Secondly, according to the embodiment, the second channel group 320 has more nanosheets than the first channel group 310. Figures 3A to 3E The diagram shows a first channel group 310 having two nanosheets and a second channel group 320 having three nanosheets. However, the inventive concept is not limited thereto. According to embodiments, the two channel groups 310 and 320 may have different numbers of nanosheets, as long as the second channel group 320 has more nanosheets than the first channel group 310.

[0054] Third, according to embodiments, although the first nanosheets in the semiconductor device 300 all have the same length L1 in the D2 direction, and the second nanosheets all have the same length L2 in the D2 direction, these lengths of the first and second nanosheets are different between the first channel group 310 and the second channel group 320 within a portion of the semiconductor device 300. Specifically, the length L1 of the first nanosheet is greater than the length L2 of the second nanosheet. However, the inventive concept is not limited thereto. According to embodiments, the first channel group 310 and the second channel group 320 can be configured such that the length of the nanosheet with the largest length among the second nanosheets is smaller than the length of the nanosheet with the smallest length among the first nanosheets.

[0055] Here, according to the embodiment, the first transistor 301 and the second transistor 302 can be NMOS and PMOS, respectively, to form its schematic diagram in Figure 3FThe inverter circuit shown is illustrated below, and the following description is based on this embodiment. However, the inventive concept is not limited thereto. According to the embodiment, the first transistor 301 and the second transistor 302 may be PMOS and NMOS respectively, or both may be PMOS or NMOS, to form different circuit elements.

[0056] The second transistor 302 is stacked above the first transistor 301, and an isolation layer 330 is formed between the second transistor 302 and the first transistor 301. The isolation layer 330 is formed between the first channel group 310 and the second channel group 320 to isolate the two transistors 301 and 302. The isolation layer 330 may be formed of SiO or silicon dioxide (SiO2), and is not limited thereto.

[0057] Each of the first gate structure 315 and the second gate structure 325 is formed in an early step of the manufacturing process of the semiconductor device 300 by replacing the dummy gate structure filled between and around the first and second nanosheets.

[0058] The first source / drain region 311 and the second source / drain region 312 are respectively formed at both ends of the first channel group 310 of the first nanosheet layer in the D2 direction to form the first transistor 301, and the third source / drain region 313 and the fourth source / drain region 314 are respectively formed at both ends of the second channel group 320 of the second nanosheet layer in the same D2 direction to form the second transistor 302. The first source / drain region 311 and the second source / drain region 312 can be formed by epitaxially growing a silicon layer of the first nanosheet layer of the first channel group 310 at a location where the first nanosheet layer is not surrounded by the first gate structure 315. The third source / drain region 313 and the fourth source / drain region 314 can be formed by epitaxially growing a silicon layer of the second nanosheet layer of the second channel group 320 at a location where the second nanosheet layer is not surrounded by the second gate structure 325.

[0059] Return to reference Figures 3A to 3E The first channel group 310 has two nanosheets and the second channel group 320 has three nanosheets to form corresponding transistors 301 and 302 of the inverter circuit. This difference in the number of nanosheets in the two channel groups 310 and 320 is caused by the size difference between the first nanosheets included in the first channel group 310 and the second nanosheets included in the second channel group 320. Specifically, since the width W2 of the second nanosheets included in the second channel group 320 is shorter than the width W1 of the first nanosheets included in the first channel group 310, the second channel group 320 has additional nanosheets compared to the first channel group 310, such that the first channel group 310 and the second channel group 320 can have substantially the same effective channel width (W1). effFor example, the sum of the effective channel widths of the first nanosheets is equal to the sum of the effective channel widths of the second nanosheets. Therefore, according to an embodiment, based on the width difference between the first nanosheets in the first channel group 310 and the second nanosheets in the second channel group 320, the second channel group 320 may have more nanosheets than the first channel group 310.

[0060] Meanwhile, according to the embodiment, since the second nanosheet in the second channel group 320 has a width W2 that is smaller than the width W1 of the first nanosheet in the first channel group 310, the third source / drain region 313 and the fourth source / drain region 314 can be formed to have a width W4 that is smaller than the width W3 of the first source / drain region 311 and the second source / drain region 312, respectively.

[0061] Figures 3A to 3E The semiconductor device 300 according to an embodiment is also shown, including a first source / drain contact structure 321, a second source / drain contact structure 322, and a third source / drain contact structure 323, a first via structure 331, a second via structure 332, a third via structure 333, and a fifth via structure 335, and a first metal pattern 341, a second metal pattern 342, a third metal pattern 343, a fourth metal pattern 344, and a fifth metal pattern 345 arranged at predetermined intervals in the D1 direction. The first metal pattern 341, the second metal pattern 342, the third metal pattern 343, the fourth metal pattern 344, and the fifth metal pattern 345 may constitute a metal layer 340. The metal layer 340 may be buried in an insulating layer disposed on the first transistor 301 and the second transistor 302.

[0062] The first source / drain contact structure 321 is connected to the first metal pattern 341, which provides the negative power supply voltage Vss, through the first via structure 331, and is also connected to the first source / drain region 311 of the first transistor 301. Therefore, the first source / drain region 311 can be used as the source of the transistor 301, which may be an NMOS transistor.

[0063] According to an embodiment, the second source / drain contact structure 322 is connected to both the second source / drain region 312 of the first transistor 301 and the fourth source / drain region 314 of the second transistor 302 via a second via structure 332, because the two transistors 301 and 302 form a structure having such a structure as shown in the embodiment. Figure 3F The inverter circuit for the common output node Vout is shown in the figure. Here, the second source / drain region 312 is used as the drain of transistor 301 (NMOS), and the fourth source / drain region 314 is used as the drain of transistor 302 (PMOS).

[0064] The third source / drain contact structure 323 is connected to the fifth metal pattern 345, which provides the positive power supply voltage Vdd, through the fifth via structure 335, and is also connected to the third source / drain region 313 of the second transistor 302. Therefore, the third source / drain region 313 can be used as the source of the transistor 302 (PMOS).

[0065] Reference Figure 3A and Figure 3D The second source / drain contact structure 322 extends straight downward from the second metal pattern 342 through the second via structure 332 to pass through the side surface of the fourth source / drain region 314 and bond to the second source / drain region 312. As described above, the smaller width of the fourth source / drain region 314 caused by the smaller width of the second nanosheet of the second channel group 320 makes this straight downward connection between the second source / drain contact structure 322 and both the second source / drain region 312 and the fourth source / drain region 314 possible. Otherwise, when the width W2 of the second nanosheet of the second channel group 320 is not smaller than the width W1 of the first nanosheet of the first channel group 310, and therefore the width W4 of the fourth source / drain region 314 is not smaller than the width W3 of the second source / drain region 312, such as Figure 2B As discussed in the previous embodiments, forming the second source / drain contact structure 322 can be complex. In other words, since the second source / drain contact structure 322, connected to the second metal pattern 342, can extend straight down to engage only on the fourth source / drain region 314, additional source / drain contact structures connected to another metal pattern formed above the fourth source / drain region 314 may have to be formed as follows: Figure 2B The bending shown to connect to the second source / drain region 312, or the separate metal structure that would require connecting the second source / drain region 312 and the fourth source / drain region 314, would be required unless the additional source / drain contact structure is buried in the substrate 305, thereby complicating the manufacturing process of the semiconductor device 300.

[0066] The aforementioned structural characteristics of the semiconductor device 300 from Figure 3A and Figure 3E It is obvious in the middle, Figure 3A and Figure 3E The first source / drain contact structure 321 is shown to extend directly downward from the first metal pattern 341 through the space allowed by the smaller width W4 of the third source / drain region 313 to engage with the first source / drain region 311. Therefore, similar to the second source / drain contact structure 322, the first source / drain contact structure 321 does not need to be bent or buried in the substrate 305.

[0067] According to the embodiment, the widths between the first nanosheets in the first channel group 310 and between the second nanosheets in the second channel group 320 can be set differently, as long as the fourth source / drain region 314 can have a width smaller than that of the second source / drain region 312, allowing the second source / drain contact structure 322 to extend directly downward to engage on the top surface of the second source / drain region 312 and form a lateral contact on the side surface of the fourth source / drain region 314, as described above. Figure 3A and Figure 3D For example, the second nanosheet layer can have a width much smaller than that of the first nanosheet layer to allow more space for source / drain contact structure connections. In this case, the second channel group 320 can have more second nanosheet layers. Specifically, when the second source / drain contact structure 322 does not need to be connected to both the second source / drain region 312 and the fourth source / drain region 314, for example, when the first transistor 301 and the second transistor 302 constitute a circuit different from the inverter circuit, the second source / drain contact structure 322 can be formed such that it does not form a lateral contact on the side surface of the fourth source / drain region 314 of the second transistor 302, but forms a direct, straight-down contact on the top surface of the second source / drain region 312 of the first transistor 301. In this case, another source / drain contact structure can be bonded to the top surface of the fourth source / drain region 314.

[0068] Additionally, according to embodiments, other dimensions such as length and width can be set differently between the first nanosheets in the first channel group 310 and between the second nanosheets in the second channel group 320, provided that the fourth source / drain region 314 can have a width smaller than the width of the second source / drain region 312 such that the second source / drain contact structure 322 can extend directly downward as described above to connect to the second source / drain region 312 with or without passing through the fourth source / drain region 314, and furthermore, provided that the first channel group 310 and the second channel group 320 can have substantially the same effective channel width (W). eff ).

[0069] In order to form its schematic diagram Figure 3F The inverter circuit shown in the figure, Figures 3A to 3F It is also shown that the first gate structure 315 of the first transistor 301 and the second gate structure 325 of the second transistor 302 are connected to each other to receive the same gate input signal Vin from the third metal pattern 343 through the third via structure 333. Here, the third via structure 333 may be referred to as the gate contact structure.

[0070] at the same time, Figure 3A and Figure 3BThe first channel group 310 and the second channel group 320 are shown with extended channel portions at their ends in the D2 direction. These extended channel portions are provided to form additional semiconductor devices besides the inverter. Therefore, the fourth metal pattern 344 can be retained to connect to one or more elements of other semiconductor devices covered by the semiconductor device 300.

[0071] Figure 4 A perspective view of an inverter structure included in a semiconductor device formed of two sets of nanosheet layers, according to an embodiment, is shown.

[0072] Figure 4 The inverter structure 400 shown is from Figure 3A A perspective view of the inverter portion of the semiconductor device 300 shown from the opposite direction.

[0073] The inverter structure 400 includes a first channel group 310 of multiple first nanosheets and a second channel group 320 of multiple second nanosheets formed on a substrate 305 to form transistors 301 (NMOS) and 302 (PMOS), respectively. The first nanosheets are surrounded by a first gate structure 315, and the second nanosheets are surrounded by a second gate structure 325. A first source / drain region 311, a second source / drain region 312, a third source / drain region 313, and a fourth source / drain region 314 are connected to the two ends of the first channel group 310 and the two ends of the second channel group 320, respectively, in the D2 direction. Here, it is understood that since these first source / drain regions 311, second source / drain regions 312, third source / drain regions 313, and fourth source / drain regions 314 respectively cover the first and second nanosheets, therefore... Figure 4 The first and second nanosheets are not visible. Figure 4 Only a perspective view of the inverter portion of the semiconductor device 300 is shown. The inverter structure 400 also includes a first source / drain contact structure 321, a second source / drain contact structure 322 and a third source / drain contact structure 323, a first via structure 331, a second via structure 332, a third via structure 333 and a fifth via structure 335, and a first metal pattern 341, a second metal pattern 342, a third metal pattern 343, a fourth metal pattern 344 and a fifth metal pattern 345 arranged at predetermined intervals in the D1 direction.

[0074] Figures 5A to 5C A corresponding diagram of a cross-section of another semiconductor device comprising a multi-stacked nanosheet structure according to an embodiment is shown. Figures 5A to 5C and Figures 3C to 3E correspond.

[0075] Reference Figures 5A to 5CAccording to an embodiment, a semiconductor device 500 includes a first channel group 510 of a plurality of first nanosheets and a second channel group 520 of a plurality of second nanosheets formed on a substrate 505 to form an NMOS 501 and a PMOS 502, respectively. Each first nanosheet is surrounded by a first gate structure 515, and each second nanosheet is surrounded by a second gate structure 525. A first source / drain region 511, a second source / drain region 512, a third source / drain region 513, and a fourth source / drain region 514 are respectively connected to the two ends of the first channel group 510 and the two ends of the second channel group 520 in the D2 direction. Here, it is understood that since these first source / drain regions 511, second source / drain regions 512, third source / drain regions 513, and fourth source / drain regions 514 can be epitaxially grown from the first nanosheets and the second nanosheets, respectively, they are shown only in cross-sectional views. Figure 5A and Figure 5C The first and second nanosheets are not visible. The aforementioned elements of the semiconductor device 500 have... Figures 3A to 3E The semiconductor device 300 shown has the same structural characteristics as the one described above (including the smaller width of the second nanosheet layer and the smaller width of the third source / drain region 513 and the fourth source / drain region 514). Therefore, its detailed description is omitted here.

[0076] However, the semiconductor device 500 differs from the semiconductor device 300 in its source / drain contact structure, via structure, and metal pattern, as described below.

[0077] Although all the metal patterns 341, 342, 343, 344 and 345 are formed on the metal layer 340 disposed on the top of the semiconductor device 300, only the second metal pattern 542, the third metal pattern 543 and the fifth metal pattern 545 are formed on the metal layer 540 disposed on the top of the semiconductor device 500, and instead, the first metal pattern 541 and the fourth metal pattern 544 are buried in the substrate 505.

[0078] Due to these structural characteristics, the first source / drain contact structure 521 can extend vertically upwards from the first metal pattern 541 buried in the substrate 505. The first metal pattern 541 provides a negative supply voltage Vss to the first source / drain region 511 of the NMOS 501 through the first source / drain contact structure 521. Figures 3A to 3E Similar to the semiconductor device 300 shown, a fourth metal pattern 544 is retained to connect to one or more elements of other semiconductor devices covered by the semiconductor device 500.

[0079] Conversely, the second source / drain contact structure 522, connected to the second metal pattern 542 via the second via structure 532, extends straight downwards to pass through the side surface of the fourth source / drain region 514 and engages with the second source / drain region 512. (As in...) Figures 3A to 3E In the previous embodiment, the smaller width of the fourth source / drain region 514 caused by the smaller width of the second nanosheet layer makes it possible for the second source / drain contact structure 522 to be connected vertically to both the second source / drain region 512 and the fourth source / drain region 514.

[0080] The third source / drain contact structure 523 is connected to the fifth metal pattern 545, which provides the positive power supply voltage Vdd, through the fifth via structure 535, and is also connected to the third source / drain region 513 of the PMOS 502.

[0081] The third metal pattern 543 provides the gate input signal Vin to the first gate structure 515 and the second gate structure 525 through the third via structure 533. Here, the third via structure 533 can be referred to as the gate contact structure.

[0082] Taking advantage of the above structural differences, semiconductor device 500 can be manufactured with only two metal pitches between the second metal pattern 542, the third metal pattern 543 and the fifth metal pattern 545, while semiconductor device 300 requires four metal pitches between the first metal pattern 341, the second metal pattern 342, the third metal pattern 343, the fourth metal pattern 344 and the fifth metal pattern 345.

[0083] In the above embodiments, semiconductor devices 300, 500 and inverter structure 400 have only two channel groups, each of which is formed from multiple nanosheet layers. However, the inventive concept is not limited thereto. According to embodiments, more than two channel groups can be stacked to form different semiconductor devices in which the lowest-positioned channel group and the source / drain regions connected to that channel group are not completely superimposed with the upper-positioned channel groups and the source / drain regions connected to those channel groups.

[0084] Furthermore, in the above embodiments, each channel group of the semiconductor device is formed of multiple nanosheet layers. However, the inventive concept is not limited thereto. Hybrid nanosheet structures can be provided according to the embodiments described below.

[0085] Figure 6 A hybrid semiconductor device according to an embodiment is shown.

[0086] A hybrid semiconductor device 600 according to an embodiment includes a first channel group 610 of a plurality of nanosheet layers in a lower stack of a semiconductor device 500. Figure 2ASimilar to the nanosheets of the first channel group 210, the nanosheets of the first channel group 610 in the lower stack of the hybrid semiconductor device 600 are completely surrounded by the first gate structure 615, except at the openings formed at the two opposite sides of the first gate structure 615 where the lower source / drain regions will grow to construct the lower transistor. However, the hybrid semiconductor device 600 includes a second channel group 620 formed by multiple finFET channel layers (i.e., fin structures), the second channel group 620 and Figure 2A The second channel group 220 is different. Each finFET channel layer is not completely surrounded by the second gate structure 625, and instead, the bottom surface of each finFET channel layer contacts the isolation layer 630 or another silicon substrate. However, source / drain regions can be formed at the openings on two opposite sides of the second gate structure 625 formed by the finFET channel layer to form the upper transistor by epitaxy on the finFET channel layer.

[0087] However, the above reference Figures 3A to 3F , Figure 4 as well as Figures 5A to 5C The inventive concept described can still be applied to the hybrid semiconductor device 600. Therefore, according to the embodiment, the hybrid semiconductor device 600 can replace... Figures 3A to 3E or Figures 5A to 5C The nanosheet structure shown is used to construct a hybrid semiconductor device corresponding to semiconductor device 300 or 500. Specifically, by adjusting the width, spacing, height, and / or number of the finFET channel layers (i.e., fin structures) of the second channel group 620, the width of the source / drain region of the upper transistor formed by the second channel group 620 can be made smaller than the width of the source / drain region of the lower transistor formed by the first channel group 610. Therefore, it is possible to obtain... Figures 3A to 3E and Figures 5A to 5C The source / drain contact structure shown in the previous embodiment is substantially the same as the source / drain contact structure, thereby achieving... Figure 3D and Figure 5A The method shown is essentially the same as implementing a direct, straight-down connection from the metal pattern of the BEOL to one of the source / drain regions of the lower transistor.

[0088] According to embodiments, the inventive concept can also be applied to different types of hybrid semiconductor devices. For example, in a hybrid semiconductor device according to an embodiment, Figure 6 The upper stacked first channel group 610 of the finFET channel layer and the lower stacked second channel group 620 of the nanosheet layer shown can be used with... Figure 6 The embodiments shown are formed in reverse order at the lower and upper stacks of the hybrid semiconductor device. Furthermore, in the hybrid semiconductor device according to the embodiments, Figure 6The upper stacked first channel group 610 of the finFET channel layer shown can be formed at both the lower stack and the upper stack of the hybrid semiconductor device. Still in these embodiments, the width, spacing, height and / or number of the channel layers of the lower stack transistor structure and / or the upper stack transistor structure can be adjusted relative to the lower stack transistor to achieve the same inventive concept described above.

[0089] Figure 7 A schematic plan view of a semiconductor module according to an embodiment is shown.

[0090] Reference Figure 7 The semiconductor module 700 according to the embodiments may include a processor 720 and a semiconductor device 730 mounted on a module substrate 710. The processor 720 and / or the semiconductor device 730 may include one or more multi-stacked transistor structures described in the above embodiments.

[0091] Figure 8 A schematic block diagram of an electronic system according to an embodiment is shown.

[0092] Reference Figure 8 The electronic system 800 according to an embodiment may include a microprocessor 810, a memory 820, and a user interface 830 that perform data communication using a bus 840. The microprocessor 810 may include a central processing unit (CPU) or an application processor (AP). The electronic system 800 may also include random access memory (RAM) 850 that communicates directly with the microprocessor 810. The microprocessor 810 and / or RAM 850 may be implemented in a single module or package. The user interface 830 may be used to input data into or output data from the electronic system 800. For example, the user interface 830 may include a keyboard, touchpad, touchscreen, mouse, scanner, voice detector, liquid crystal display (LCD), micro light-emitting device (LED), organic light-emitting diode (OLED) device, active matrix light-emitting diode (AMOLED) device, printer, lighting equipment, or various other input / output devices, without limitation. The memory 820 may store the operating code of the microprocessor 810, data processed by the microprocessor 810, or data received from external devices. The memory 820 may include a memory controller, a hard disk, or a solid-state drive (SSD).

[0093] At least the microprocessor 810, memory 820, and / or RAM 850 in the electronic system 800 may include one or more multi-stacked transistor structures described in the above embodiments.

[0094] Due to the differences in structural dimensions (such as the width of the channel layer) between the multiple stacked bodies in the aforementioned multi-stacked transistor structure, more space can be obtained during the fabrication of the semiconductor device for direct and straight connections between the source / drain contact structure and the source / drain regions of the multi-stacked transistors. Furthermore, when the metal pattern connected to the power supply is buried within the substrate of the multi-stacked transistor, the metal spacing can be reduced to decrease the size of the semiconductor device.

[0095] The foregoing is an illustrative description of exemplary embodiments and should not be construed as limiting them. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the above embodiments without substantially departing from the inventive concept.

Claims

1. A semiconductor device, the semiconductor device comprising: Base; A first transistor is formed on a substrate. The first transistor includes a first channel group of a plurality of first nanosheets, a first gate structure surrounding the plurality of first nanosheets, and a first source / drain region and a second source / drain region located at both ends of the first channel group. The second transistor is formed vertically above the first transistor. The second transistor includes a second channel group of multiple second nanosheets, a second gate structure surrounding the multiple second nanosheets, and a third source / drain region and a fourth source / drain region located at both ends of the second channel group. as well as The source / drain contact structure connects to the second source / drain region through a space where the fourth source / drain region is not vertically superimposed on the second source / drain region. The second source / drain region has a wider width than the fourth source / drain region, such that the fourth source / drain region is vertically superimposed only on a portion of the second source / drain region. Wherein, the sum of the effective channel widths of the plurality of first nanosheets is equal to the sum of the effective channel widths of the plurality of second nanosheets.

2. The semiconductor device according to claim 1, wherein, The source / drain contact structure makes lateral contact with the side surface of the fourth source / drain region and with the top surface of the second source / drain region.

3. The semiconductor device according to claim 1, wherein, The plurality of first nanosheets have a width greater than the plurality of second nanosheets, and The second channel group is vertically superimposed only on a portion of the first channel group.

4. The semiconductor device according to claim 1, wherein, The first source / drain region has a wider width than the third source / drain region.

5. The semiconductor device according to claim 1 or 2, wherein, The width of the second nanosheet with the largest width among the plurality of second nanosheets is smaller than the width of the first nanosheet with the smallest width among the plurality of first nanosheets.

6. The semiconductor device according to claim 5, wherein, The number of the plurality of second nanosheets is greater than the number of the plurality of first nanosheets.

7. The semiconductor device according to claim 6, further comprising: A gate contact structure is connected to at least a second gate structure; The first source / drain contact structure is connected to the first source / drain region; as well as The third source / drain contact structure is connected to the third source / drain region. Among them, the source / drain contact structure that connects to the second source / drain region through the space where the fourth source / drain region is not vertically superimposed with the second source / drain region is the second source / drain contact structure, wherein the second source / drain contact structure laterally contacts the side surface of the fourth source / drain region and contacts the top surface of the second source / drain region.

8. The semiconductor device according to claim 7, further comprising: A first metal pattern, a second metal pattern, a third metal pattern, and a fourth metal pattern are formed above the second transistor. The first metal pattern is connected to the first source / drain contact structure to provide one of a positive power supply voltage and a negative power supply voltage. The second metal pattern is connected to the second source / drain contact structure. The third metal pattern is connected to the gate contact structure, and The fourth metal pattern is connected to the third source / drain contact structure to provide the other of the positive and negative power supply voltages.

9. The semiconductor device according to claim 8, further comprising: A fifth metal pattern is formed above the second transistor and positioned between the third and fourth metal patterns.

10. The semiconductor device of claim 7, further comprising: The first metallic pattern is embedded in the base. And a second metal pattern, a third metal pattern, and a fourth metal pattern are formed above the second transistor. The first metal pattern is connected to the first source / drain contact structure to provide one of a positive power supply voltage and a negative power supply voltage. The second metal pattern is connected to the second source / drain contact structure. The third metal pattern is connected to the gate contact structure, and The fourth metal pattern is connected to the third source / drain contact structure to provide the other of the positive and negative power supply voltages.

11. The semiconductor device according to claim 10, wherein, The first transistor and the second transistor are formed in an inverter with a dimension of two metal pitches in the channel width direction.

12. A semiconductor device, the semiconductor device comprising: Base; A first transistor is formed on a substrate. The first transistor includes a first channel group of a plurality of first nanosheets, a first gate structure surrounding the plurality of first nanosheets, and a first source / drain region and a second source / drain region located at both ends of the first channel group. as well as The second transistor is formed vertically above the first transistor. The second transistor includes a second channel group of multiple second nanosheets, a second gate structure surrounding the multiple second nanosheets, and a third source / drain region and a fourth source / drain region located at both ends of the second channel group. The first channel group has a wider width than the second channel group. Wherein, the number of the plurality of first nanosheets is smaller than the number of the plurality of second nanosheets, and Wherein, the sum of the effective channel widths of the plurality of first nanosheets is equal to the sum of the effective channel widths of the plurality of second nanosheets.

13. The semiconductor device according to claim 12, wherein, The second channel group is vertically superimposed only on a portion of the first channel group.

14. The semiconductor device according to claim 13, wherein, The second source / drain region has a width greater than that of the fourth source / drain region, such that the fourth source / drain region is vertically superimposed only on a portion of the second source / drain region.

15. The semiconductor device according to claim 14, wherein, The first source / drain region has a wider width than the third source / drain region.

16. The semiconductor device of claim 14, further comprising: The source / drain contact structure is connected to the second source / drain region through a space where the fourth source / drain region is not vertically superimposed with the second source / drain region.

17. The semiconductor device of claim 16, further comprising: A gate contact structure is connected to at least a second gate structure; The first source / drain contact structure is connected to the first source / drain region; as well as The third source / drain contact structure is connected to the third source / drain region. Among them, the source / drain contact structure that connects to the second source / drain region through the space where the fourth source / drain region is not vertically superimposed with the second source / drain region is the second source / drain contact structure, and The second source / drain contact structure laterally contacts the side surface of the fourth source / drain region and the top surface of the second source / drain region.

18. The semiconductor device of claim 17, further comprising: A first metal pattern, a second metal pattern, a third metal pattern, and a fourth metal pattern are formed on the second transistor. The first metal pattern is connected to the first source / drain contact structure to provide one of a positive power supply voltage and a negative power supply voltage. The second metal pattern is connected to the second source / drain contact structure. The third metal pattern is connected to the gate contact structure, and The fourth metal pattern is connected to the third source / drain contact structure to provide the other of the positive and negative power supply voltages.

19. The semiconductor device of claim 18, further comprising: A fifth metal pattern is formed above the second transistor and positioned between the third and fourth metal patterns.

20. The semiconductor device of claim 17, further comprising: The first metallic pattern is embedded in the base. And a second metal pattern, a third metal pattern, and a fourth metal pattern are formed above the second transistor. The first metal pattern is connected to the first source / drain contact structure to provide one of a positive power supply voltage and a negative power supply voltage. The second metal pattern is connected to the second source / drain contact structure. The third metal pattern is connected to the gate contact structure, and The fourth metal pattern is connected to the third source / drain contact structure to provide the other of the positive and negative power supply voltages.

21. The semiconductor device according to claim 20, wherein, The first transistor and the second transistor form an inverter having two metal spacings in the channel width direction.

22. A semiconductor device, the semiconductor device comprising: Base; A first transistor is formed on a substrate, and the first transistor includes at least two first channel layers and a first source / drain region and a second source / drain region. A second transistor is stacked vertically above a first transistor, and the second transistor includes at least two second channel layers and a third source / drain region and a fourth source / drain region; and The source / drain contact structure connects to the second source / drain region through a space in the fourth source / drain region that does not overlap with the second source / drain region in the vertical direction. The second source / drain region partially overlaps with the fourth source / drain region in the vertical direction. Wherein, at least one of the at least two first channel layers partially overlaps with any one of the at least two second channel layers in the vertical direction. Wherein, the sum of the effective channel widths of the at least two first channel layers is equal to the sum of the effective channel widths of the at least two second channel layers.

23. The semiconductor device according to claim 22, wherein, The at least two first channel layers are nanosheet channels, and the at least two second channel layers are finFET channel layers.

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