Metal oxide semiconductor field effect transistor, manufacturing method and electronic device

Abstract

The application discloses a metal oxide semiconductor field effect transistor, a manufacturing method and an electronic device. The metal oxide semiconductor field effect transistor comprises an active region, isolation structures respectively located on two sides of the active region, a gate oxide layer located on the active region, and two sides of the gate oxide layer respectively in contact with the isolation structures on the two sides of the active region. A gate layer is located on the isolation structures and the gate oxide layer. Two gate non-overlapping regions are respectively formed on the upper two sides of the active region, and the gate non-overlapping regions are covered by the isolation structures. The metal oxide semiconductor field effect transistor has two gate non-overlapping regions on the upper two sides of the active region, which can effectively eliminate the parasitic transistor phenomenon caused by the shallow trench structure and greatly reduce the subthreshold hump phenomenon.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a metal oxide semiconductor field effect transistor, a manufacturing method and an electronic device. BACKGROUND

[0002] STI (Shallow Trench Isolation) technology is an important isolation method for manufacturing high-integration large-scale integrated circuits. However, the electrical properties of a MOSFET manufactured by using an STI isolation structure are affected by the shape of the upper part of the trench isolation and by the different gap filling materials. The field oxide of the STI corner concentrates the electric field due to the recess, and the boron concentration decreases due to the isolation, resulting in the occurrence of a subthreshold hump phenomenon, which changes the characteristics of the MOSFET. The threshold voltage Vth changes according to the gate voltage of the MOSFET, which results in the inability to control the current. As shown in FIG. 1, the active region 5, the first isolation structure 6 (which can be field oxide, for example), the gate oxide layer 3, the polysilicon gate 7, the field crowding region 8, the boron depletion region 9, and the oxide recess region 10 of the prior art MOSFET, the corner part of the field oxide generated in the STI corner generates an electric field concentration phenomenon and a concentration decrease phenomenon caused by the isolation of boron, resulting in the formation of an inverted transistor in the corner part of the channel at a lower gate voltage than the central part, and a parasitic transistor phenomenon occurs. The subthreshold hump phenomenon caused by the parasitic transistor changes the characteristics of the MOSFET, as described above, and the result is a change in the Vth control generated according to the gate voltage, which can cause a loss of control and a significant obstacle to the operation of the circuit. Figures 1-4 SUMMARY

[0003] The object of the present application is to provide a metal oxide semiconductor field effect transistor, a manufacturing method and an electronic device. To have a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not a general review, nor is it intended to determine the key / important components or delineate the scope of protection of these embodiments. Its only purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0004] According to an aspect of an embodiment of the present application, a metal oxide semiconductor field effect transistor is provided, comprising:

[0005] an active region;

[0006] isolation structures respectively located on both sides of the active region;

[0007] a gate oxide layer located on the active region; both sides of the gate oxide layer are in contact with the isolation structures on both sides of the active region;

[0008] ​a gate layer covering the gate oxide layer and the isolation structure.

[0009] The upper two sides of the active region are respectively formed with two gate non-overlapping regions.

[0010] According to another aspect of the embodiments of the present application, a manufacturing method of a metal oxide semiconductor field effect transistor is provided, comprising:

[0011] forming an active region;

[0012] forming an isolation structure on the two sides of the active region;

[0013] forming two gate non-overlapping regions on the upper two sides of the active region respectively;

[0014] covering the two gate non-overlapping regions with the isolation structure;

[0015] forming a gate oxide layer on the active region;

[0016] forming a gate layer covering the gate oxide layer and the isolation structure.

[0017] According to another aspect of the embodiments of the present application, an electronic device is provided, comprising the metal oxide semiconductor field effect transistor described above.

[0018] One of the aspects of the embodiments of the present application can provide technical solutions including the following beneficial effects:

[0019] The metal oxide semiconductor field effect transistor provided by the embodiments of the present application has two gate non-overlapping regions on the upper two sides of the active region, which can effectively eliminate the parasitic transistor phenomenon caused by the shallow trench structure and can greatly reduce the sub-threshold hump phenomenon.

[0020] Other features and advantages of the present application will be described in the following description and, in part, will become apparent from the description or can be learned from the description, or can be realized and attained by practice of the embodiments of the present application. The purposes and other advantages of the present application can be realized and attained by the structure particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0022] Figure 1 A structural diagram of a prior art MOSFET is shown;

[0023] Figure 2 A structural diagram of another view of a prior art MOSFET is shown;

[0024] Figure 3 A structural diagram of another MOSFET of the prior art is shown;

[0025] Figure 4 A structural diagram of a partial portion A of Figure 1 is shown;

[0026] Figure 5 A Vg-Id characteristic curve diagram of a prior art MOSFET is shown;

[0027] Figure 6 A schematic diagram of a metal oxide semiconductor field effect transistor after forming an active region in a manufacturing method of the metal oxide semiconductor field effect transistor according to an embodiment of the present application is shown;

[0028] Figure 7 A schematic diagram of another position of the active region is shown;

[0029] Figure 8 A structural diagram after forming a first nitride layer on the basis of the structure shown in Figure 6 is shown;

[0030] Figure 9 A structural diagram after selectively etching the first nitride layer to expose two first corner sides of a top surface of the active region on the basis of the structure shown in Figure 8 is shown;

[0031] Figure 10 A structural diagram after etching the first corner sides to form a first gate non-overlapping region and a second corner side located above the first gate non-overlapping region on the basis of the structure shown in Figure 9 is shown;

[0032] Figure 11 A structural diagram after forming a second isolation structure on the basis of the structure shown in Figure 10 is shown;

[0033] Figure 12 A structural diagram after forming a second trench on the basis of the structure shown in Figure 11 is shown;

[0034] Figure 13 A structural diagram after forming a gate oxide layer on the basis of the structure shown in Figure 12 is shown;

[0035] Figure 14A structure diagram after forming a gate polysilicon layer on the basis of the structure shown in Figure 13 A structure diagram after forming a gate polysilicon layer on the basis of the structure shown in

[0036] Figure 15 Another diagram corresponding to the structure shown in Figure 14 DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0038] In the drawings, various structure diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and precision, and certain details can be omitted. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the drawings are merely exemplary, and in actuality, they can deviate due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes, and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0039] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly located on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0040] As shown in Figure 15 One embodiment of the present application provides a metal oxide semiconductor field effect transistor, comprising:

[0041] An active region 5; the cross-sectional shape profile of the active region 5 is substantially a right trapezoidal shape.

[0042] A second isolation structure 6'; each side of the active region 5 has a second isolation structure 6'. The second isolation structure 6' has a trench thereon. The second isolation structure 6' can be a field oxide layer or a shallow trench isolation. In this embodiment, the second isolation structure 6' is taken as an example of a field oxide layer. The edge portions of the active region 5 are covered by the second isolation structure 6' respectively.

[0043] ​A gate oxide layer 3 is located on the active region 5. The lateral dimension of the gate oxide layer 3 is smaller than the lateral dimension of the top surface of the active region 5. The gate oxide layer 3 is recessed in the channel direction relative to the second isolation structure 6' on the active region 5. The upper two side edges of the active region 5 are not covered by the gate oxide layer 3. The top surface of the active region 5 is divided into a middle part and two edge parts by the gate oxide layer 3, and the two edge parts are located on both sides of the middle part. The middle part is the part in contact with the gate oxide layer 3. The two edge parts are not in contact with the gate oxide layer 3. The upper two sides of the active region 5 have two gate non-overlapping regions, namely a first gate non-overlapping region 4 and a second gate non-overlapping region 10, and the position of the second gate non-overlapping region 10 is higher than that of the first gate non-overlapping region 4. The two sides of the gate oxide layer 3 are in contact with the second isolation structures 6' on both sides of the active region 5. The gate non-overlapping regions are not in contact with the gate oxide layer 3. The first gate non-overlapping region 4 and the second gate non-overlapping region 10 both include a corner portion, and the angle of the corner in this embodiment is an obtuse angle.

[0044] The gate polysilicon layer 12 covers the second isolation structure 6' and the gate oxide layer 3, and the trenches on the second isolation structure 6' are also filled by the gate polysilicon layer 12.

[0045] The gate polysilicon layer 12 can be replaced with a metal gate layer.

[0046] The cross-sectional shapes of the active region 5 and the second isolation structure 6' are both axisymmetric figures.

[0047] The active region 5 has two non-overlapping gate regions on its upper sides. These non-overlapping gate regions can effectively eliminate the parasitic transistor phenomenon generated by the shallow trench structure and reduce the subthreshold hump phenomenon caused by the parasitic transistor phenomenon. In this embodiment, the active region 5 has two non-overlapping gate regions, which has a better effect on eliminating the parasitic transistor phenomenon generated by the shallow trench structure and can reduce the subthreshold hump phenomenon to a greater extent.

[0048] like Figures 6-15 As shown, another embodiment of this application provides a method for manufacturing a metal-oxide-semiconductor field-effect transistor, including the following steps:

[0049] S10, forming active region 5, such as Figure 6 and Figure 7 As shown.

[0050] In some embodiments, the step of forming the active region 5 comprises: providing a semiconductor substrate; forming a pad oxide layer of silicon oxide material on the semiconductor substrate by thermal oxidation; forming an etching stop layer of silicon nitride material on the pad oxide layer by chemical vapor deposition; forming a photoresist layer on the etching stop layer by spin coating, defining active region patterns by exposure and development; etching the etching stop layer, the pad oxide layer and the semiconductor substrate to form the first trench 8 using dry etching with the photoresist layer as a mask; and removing the remaining pad oxide layer and the remaining etching stop layer, wherein the region between two adjacent first trenches 8 is the active region 5, and the first trench 8 is between two adjacent active regions 5. The bottom of the two adjacent active regions 5 is connected. The cross section of the first trench 8 is an axisymmetric inverted trapezoidal shape.

[0051] S20, forming the first isolation structure 6 in the first trench 8 between two adjacent active regions 5.

[0052] As shown in Figure 6 and Figure 7 , the top surface of the first isolation structure 6 is slightly lower than the top surface of the active region 5. The two sides of the active region 5 each have a first isolation structure 6. The cross section of the first isolation structure 6 is an axisymmetric inverted trapezoidal shape. The cross section of the active region 5 is a right trapezoidal shape. The first isolation structure 6 can be field oxide.

[0053] S30, forming the first nitride layer 7 completely covering the top surface of the active region 5, as shown in Figure 8 .

[0054] Specifically, as shown in Figure 8 , depositing a nitride material on the top surface of the active region 5 to form the first nitride layer 7 completely covering the top surface of the active region 5.

[0055] S40, selectively etching the first nitride layer 7 to expose the two first corners 9 on the top surface of the active region 5, so that the remaining part 7' of the first nitride layer 7 covers the middle part of the active region 5, as shown in Figure 9 .

[0056] As shown in Figure 9 , the two first corners 9 on the top of the active region 5 are also called STI (Shallow Trench Isolation) edge regions or STI corner parts.

[0057] S50, etching the first corner 9 to form the first gate non-overlapping region 4 and the second corner above the first gate non-overlapping region 4, as shown in Figure 10 . The top surface of the first gate non-overlapping region 4 is flush with the top surface of the first isolation structure 6. The first gate non-overlapping region 4 is also a corner of the active region 5.

[0058] The second corner forms the second gate non-overlapping region 10. The two corners on the two sides of the active region 5 correspond to the first gate non-overlapping region 4 and the second gate non-overlapping region 10.

[0059] S60, between the remaining portions 7' of the two adjacent first nitride layers 7, fill the same material as the first isolation structure 6 to form a second isolation structure 6', as shown in Figure 11 .

[0060] The two sides of the second isolation structure 6' cover the first gate non-overlapping region 4 and the second gate non-overlapping region 10 of the active region. The top surface of the second isolation structure 6' is flush with the top surface of the remaining portion 7' of the first nitride layer 7. In the space surrounded by the remaining portion 7', the first isolation structure 6 and the active region 5, fill the same material as the first isolation structure 6 to form a second isolation structure 6' with a top surface flush with the top surface of the remaining portion 7'.

[0061] S70, form a second trench 11 on the top surface of the second isolation structure 6', as shown in Figure 12 .

[0062] The second trench 11 is formed by selective oxidation through dichloroethylene and halogen oxide reaction.

[0063] S80, etch and remove the remaining portion 7' of the first nitride layer 7, and then form a gate oxide layer 3 on the middle portion of the active region 5. The top surface of the gate oxide layer 3 is lower than the top surface of the second isolation structure 6', but higher than the bottom surface of the second trench 11, as shown in Figure 13 . The gate oxide layer 3 is symmetrical about the symmetry axis of the active region 5. The first gate non-overlapping region 4 and the second gate non-overlapping region 10 are not in contact with the gate oxide layer 3.

[0064] S90, deposit to form a gate polysilicon layer 12 on the structure obtained by S80, as shown in Figure 14 and Figure 15 .

[0065] Another embodiment of the present application provides an electronic device comprising the metal oxide semiconductor field effect transistor described above. The electronic device includes a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, and a mobile power supply.

[0066] The MOSFET of the embodiment of the present application has two gate non-overlapping regions on the active region, which has a better effect of eliminating the parasitic transistor phenomenon caused by the shallow trench structure, can more greatly reduce the sub-threshold hump phenomenon, thereby reducing the transistor characteristic deviation, preventing the transistor characteristic deformation (deterioration), etc., and effectively improving the standby leakage current and power consumption.

[0067] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, it should be understood by those skilled in the art that the layers, regions, etc. of the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0068] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a metal-oxide-semiconductor field-effect transistor, characterized in that, include: An active region is formed between adjacent first trenches, and the cross-section of the active region is a trapezoidal shape; A first isolation structure is formed on both sides of the active region; The top surface of the first isolation structure is lower than the top surface of the active region; the cross-section of the first isolation structure is an axisymmetric inverted trapezoid. A first nitride layer is formed on the active region, completely covering the top surface of the active region; The first nitride layer is selectively etched to expose the first corners on both sides of the top surface of the active region, so that the remaining part of the first nitride layer covers the middle part of the active region; The first corner is etched to form a first gate non-overlapping region and a second gate non-overlapping region located above the first gate non-overlapping region, and the first gate non-overlapping region and the second gate non-overlapping region form a step, with the top surface of the first gate non-overlapping region being flush with the top surface of the first isolation structure. Between the remaining portions of two adjacent first nitride layers, the same material as the first isolation structure is filled to form a second isolation structure; The top surface of the second isolation structure is flush with the top surface of the remaining portion of the first nitride layer; The second isolation structure covers the first gate non-overlapping region and the second gate non-overlapping region on both sides, respectively; A second groove is formed on the top surface of the second isolation structure; The remaining portion of the first nitride layer is etched away, and then a gate oxide layer is formed on the middle portion of the active region; the top surface of the gate oxide layer is lower than the top surface of the second isolation structure and higher than the bottom surface of the second trench; A gate layer is formed covering the gate oxide layer and the second isolation structure.

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