Thin Film Transistor

Abstract

A thin film transistor comprises: a semiconductor layer, a first gate, a first gate insulating layer, a second gate, a third gate, and a second gate insulating layer. The first gate is located on one side of the semiconductor layer. The first gate insulating layer is located between the first gate and the semiconductor layer. The second gate and the third gate are located on the other side of the semiconductor layer, and the second gate is separated from the third gate. The second gate insulating layer is located between the second gate and the third gate and the semiconductor layer. The orthographic projection of the first gate on the semiconductor layer partially overlaps the orthographic projection of the second gate on the semiconductor layer, and the orthographic projection of the first gate on the semiconductor layer partially overlaps the orthographic projection of the third gate on the semiconductor layer.

Description

Technical Field

[0001] The invention relates to a switch element, and in particular to a thin film transistor. Background Art

[0002] As the feature size of thin film transistors continues to shrink, the drain-induced barrier lowering (DIBL) can no longer be ignored. DIBL will change the threshold voltage of thin film transistors, resulting in poor control of the gate, making it impossible to apply to advanced circuit designs, such as pixel compensation of active matrix organic light emitting diodes (AMOLEDs) and pulse width modulation (PWM) pixel circuits of micro-LEDs. Therefore, how to suppress DIBL is still one of the goals that related industries are seeking to improve. Summary of the invention

[0003] The present invention provides a thin film transistor capable of suppressing drain induced barrier lowering (DIBL).

[0004] One embodiment of the present invention provides a thin film transistor, comprising: a semiconductor layer; a first gate electrode located on one side of the semiconductor layer; a first gate insulating layer located between the first gate electrode and the semiconductor layer; a second gate electrode and a third gate electrode located on the other side of the semiconductor layer, and the second gate electrode is separated from the third gate electrode; and a second gate insulating layer located between the second gate electrode and the third gate electrode and the semiconductor layer, wherein the orthographic projection of the first gate electrode on the semiconductor layer partially overlaps the orthographic projection of the second gate electrode on the semiconductor layer, and the orthographic projection of the first gate electrode on the semiconductor layer partially overlaps the orthographic projection of the third gate electrode on the semiconductor layer.

[0005] In one embodiment of the present invention, the ratio of the sum of the area of ​​the second gate overlapping the semiconductor layer and the first gate and the area of ​​the third gate overlapping the semiconductor layer and the first gate to the area of ​​the first gate overlapping the semiconductor layer is between 40% and 60%.

[0006] In one embodiment of the present invention, the first gate, the second gate and the third gate are electrically connected.

[0007] In one embodiment of the present invention, the center line of the first grid overlaps the center line between the second grid and the third grid.

[0008] In one embodiment of the present invention, the second gate and the third gate have the same size.

[0009] In one embodiment of the present invention, the second gate insulating layer covers the second gate and the third gate.

[0010] In one embodiment of the present invention, the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer.

[0011] In one embodiment of the present invention, the thin film transistor further comprises a source electrode electrically connected to one end of the semiconductor layer, and an orthographic projection of the second gate electrode on the semiconductor layer is located between an orthographic projection of the source electrode on the semiconductor layer and an orthographic projection of the first gate electrode on the semiconductor layer.

[0012] In one embodiment of the present invention, the thin film transistor further comprises a drain electrically connected to the other end of the semiconductor layer, and an orthographic projection of the third gate on the semiconductor layer is located between an orthographic projection of the drain on the semiconductor layer and an orthographic projection of the first gate on the semiconductor layer.

[0013] In one embodiment of the present invention, the minimum distance between the second gate and the third gate is 1.2 μm.

[0014] In one embodiment of the present invention, the material of the semiconductor layer includes oxide semiconductor material, silicon semiconductor material or organic semiconductor material.

[0015] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 1 is a cross-sectional diagram of a thin film transistor 10 according to an embodiment of the present invention.

[0017] Figure 2 yes Figure 1 A circuit diagram of a thin film transistor 10 is shown.

[0018] Figure 3 yes Figure 1 A top view of the thin film transistor 10 is shown.

[0019] Figure 4 It is a graph showing the DIBL and on-current decay (Ion decay) of the thin film transistor 10 as a function of (a2+a3) / a1.

[0020] Description of reference numerals:

[0021] 10: Thin Film Transistor

[0022] A1, A2, A3: Area

[0023] BF: Buffer layer

[0024] CH: Semiconductor layer

[0025] CL: Center Line

[0026] D1: Spacing

[0027] DE: Drain

[0028] E1: First End

[0029] E2: Second end

[0030] G1: First gate

[0031] G2: Second gate

[0032] G3: The third grid

[0033] GH1, GH2, GH3: Thickness

[0034] I1: First gate insulating layer

[0035] I2: Second gate insulation layer

[0036] I3: Flat layer

[0037] IH1, IH2: Thickness

[0038] L1, L2, L3: Length

[0039] SB: Substrate

[0040] SE: Source

[0041] SL1, SL2: signal line

[0042] VD, VS: Through hole

[0043] W2, W3: Width

[0044] WR: Wire DETAILED DESCRIPTION

[0045] In the accompanying drawings, for the sake of clarity, the thickness of layers, films, panels, regions, etc. is magnified. Throughout the specification, the same reference numerals represent the same elements. It should be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to another element, or an intermediate element can also exist. On the contrary, when an element is referred to as being "directly on" or "directly connected to" another element, there is no intermediate element. As used herein, "connection" can refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" can be other elements between two elements.

[0046] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first "element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

[0047] The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include multiple forms, including "at least one" or to represent "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "comprising" and / or "including" specify the presence of the features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or combinations thereof.

[0048] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is turned over, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in one figure is turned over, the element described as being "lower" or "below" the other elements will be oriented as being "above" the other elements. Therefore, the exemplary term "lower" or "below" can include both above and below orientations.

[0049] As used herein, "about," "approximately," or "substantially" includes the stated value and an average value within an acceptable deviation range of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about," "approximately," or "substantially" may be selected based on the optical properties, etching properties, or other properties, and may not apply to all properties with one standard deviation.

[0050] Figure 1 1 is a cross-sectional schematic diagram of a thin film transistor 10 according to an embodiment of the present invention. The thin film transistor 10 includes: a semiconductor layer CH; a first gate electrode G1, located on one side of the semiconductor layer CH; a first gate insulating layer I1, located between the first gate electrode G1 and the semiconductor layer CH; a second gate electrode G2 and a third gate electrode G3, located on the other side of the semiconductor layer CH, and the second gate electrode G2 is separated from the third gate electrode G3; and a second gate insulating layer I2, located between the second gate electrode G2 and the third gate electrode G3 and the semiconductor layer CH, wherein the orthographic projection of the first gate electrode G1 on the semiconductor layer CH partially overlaps the orthographic projection of the second gate electrode G2 on the semiconductor layer CH, and the orthographic projection of the first gate electrode G1 on the semiconductor layer CH partially overlaps the orthographic projection of the third gate electrode G3 on the semiconductor layer CH.

[0051] In the thin film transistor 10 of one embodiment of the present invention, by providing a separate second gate G2 and a third gate G3 on the other side of the semiconductor layer CH relative to the first gate G1, the drain-induced barrier lowering (DIBL) can be suppressed. Hereinafter, the implementation of each element of the thin film transistor 10 will be further described in conjunction with the accompanying drawings, but the present invention is not limited thereto.

[0052] In this embodiment, the thin film transistor 10 may be located on a substrate SB. The material of the substrate SB may be glass. However, in some embodiments, the material of the substrate SB may also be quartz, an organic polymer, or an opaque / reflective material (e.g., a wafer, ceramic, etc.), or other applicable materials. In some embodiments, a buffer layer BF may be further provided between the thin film transistor 10 and the substrate SB to prevent impurities in the substrate SB from affecting the film layer formed subsequently.

[0053] The semiconductor layer CH of the thin film transistor 10 is located on the substrate SB. The material of the semiconductor layer CH may include an oxide semiconductor material, a silicon semiconductor material (such as polycrystalline silicon, amorphous silicon, etc.) or an organic semiconductor material. For example, the oxide semiconductor material may include at least one of IGZO (InGaZnO), IZO (InZnO), IGO (InGaO), ITO (InSnO), IGZTO (InGaZnSnO), GZTO (GaZnSnO), GZO (GaZnO), ZTO (ZnSnO) and ITZO (InSnZnO), but is not limited thereto. The organic semiconductor material may include, for example, various fused heterocycles (such as perylene imide and naphthalene imide small molecules or polymers), polymers (such as polypyrrole, polyfuran), derivatives of the above materials, or other suitable materials, or combinations of the above materials.

[0054] The first gate G1, the second gate G2 and the third gate G3 of the thin film transistor 10 may be located on opposite sides of the semiconductor layer CH, and the second gate G2 and the third gate G3 may be located on the same side of the semiconductor layer CH, and the first gate G1 may be located on a different side from the second gate G2 and the third gate G3. For example, in the present embodiment, the first gate G1 may be located on the upper side of the semiconductor layer CH, that is, the side away from the substrate SB, and the second gate G2 and the third gate G3 may be located on the lower side of the semiconductor layer CH, that is, the side close to the substrate SB, that is, the second gate G2 and the third gate G3 may be located between the semiconductor layer CH and the substrate SB, but is not limited thereto. In some embodiments, the first gate G1 may be located on the lower side of the semiconductor layer CH, and the second gate G2 and the third gate G3 may be located on the upper side of the semiconductor layer CH. In addition, the orthographic projections of the first gate G1, the second gate G2 and the third gate G3 on the substrate SB are all located within the orthographic projection of the semiconductor layer CH on the substrate SB.

[0055] In this embodiment, the second gate G2 is physically separated from the third gate G3 , and the second gate G2 is electrically connected to the third gate G3 . Figure 2 yes Figure 1 1 is a circuit diagram of the thin film transistor 10 shown in FIG. 1 . For example, in this embodiment, the first gate G1, the second gate G2, and the third gate G3 can be electrically connected via the wire WR. When the first gate G1, the second gate G2, and the third gate G3 receive a signal from the signal line SL1 to turn on the thin film transistor 10, the signal received by the source electrode SE from the signal line SL2 can be transmitted to the drain electrode DE through the semiconductor layer CH. In other embodiments, the first gate G1, the second gate G2, and the third gate G3 can be electrically separated from each other.

[0056] In this embodiment, the material of the first gate G1, the second gate G2 and the third gate G3 may include a metal with good conductivity, such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), silver (Ag), chromium (Cr), or neodymium (Nd), or an alloy of any combination of the above metals. In some embodiments, the first gate G1, the second gate G2 and the third gate G3 may also use other conductive materials, such as: metal nitride, metal oxide, metal oxynitride, a stacked layer of metal and other conductive materials, or other materials with conductive properties.

[0057] The first gate insulating layer I1 electrically separates the first gate G1 from the semiconductor layer CH. In some embodiments, the thickness IH1 of the first gate insulating layer I1 may be less than the thickness GH1 of the first gate G1. Similarly, the second gate insulating layer I2 electrically separates the second gate G2 and the third gate G3 from the semiconductor layer CH. In some embodiments, the second gate insulating layer I2 may cover the second gate G2 and the third gate G3, that is, the thickness IH2 of the second gate insulating layer I2 may be greater than the thickness GH2 of the second gate G2, and the thickness IH2 of the second gate insulating layer I2 may be greater than the thickness GH3 of the third gate G3. In addition, the thickness GH2 of the second gate G2 and the thickness GH3 of the third gate G3 may be the same or different. In some embodiments, the thickness IH2 of the second gate insulating layer I2 may be greater than the thickness IH1 of the first gate insulating layer I1. In some embodiments, the thickness GH1 of the first gate G1, the thickness GH2 of the second gate G2, and the thickness GH3 of the third gate G3 may be the same. In addition, the material of the first gate insulating layer I1 and the second gate insulating layer I2 may include a transparent insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, a dielectric polymer, or a stack of the above materials, but is not limited thereto.

[0058] In this embodiment, the thin film transistor 10 may further include a planar layer I3, and the planar layer I3 may cover the first gate G1, the semiconductor layer CH, the first gate insulating layer I1, and the second gate insulating layer I2. The material of the planar layer I3 may include a transparent insulating material, such as acrylic, siloxane polymer, polyimide, epoxy, etc., but is not limited thereto.

[0059] The thin film transistor 10 may further include a source electrode SE and a drain electrode DE, wherein the source electrode SE is electrically connected to the first end E1 of the semiconductor layer CH, and the drain electrode DE is electrically connected to the second end E2 of the semiconductor layer CH. For example, in the present embodiment, the source electrode SE may be electrically connected to the first end E1 of the semiconductor layer CH through a through hole VS in the planar layer I3, and the drain electrode DE may be electrically connected to the second end E2 of the semiconductor layer CH through a through hole VD in the planar layer I3. In some embodiments, the portion of the semiconductor layer CH connected to the source electrode SE and the drain electrode DE may further include dopants, such as hydrogen, boron, or phosphorus, as needed. In some embodiments, the orthographic projection of the second gate electrode G2 on the semiconductor layer CH may be located between the orthographic projection of the source electrode SE on the semiconductor layer CH and the orthographic projection of the first gate electrode G1 on the semiconductor layer CH, and the orthographic projection of the third gate electrode G3 on the semiconductor layer CH may be located between the orthographic projection of the drain electrode DE on the semiconductor layer CH and the orthographic projection of the first gate electrode G1 on the semiconductor layer CH.

[0060] Figure 3 yes Figure 1 FIG. 1 is a top view of the thin film transistor 10 shown in FIG. 1. In the present embodiment, a distance D1 may be provided between the second gate G2 and the third gate G3, and the minimum value of the distance D1 may be about 1.2 μm. In some embodiments, when limited by the exposure limit of the photolithography process, the second gate G2 and the third gate G3 may be patterned sequentially by double exposure.

[0061] In some embodiments, the length L1 of the first gate G1 may be between 4 μm and 20 μm, for example, 6 μm or 10 μm. In some embodiments, the second gate G2 may have a length L2 and a width W2, the third gate G3 may have a length L3 and a width W3, and the size of the second gate G2 may be the same as the size of the third gate G3, that is, the length L2 and the length L3 may be the same, and the width W2 and the width W3 may be the same. In some embodiments, the center line CL of the first gate G1 may substantially overlap the center line between the second gate G2 and the third gate G3. When the second gate G2 and the third gate G3 have the same size, the center line between the second gate G2 and the third gate G3 is the axis of symmetry of the second gate G2 and the third gate G3.

[0062] like Figure 3 As shown, in this embodiment, region A1 of the first gate G1 can overlap the semiconductor layer CH, region A2 of the second gate G2 can overlap both the semiconductor layer CH and the first gate G1, and region A3 of the third gate G3 can overlap both the semiconductor layer CH and the first gate G1, wherein region A1 has an area a1, region A2 has an area a2, region A3 has an area a3, and the ratio of the sum of the areas of region A2 and region A3 to the area of ​​region A1 is (a2+a3) / a1.

[0063] Figure 4 is a graph showing the DIBL and on-current decay (Ion decay) of the thin film transistor 10 as a function of (a2+a3) / a1. Figure 4 It can be seen that when (a2+a3) / a1 increases from 0% to 100%, DIBL can be reduced from about 15mV / V to less than 2mV / V, indicating that increasing the overlapping area of ​​the second gate G2 and the third gate G3 with the first gate G1 within the semiconductor layer CH can significantly suppress DIBL, but the ratio of on-current decay increases from about 1% to 9%. Therefore, (a2+a3) / a1 can be set between 40% and 60% to balance the performance of DIBL and on-current decay, so that the DIBL phenomenon of the thin film transistor 10 can be suppressed, and at the same time, the thin film transistor can be prevented from deteriorating and affecting reliability.

[0064] In summary, the thin film transistor of the present invention can suppress DIBL and avoid affecting the reliability of the thin film transistor by disposing the separated second gate and the third gate on the other side of the semiconductor layer relative to the first gate.

[0065] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A thin film transistor, comprising: Semiconductor layer; A first gate, located at one side of the semiconductor layer; A first gate insulating layer, located between the first gate and the semiconductor layer; A second gate and a third gate are located on the other side of the semiconductor layer, and the second gate is separated from the third gate; and A second gate insulating layer is located between the second gate and the third gate and the semiconductor layer, The orthographic projection of the first gate on the semiconductor layer partially overlaps the orthographic projection of the second gate on the semiconductor layer, and the orthographic projection of the first gate on the semiconductor layer partially overlaps the orthographic projection of the third gate on the semiconductor layer. The first gate, the second gate and the third gate are electrically connected.

2. The thin film transistor as claimed in claim 1, wherein the ratio of the sum of the area of ​​the second gate overlapping the semiconductor layer and overlapping the first gate and the area of ​​the third gate overlapping the semiconductor layer and overlapping the first gate to the area of ​​the first gate overlapping the semiconductor layer is between 40% and 60%. 3 . The thin film transistor of claim 1 , wherein a center line of the first gate overlaps a center line between the second gate and the third gate. The thin film transistor according to claim 1 , wherein the second gate electrode and the third gate electrode have the same size. The thin film transistor as claimed in claim 1 , wherein the second gate insulating layer covers the second gate and the third gate. 6 . The thin film transistor of claim 1 , wherein a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer.

7. The thin film transistor as described in claim 1 further includes a source electrode electrically connected to one end of the semiconductor layer, and the orthographic projection of the second gate electrode on the semiconductor layer is located between the orthographic projection of the source electrode on the semiconductor layer and the orthographic projection of the first gate electrode on the semiconductor layer.

8. The thin film transistor as described in claim 7 further includes a drain electrode electrically connected to the other end of the semiconductor layer, and the orthographic projection of the third gate electrode on the semiconductor layer is located between the orthographic projection of the drain electrode on the semiconductor layer and the orthographic projection of the first gate electrode on the semiconductor layer. 9 . The thin film transistor according to claim 1 , wherein a minimum distance between the second gate and the third gate is 1.2 μm. 10 . The thin film transistor as claimed in claim 1 , wherein a material of the semiconductor layer comprises an oxide semiconductor material, a silicon semiconductor material or an organic semiconductor material. 11 . The thin film transistor according to claim 1 , further comprising a planarization layer covering the first gate and directly contacting the semiconductor layer.

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