A wafer-level packaging structure of a sensor and a packaging method thereof

Abstract

The present invention discloses a wafer-level packaging structure of a sensor and a packaging method thereof. The wafer-level packaging method of the sensor comprises: providing a first substrate, the first substrate comprising a base and a dielectric layer arranged on the surface of the base; forming a detection structure layer on the first substrate, the detection structure layer comprising a detection structure; providing a second substrate, the second substrate having a first cavity; bonding the second substrate on the first substrate, the first cavity facing the detection structure layer; removing the base; providing a third substrate; providing at least part of a cofferdam on a side of the detection structure layer away from the second substrate and / or on the third substrate; bonding the third substrate on a side of the detection structure layer away from the second substrate via the cofferdam, the cofferdam and the third substrate enclosing a second cavity, the second cavity facing the detection structure layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and in particular to a wafer-level packaging structure of a sensor and a packaging method thereof. Background Art

[0002] With the continuous development of MEMS sensing technology, sensor packaging pursues higher performance. Sensors with thermopiles as core components have been widely used in infrared temperature measurement, infrared detection, infrared alarm, infrared imaging, infrared guidance and other fields. The basic principle of the sensor is based on the Seebeck effect of thermoelectric materials. Generally, multiple pairs of thermocouples are connected into a "pile" to convert the infrared radiation signal absorbed by the outside world into an electrical signal to achieve temperature measurement. Of the two ends, the end that absorbs infrared is called the hot zone, and the substrate end is called the cold zone. Most traditional sensors use TO packaging. With the increasing demand for integrated temperature measurement chips in electronic products such as mobile phones and wearable devices, the size of the chip has also been miniaturized.

[0003] However, the traditional TO packaging process is to stick the thermopile chip on the packaging base, then connect the chip pad and the base pins through wire bonding, and finally seal the cap and the base. The package size is large (5×5×3mm) and the pins are very long, which seriously restricts its application in miniaturized equipment.

[0004] Therefore, how to improve the packaging method of the sensor, reduce the packaging size of the chip, and meet its application needs in miniaturized devices is the current problem. Summary of the invention

[0005] The object of the present invention is to provide a wafer-level packaging structure of a sensor and a packaging method thereof, which can solve the problems of poor packaging process accuracy of the sensor, large packaging size, and inability to meet application requirements in miniaturized equipment.

[0006] In order to achieve the above object, the present invention provides a wafer-level packaging method for a sensor, comprising:

[0007] Providing a first substrate, the first substrate comprising a base and a dielectric layer disposed on a surface of the base;

[0008] forming a detection structure layer on the first substrate, wherein the detection structure layer includes a detection structure;

[0009] providing a second substrate, wherein the second substrate has a first cavity;

[0010] bonding the second substrate on the first substrate, with the first cavity facing the detection structure layer;

[0011] removing the substrate;

[0012] providing a third substrate;

[0013] At least a portion of the cofferdam is provided on a side of the detection structure layer away from the second substrate and / or on the third substrate;

[0014] The third substrate is bonded to a side of the detection structure layer away from the second substrate through the dam, and the dam and the third substrate enclose a second cavity, and the second cavity faces the detection structure layer.

[0015] The present invention also provides a wafer-level packaging structure of a sensor, comprising:

[0016] a second substrate having a first cavity;

[0017] a detection structure layer, the detection structure layer comprising at least a detection structure, the detection structure being at least partially located above the first cavity;

[0018] a dielectric layer, covering a surface of the detection structure layer away from the second substrate;

[0019] A metal cofferdam, wherein the metal cofferdam is located above the dielectric layer;

[0020] a third substrate, the third substrate being located above the metal cofferdam, the metal cofferdam and the third substrate forming a second cavity, and the second cavity surrounding at least a portion of the detection structure;

[0021] An electrical connection structure is used to electrically lead out the detection structure.

[0022] The beneficial effects of the present invention are:

[0023] The third substrate is bonded to the prepared detection structure layer to enclose the second cavity, and an electrical connection structure is set to lead out the electrical properties of the thermocouple to complete the packaging of the detection structure layer, thereby greatly reducing the package size and meeting the application needs of the sensor in miniaturized equipment. The second cavity is not etched on the third substrate, but is bonded to form a cavity separately, which avoids the problem of poor control of the back cavity etching process and poor cavity size accuracy, and improves the measurement accuracy of the sensor. The wafer-level manufacturing process has a short cycle, high efficiency and low cost.

[0024] Furthermore, the first substrate includes top silicon, and the material of the top silicon is single crystal silicon, so that the top silicon of the SOI substrate can be directly used to form the first thermoelectric strip and / or the second thermoelectric strip of the thermocouple, which simplifies the process and improves packaging efficiency.

[0025] Furthermore, the electrical connection structure is divided into a first connection part, a second connection part and a third connection part, and the above three parts are formed in different processes respectively, which reduces the process difficulty and improves the yield and reliability of the wafer-level packaging of the sensor.

[0026] Furthermore, a metal cofferdam is formed, and a third substrate is bonded on the cofferdam to form a second cavity, which improves the airtightness and structural strength of the sensor's wafer-level packaging, is beneficial to the temperature concentration and interference shielding of the sensor, and improves the quality, reliability and yield of the sensor's wafer-level packaging.

[0027] Furthermore, a flat layer is provided and flattened, and the second substrate and the detection structure layer are bonded by a melt bonding method, thereby improving the bonding alignment accuracy and the structural strength of the sensor's wafer-level packaging, while simplifying the process, and the bonding material of the melt bonding is easy to obtain, thereby improving the packaging efficiency and reducing the packaging cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figures 1 to 20 A schematic structural diagram corresponding to different steps in the wafer-level packaging method for a sensor according to Embodiment 1 of the present invention is shown.

[0030] Description of reference numerals:

[0031] 10-substrate; 11-dielectric layer; 111-second through hole; 21-first thermoelectric material layer; 211-first thermoelectric strip; 22-isolation layer; 221-first groove; 23-second thermoelectric strip; 24-passivation layer; 25-flat layer; 26-second substrate; 27-first cavity; 30-first connecting part; 31-dam; 32-third substrate; 321-second through hole; 33-second cavity; 34-second connecting part; 35-insulating layer; 351-third through hole; 36-third connecting part. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0033] The terms "first", "second", etc. in the specification and claims are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that, where appropriate, these terms used in this way are interchangeable, for example, so that the embodiments of the invention described herein can be operated in other orders than those described or shown herein. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. If the components in a certain figure are the same as the components in other figures, although these components can be easily identified in all figures, in order to make the description of the figures clearer, this specification will not mark all the same component numbers in each figure.

[0034] The present invention provides a wafer-level packaging method for a sensor, wherein a detection structure is used as a sensing structure of the sensor, such as a MEMS cantilever structure, a thermopile structure, a filter structure, etc.

[0035] Example 1

[0036] Embodiment 1 of the present invention provides a wafer-level packaging method for a sensor. The wafer-level packaging method for a sensor includes:

[0037] S01: providing a first substrate, the first substrate comprising a base 10 and a dielectric layer 11 disposed on a surface of the base 10;

[0038] S02: forming a detection structure layer on the first substrate, wherein the detection structure layer includes a detection structure;

[0039] S03: providing a second substrate 26, wherein the second substrate 26 has a first cavity 27; bonding the second substrate 26 to the first substrate, wherein the first cavity 27 faces the detection structure layer;

[0040] S04: removing the substrate 10;

[0041] S05: Provide a third substrate 32, and provide at least a partial cofferdam 31 on the side of the detection structure layer away from the second substrate 26 and / or on the third substrate 32, and bond the third substrate 32 to the side of the detection structure layer away from the second substrate 26 through the cofferdam 31, and the cofferdam 31 and the third substrate 32 enclose a second cavity 33, and the second cavity 33 faces the detection structure layer.

[0042] It should be noted that the above steps S0N do not represent the order of precedence.

[0043] Please refer to the following Figures 1 to 20 The wafer-level packaging method of sensors is explained. Figures 1 to 20Schematic diagram of the structures corresponding to different steps in an embodiment of a wafer-level packaging method for sensors of the present invention.

[0044] refer to Figure 1 to Figure 2 , perform step S01: provide a first substrate, the first substrate includes a base 10 and a dielectric layer 11 arranged on the surface of the base 10.

[0045] Specifically, the material of the substrate 10 includes semiconductor materials, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, and can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or ceramic substrates 10 such as alumina, quartz or glass substrates 10, etc.

[0046] In this embodiment, the material of the substrate 10 is silicon. Figure 2 After forming the substrate 10, a dielectric layer 11 is formed on the substrate 10. The material of the dielectric layer 11 includes silicon nitride or silicon oxide. The dielectric layer 11 serves as a stop layer for the subsequent thinning process, and after the thinning process, it supports the structure subsequently formed on the dielectric layer 11, and also serves as a dielectric isolation. It also has a heat insulation function, preventing the subsequently formed structural layer from exchanging temperature with the outside in the direction close to the dielectric layer 11, thereby improving the sensitivity and accuracy of the sensor and ensuring the quality and reliability of the sensor. The dielectric layer 11 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The dielectric layer 11 can be formed on the substrate 10 by thermal oxidation and deposition, and has a contact interface.

[0047] In other embodiments, the first substrate further includes top silicon, which is located on the dielectric layer 11 and is made of single crystal silicon. In this case, the first substrate constitutes an SOI substrate, which can eliminate parasitic latch effects in the circuit.

[0048] refer to Figures 3 to 8 , perform step S02: forming a detection structure layer on the first substrate, the detection structure layer including a detection structure. In this embodiment, the detection structure layer may cover the surface of the first substrate, and in other embodiments, only the functional area of ​​the first substrate may be covered with the detection structure layer, that is, the detection structure layer exposes part of the first substrate.

[0049] In this embodiment, the detection structure includes at least part of the thermocouple, and the thermocouple includes a first thermoelectric strip 211 and a second thermoelectric strip 23 connected to each other. The thermocouple uses the principle of "Seebeck effect" to manufacture a circuit with the first thermoelectric strip 211 and the second thermoelectric strip 23, and generates a thermoelectric potential by generating a temperature difference, thereby measuring the amount of infrared rays incident on the infrared sensor. In this embodiment, by setting a plurality of thermocouples in series, the high sensitivity of the sensor is achieved, and the quality and reliability of the sensor are improved. Among them, the first thermoelectric strip 211 and the second thermoelectric strip 23 can be arranged in parallel on the same horizontal plane, or can be stacked in a direction perpendicular to the first substrate. The part where the first thermoelectric strip 211 and the second thermoelectric strip 23 are connected to each other serves as the hot end of the thermocouple, and the part of the thermocouple away from the hot end serves as the cold end. In one embodiment, there are multiple thermocouples, and the multiple thermocouples are arranged in an array. In other embodiments, the detection structure as a sensing structure of the sensor can be a MEMS cantilever structure, a thermopile structure, a filter structure, etc., and can also include at least part of thermistors or at least part of photoresistors.

[0050] In this embodiment, the method for forming the detection structure layer includes: referring to Figure 3 , forming a first thermoelectric material layer 21 on the first substrate; referring to Figure 4 , patterning the first thermoelectric material layer 21 to form a plurality of discrete first thermoelectric strips 211; Figure 5 , forming an isolation layer 22 on the first substrate and the first thermoelectric strip 211, covering the first thermoelectric strip 211 and the first substrate, referring to Figure 6 , patterning the isolation layer 22 to form a first groove 221, the first groove 221 penetrates the isolation layer 22 and exposes a portion of the surface of the first thermoelectric strip 211; Figure 7, a second thermoelectric material layer is formed on the isolation layer 22 and the first thermoelectric strip 211, and the second thermoelectric material layer is patterned to form a plurality of discrete second thermoelectric strips 23, and the second thermoelectric strips 23 and the corresponding first thermoelectric strips 211 are electrically connected to each other through the first groove 221. The material combination of the first thermoelectric strip 211 and the second thermoelectric strip 23 includes: p-type single crystal silicon and n-type single crystal silicon, single crystal silicon and polycrystalline silicon, single crystal silicon and metal, polycrystalline silicon and metal, p-type polycrystalline silicon and n-type polycrystalline silicon, and the metal includes aluminum, copper, gold, titanium or tungsten. The material of the isolation layer 22 includes dielectric materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), and aluminum oxide (Al2O3). When the isolation layer 22 is silicon dioxide (SiO2), silicon nitride (Si3N4), and aluminum oxide (Al2O3), it can be formed by a deposition process. The first thermoelectric material layer 21 and / or the second thermoelectric material layer can be formed by physical vapor deposition or chemical vapor deposition methods such as magnetron sputtering and evaporation. The method of patterning the first thermoelectric material layer 21, the isolation layer 22 and the second thermoelectric material layer includes a dry etching process, and the dry etching process includes but is not limited to reactive ion etching (RIE), ion beam etching, plasma etching or laser cutting.

[0051] In this embodiment, the number of the first thermoelectric strips 211 and the second thermoelectric strips 23 is equal, the second thermoelectric strips 23 and the corresponding first thermoelectric strips 211 are electrically connected to each other to form a plurality of thermocouples, the plurality of thermocouples are in a series relationship, the material of the first thermoelectric strips 211 is polysilicon, and the material of the second thermoelectric strips 23 is metal. In other embodiments, when the material of the thermocouple includes metal, the first thermoelectric strips 211 and the second thermoelectric strips 23 are directly connected, and when the material of the thermocouple does not include metal, the first thermoelectric strips 211 and the second thermoelectric strips 23 are connected through metal materials such as aluminum, copper, gold, titanium or tungsten. In another embodiment, the first thermoelectric strips 211 and / or the second thermoelectric strips 23 are formed by patterning the top silicon of the SOI substrate, thereby simplifying the process and improving the packaging efficiency.

[0052] refer to Figure 8 In this embodiment, after forming the thermocouple, it also includes forming a passivation layer 24 to cover the thermocouple. The material of the passivation layer 24 includes a single layer of silicon nitride, silicon dioxide, phosphosilicate glass, borophosphosilicate glass or polyimide film or a stacked insulating film formed by them. The passivation layer 24 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, laser ablation deposition or molecular beam deposition. The passivation layer 24 can play a dielectric isolation role, and can also serve as an absorption layer that absorbs infrared rays, effectively transferring the heat generated by absorbing infrared rays to the detection structure layer, thereby improving the performance of the device.

[0053] refer to Figures 9 and 10, performing step S03: providing a second substrate 26, the second substrate 26 having a first cavity 27; bonding the second substrate 26 on the first substrate, the first cavity 27 facing the detection structure layer.

[0054] The material of the second substrate 26 refers to the material of the base 10 of the first substrate. In this embodiment, the material of the second substrate 26 is a semiconductor material that can transmit infrared rays, thereby improving the performance of the device. In other embodiments, the second substrate can also be an optical material, such as glass, a filter, a lens, etc., or a polymer material, such as a dry film, a molding compound, etc.

[0055] In this embodiment, the first cavity 27 is formed by an etching process, and the shape of the bottom surface of the first cavity 27 is a rectangle. However, in other embodiments of the present invention, the shape of the bottom surface of the first cavity 27 may also be a circle, an ellipse, or a polygon other than a rectangle, such as a pentagon, a hexagon, etc. In this embodiment, the first cavity 27 surrounds the thermocouple at the hot end portion, and the transmittance of infrared rays is improved by forming the first cavity 27. At the same time, it also plays a role in heat insulation, preventing the detection structure layer from exchanging temperature with the outside in the direction close to the passivation layer 24, thereby improving the performance of the device.

[0056] In this embodiment, the detection structure layer covers the surface of the first substrate, and the second substrate is bonded to the detection structure layer on the first substrate. In other embodiments, the second substrate can be bonded to the surface of the first substrate where the detection structure layer is exposed.

[0057] In this embodiment, the method for bonding the second substrate 26 to the detection structure layer includes forming a flat layer 25 on the detection structure layer, the second substrate 26 and the flat layer 25 are melt-bonded, the material of the flat layer 25 includes: silicon oxide, silicon nitride or silicon oxynitride, the flat layer 25 is flattened before melt bonding, and the first cavity 27 faces the direction of the thermocouple after melt bonding. The flat layer 25 is formed on the detection structure layer and flattened, and then the second substrate 26 and the detection structure layer are bonded by melt bonding, which improves the alignment accuracy of the bonding and the structural strength of the wafer-level packaging of the sensor, simplifies the process, and the bonding material of the melt bonding is easy to obtain, thereby improving the packaging efficiency and reducing the packaging cost.

[0058] refer to Fig.11 , step S04 is performed: removing the substrate 10. After removing the substrate 10, the dielectric layer 11 is exposed.

[0059] In this embodiment, the substrate 10 is removed by etching or mechanical grinding, and the dielectric layer 11 serves as a stop layer for the grinding process to prevent excessive grinding. In other examples, a temporary bonding layer is provided between the substrate 10 and the dielectric layer 11, and the substrate 10 can be removed by corroding the temporary bonding layer, which helps to quickly peel off the substrate 10 and improve the process efficiency. In another example, the temporary bonding layer can be replaced by a heat expansion tape, and the substrate 10 can be peeled off by heating the heat expansion tape to make it lose its stickiness.

[0060] refer to Figure 12 to Figure 14 , execute step S05: provide a third substrate 32, and provide at least a partial cofferdam 31 on the side of the detection structure layer away from the second substrate 26 and / or on the third substrate 32, and bond the third substrate 32 to the side of the detection structure layer away from the second substrate 26 through the cofferdam 31, and the cofferdam 31 and the third substrate 32 enclose a second cavity 33, and the second cavity 33 faces the detection structure layer.

[0061] The material of the third substrate 32 refers to the material of the base 10 of the first substrate, and will not be described in detail here.

[0062] refer to Fig.12 The cofferdam 31 may be formed on the third substrate 32, or refer to Fig.13 , the cofferdam 31 can be formed on the side of the detection structure layer away from the second substrate 26, or part of the cofferdam 31 is formed on the third substrate 32, and part of the cofferdam 31 is formed on the side of the detection structure layer away from the second substrate 26. In this embodiment, the cofferdam 31 is formed on the side of the dielectric layer 11 away from the second substrate 26. The material of the cofferdam 31 includes dry film, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, ethyl silicate, polysilicon, a single layer of aluminum, titanium, nickel, gold, chromium, copper or platinum, alloy or a stacked film thereof. In this embodiment, the material of the cofferdam 31 is metal, and a metal film layer is formed on the surface of the side of the dielectric layer 11 away from the second substrate 26, and then the cofferdam 31 is formed by an etching process. The shape of the cofferdam 31 can be annular or polygonal. In this embodiment, the width between the inner surface and the outer surface of the cofferdam 31 meets the support of the second cavity, and the height range of the cofferdam 31 includes 1-20 microns, such as 5 microns, 10 microns, and 15 microns. The cofferdam within this range can support the second cavity, reduce temperature loss, and prevent the cofferdam from corrosion or oxidation in the environment, thereby improving product reliability. The cofferdam 31 is located outside at least part of the thermocouple and surrounds at least part of the thermocouple.

[0063] In other embodiments, the material selected for the cofferdam 31 is a photolithographic material, such as a dry film, and the cofferdam 31 is formed by a film lamination process. The cofferdam 31 is formed on the third substrate 32, which enables the process of forming the third substrate 32 and the cofferdam 31 to be separated from the process of forming the detection structure layer, thereby improving the packaging efficiency.

[0064] In other embodiments, the third substrate 32 also includes a third cavity, the cofferdam 31 surrounds the third cavity, the formation process of the third cavity refers to the formation process of the first cavity 27, the distance from the detection structure layer to the bottom of the third cavity is 10 microns to 200 microns, such as 50 microns, 100 microns, 150 microns, etc. The cavity of this depth has a better suppression of temperature conduction performance, and the process is less difficult to implement. The third cavity is formed to better play a heat insulation role, prevent the detection structure layer from exchanging temperature with the outside in the direction close to the dielectric layer 11, and ensure the quality and reliability of the sensor.

[0065] In other embodiments, a second cavity 33 is formed in the third substrate 32, and the sidewall of the second cavity 33 serves as at least a portion of the cofferdam 31. In this case, the material of at least a portion of the cofferdam 31 is the same as the material of the third substrate 32. By directly forming the second cavity 33 on the third substrate 32, the process of forming the cofferdam 31 is simplified, thereby improving the packaging efficiency.

[0066] refer to Fig.14 In this embodiment, a metal bonding process is applied, and the third substrate 32 is bonded to the side of the dielectric layer 11 away from the second substrate 26 through the cofferdam 31. The cofferdam 31 and the third substrate 32 enclose a second cavity 33, and the second cavity 33 surrounds the thermocouple of the hot end part. The shape of the bottom surface of the second cavity 33 can also be a circle, an ellipse or a polygon other than a rectangle, such as a pentagon, a hexagon, etc. The function of the second cavity 33 is heat insulation, and it cooperates with the dielectric layer 11 to prevent the detection structure layer from exchanging temperature with the outside in the direction close to the dielectric layer 11, thereby ensuring the quality and reliability of the sensor. In addition, the cofferdam 31 made of metal material is formed, and the second cavity 33 is formed by bonding the third substrate 32 on the cofferdam 31, thereby improving the air tightness and structural strength of the wafer-level packaging of the sensor, and is conducive to the temperature concentration and shielding interference of the sensor, thereby improving the quality, reliability and yield rate of the wafer-level packaging of the sensor. Moreover, the second cavity 33 is not etched on the substrate 10, but is bonded into a cavity by the cofferdam 31, thereby avoiding the problem of poor control of the back cavity etching process and poor cavity size accuracy, and can improve the measurement accuracy of the sensor.

[0067] refer to Figures 15 to 20 In this embodiment, the method further includes forming an electrical connection structure, wherein the electrical connection structure electrically leads out the detection structure layer.

[0068] In this embodiment, the method for forming the electrical connection structure includes: after removing the substrate 10, patterning the dielectric layer 11, forming a first through hole, forming a first connection part 30, electrically connecting the thermocouple and penetrating the first through hole; bonding the third substrate 32; patterning the third substrate 32, forming a second through hole 321, forming a second connection part 34, electrically connecting the first connection part 30 and penetrating the second through hole 321; after forming the second connection part 34, forming a third connection part 36 to electrically connect the second connection part 34, and the electrical connection structure includes the first connection part 30, the second connection part 34 and the third connection part 36. The material of the electrical connection structure includes: polysilicon, a single layer of aluminum, titanium, nickel, gold, chromium, copper or platinum, an alloy or a stacked film thereof. In this embodiment, there are two electrical connection structures, and they are isolated from each other.

[0069] refer to Fig.15 After removing the substrate 10 and before forming the second cavity 33, the dielectric layer 11 is etched by an etching process to form a first through hole. The shape of the first through hole is not limited, and it can be a circular through hole or a square through hole. In this embodiment, there are two first through holes, and the first through holes penetrate the dielectric layer 11, respectively exposing a portion of the surface of the first thermoelectric strip 211. In other embodiments, the first through holes expose a portion of the surface of the first thermoelectric strip 211 and a portion of the surface of the second thermoelectric strip 23.

[0070] refer to Fig.13 , an electrical connection structure material layer is formed on the dielectric layer 11, the first through hole is filled and the dielectric layer 11 is covered, and the first connection part 30 is patterned to form the first connection part 30, the first connection part 30 fills the first through hole and protrudes from the surface of the dielectric layer 11. In this embodiment, the width of the first connection part 30 is the same as that of the first through hole, and while forming the first connection part 30, a cofferdam 31 is formed by patterning the electrical connection structure material layer, the cofferdam 31 is located at the periphery of the first connection part 30, the second cavity 33 surrounds the first connection part 30, and the surface of the cofferdam 31 away from the detection structure layer is flush with the surface of the first connection part 30 away from the detection structure layer. By forming the first connection part 30 and the cofferdam 31 in the same process, the process is simplified and the packaging efficiency is improved. In one embodiment, the third substrate 32 has a third cavity, and the first connection part 30 is formed at the periphery of the third cavity, which is conducive to improving the structural strength of the device and improving the heat insulation effect of the third cavity, thereby improving the device performance.

[0071] refer to Fig.16 , patterning the third substrate 32 to form a second through hole 321, the second through hole 321 penetrates the third substrate 32, in this embodiment, there are two second through holes 321, and the projections of the two second through holes 321 in the direction perpendicular to the dielectric layer 11 overlap with the projections of the two first through holes in the direction perpendicular to the dielectric layer 11, reference Fig.17, an electrical connection structure material layer is formed on the third substrate 32, the second through hole 321 is filled and covers the third substrate 32, and the second connection portion 34 is patterned. The second connection portion 34 fills the second through hole 321 and covers the periphery of the second through hole 321. In this embodiment, the third substrate 32 is bonded first, and then the second through hole 321 is patterned. In other embodiments, the second through hole 321 may also be patterned first, and then the third substrate 32 is bonded.

[0072] refer to Fig.18 In this embodiment, after forming the second connection part 34, it also includes forming an insulating layer 35 on the third substrate 32 and the second connection part 34 to cover the third substrate 32 and the second connection part 34. The material of the insulating layer 35 refers to the material of the dielectric layer 11. The insulating layer 35 plays a role in protecting the electrical connection structure and dielectric isolation, thereby improving the reliability of the wafer-level packaging of the sensor. Fig.19 , patterning the insulating layer 35, forming a third through hole 351, the third through hole 351 penetrates the insulating layer 35, in this embodiment, there are two third through holes 351, respectively exposing a portion of the surface of the two second connecting portions 34, forming an electrical connection structure material layer on the insulating layer 35, filling the third through hole 351, and covering the insulating layer 35, reference Fig. 20 , a third connection portion 36 is graphically formed. In this embodiment, there are two third connection portions 36 that are isolated from each other. The third connection portions 36 fill the third through hole 351 and protrude from the surface of the insulating layer 35 .

[0073] In this embodiment, the electrical connection structure is used to lead out the electrical properties of the thermocouple and connect to an external circuit. The electrical connection structure is divided into a first connection part 30, a second connection part 34 and a third connection part 36, and the above three parts are formed in different processes respectively, thereby forming an electrical connection structure, which reduces the process difficulty and improves the yield and reliability of the wafer-level packaging of the sensor. The present invention bonds a third substrate 32 to the prepared detection structure layer to enclose a second cavity 33, and sets an electrical connection structure to lead out the electrical properties of the thermocouple to complete the packaging of the detection structure layer, thereby greatly reducing the package size and meeting the application needs of the sensor in miniaturized equipment. Wafer-level manufacturing process, short cycle, high efficiency and low cost.

[0074] Example 2

[0075] Embodiment 2 of the present invention provides a wafer-level packaging structure of a sensor, please refer to Fig. 20 , the wafer-level packaging structure of the sensor includes:

[0076] A second substrate 26, the second substrate 26 having a first cavity 27;

[0077] A detection structure layer, the detection structure layer includes a detection structure, and the detection structure is at least partially located above the first cavity 27;

[0078] The dielectric layer 11 covers the surface of the detection structure layer away from the second substrate 26;

[0079] A metal cofferdam 31, wherein the metal cofferdam 31 is located above the dielectric layer 11;

[0080] A third substrate 32, the third substrate 32 is located above the metal cofferdam 31, the metal cofferdam 31 and the third substrate 32 form a second cavity 33, and the second cavity 33 surrounds at least a portion of the detection structure;

[0081] The electrical connection structure leads out the electrical properties of the detection structure.

[0082] In this embodiment, the metal cofferdam 31 has the same layer structure as at least part of the electrical connection structure, that is, the metal cofferdam 31 is formed together with the electrical connection structure, such as by deposition or electroplating. The metal cofferdam 31 and part of the electrical connection structure, such as the structure in which the first connecting part 30 is higher than the dielectric layer 11, have the same material, thickness, number of layers, density, etc.

[0083] In this embodiment, the detection structure includes at least part of the thermocouple, the thermocouple includes a first thermoelectric strip and a second thermoelectric strip connected to each other, and the first thermoelectric strip and the second thermoelectric strip are stacked or arranged in parallel. In other embodiments, the detection structure as a sensing structure of the sensor can be a MEMS cantilever structure, a thermopile structure, a filter structure, etc., and the detection structure can also include at least part of thermistors or at least part of photoresistors.

[0084] In this embodiment, top silicon is also included. The top silicon is located on the side of the dielectric layer 11 away from the third substrate 32. The material of the top silicon is single crystal silicon. The first thermoelectric strip 211 and / or the second thermoelectric strip 23 are formed by the top silicon.

[0085] In this embodiment, a planarization layer 25 is included between the detection structure layer and the second substrate 26 .

[0086] In this embodiment, there are multiple detection structures, and the multiple detection structures are arranged in an array.

[0087] In this embodiment, a third cavity is provided on the side of the third substrate 32 facing the thermoelectric induction element.

[0088] In this embodiment, the third substrate 32 includes circuits.

[0089] Regarding the materials, structures and positional relationships of the second substrate 26, the flat layer 25, the thermocouple, the dielectric layer 11, the metal cofferdam 31, the third substrate 32 and the electrical connection structure, refer to the previous method embodiment part. Regarding the structures of the first cavity 27, the second cavity 33 and the third cavity, refer to the previous method embodiment part, and will not be repeated here.

[0090] The embodiment of the present invention bonds a third substrate 32 to the prepared detection structure layer to enclose a second cavity 33, and sets an electrical connection structure to lead out the electrical properties of the thermocouple to complete the packaging of the detection structure layer, thereby greatly reducing the package size and meeting the application needs of the sensor in miniaturized equipment. The second cavity 33 is not etched on the third substrate 32, but is bonded separately to enclose a cavity, which avoids the problem of poor control of the back cavity etching process and poor cavity size accuracy, and improves the measurement accuracy of the sensor. Wafer-level manufacturing process, short cycle, high efficiency, and low cost.

[0091] Furthermore, the first substrate includes top silicon, and the material of the top silicon is single crystal silicon, so that the top silicon of the SOI substrate can be directly used to form the first thermoelectric strip 211 and / or the second thermoelectric strip 23 of the thermocouple, which simplifies the process and improves the packaging efficiency.

[0092] Furthermore, the electrical connection structure is divided into a first connection part 30, a second connection part 34 and a third connection part 36, and the above three parts are formed in different processes respectively, which reduces the process difficulty and improves the yield and reliability of the wafer-level packaging of the sensor.

[0093] Furthermore, a metal cofferdam 31 is formed, and a third substrate 32 is bonded to the cofferdam 31 to form a second cavity 33, which improves the airtightness and structural strength of the sensor's wafer-level packaging, is beneficial to the temperature concentration and interference shielding of the sensor, and improves the quality, reliability and yield of the sensor's wafer-level packaging.

[0094] Furthermore, a flat layer 25 is provided and flattened, and the second substrate 26 and the detection structure layer are bonded by a melt bonding method, thereby improving the bonding alignment accuracy and the structural strength of the wafer-level packaging of the sensor, while simplifying the process, and the bonding material of the melt bonding is easy to obtain, thereby improving the packaging efficiency and reducing the packaging cost.

[0095] It should be noted that the various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the structural embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0096] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A wafer-level packaging method for a sensor, It is characterized in that include: Providing a first substrate, the first substrate comprising a base and a dielectric layer disposed on a surface of the base; forming a detection structure layer on the first substrate, wherein the detection structure layer includes a detection structure; providing a second substrate, wherein the second substrate has a first cavity; bonding the second substrate on the first substrate, with the first cavity facing the detection structure layer; removing the substrate; providing a third substrate; At least a portion of the cofferdam is provided on a side of the detection structure layer away from the second substrate and / or on the third substrate; The third substrate is bonded to the detection structure layer at a side away from the second substrate by the cofferdam, the cofferdam and the third substrate enclose a second cavity, and the second cavity faces the detection structure layer; An electrical connection structure is formed, wherein the electrical connection structure electrically leads out the detection structure layer, and the method for forming the electrical connection structure comprises: after removing the substrate, patterning the dielectric layer to form a first through hole, forming a first connection portion, and electrically connecting the detection structure through the first through hole; bonding the third substrate; Patterning the third substrate to form a second through hole, forming a second connecting portion, and electrically connecting the first connecting portion through the second through hole; After forming the second connection part, a third connection part is formed to electrically connect the second connection part, and the electrical connection structure includes the first connection part, the second connection part and the third connection part.

2. The wafer-level packaging method of the sensor according to claim 1, It is characterized in that The detection structure includes at least a portion of a thermocouple, wherein the thermocouple includes a first thermoelectric strip and a second thermoelectric strip connected to each other, wherein the first thermoelectric strip and the second thermoelectric strip are stacked or arranged in parallel.

3. The wafer-level packaging method of the sensor according to claim 2, It is characterized in that The first substrate further includes a top layer of silicon, the top layer of silicon is located on the dielectric layer, and the material of the top layer of silicon is single crystal silicon.

4. The wafer-level packaging method of the sensor according to claim 3, It is characterized in that The first thermoelectric strip and / or the second thermoelectric strip are formed by patterning the top layer of silicon.

5. The wafer-level packaging method of the sensor according to claim 2, It is characterized in that The material combinations of the thermocouple include: p-type single crystal silicon and n-type single crystal silicon, single crystal silicon and polycrystalline silicon, single crystal silicon and metal, polycrystalline silicon and metal, p-type polycrystalline silicon and n-type polycrystalline silicon, and the metal includes aluminum, copper, gold, titanium or tungsten.

6. The wafer-level packaging method of a sensor according to claim 1, It is characterized in that The method of removing the substrate includes grinding, etching or a combination thereof.

7. The wafer-level packaging method of a sensor according to claim 1, It is characterized in that The dam is formed at the same time as the first connection portion is formed. The first connection portion and the dam are made of the same material, and the dam material includes metal or polysilicon.

8. The wafer-level packaging method of a sensor according to claim 1, It is characterized in that The cofferdam is made of the same material as the third substrate.

9. The wafer-level packaging method of the sensor according to claim 8, It is characterized in that The dam is isolated from the electrical connection structure, the height of the dam is 1-20 microns, and the surface of the dam away from the detection structure layer is flush with the surface of the first connection portion away from the detection structure layer.

10. The wafer-level packaging method of a sensor according to claim 1, It is characterized in that The third substrate has a third cavity, and the cofferdam is located at the outer periphery of the third cavity.

11. The wafer-level packaging method of a sensor according to claim 10, It is characterized in that The distance between the detection structure layer and the bottom of the third cavity is 10 microns to 200 microns.

12. The wafer-level packaging method of a sensor according to claim 2, It is characterized in that After forming the thermocouple and before bonding the second substrate to the detection structure layer, the method further includes: forming a passivation layer on the thermocouple to cover the thermocouple and the first substrate.

13. The wafer-level packaging method of a sensor according to claim 1, It is characterized in that A flat layer is disposed on the detection structure layer, and the second substrate is melt-bonded to the flat layer.

14. The wafer-level packaging method of a sensor according to claim 2, It is characterized in that There are multiple thermocouples, and the multiple thermocouples are arranged in an array.

15. The wafer-level packaging method of a sensor according to claim 2, It is characterized in that The material of the second substrate includes: optical material, polymer material or semiconductor material, and the semiconductor material can transmit infrared rays.

16. A wafer-level packaging structure for a sensor, It is characterized in that include: a second substrate having a first cavity; a detection structure layer, the detection structure layer comprising a detection structure, wherein the detection structure is at least partially located above the first cavity; a dielectric layer, covering a surface of the detection structure layer away from the second substrate; A metal cofferdam, wherein the metal cofferdam is located above the dielectric layer; a third substrate, the third substrate being located above the metal cofferdam, the metal cofferdam and the third substrate forming a second cavity, and the second cavity surrounding at least a portion of the detection structure; An electrical connection structure, wherein the electrical connection structure electrically leads out the detection structure, and the electrical connection structure includes a first connection part, a second connection part, and a third connection part formed in different processes respectively, the first connection part passes through the dielectric layer and is electrically connected to the detection structure, the first connection part is located in the second cavity and is isolated from the metal cofferdam, the second connection part passes through the third substrate and is electrically connected to the first connection part, and the third connection part is electrically connected to the second connection part.

17. The wafer-level packaging structure of the sensor according to claim 16, It is characterized in that The detection structure includes at least a portion of a thermocouple, wherein the thermocouple includes a first thermoelectric strip and a second thermoelectric strip connected to each other, wherein the first thermoelectric strip and the second thermoelectric strip are stacked or arranged in parallel.

18. The wafer-level packaging structure of the sensor according to claim 16, It is characterized in that The metal dam and at least a portion of the electrical connection structure have the same layer structure.

19. The wafer-level packaging structure of the sensor according to claim 16, It is characterized in that A planar layer is included between the detection structure layer and the second substrate.

20. The wafer-level packaging structure of the sensor according to claim 16, It is characterized in that There are multiple detection structures, and the multiple detection structures are arranged in an array.

21. The wafer-level packaging structure of the sensor according to claim 16, It is characterized in that A third cavity is provided on a side of the third substrate facing the detection structure.

22. The wafer-level packaging structure of the sensor according to claim 16, It is characterized in that The third substrate contains a circuit.

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