Frequency Response Masking Filter System and Generation Method

Abstract

The present application proposes a frequency response masking (FRM) filter system and a generation method. The system includes: a controller, a storage array, and an FRM filter component; wherein, one end of the controller is connected to the signal input end, and the other end is connected to the control end of the storage array; the configuration end of the FRM filter component is connected to the output end of the storage array, the input end of the FRM filter component is connected to the signal input end, and the output end of the FRM filter component is used to output the signal after FRM processing; the controller is configured to retrieve the target parameters corresponding to the current working bandwidth from the storage array and send them to the FRM filter component to generate an FRM filter matching the current working bandwidth according to the target parameters. Thus, through this FRM filter system, the FRM filter link multiplexing of multi-bandwidth cells is realized, and the resource occupancy is reduced.

Description

Technical Field

[0001] This application relates to the field of mobile communication technologies, and in particular, to a Frequency-Response-Masking (FRM) filter system and a generation method thereof. Background Art

[0002] The Active Antenna Unit (AAU), different from the RRU and antenna separation solution in the 4G era, integrates the antenna and the RRU and is a key device for 5G.

[0003] In related technologies, under the condition that a cell requires multiple bandwidth configurations, the AAU product needs to support the operating modes of carriers under different bandwidth configurations. However, when the carrier is under different bandwidth configurations, different coefficients of FRM filters need to be switched, resulting in high resource occupancy. Summary of the Invention

[0004] The FRM filter system and generation method proposed in this application are used to solve the problem in related technologies that when a cell requires multiple bandwidth configurations, the AAU needs to switch different coefficients of FRM filters when the carrier is under different bandwidth configurations, resulting in high resource occupancy.

[0005] The FRM filter system proposed in an embodiment of one aspect of this application includes: a controller, a storage array, and a Frequency-Response-Masking (FRM) filter component; wherein, one end of the controller is connected to a signal input end, and the other end is connected to a control end of the storage array; a configuration end of the FRM filter component is connected to an output end of the storage array, an input end of the FRM filter component is connected to the signal input end, and an output end of the FRM filter component is used to output a signal after FRM processing; the controller is configured to retrieve a target parameter corresponding to the current operating bandwidth from the storage array, so that the storage array sends the target parameter to the FRM filter component; the FRM filter component is configured to generate an FRM filter matching the current operating bandwidth according to the target parameter.

[0006] Optionally, in a possible implementation manner of an embodiment of the first aspect of this application, the FRM filter component includes: a first shift register, a first Digital Signal Processor (DSP) array, a second DSP array, a third DSP array, an adder, and a subtractor;

[0007] A configuration end of the first shift register, a configuration end of the first DSP array, a configuration end of the second DSP array, and a configuration end of the third DSP array are respectively connected to respective output ends of the storage array;

[0008] The input end of the first DSP array and the input end of the first shift register are connected to the signal input end. The output end of the first DSP array is respectively connected to the input end of the second DSP array and the first input end of the subtractor;

[0009] The output end of the second DSP array is connected to the first input end of the adder;

[0010] The output end of the first shift register is connected to the second input end of the subtractor;

[0011] The output end of the subtractor is connected to the input end of the third DSP array;

[0012] The output end of the third DSP array is connected to the second input end of the adder;

[0013] The adder is configured to output the processed signal.

[0014] Optionally, in another possible implementation manner of the first aspect embodiment of the present application, the first DSP array includes M1 first DSPs that are connected in sequence and connected end to end, where M1 is the value obtained by rounding up N1 / 2;

[0015] The second DSP array includes M2 second DSPs that are connected in sequence and connected end to end, where M2 is the value obtained by rounding up N2 / 2;

[0016] The third DSP array includes M3 third DSPs that are connected in sequence and connected end to end, where M3 is the value obtained by rounding up N3 / 2;

[0017] Among them, N1 is the highest order of the interpolation prototype filter in each FRM filter corresponding to the system, N2 is the highest order of the first shielding filter in each FRM filter corresponding to the system, and N3 is the highest order of the second shielding filter in each FRM filter corresponding to the system.

[0018] Optionally, in yet another possible implementation manner of the first aspect embodiment of the present application, the system further includes: 2(M1 - 1) second shift registers connected in sequence;

[0019] Among them, the input end of the first second shift register is connected to the signal input end;

[0020] The configuration terminal of each of the second shift registers is connected to the output terminal of the memory in the storage array for storing the first delay parameter, and the output terminal of the i-th second shift register and the output terminal of the 2(M1 - 1) - (i - 1)-th second shift register are respectively connected to an input terminal of the (i + 1)-th first DSP, where i is a positive integer greater than 0 and less than or equal to M1 - 1.

[0021] Optionally, in another possible implementation manner of the first aspect embodiment of the present application, the storage array includes K memories, where K = M1 + M2 + M3 + 2, where M1 memories are respectively configured to store parameters corresponding to M1 first DSPs; M2 memories are respectively configured to store parameters corresponding to M2 second DSPs; M3 memories are respectively configured to store parameters corresponding to M3 third DSPs, one memory is configured to store the second delay parameter corresponding to the first shift register, and another memory is configured to store the first delay parameter corresponding to the M1 - 1 second shift registers.

[0022] Optionally, in another possible implementation manner of the first aspect embodiment of the present application, the system corresponds to L working bandwidths, and each memory stores L parameters respectively corresponding to the L working bandwidths.

[0023] The FRM filter generation method proposed in the second aspect embodiment of the present application includes: obtaining the current working bandwidth of the system; reading the target parameter corresponding to the current working bandwidth from the storage array; and sending the target parameter to the FRM filter component to generate an FRM filter matching the current working bandwidth.

[0024] Optionally, in a possible implementation manner of the second aspect embodiment of the present application, the reading the target parameter corresponding to the current working bandwidth from the storage array includes:

[0025] obtaining the correspondence between each parameter and the bandwidth in each memory of the storage array;

[0026] determining the target address corresponding to the current working bandwidth according to the correspondence between each parameter and the bandwidth and the position of each parameter in the memory;

[0027] reading the target parameter corresponding to the target address from the storage array.

[0028] Optionally, in another possible implementation manner of the second aspect embodiment of the present application, the order of the interpolation prototype filter in the FRM filter corresponding to the current working bandwidth is N1. Determining the target address corresponding to the current working bandwidth according to the corresponding relationship between each parameter and the bandwidth and the positions of the respective parameters in the memory includes:

[0029] Determine M1 memories respectively corresponding to the N1-order interpolation prototype filter, where M1 is the value obtained by rounding up N1 / 2;

[0030] According to the corresponding relationship between each parameter and the bandwidth in each memory and the positions of the respective parameters in the memory, determine M1 target addresses corresponding to the current working bandwidth.

[0031] Optionally, in yet another possible implementation manner of the second aspect embodiment of the present application, the FRM filter component includes a first DSP array, a first shift register, a second DSP array, and a third DSP array. The target parameters include filtering parameters, second delay parameters, first masking parameters, and second masking parameters. Sending the target parameters to the FRM filter component includes:

[0032] Send the filtering parameters to the first DSP array;

[0033] Send the second delay parameters to the first shift register;

[0034] Send the first masking parameters to the second DSP array;

[0035] Send the second masking parameters to the third DSP array.

[0036] Optionally, in yet another possible implementation manner of the second aspect embodiment of the present application, the FRM filter component further includes 2(M1 - 1) second shift registers connected in sequence. The target parameters further include first delay parameters. Sending the target parameters to the FRM filter component includes:

[0037] Send the first delay parameters to the 2(M1 - 1) second shift registers respectively, where M1 is the value obtained by rounding up N1 / 2, and N1 is the highest order of the interpolation prototype filter in each FRM filter corresponding to the FRM filter component.

[0038] The FRM filter system and generation method provided by the embodiments of the present application store the target parameters corresponding to each working bandwidth through a storage array, and the controller retrieves the target parameters corresponding to the current working bandwidth from the storage array and sends them to the FRM filter component, so that the FRM filter component generates an FRM filter matching the current working bandwidth according to the target parameters. Thus, by pre-storing the target parameters corresponding to each working bandwidth in the storage array, the target parameters are retrieved from the storage component according to the actual working bandwidth to adjust the FRM filter component, so that when the working bandwidth changes, there is no need to switch between different filter modules, and only one FRM filter module can support the working modes corresponding to multiple working bandwidths, realizing the link multiplexing of the FRM filter in a multi-bandwidth cell and reducing the resource occupancy.

[0039] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, in which:

[0041] Figure 1 is a schematic structural diagram of an FRM filter system provided by an embodiment of the present application;

[0042] Figure 2 is a schematic structural diagram of another FRM filter system provided by an embodiment of the present application;

[0043] Figure 3 is a schematic structural diagram of still another FRM filter system provided by an embodiment of the present application;

[0044] Figure 4 is a schematic structural diagram of yet another FRM filter system provided by an embodiment of the present application;

[0045] Figure 5 is a schematic flowchart of an FRM filter generation method provided by an embodiment of the present application;

[0046] Figure 6 is a schematic flowchart of another FRM filter generation method provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] In the embodiments of the present application, the term "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0048] In the embodiments of the present application, the term "plurality" means two or more, and other quantifiers are similar thereto.

[0049] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0050] The embodiments of the present application provide an FRM filter system and a generation method to address the problem in the related art that when a cell requires multiple bandwidth configurations, the AAU needs to switch FRM filters with different coefficients under different bandwidth configurations of the carrier, resulting in high resource occupancy.

[0051] Among them, the method and the device are based on the same inventive concept. Since the principles of solving problems by the method and the device are similar, the implementation of the device and the method can be referred to each other, and the repeated parts will not be elaborated.

[0052] The FRM filter system provided by the embodiments of the present application stores the target parameters corresponding to each working bandwidth through a storage array, and the controller retrieves the target parameters corresponding to the current working bandwidth from the storage array and sends them to the FRM filter component, so that the FRM filter component generates an FRM filter matching the current working bandwidth according to the target parameters. Thus, by pre-storing the target parameters corresponding to each working bandwidth in the storage array, the target parameters are retrieved from the storage component according to the actual working bandwidth to adjust the FRM filter component, so that when the working bandwidth changes, there is no need to switch between different filter modules, and only one FRM filter module can support the working modes corresponding to multiple working bandwidths, realizing the link multiplexing of the FRM filter in a multi-bandwidth cell and reducing the resource occupancy.

[0053] Next, the FRM filter system and the generation method provided by the present application will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 It is a schematic structural diagram of an FRM filter system provided by the embodiments of the present application.

[0055] As Figure 1 shown, the FRM filter system 100 includes: a controller 110, a storage array 120, and an FRM filter component 130.

[0056] Among them, one end of the controller 110 is connected to the signal input end, and the other end is connected to the control end of the storage array 120;

[0057] The configuration terminal of the FRM filter component 130 is connected to the output terminal of the storage array 120, the input terminal of the FRM filter component 130 is connected to the signal input terminal, and the output terminal of the FRM filter component 130 is used to output the signal after FRM processing;

[0058] The controller 110 is configured to retrieve the target parameters corresponding to the current working bandwidth from the storage array 120, so that the storage array 120 sends the target parameters to the FRM filter component 130;

[0059] The FRM filter component 130 is configured to generate an FRM filter that matches the current working bandwidth according to the target parameters.

[0060] Among them, the controller 110 refers to a component that can direct each component in the system to work in coordination according to the functional requirements of the instructions. For example, the controller 110 can be a processor with a relatively complex structure and strong computing power such as a CPU or a GPU, or an MCU with a relatively simple structure and low computing power, etc. The embodiments of the present application do not make any limitations in this regard.

[0061] Among them, the storage array 120 can be any storage medium composed of a large number of storage units and having write and read functions. For example, the storage array 120 can be a ROM.

[0062] Among them, the FRM filter component 130 refers to a filter module with FRM filtering function, which can be composed of multiple filters. In actual use, the appropriate FRM filter component 130 can be designed according to actual needs. The embodiments of the present application do not make any limitations in this regard.

[0063] In the embodiments of the present application, the FRM filter system 100 of the embodiments of the present application can perform filtering processing on the input signal to generate a filtered signal. However, since the performance and parameters of the filters required for input signals with different bandwidths are different, the filter parameters corresponding to each working bandwidth can be determined according to all possible working bandwidths in the actual application scenario and stored in the storage array 120 respectively.

[0064] In the embodiment of the present application, one end of the controller 110 is connected to the signal input terminal. Thus, when the controller 110 obtains the signal input from the signal input terminal, it can determine the current working bandwidth according to the obtained signal. Then, the controller 110 can retrieve the target parameter corresponding to the current working bandwidth from the storage array 120 according to the corresponding relationship between the working bandwidth and the filter parameter. After determining the target parameter, the target parameter can be sent to the FRM filter component 130 through the storage array 120, so that the FRM filter component 130 can switch the internal parameter to the target parameter to generate an FRM filter matching the current working bandwidth; and use the generated FRM filter matching the current working bandwidth to perform filtering processing on the signal input to the FRM filter component 130 to output the signal after FRM processing.

[0065] As a possible implementation, the filter parameters corresponding to each working bandwidth can be determined first according to the specific characteristics of each working bandwidth, and the corresponding relationship between the bandwidth and the filter parameter can be stored in the storage array 120. Thus, after the controller 110 determines the current working bandwidth, it can obtain the corresponding relationship between each parameter and the bandwidth in each memory of the storage array 120 from the storage array 120. Then, it can determine the target parameter corresponding to the current working bandwidth according to the corresponding relationship between each parameter and the bandwidth, and further determine the position of the target parameter in the memory according to the position of each parameter in the memory, and determine the position of the target parameter in the memory as the target address corresponding to the current working bandwidth, and read the target parameter corresponding to the target address from the storage array 120.

[0066] The FRM filter system provided by the embodiment of the present application stores the target parameters corresponding to each working bandwidth through the storage array, and the controller retrieves the target parameter corresponding to the current working bandwidth from the storage array and sends it to the FRM filter component, so that the FRM filter component generates an FRM filter matching the current working bandwidth according to the target parameter. Thus, by pre-storing the target parameters corresponding to each working bandwidth in the storage array, the target parameters are retrieved from the storage component according to the actual working bandwidth to adjust the FRM filter component, so that when the working bandwidth changes, there is no need to switch between different filter modules, and only one FRM filter module can support the working modes corresponding to multiple working bandwidths, realizing the link multiplexing of the FRM filter in multi-bandwidth cells and reducing the resource occupancy.

[0067] In a possible implementation form of the present application, the FRM filter component can be designed by a complementary filter and a shielding filter to further reduce the computational complexity of the FRM filter component design.

[0068] The following combines Figure 2, a further description of the FRM filter system provided by the embodiments of the present application will be given.

[0069] Figure 2 FIG. is a schematic structural diagram of another FRM filter system provided by the embodiments of the present application.

[0070] As Figure 2 shown, on the basis of the embodiment shown in Figure 1 the FRM filter component 130 may include: a first shift register 131, a first Digital Signal Processor (DSP) array 132, a second DSP array 133, a third DSP array 134, an adder 135, and a subtractor 136;

[0071] Among them, the configuration terminals of the first shift register 131, the first DSP array 132, the second DSP array 133, and the third DSP array 134 are respectively connected to the output terminals of the storage array 120;

[0072] The input terminal of the first DSP array 132 and the input terminal of the first shift register 131 are connected to the signal input terminal, and the output terminal of the first DSP array 132 is respectively connected to the input terminal of the second DSP array 133 and the first input terminal of the subtractor 136;

[0073] The output terminal of the second DSP array 133 is connected to the first input terminal of the adder 135;

[0074] The output terminal of the first shift register 131 is connected to the second input terminal of the subtractor 136;

[0075] The output terminal of the subtractor 136 is connected to the input terminal of the third DSP array 134;

[0076] The output terminal of the third DSP array 134 is connected to the second input terminal of the adder 135;

[0077] The adder 135 is configured to output the processed signal.

[0078] In the embodiments of the present application, the first DSP array 132 may be an interpolation prototype filter, and the second DSP array 133 and the third DSP array 134 may be masking filters. The first shift register 131 and the subtractor 136 may be used to determine the output of the interpolation complementary prototype filter corresponding to the interpolation prototype filter according to the signal input at the signal input terminal and the output of the first DSP array 132 (i.e., the interpolation prototype filter).

[0079] It should be noted that the FRM filter component 130 can be implemented by a pair of complementary filters to reduce the number of DSPs in the FRM filter component 130 and lower the hardware complexity of the FRM filter component 130. Among them, if the frequency responses of two linear-phase filters H a and H c satisfy |H a (e jw ) + H c (e jw )| = 1, then they are called complementary filters, where H a (e jw ) is the frequency response of the linear-phase filter H a , and H c (e jw ) is the frequency response of the linear-phase filter H c . When the frequency response is transferred to the Z domain, |H a (z) + H c (z)| = z -(N-1)*M / 2 , where N is the length of the linear-phase filter and M is the interpolation factor. It can be seen that for a pair of complementary filters, the output of the linear-phase filter H c can be obtained by subtracting the output of the linear-phase filter H a from the delayed form of the input signal.

[0080] Therefore, in the embodiment of the present application, a first shift register 131 and a subtractor 136 can be introduced into the FRM filter component 130. The input end of the first shift register 131 is connected to the signal input end, and the output end of the first shift register 131 is connected to the second input end of the subtractor 136, so as to delay the input signal through the first shift register 131, generate a delayed form of the input signal and input it into the subtractor 136; and the output end of the first DSP array 132 is connected to the first input end of the subtractor 136, so as to subtract the output of the first DSP array 132 from the delayed form of the input signal through the subtractor 136 to generate the output of the interpolation complementary prototype filter corresponding to the first DSP array 132.

[0081] In the embodiment of the present application, as Figure 2As shown in the figure, the FRM filter component 130 includes two branches. The upper branch consists of a first DSP array 132 (i.e., the interpolation prototype filter) and a second DSP array 133 (i.e., the first shielding filter), and the lower branch consists of a first shift register 131, a subtractor (i.e., the interpolation complementary prototype filter), and a third DSP array 134 (the second shielding filter). Among them, the function of the second DSP array 133 is to select the required frequency components from the output of the first DSP array 132 (i.e., the interpolation prototype filter); the function of the third DSP array 134 is to select the required frequency components from the output of the subtractor 136 (i.e., the interpolation complementary prototype filter). Then, the adder 135 adds the output of the second DSP array 133 and the output of the third DSP array 134 to generate the processed output signal.

[0082] It should be noted that the second DSP array 133 and the third DSP array 134 need to have the same group delay, so that when the adder 135 adds their outputs, they can be properly complemented within the passband. When the parameters of the second DSP array 133 and the third DSP array 134 are inconsistent, a little delay needs to be added before and after to balance their group delay characteristics.

[0083] In the embodiment of the present application, since the first shift register 131, the first DSP array 132, the second DSP array 133, and the third DSP array 134 all have their own parameters, the configuration terminals of the first shift register 131, the first DSP array 132, the second DSP array 133, and the third DSP array 134 can be connected to the output terminal of the storage array 120, so that the storage array 120 transmits the parameters corresponding to the first shift register 131, the first DSP array 132, the second DSP array 133, and the third DSP array 134 included in the target parameters to the first shift register 131, the first DSP array 132, the second DSP array 133, and the third DSP array 134 respectively, so that the first shift register 131, the first DSP array 132, the second DSP array 133, and the third DSP array 134 adjust their internal parameters according to their respective parameters to generate an FRM filter matching the current working bandwidth, and then process the signal input to the system at the signal input end through the generated FRM filter to generate the processed signal.

[0084] Furthermore, since both the interpolation prototype filter and the shielding filter can be composed of multiple DSPs, and the DSPs in symmetric positions can be reused to reduce the number of DSPs and further reduce the hardware complexity of the FRM filter component. That is, in a possible implementation form of the embodiment of the present application, as Figure 3 shown, in Figure 2Based on the illustrated embodiments, the first DSP array 132 may include M1 first DSPs (1321) connected in sequence and end to end, where M1 is the value obtained by rounding up N1 / 2; the second DSP array 133 includes M2 second DSPs (not shown in the figure) connected in sequence and end to end, where M2 is the value obtained by rounding up N2 / 2; the third DSP array 134 includes M3 third DSPs (not shown in the figure) connected in sequence and end to end, where M3 is the value obtained by rounding up N3 / 2; where N1 is the highest order of the interpolation prototype filter in each FRM filter corresponding to the system, N2 is the highest order of the first shielding filter in each FRM filter corresponding to the system, and N3 is the highest order of the second shielding filter in each FRM filter corresponding to the system.

[0085] It should be noted that since the system works at different bandwidths, the orders of the FRM filters in the system may be different. Therefore, the maximum value of the orders of the FRM filters at different bandwidths can be determined as the highest order of the FRM filter. For example, for a cell that can work at three bandwidths of 60M, 80M, and 100M, when the cell works at the three bandwidths of 60M, 80M, and 100M respectively, the corresponding orders of the interpolation prototype filters are 29, 39, and 39. Therefore, the highest order N1 of the interpolation prototype filter can be determined to be 39.

[0086] In the embodiments of the present application, since the parameters of the first DSPs (1321) in the first DSP array 132 are symmetrically set, and the symmetric parameters can reuse the same DSP, the number of the first DSPs (1321) included in the first DSP array 132 can be determined according to half of the highest order of the interpolation prototype filter. For example, if the highest order N1 of the interpolation prototype filter is 39, then M1 = 19, that is, the first DSP array 132 includes 19 first DSPs (1321) connected in sequence and end to end. Correspondingly, the values of M2 and M3 can also be determined in the same manner as described above, which will not be elaborated here; and the connection manner of the second DSPs in the second DSP array 133 and the connection manner of the third DSPs in the third DSP array 134 are the same as the connection manner of the first DSPs (1321) in the first DSP array 132, so they are not shown in Figure 3 the figure.

[0087] Furthermore, since different interpolation factors M will also cause different delays between the DSPs in the interpolation prototype filter, different delay registers can be used to transmit delay parameters to each first DSP respectively to perform group delay processing on the first DSP array 132. That is, in a possible implementation form of the embodiments of the present application, as Figure 4 shown, inFigure 3 Based on the illustrated embodiments, the above FRM filter system 100 may further include: 2(M1 - 1) second shift registers 140 connected in sequence;

[0088] wherein, the input end of the first second shift register is connected to the signal input end;

[0089] The configuration end of each second shift register 140 is connected to the output end of the memory in the storage array 120 for storing the first delay parameter, and the output end of the i-th second shift register 140 and the output end of the 2(M1 - 1) - (i - 1)-th second shift register 140 are respectively connected to an input end of the (i + 1)-th first DSP (1321), where i is a positive integer greater than 0 and less than or equal to M1 - 1.

[0090] As a possible implementation, since symmetric delay parameters can reuse the same DSP to reduce the number of DSPs, the output ends of two second shift registers 140 with symmetric delay parameters can be connected to the input end of the same first DSP (1321) to achieve the reuse of DSPs.

[0091] For example, if N1 = 39, then M1 = 19, and the number of second shift registers 140 is 36. Since the first first DSP (1321) does not require delay, the output ends of the first and 36th second shift registers 140 can be connected to an input end of the second first DSP (1321); the output ends of the second and 35th second shift registers 140 can be connected to an input end of the third first DSP (1321); the output ends of the third and 34th second shift registers 140 can be connected to an input end of the fourth first DSP (1321), and so on.

[0092] In the embodiments of the present application, the delay parameters between the first DSPs 1321 in the first DSP array 132 can be determined according to the interpolation factor of the interpolation prototype filter and stored in the memory of the storage array 120. Thus, when the controller 110 obtains the signal input from the signal input end, it can retrieve the delay parameters from the memory storing the delay parameters and send them to each second shift register 140 through the storage array 120. Then, each second shift register 140 delays the signal input from the signal input end, and then each second shift register 140 sends the delayed signal to the first DSP (1321) connected thereto.

[0093] It should be noted that the method for retrieving the delay parameter from the storage array 120 is the same as the method for retrieving the target parameter from the storage array 120. The specific implementation process and principle can refer to the detailed description of the above embodiments, which will not be elaborated here.

[0094] Furthermore, different memories in the storage array 120 can be used to store the parameters of different DSPs to improve the data reading speed. That is, in a possible implementation manner of the embodiment of the present application, the storage array 120 may include K memories, where K = M1 + M2 + M3 + 2. Among them, M1 memories are respectively configured to store the parameters corresponding to M1 first DSPs; M2 memories are respectively configured to store the parameters corresponding to M2 second DSPs; M3 memories are respectively configured to store the parameters corresponding to M3 third DSPs, one memory is configured to store the second delay parameter corresponding to the first shift register, and another memory is configured to store the first delay parameter corresponding to M1 - 1 second shift registers.

[0095] In the embodiment of the present application, one memory in the storage array 120 can store the parameters corresponding to one DSP, so as to directly read the parameters corresponding to each DSP from the memory according to the position or address information of the memory, improving the data reading speed. Therefore, assuming that the first DSP (1321), the second DSP, and the third DSP are all 19, that is, M1 = M2 = M3 = 19, it can be determined that the storage array 120 may include 59 memories. Among them, 19 memories are respectively used to store the parameters corresponding to 19 first DSPs (1321), 19 memories are respectively used to store the parameters corresponding to 19 second DSPs, and 19 memories are respectively used to store the parameters corresponding to 19 third DSPs; in addition, for the remaining two memories, one memory is used to store the second delay parameter corresponding to the first shift register 131, and another memory is used to store the first delay parameter corresponding to each second shift register 140.

[0096] Furthermore, since the parameters corresponding to each DSP may be different when there are multiple working bandwidths in the cell, one memory can store multiple parameters corresponding to one DSP. That is, in a possible implementation form of the embodiment of the present application, the above FRM filter system 100 corresponds to L working bandwidths, and each memory stores L parameters respectively corresponding to the L working bandwidths.

[0097] For example, if the FRM filter system 100 is applied to a cell that can operate at three bandwidths of 60M, 80M, and 100M, the FRM filter system 100 corresponds to three operating bandwidths. Thus, three parameters corresponding to each DSP in the FRM filter component 130 can be pre-calculated at the three operating bandwidths, and then the three parameters corresponding to one DSP are stored in the same memory.

[0098] The FRM filter system provided by the embodiments of the present application stores the target parameters corresponding to each operating bandwidth through a storage array, and the controller retrieves the target parameters corresponding to the current operating bandwidth from the storage array and sends them to the FRM filter component, so that the FRM filter component generates an FRM filter matching the current operating bandwidth according to the target parameters. Moreover, the FRM filter component is designed by a complementary filter and a shielding filter, and the DSPs are reused with symmetric parameters. Furthermore, the parameters corresponding to one DSP are stored in one memory in the storage array. Therefore, not only the FRM filter link multiplexing in a multi-bandwidth cell is realized, the resource occupancy is reduced, but also the number of DSPs is further reduced, the hardware complexity of the FRM filter is reduced, and the data reading speed is improved.

[0099] To implement the above embodiments, the present application also proposes an FRM filter generation method.

[0100] Figure 5 It is a schematic flowchart of an FRM filter generation method provided by the embodiments of the present application.

[0101] As Figure 5 shown, the FRM filter generation method includes the following steps:

[0102] Step 101, obtain the current operating bandwidth of the system.

[0103] It should be noted that the system may be the FRM filter system in the above embodiments. The FRM filter system of the embodiments of the present application can filter the input signal to generate a filtered signal. However, since the performance and parameters of the filters required for input signals with different bandwidths are different, the filter parameters corresponding to each operating bandwidth can be determined according to all possible operating bandwidths in the actual application scenario and stored in the storage array of the FRM filter system respectively.

[0104] In the embodiments of the present application, one end of the controller of the FRM filter system can be connected to the signal input end. Thus, when the controller obtains the signal input from the signal input end, the current operating bandwidth can be determined according to the obtained signal.

[0105] Step 102, read the target parameters corresponding to the current operating bandwidth from the storage array.

[0106] In an embodiment of the present application, after the controller determines the current operating bandwidth, the target parameters corresponding to the current operating bandwidth can be retrieved from the storage array according to the corresponding relationship between the operating bandwidth and the filter parameters.

[0107] As a possible implementation, step 102 above may include:

[0108] Obtain the corresponding relationship between each parameter and the bandwidth in each memory of the storage array;

[0109] Determine the target address corresponding to the current operating bandwidth according to the corresponding relationship between each parameter and the bandwidth and the positions of the respective parameters in the memory;

[0110] Read the target parameters corresponding to the target address from the storage array.

[0111] As a possible implementation, the filter parameters corresponding to each operating bandwidth can be determined first according to the specific characteristics of each operating bandwidth, and the corresponding relationship between the bandwidth and the filter parameters can be stored in the storage array. Thus, after the current operating bandwidth is determined, the corresponding relationship between each parameter and the bandwidth in each memory of the storage array can be obtained from the storage array. Then, the target parameters corresponding to the current operating bandwidth can be determined according to the corresponding relationship between each parameter and the bandwidth. Furthermore, according to the positions of the respective parameters in the memory, the position of the target parameters in the memory can be determined, and the position of the target parameters in the memory can be determined as the target address corresponding to the current operating bandwidth, so as to read the target parameters corresponding to the target address from the storage array.

[0112] Furthermore, since each FRM filter in the FRM filter system may include multiple DSPs, and the parameters corresponding to each DSP can be stored in one memory, the memories corresponding to each FRM filter can be determined first, and then the specific addresses of the respective parameters corresponding to the FRM filter can be further determined. That is, in a possible implementation form of an embodiment of the present application, if the order of the interpolation prototype filter in the FRM filter corresponding to the current operating bandwidth is N1, then the determining the target address corresponding to the current operating bandwidth according to the corresponding relationship between each parameter and the bandwidth and the positions of the respective parameters in the memory may include:

[0113] Determine M1 memories respectively corresponding to the N1-order interpolation prototype filter, where M1 is the value obtained by rounding up N1 / 2;

[0114] Determine M target addresses corresponding to the current operating bandwidth according to the corresponding relationship between each parameter and the bandwidth in each memory and the positions of the respective parameters in the memory.

[0115] In the embodiment of the present application, since the FRM filter system may include an interpolation prototype filter and two shield filters, and multiple DSPs may be included in both the interpolation prototype filter and the two shield filters, and one memory in the storage array can be used to store the parameters corresponding to one DSP to improve the data reading speed. Therefore, the memories corresponding to each filter can be determined in sequence, and then the addresses corresponding to the Mig filter can be determined from the positions of the memories corresponding to each filter in the storage array. The following takes the interpolation prototype filter as an example for specific description.

[0116] In the embodiment of the present application, the order of the interpolation prototype filter can determine the number of parameters and the number of DSPs corresponding to the interpolation prototype filter. For example, the number of DSPs corresponding to the Nth-order interpolation prototype filter can be M1, and correspondingly, the number of parameters is also M1. Therefore, the positions of the M1 memories corresponding to the Nth-order interpolation prototype filter in the storage array can be determined first, and then according to the correspondence between the parameters and the working bandwidth, the M1 target parameters corresponding to the current working bandwidth can be determined; furthermore, according to the positions of the parameters in the M1 memories in the memories, the positions of the M1 target parameters in the M1 memories can be determined, that is, the M1 target addresses corresponding to the current working bandwidth.

[0117] It should be noted that the method for determining the target addresses of the parameters corresponding to other filters in the system is the same as the above method, and will not be elaborated here.

[0118] Step 103: Send the target parameters to the FRM filter component to generate an FRM filter matching the current working bandwidth.

[0119] In the embodiment of the present application, after the controller determines the target parameters, the target parameters can be sent to the FRM filter component in the system through the storage array, so that the FRM filter component can switch the internal parameters to the target parameters to generate an FRM filter matching the current working bandwidth; and use the generated FRM filter matching the current working bandwidth to filter the signal input to the FRM filter component to output the signal after FRM processing.

[0120] The FRM filter generation method provided by the embodiments of the present application stores the target parameters corresponding to each working bandwidth in a storage array, and the controller retrieves the target parameters corresponding to the current working bandwidth from the storage array and sends them to the FRM filter component, so that the FRM filter component generates an FRM filter matching the current working bandwidth according to the target parameters. Thus, by pre-storing the target parameters corresponding to each working bandwidth in the storage array, the target parameters are retrieved from the storage component according to the actual working bandwidth to adjust the FRM filter component, so that when the working bandwidth changes, there is no need to switch between different filter modules, and only one FRM filter module can support the working modes corresponding to multiple working bandwidths, realizing the link multiplexing of the FRM filter in a multi-bandwidth cell and reducing the resource occupancy.

[0121] In a possible implementation form of the present application, since the FRM filter component may include multiple filters, the parameters corresponding to each filter can be sent to each filter respectively to improve the efficiency and accuracy of parameter transmission.

[0122] The following combines Figure 6 , and further illustrates the FRM filter generation method provided by the embodiments of the present application.

[0123] Figure 6 It is a schematic flowchart of another FRM filter generation method provided by the embodiments of the present application.

[0124] As Figure 6 shown, the FRM filter generation method includes the following steps:

[0125] Step 201, obtain the current working bandwidth of the system.

[0126] For the specific implementation process and principle of the above step 201, reference can be made to the detailed description of the above embodiments, which will not be elaborated here.

[0127] Step 202, read the target parameters corresponding to the current working bandwidth from the storage array, where the target parameters include filtering parameters, second delay parameters, first shielding parameters, and second shielding parameters.

[0128] In the embodiments of the present application, the FRM filter component may include a first DSP array, a first shift register, a second DSP array, and a third DSP array. Therefore, the target parameters may include the filtering parameters corresponding to the first DSP array, the second delay parameters corresponding to the first shift register, the first shielding parameters corresponding to the second DSP array, and the second shielding parameters corresponding to the third DSP array.

[0129] For the specific implementation process and principle of the above step 202, reference can be made to the detailed description of the above embodiments, which will not be elaborated here.

[0130] Step 203: Send the filtering parameters to the first DSP array.

[0131] In the embodiment of the present application, since the first shift register, the first DSP array, the second DSP array, and the third DSP array all have their own parameters, the configuration terminals of the first shift register, the first DSP array, the second DSP array, and the third DSP array can be connected to the output terminal of the storage array, so that the storage array transmits the filtering parameters, the second delay parameter, the first shielding parameter, and the second shielding parameter included in the target parameters to the first DSP array, the first shift register, the second DSP array, and the third DSP array respectively, so that the first DSP array, the first shift register, the second DSP array, and the third DSP array respectively adjust their internal parameters according to their own parameters to generate an FRM filter matching the current working bandwidth, and then process the signal input into the system at the signal input terminal through the generated FRM filter to generate a processed signal.

[0132] Furthermore, since both the interpolation prototype filter and the shielding filter can be composed of multiple DSPs, and the DSPs in symmetric positions can be reused to reduce the number of DSPs and further reduce the hardware complexity of the FRM filter component. That is, in a possible implementation form of the embodiment of the present application, the above FRM filter component may further include 2(M1 - 1) second shift registers connected in sequence, and the target parameter may further include a first delay parameter; correspondingly, the above step 203 may include:

[0133] Send the first delay parameter to 2(M1 - 1) second shift registers respectively, where M1 is the value obtained by rounding up N1 / 2, and N1 is the highest order of the interpolation prototype filter in each FRM filter corresponding to the FRM filter component.

[0134] In the embodiment of the present application, since different interpolation factors M will also cause different delays between the DSPs in the interpolation prototype filter, different delay registers can be used to transmit the delay parameters to each first DSP respectively to perform group delay processing on the first DSP array 132.

[0135] As a possible implementation method, since symmetric delay parameters can reuse the same DSP to reduce the number of DSPs, the output terminals of two second shift registers with symmetric delay parameters can be connected to the input terminal of the same first DSP in the first DSP array to achieve DSP reuse.

[0136] For example, if N1 = 39, then M1 = 19, and the number of second shift registers is 36. Since the first first DSP does not need to introduce a delay, the output terminals of the first and 36th second shift registers can be connected to an input terminal of the second first DSP; the output terminals of the second and 35th second shift registers can be connected to an input terminal of the third first DSP; the output terminals of the third and 34th second shift registers can be connected to an input terminal of the fourth first DSP, and so on.

[0137] In the embodiment of the present application, the delay parameters between the first DSPs in the first DSP array can be determined according to the interpolation factor of the interpolation prototype filter and stored in the memory of the storage array. Thus, when the controller obtains the signal input from the signal input terminal, the delay parameters can be retrieved from the memory storing the delay parameters and sent to each second shift register through the storage array. Then, each second shift register performs a delay process on the signal input from the signal input terminal, and then each second shift register sends the delayed signal to the first DSP connected thereto.

[0138] It should be noted that the manner of retrieving the delay parameters from the storage array is the same as the manner of retrieving the target parameters from the storage array. The specific implementation process and principle can refer to the detailed description of the above embodiments and will not be elaborated here.

[0139] Step 204: Send the second delay parameter to the first shift register.

[0140] Step 205: Send the first masking parameter to the second DSP array.

[0141] Step 206: Send the second masking parameter to the third DSP array to generate an FRM filter matching the current working bandwidth.

[0142] In the embodiment of the present application, since the configuration terminals of the first shift register, the first DSP array, the second DSP array, and the third DSP array are all connected to the output terminal of the storage array, after obtaining the target parameters, the second delay parameter, the first masking parameter, and the second masking parameter included in the target parameters can be respectively transmitted to the first shift register, the second DSP array, and the third DSP array through the configuration terminals of the first shift register, the second DSP array, and the third DSP array, so that the first shift register, the second DSP array, and the third DSP array respectively adjust their internal parameters according to their respective parameters to generate an FRM filter matching the current working bandwidth. Then, the signal input into the system from the signal input terminal is processed by the generated FRM filter to generate a processed signal.

[0143] The FRM filter generation method provided by the embodiments of this application stores the target parameters corresponding to each working bandwidth in a storage array, and the controller retrieves the target parameters corresponding to the current working bandwidth from the storage array and sends them to the FRM filter component, so that the FRM filter component generates an FRM filter matching the current working bandwidth according to the target parameters; moreover, the FRM filter component is designed by a complementary filter and a shielding filter, and the DSP is reused by symmetric parameters. Furthermore, a memory in the storage array stores the parameters corresponding to one DSP, thereby not only realizing the link multiplexing of the FRM filter for multi-bandwidth cells, reducing the resource occupancy, but also further reducing the number of DSPs, reducing the hardware complexity of the FRM filter, and improving the data reading speed.

[0144] It should be noted here that the above method provided by the embodiments of this application can achieve all the functions implemented by the above system embodiments and can achieve the same technical effects. Therefore, the same parts and beneficial effects as those in the system embodiments will not be specifically described in this embodiment.

[0145] Those skilled in the art should understand that the embodiments of this application can be provided as a method, a system, or a computer program product. Therefore, this application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories and optical memories, etc.) containing computer-usable program code.

[0146] This application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of this application. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer-executable instructions. These computer-executable instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0147] These processor-executable instructions can also be stored in a processor-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the processor-readable memory generate a manufactured article including an instruction device, and the instruction device realizes the functions in Figure 1 one process or multiple processes and / or blocks Figure 1The functions specified in one or more blocks.

[0148] These processor-executable instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the steps of the functions specified in Figure 1 one process or more processes and / or blocks Figure 1 the functions specified in one block or more blocks.

[0149] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these changes and modifications.

Claims

1. A frequency response shielding filter system, characterized in that, Comprising: A controller, a storage array, and a frequency response masking (FRM) filter component; Wherein, one end of the controller is connected to a signal input end, and the other end is connected to a control end of the storage array; A configuration end of the FRM filter component is connected to an output end of the storage array, an input end of the FRM filter component is connected to the signal input end, and an output end of the FRM filter component is used to output a signal after FRM processing; The controller is configured to retrieve a target parameter corresponding to a current working bandwidth from the storage array, so that the storage array sends the target parameter to the FRM filter component; The FRM filter component is configured to generate an FRM filter matching the current working bandwidth according to the target parameter; wherein, the FRM filter component includes two branches, the upper branch is composed of an interpolation prototype filter and a first masking filter, and the lower branch is composed of a first shift register, an interpolation complementary prototype filter, and a second masking filter. The first masking filter is configured to select required frequency components from the output of the prototype filter, and the second masking filter is configured to select required frequency components from the output of the interpolation complementary prototype filter.

2. The system according to claim 1, wherein The FRM filter component includes: a first shift register, a first digital signal processor (DSP) array, a second DSP array, a third DSP array, an adder, and a subtractor; A configuration end of the first shift register, a configuration end of the first DSP array, a configuration end of the second DSP array, and a configuration end of the third DSP array are respectively connected to respective output ends of the storage array; An input end of the first DSP array and an input end of the first shift register are connected to the signal input end, and an output end of the first DSP array is respectively connected to an input end of the second DSP array and a first input end of the subtractor; An output end of the second DSP array is connected to a first input end of the adder; An output end of the first shift register is connected to a second input end of the subtractor; An output end of the subtractor is connected to an input end of the third DSP array; An output end of the third DSP array is connected to a second input end of the adder; The adder is configured to output a processed signal.

3. The system according to claim 2, wherein The first DSP array includes M1 first DSPs connected in sequence and end to end, where M1 is the value obtained by rounding up N1 / 2; The second DSP array includes M2 second DSPs connected in sequence and end to end, where M2 is the value obtained by rounding up N2 / 2; The third DSP array includes M3 third DSPs connected in sequence and end to end, where M3 is the value obtained by rounding up N3 / 2; Wherein, N1 is the highest order of the interpolation prototype filter in each FRM filter corresponding to the system, N2 is the highest order of the first shielding filter in each FRM filter corresponding to the system, and N3 is the highest order of the second shielding filter in each FRM filter corresponding to the system.

4. The system according to claim 3, wherein It further includes: 2(M1 - 1) second shift registers connected in sequence; Wherein, the input end of the first second shift register is connected to the signal input end; The configuration end of each second shift register is connected to the output end of the memory in the storage array for storing the first delay parameter, and the output end of the i-th second shift register and the output end of the 2(M1 - 1)-(i - 1)-th second shift register are respectively connected to an input end of the (i + 1)-th first DSP, where i is a positive integer greater than 0 and less than or equal to M1 - 1.

5. The system according to claim 4, wherein The storage array includes K memories, where K = M1 + M2 + M3 + 2. Among them, M1 memories are respectively configured to store the parameters corresponding to M1 first DSPs; M2 memories are respectively configured to store the parameters corresponding to M2 second DSPs; M3 memories are respectively configured to store the parameters corresponding to M3 third DSPs, one memory is configured to store the second delay parameter corresponding to the first shift register, and another memory is configured to store the first delay parameter corresponding to the M1 - 1 second shift registers.

6. The system according to claim 5, wherein The system corresponds to L working bandwidths, and each memory stores L parameters respectively corresponding to the L working bandwidths.

7. A method for generating a frequency response shielding filter, characterized in that, It includes: Obtain the current working bandwidth of the system; Read the target parameter corresponding to the current working bandwidth from the storage array; Send the target parameter to the FRM filter component to generate an FRM filter matching the current working bandwidth. Among them, the FRM filter component includes two branches. The upper branch is composed of an interpolation prototype filter and a first shielding filter, and the lower branch is composed of a first shift register, an interpolation complementary prototype filter, and a second shielding filter. Among them, the first shielding filter is configured to select the required frequency components from the output of the prototype filter, and the second shielding filter is configured to select the required frequency components from the output of the interpolation complementary prototype filter.

8. The method according to claim 7, wherein The step of reading the target parameter corresponding to the current working bandwidth from the storage array includes: Obtain the correspondence between each parameter and the bandwidth in each memory of the storage array; Determine the target address corresponding to the current working bandwidth according to the correspondence between each parameter and the bandwidth and the position of each parameter in the memory; Read the target parameter corresponding to the target address from the storage array.

9. The method according to claim 8, wherein The order of the interpolation prototype filter in the FRM filter corresponding to the current working bandwidth is N1. The step of determining the target address corresponding to the current working bandwidth according to the correspondence between each parameter and the bandwidth and the position of each parameter in the memory includes: Determine the M1 memories corresponding to the N1 - order interpolation prototype filters respectively, where M1 is the value obtained by rounding up N1 / 2; Determine the M1 target addresses corresponding to the current working bandwidth according to the corresponding relationship between each parameter in each memory and the bandwidth and the position of each parameter in the memory.

10. The method according to claim 7, characterized in that The FRM filter component includes a first DSP array, a first shift register, a second DSP array and a third DSP array. The target parameters include filter parameters, second delay parameters, first masking parameters and second masking parameters. Sending the target parameters to the FRM filter component includes: Sending the filter parameters to the first DSP array; Sending the second delay parameters to the first shift register; Sending the first masking parameters to the second DSP array; Sending the second masking parameters to the third DSP array.

11. The method according to claim 10, wherein The FRM filter component further includes 2(M1 - 1) second shift registers connected in sequence. The target parameters further include first delay parameters. Sending the target parameters to the FRM filter component includes: Sending the first delay parameters to the 2(M1 - 1) second shift registers respectively, where M1 is the value obtained by rounding up N1 / 2, and N1 is the highest order of the interpolation prototype filters in each FRM filter corresponding to the FRM filter component.

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