A voltage monitoring circuit with hysteresis characteristics

Abstract

The present invention belongs to the technical field of voltage monitoring circuits, and more particularly to a voltage monitoring circuit with hysteresis characteristics. By providing a seventh field-effect transistor (FET), the present application creates a positive feedback branch in the circuit. This positive feedback branch is a parallel voltage positive feedback circuit in which the signal at the drain of the seventh FET is amplified by two stages, namely, the second and seventh FETs, and then returns to the drain of the seventh FET. When the voltage at the negative input of the hysteresis comparator exceeds the voltage at the positive input, the seventh FET conducts during the decreasing phase, providing a hysteresis voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of voltage monitoring circuits, and in particular relates to a voltage monitoring circuit with hysteresis characteristics. Background Art

[0002] During read, write, and erase operations on Nor Flash, power supply fluctuations are uncontrollable. Since read operations only retrieve information from Nor Flash, while erase and write operations modify the Nor Flash's internal state, higher reliability is required to prevent incorrect data from being written. The voltage monitoring circuit ensures that the chip operates normally within a safe voltage range.

[0003] In actual applications, the power supply voltage is not a stable value and may fluctuate due to noise or internal operation power consumption. If the power supply voltage jitters, the output value of the traditional voltage monitoring circuit will also jitter, reducing the reliability of the chip.

[0004] Therefore, the existing technology needs to be improved and developed. Summary of the Invention

[0005] The purpose of this application is to provide a voltage monitoring circuit with hysteresis characteristics, which can improve the anti-interference ability of the voltage monitoring circuit and enhance the reliability of the chip.

[0006] To solve the above technical problems, the present application provides a voltage monitoring circuit with hysteresis characteristics, including a first field-effect transistor, a pull-up resistor, a pull-down resistor and a NAND gate, and also includes a hysteresis comparator, the hysteresis comparator including a positive feedback module for providing a hysteresis voltage, the first field-effect transistor, the pull-up resistor and the pull-down resistor are connected in series in sequence, the gate of the first field-effect transistor is connected to the inverted signal of the enable signal, the source of the first field-effect transistor is connected to the power supply voltage, the drain of the first field-effect transistor is connected to the pull-up resistor, the pull-down resistor is grounded, the negative input of the hysteresis comparator is connected to the series node of the pull-up resistor and the pull-down resistor, the positive input of the hysteresis comparator is connected to a reference voltage, the output of the hysteresis comparator is connected to the first input of the NAND gate, the second input of the NAND gate is connected to the enable signal, and the output of the NAND gate outputs a voltage monitoring signal.

[0007] The voltage monitoring circuit is provided with a hysteresis comparator, which improves the anti-interference ability of the voltage monitoring circuit and enhances the reliability of the chip.

[0008] Furthermore, the hysteresis comparator includes a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor and the positive feedback module;

[0009] The gate of the third field effect transistor is the positive input terminal of the hysteresis comparator, the gate of the fifth field effect transistor is the negative input terminal of the hysteresis comparator, and the parallel connection node of the drain of the fifth field effect transistor and the output terminal of the positive feedback module is the output terminal of the hysteresis comparator;

[0010] The source of the second field-effect transistor and the source of the fourth field-effect transistor are respectively connected to the power supply voltage, the drain of the second field-effect transistor is connected to the drain of the third field-effect transistor, the source of the third field-effect transistor is connected in parallel with the source of the fifth field-effect transistor and then connected to the drain of the sixth field-effect transistor, the gate of the second field-effect transistor is connected to the gate of the fourth field-effect transistor, the drain of the second field-effect transistor is connected to the gate of the second field-effect transistor, the drain of the fourth field-effect transistor is connected to the drain of the fifth field-effect transistor, the gate of the sixth field-effect transistor is connected to the bias voltage, and the source of the sixth field-effect transistor is grounded.

[0011] The positive feedback module of the hysteresis comparator creates a positive feedback branch in the circuit. The positive feedback branch makes the reference voltage smaller, and the smaller power supply voltage division can cause the hysteresis comparator to flip.

[0012] Furthermore, it also includes a voltage-dividing resistor, which is connected between the pull-up resistor and the pull-down resistor, and the negative input terminal of the hysteresis comparator is connected to the series node of the pull-up resistor and the voltage-dividing resistor.

[0013] The slope of Vin rising or falling can be controlled by adjusting the resistance of the voltage divider resistor.

[0014] Furthermore, the hysteresis comparator is a voltage comparator.

[0015] Furthermore, the positive feedback module is a seventh field effect transistor.

[0016] Furthermore, the seventh field effect transistor is a PMOS transistor.

[0017] Furthermore, the gate of the seventh field effect tube is the input end of the positive feedback module, the source of the seventh field effect tube is connected to the power supply voltage, and the drain of the seventh field effect tube is connected to the gate of the fourth field effect tube.

[0018] Furthermore, the first field effect transistor is a PMOS transistor.

[0019] Furthermore, the second field effect transistor and the fourth field effect transistor are both PMOS transistors.

[0020] Furthermore, the third field effect transistor, the fifth field effect transistor and the sixth field effect transistor are all NMOS transistors.

[0021] As can be seen from the above, the present application, by providing a seventh FET, creates a positive feedback branch in the circuit. This positive feedback branch is a parallel voltage positive feedback, where the signal at the drain of the seventh FET is amplified by the second and seventh FETs and then returns to the drain of the seventh FET. When the voltage at the negative input of the hysteresis comparator exceeds the voltage at the positive input, the seventh FET conducts during the decreasing phase, providing a hysteresis voltage.

[0022] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural diagram of a voltage monitoring circuit in the prior art.

[0024] Figure 2 for Figure 1 Timing diagram of circuit operation.

[0025] Figure 3 This is a schematic structural diagram of a voltage monitoring circuit according to the first embodiment of the present application.

[0026] Figure 4 Schematic diagram of the structure of the hysteresis comparator in the first embodiment of the present application.

[0027] Figure 5 for Figure 3 Timing diagram of circuit operation.

[0028] Figure 6 FIG. 1 is a structural diagram of a voltage monitoring circuit according to a second embodiment of the present application.

[0029] Explanation of labels: 1. First field-effect transistor; 2. Pull-up resistor; 3. Voltage divider resistor; 4. Pull-down resistor; 5. Hysteresis comparator; 51. Second field-effect transistor; 52. Third field-effect transistor; 53. Fourth field-effect transistor; 54. Fifth field-effect transistor; 55. Sixth field-effect transistor; 56. Positive feedback module; 6. NAND gate; 7. Single-limit comparator. DETAILED DESCRIPTION

[0030] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention.

[0031] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0032] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections, or mutual communication; direct connections or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0033] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0034] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0035] Figure 1 The schematic diagram of the voltage monitoring circuit in the prior art is shown. The voltage detection circuit includes a first field effect transistor 1, a pull-up resistor 2, a pull-down resistor 4, a single-limit comparator 7, and a NAND gate 6. The first field effect transistor 1, the pull-up resistor 2, and the pull-down resistor 4 are connected in series. The gate of the first field effect transistor 1 is connected to the inverted signal enb of the enable signal en, and the source of the first field effect transistor 1 is connected to the power supply voltage V cc The drain of the first field effect transistor 1 is connected to the pull-up resistor 2, the pull-down resistor 4 is grounded, the negative input terminal of the single-limit comparator 7 is connected to the series node of the pull-up resistor 2 and the pull-down resistor 4, and the positive input terminal of the single-limit comparator 7 is connected to the reference voltage V ref The output end of the single limit comparator 7 is connected to the first input end of the NAND gate 6, the second input end of the NAND gate 6 is connected to the enable signal en, and the output end of the NAND gate 6 outputs the voltage monitoring signal V cc_detect .

[0036] The first field-effect transistor 1 is a PMOS transistor, which is generally used as the upper transistor, and the NMOS transistor is generally used as the lower transistor. The field-effect transistor that supplies power or connects to high voltage is called the upper transistor, and the field-effect transistor that connects to ground, low voltage, or negative voltage is called the lower transistor. Pull-up resistor 2 is used to clamp an uncertain signal to a high level, and pull-down resistor 4 is used to clamp an uncertain signal to a low level. Pull-up resistor 2 and pull-down resistor 4 are typically fixed resistance values.

[0037] When the gate of the first field effect tube 1 is 1, the first field effect tube 1 is turned off, and V in When the gate of the first field effect tube 1 is 0, the first field effect tube 1 is turned on, and the power supply V cc Divide the voltage to V in , V in =R2 / (R0+R2)*V cc , V in Input to the negative input terminal of the single limit comparator 7, the reference voltage V ref Input to the positive input terminal of the single limit comparator 7. When the positive input terminal voltage V ref Higher than the negative input voltage Vin When the single limit comparator 7 outputs 1, when the positive input voltage V ref Lower than the negative input voltage V in When , the output of single limit comparator 7 is 0.

[0038] When en=0 and enb=1, one of the inputs of NAND gate 6 is 0 and the output is 1, that is, whether Vin is greater than V ref , voltage monitoring signal V cc_detect Both are 1, indicating that the voltage monitoring circuit is not working; when en=1 and enb=0, the first field effect transistor 1 is turned on and the voltage monitoring circuit starts working.

[0039] During the voltage monitoring circuit monitoring process, the power supply voltage V cc Will experience a rising or falling process, V in Follow the power supply voltage V cc Synchronously rise or fall. When V in >V ref When the single limit comparator 7 outputs 0, the output of the NAND gate 6 is 1 after the logic operation, indicating that the power supply voltage is safe and the erase and write operation can be performed; when V in <V ref When , the output of the single limit comparator 7 is 1, and the output of the NAND gate 6 is 0 after the logic operation, indicating that the power supply voltage is too low and the erase and write operation cannot be performed.

[0040] Figure 2 FIG. 1 shows a timing diagram of the operation of a voltage monitoring circuit in the prior art. in linearly rises to V ref When they are equal, the intersection point is a, V in Exceed V ref Then it decreases linearly to the value of V ref When they are equal, the intersection point is b, and the erase and write operation can be performed from a to b.

[0041] However, the power supply voltage does not necessarily rise or fall linearly, and may fluctuate due to external interference. If fluctuations occur during the decline process, the voltage monitoring circuit will frequently switch between high and low levels. For this reason, the present application provides a voltage monitoring circuit with hysteresis characteristics.

[0042] First embodiment

[0043] Figure 3The schematic diagram of the voltage monitoring circuit of the first embodiment of the present application is shown. A voltage monitoring circuit with hysteresis characteristics includes a first field effect transistor 1, a pull-up resistor 2, a pull-down resistor 4, a hysteresis comparator 5 and a NAND gate 6. The hysteresis comparator 5 is provided with a positive feedback module 56 for providing a hysteresis voltage. The first field effect transistor 1, the pull-up resistor 2 and the pull-down resistor 4 are connected in series in sequence. The gate of the first field effect transistor 1 is connected to the inverted signal enb of the enable signal en, and the source of the first field effect transistor 1 is connected to the power supply voltage V cc The drain of the first field effect transistor 1 is connected to the pull-up resistor 2, the pull-down resistor 4 is grounded, the negative input terminal of the hysteresis comparator 5 is connected to the series node of the pull-up resistor 2 and the pull-down resistor 4, and the positive input terminal of the hysteresis comparator 5 is connected to the reference voltage V ref The output of the hysteresis comparator 5 is connected to the first input of the NAND gate 6, the second input of the NAND gate 6 is connected to the enable signal en, and the output of the NAND gate 6 outputs the voltage monitoring signal V cc_detect .

[0044] Figure 4 FIG2 shows a schematic diagram of the structure of the hysteresis comparator 5 in the first embodiment of the present application. The hysteresis comparator 5 includes a second field effect transistor 51 , a third field effect transistor 52 , a fourth field effect transistor 53 , a fifth field effect transistor 54 , a sixth field effect transistor 55 and a positive feedback module 56 .

[0045] The second field effect transistor 51 and the fourth field effect transistor 53 are both PMOS transistors, and the third field effect transistor 52 , the fifth field effect transistor 54 and the sixth field effect transistor 55 are all NMOS transistors.

[0046] The gate of the third field effect transistor 52 is the positive input terminal of the hysteresis comparator 5, the gate of the fifth field effect transistor 54 is the negative input terminal of the hysteresis comparator 5, and the parallel connection node of the drain of the fifth field effect transistor 54 and the output terminal of the positive feedback module 56 is the output terminal of the hysteresis comparator 5;

[0047] The source of the second field effect transistor 51 and the source of the fourth field effect transistor 53 are respectively connected to the power supply voltage V cc The drain of the second field effect transistor 51 is connected to the drain of the third field effect transistor 52. The source of the third field effect transistor 52 is connected in parallel with the source of the fifth field effect transistor 54 and then connected to the drain of the sixth field effect transistor 55. The gate of the second field effect transistor 51 is connected to the gate of the fourth field effect transistor 53. The drain of the second field effect transistor 51 is connected to the gate of the second field effect transistor 51. The drain of the fourth field effect transistor 53 is connected to the drain of the fifth field effect transistor 54. The source of the fifth field effect transistor 54 is connected to the drain of the sixth field effect transistor 55. The gate of the sixth field effect transistor 55 is connected to the bias voltage V bias , the source of the sixth field effect transistor 55 is grounded.

[0048] The positive feedback module 56 is a seventh field effect tube, specifically a PMOS tube. The gate of the seventh field effect tube is the input end of the positive feedback module 56. The source of the seventh field effect tube is connected to the power supply voltage V cc , the drain of the seventh field effect transistor is connected to the gate of the fourth field effect transistor 53.

[0049] During power-up, the power supply voltage V cc Rising, V in <V ref When 1=1, the fifth FET 54 is turned off, the fourth FET 53 is turned on, the drain of the fourth FET 53 is at a high level, the seventh FET is turned off, and the hysteresis comparator 5 outputs Out = 1. Current flows through the second FET 51 and the third FET 52, while the current flowing through the fourth FET 53, the fifth FET 54, and the seventh FET is zero.

[0050] V in Linearly rising, when V in >V ref When the hysteresis comparator 5 outputs Out = 0, the seventh FET is turned on, and part of the current flows through the seventh FET. This process continues until the current of the third FET 52 is equal to the sum of the currents of the seventh FET and the second FET 51, and the current of the fifth FET 54 is equal to the current of the fourth FET 53. At this time, the third FET 52 and the fifth FET 54 are operating in the saturation region.

[0051] With the following relationship:

[0052]

[0053]

[0054] The current flowing through the Nth field effect tube is represented by I N For example, the current flowing through the second field effect transistor 51 is I2, and so on. The same is true for other physical quantities below. For example, the length of the Nth field effect transistor channel is represented by L N .

[0055] The current-voltage relationship of the field effect tube working in the saturation region is:

[0056]

[0057] Substituting the above formula into the drain current of the third field effect transistor 52 and the fifth field effect transistor 54 is obtained as follows:

[0058]

[0059]

[0060] again

[0061]

[0062]

[0063]

[0064] Get the positive input voltage of the hysteresis comparator:

[0065]

[0066] Get the negative input voltage of the hysteresis comparator:

[0067]

[0068] in, is the drain saturation current, is the drain saturation voltage, C ox represents the capacitance of the isolation gate and channel oxide layer, μ n Indicates the mobility of electrons in the channel of the NMOS tube, L and W represent the length and width of the field effect tube channel respectively, V G is the gate voltage, V S is the source voltage, V GS is the gate-source voltage, V T is the threshold voltage.

[0069] During power-down, the power supply voltage V cc It drops and reaches the critical point of the hysteresis comparator flip. According to the positive input voltage of the flip state, the hysteresis voltage (Hysteresis Voltage) V is calculated. H :

[0070]

[0071]

[0072] Until the hysteresis comparator reaches the flip critical point, the positive input voltage of the hysteresis comparator is equal to the negative input voltage. , where V H The amplitude is positive, V ref Smaller than before, so smaller V in To flip the comparator output, refer to Figure 5 , V in linearly rises to V ref When they are equal, the intersection point is a, V in Exceed V ref Then it decreases linearly to the value of V refWhen they are equal, the intersection is c, and the erase and write operation can be performed from stage a to c. This shows that the monitored voltage value is lower during power failure, and the stage from a to c is longer than the stage from a to b in the existing technology. Power supply voltage fluctuations will not cause fluctuations in the voltage monitoring module's output value, improving the voltage monitoring circuit's anti-interference ability and enhancing chip reliability.

[0073] In summary, by providing a seventh field-effect transistor in the comparator, this application creates a positive feedback branch in the circuit. This positive feedback branch is a parallel voltage positive feedback circuit where the signal at the drain of the seventh field-effect transistor is amplified by the second field-effect transistor 51 and the seventh field-effect transistor before returning to the drain of the seventh field-effect transistor. When the voltage at the negative input of the hysteresis comparator exceeds the voltage at the positive input, the seventh field-effect transistor conducts during the decreasing phase, providing a hysteresis voltage.

[0074] Second embodiment

[0075] Figure 6 : is a schematic diagram of the structure of the voltage monitoring circuit of the second embodiment of the present application. Different from the first embodiment, a voltage divider resistor 3 is connected in series between the pull-up resistor 2 and the pull-down resistor 4, and the negative input terminal of the hysteresis comparator 5 is connected to the series node of the pull-up resistor 2 and the voltage divider resistor 3. The power supply voltage V cc Divide the voltage to V in , Therefore, the resistance value of the voltage divider resistor 3 can be adjusted to control V in The slope of an increase or decrease.

[0076] Throughout this specification, reference to terms such as "one embodiment," "certain embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0077] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the inventive concept of the present invention, which all fall within the scope of protection of the present invention.

Claims

1. A voltage monitoring circuit with hysteresis characteristics, comprising a first field effect transistor, a pull-up resistor, a pull-down resistor, and a NAND gate, characterized in that: It also includes a hysteresis comparator, which includes a positive feedback module that provides a hysteresis voltage, the first field effect transistor, the pull-up resistor, and the pull-down resistor are connected in series in sequence, the gate of the first field effect transistor is connected to the inverted signal of the enable signal, the source of the first field effect transistor is connected to the power supply voltage, the drain of the first field effect transistor is connected to the pull-up resistor, the pull-down resistor is grounded, the negative input of the hysteresis comparator is connected to the series node of the pull-up resistor and the pull-down resistor, the positive input of the hysteresis comparator is connected to a reference voltage, the output of the hysteresis comparator is connected to the first input of the NAND gate, the second input of the NAND gate is connected to the enable signal, and the output of the NAND gate outputs a voltage monitoring signal; The hysteresis comparator includes a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor and the positive feedback module; The gate of the third field effect transistor is the positive input terminal of the hysteresis comparator, the gate of the fifth field effect transistor is the negative input terminal of the hysteresis comparator, and the parallel connection node of the drain of the fifth field effect transistor and the output terminal of the positive feedback module is the output terminal of the hysteresis comparator; The source of the second field-effect transistor and the source of the fourth field-effect transistor are respectively connected to a power supply voltage, the drain of the second field-effect transistor is connected to the drain of the third field-effect transistor, the source of the third field-effect transistor is connected in parallel with the source of the fifth field-effect transistor and then connected to the drain of the sixth field-effect transistor, the gate of the second field-effect transistor is connected to the gate of the fourth field-effect transistor, the drain of the second field-effect transistor is connected to the gate of the second field-effect transistor, the drain of the fourth field-effect transistor is connected to the drain of the fifth field-effect transistor, the gate of the sixth field-effect transistor is connected to a bias voltage, and the source of the sixth field-effect transistor is grounded; The positive feedback module is a seventh field effect tube; The seventh field effect transistor is a PMOS tube; The gate of the seventh field effect tube is the input end of the positive feedback module, the source of the seventh field effect tube is connected to the power supply voltage, and the drain of the seventh field effect tube is connected to the gate of the fourth field effect tube.

2. The voltage monitoring circuit with hysteresis characteristics according to claim 1, characterized in that: A voltage-dividing resistor is further included, wherein the voltage-dividing resistor is connected between the pull-up resistor and the pull-down resistor, and the negative input terminal of the hysteresis comparator is connected to a series node of the pull-up resistor and the voltage-dividing resistor.

3. The voltage monitoring circuit with hysteresis characteristics according to claim 2, characterized in that: The hysteresis comparator is a voltage comparator.

4. The voltage monitoring circuit with hysteresis characteristics according to claim 1, wherein: The first field effect transistor is a PMOS transistor.

5. The voltage monitoring circuit with hysteresis characteristics according to claim 1, characterized in that: The second field effect transistor and the fourth field effect transistor are both PMOS transistors.

6. The voltage monitoring circuit with hysteresis characteristics according to claim 1, characterized in that: The third field effect transistor, the fifth field effect transistor and the sixth field effect transistor are all NMOS transistors.

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